2 * Intel Sunrisepoint LPSS core support.
4 * Copyright (C) 2015, Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * Heikki Krogerus <heikki.krogerus@linux.intel.com>
9 * Jarkko Nikula <jarkko.nikula@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/clk.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk-provider.h>
19 #include <linux/debugfs.h>
20 #include <linux/idr.h>
21 #include <linux/ioport.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mfd/core.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/property.h>
28 #include <linux/seq_file.h>
29 #include <linux/io-64-nonatomic-lo-hi.h>
31 #include "intel-lpss.h"
33 #define LPSS_DEV_OFFSET 0x000
34 #define LPSS_DEV_SIZE 0x200
35 #define LPSS_PRIV_OFFSET 0x200
36 #define LPSS_PRIV_SIZE 0x100
37 #define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
38 #define LPSS_IDMA64_OFFSET 0x800
39 #define LPSS_IDMA64_SIZE 0x800
41 /* Offsets from lpss->priv */
42 #define LPSS_PRIV_RESETS 0x04
43 #define LPSS_PRIV_RESETS_FUNC BIT(2)
44 #define LPSS_PRIV_RESETS_IDMA 0x3
46 #define LPSS_PRIV_ACTIVELTR 0x10
47 #define LPSS_PRIV_IDLELTR 0x14
49 #define LPSS_PRIV_LTR_REQ BIT(15)
50 #define LPSS_PRIV_LTR_SCALE_MASK 0xc00
51 #define LPSS_PRIV_LTR_SCALE_1US 0x800
52 #define LPSS_PRIV_LTR_SCALE_32US 0xc00
53 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
55 #define LPSS_PRIV_SSP_REG 0x20
56 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
58 #define LPSS_PRIV_REMAP_ADDR 0x40
60 #define LPSS_PRIV_CAPS 0xfc
61 #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
62 #define LPSS_PRIV_CAPS_TYPE_SHIFT 4
63 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
65 /* This matches the type field in CAPS register */
66 enum intel_lpss_dev_type
{
73 const struct intel_lpss_platform_info
*info
;
74 enum intel_lpss_dev_type type
;
76 struct clk_lookup
*clock
;
77 struct mfd_cell
*cell
;
80 u32 priv_ctx
[LPSS_PRIV_REG_COUNT
];
85 struct dentry
*debugfs
;
88 static const struct resource intel_lpss_dev_resources
[] = {
89 DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET
, LPSS_DEV_SIZE
, "lpss_dev"),
90 DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET
, LPSS_PRIV_SIZE
, "lpss_priv"),
94 static const struct resource intel_lpss_idma64_resources
[] = {
95 DEFINE_RES_MEM(LPSS_IDMA64_OFFSET
, LPSS_IDMA64_SIZE
),
99 #define LPSS_IDMA64_DRIVER_NAME "idma64"
102 * Cells needs to be ordered so that the iDMA is created first. This is
103 * because we need to be sure the DMA is available when the host controller
106 static const struct mfd_cell intel_lpss_idma64_cell
= {
107 .name
= LPSS_IDMA64_DRIVER_NAME
,
108 .num_resources
= ARRAY_SIZE(intel_lpss_idma64_resources
),
109 .resources
= intel_lpss_idma64_resources
,
112 static const struct mfd_cell intel_lpss_i2c_cell
= {
113 .name
= "i2c_designware",
114 .num_resources
= ARRAY_SIZE(intel_lpss_dev_resources
),
115 .resources
= intel_lpss_dev_resources
,
118 static const struct mfd_cell intel_lpss_uart_cell
= {
119 .name
= "dw-apb-uart",
120 .num_resources
= ARRAY_SIZE(intel_lpss_dev_resources
),
121 .resources
= intel_lpss_dev_resources
,
124 static const struct mfd_cell intel_lpss_spi_cell
= {
125 .name
= "pxa2xx-spi",
126 .num_resources
= ARRAY_SIZE(intel_lpss_dev_resources
),
127 .resources
= intel_lpss_dev_resources
,
130 static DEFINE_IDA(intel_lpss_devid_ida
);
131 static struct dentry
*intel_lpss_debugfs
;
133 static int intel_lpss_request_dma_module(const char *name
)
135 static bool intel_lpss_dma_requested
;
137 if (intel_lpss_dma_requested
)
140 intel_lpss_dma_requested
= true;
141 return request_module("%s", name
);
144 static void intel_lpss_cache_ltr(struct intel_lpss
*lpss
)
146 lpss
->active_ltr
= readl(lpss
->priv
+ LPSS_PRIV_ACTIVELTR
);
147 lpss
->idle_ltr
= readl(lpss
->priv
+ LPSS_PRIV_IDLELTR
);
150 static int intel_lpss_debugfs_add(struct intel_lpss
*lpss
)
154 dir
= debugfs_create_dir(dev_name(lpss
->dev
), intel_lpss_debugfs
);
158 /* Cache the values into lpss structure */
159 intel_lpss_cache_ltr(lpss
);
161 debugfs_create_x32("capabilities", S_IRUGO
, dir
, &lpss
->caps
);
162 debugfs_create_x32("active_ltr", S_IRUGO
, dir
, &lpss
->active_ltr
);
163 debugfs_create_x32("idle_ltr", S_IRUGO
, dir
, &lpss
->idle_ltr
);
169 static void intel_lpss_debugfs_remove(struct intel_lpss
*lpss
)
171 debugfs_remove_recursive(lpss
->debugfs
);
174 static void intel_lpss_ltr_set(struct device
*dev
, s32 val
)
176 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
180 * Program latency tolerance (LTR) accordingly what has been asked
181 * by the PM QoS layer or disable it in case we were passed
182 * negative value or PM_QOS_LATENCY_ANY.
184 ltr
= readl(lpss
->priv
+ LPSS_PRIV_ACTIVELTR
);
186 if (val
== PM_QOS_LATENCY_ANY
|| val
< 0) {
187 ltr
&= ~LPSS_PRIV_LTR_REQ
;
189 ltr
|= LPSS_PRIV_LTR_REQ
;
190 ltr
&= ~LPSS_PRIV_LTR_SCALE_MASK
;
191 ltr
&= ~LPSS_PRIV_LTR_VALUE_MASK
;
193 if (val
> LPSS_PRIV_LTR_VALUE_MASK
)
194 ltr
|= LPSS_PRIV_LTR_SCALE_32US
| val
>> 5;
196 ltr
|= LPSS_PRIV_LTR_SCALE_1US
| val
;
199 if (ltr
== lpss
->active_ltr
)
202 writel(ltr
, lpss
->priv
+ LPSS_PRIV_ACTIVELTR
);
203 writel(ltr
, lpss
->priv
+ LPSS_PRIV_IDLELTR
);
205 /* Cache the values into lpss structure */
206 intel_lpss_cache_ltr(lpss
);
209 static void intel_lpss_ltr_expose(struct intel_lpss
*lpss
)
211 lpss
->dev
->power
.set_latency_tolerance
= intel_lpss_ltr_set
;
212 dev_pm_qos_expose_latency_tolerance(lpss
->dev
);
215 static void intel_lpss_ltr_hide(struct intel_lpss
*lpss
)
217 dev_pm_qos_hide_latency_tolerance(lpss
->dev
);
218 lpss
->dev
->power
.set_latency_tolerance
= NULL
;
221 static int intel_lpss_assign_devs(struct intel_lpss
*lpss
)
223 const struct mfd_cell
*cell
;
226 type
= lpss
->caps
& LPSS_PRIV_CAPS_TYPE_MASK
;
227 type
>>= LPSS_PRIV_CAPS_TYPE_SHIFT
;
231 cell
= &intel_lpss_i2c_cell
;
234 cell
= &intel_lpss_uart_cell
;
237 cell
= &intel_lpss_spi_cell
;
243 lpss
->cell
= devm_kmemdup(lpss
->dev
, cell
, sizeof(*cell
), GFP_KERNEL
);
252 static bool intel_lpss_has_idma(const struct intel_lpss
*lpss
)
254 return (lpss
->caps
& LPSS_PRIV_CAPS_NO_IDMA
) == 0;
257 static void intel_lpss_set_remap_addr(const struct intel_lpss
*lpss
)
259 resource_size_t addr
= lpss
->info
->mem
->start
;
261 lo_hi_writeq(addr
, lpss
->priv
+ LPSS_PRIV_REMAP_ADDR
);
264 static void intel_lpss_deassert_reset(const struct intel_lpss
*lpss
)
266 u32 value
= LPSS_PRIV_RESETS_FUNC
| LPSS_PRIV_RESETS_IDMA
;
268 /* Bring out the device from reset */
269 writel(value
, lpss
->priv
+ LPSS_PRIV_RESETS
);
272 static void intel_lpss_init_dev(const struct intel_lpss
*lpss
)
274 u32 value
= LPSS_PRIV_SSP_REG_DIS_DMA_FIN
;
276 intel_lpss_deassert_reset(lpss
);
278 intel_lpss_set_remap_addr(lpss
);
280 if (!intel_lpss_has_idma(lpss
))
283 /* Make sure that SPI multiblock DMA transfers are re-enabled */
284 if (lpss
->type
== LPSS_DEV_SPI
)
285 writel(value
, lpss
->priv
+ LPSS_PRIV_SSP_REG
);
288 static void intel_lpss_unregister_clock_tree(struct clk
*clk
)
293 parent
= clk_get_parent(clk
);
299 static int intel_lpss_register_clock_divider(struct intel_lpss
*lpss
,
304 struct clk
*tmp
= *clk
;
306 snprintf(name
, sizeof(name
), "%s-enable", devname
);
307 tmp
= clk_register_gate(NULL
, name
, __clk_get_name(tmp
), 0,
308 lpss
->priv
, 0, 0, NULL
);
312 snprintf(name
, sizeof(name
), "%s-div", devname
);
313 tmp
= clk_register_fractional_divider(NULL
, name
, __clk_get_name(tmp
),
314 0, lpss
->priv
, 1, 15, 16, 15, 0,
320 snprintf(name
, sizeof(name
), "%s-update", devname
);
321 tmp
= clk_register_gate(NULL
, name
, __clk_get_name(tmp
),
322 CLK_SET_RATE_PARENT
, lpss
->priv
, 31, 0, NULL
);
330 static int intel_lpss_register_clock(struct intel_lpss
*lpss
)
332 const struct mfd_cell
*cell
= lpss
->cell
;
337 if (!lpss
->info
->clk_rate
)
341 clk
= clk_register_fixed_rate(NULL
, dev_name(lpss
->dev
), NULL
, 0,
342 lpss
->info
->clk_rate
);
346 snprintf(devname
, sizeof(devname
), "%s.%d", cell
->name
, lpss
->devid
);
349 * Support for clock divider only if it has some preset value.
350 * Otherwise we assume that the divider is not used.
352 if (lpss
->type
!= LPSS_DEV_I2C
) {
353 ret
= intel_lpss_register_clock_divider(lpss
, devname
, &clk
);
355 goto err_clk_register
;
360 /* Clock for the host controller */
361 lpss
->clock
= clkdev_create(clk
, lpss
->info
->clk_con_id
, "%s", devname
);
363 goto err_clk_register
;
370 intel_lpss_unregister_clock_tree(clk
);
375 static void intel_lpss_unregister_clock(struct intel_lpss
*lpss
)
377 if (IS_ERR_OR_NULL(lpss
->clk
))
380 clkdev_drop(lpss
->clock
);
381 intel_lpss_unregister_clock_tree(lpss
->clk
);
384 int intel_lpss_probe(struct device
*dev
,
385 const struct intel_lpss_platform_info
*info
)
387 struct intel_lpss
*lpss
;
390 if (!info
|| !info
->mem
|| info
->irq
<= 0)
393 lpss
= devm_kzalloc(dev
, sizeof(*lpss
), GFP_KERNEL
);
397 lpss
->priv
= devm_ioremap(dev
, info
->mem
->start
+ LPSS_PRIV_OFFSET
,
404 lpss
->caps
= readl(lpss
->priv
+ LPSS_PRIV_CAPS
);
406 dev_set_drvdata(dev
, lpss
);
408 ret
= intel_lpss_assign_devs(lpss
);
412 lpss
->cell
->properties
= info
->properties
;
414 intel_lpss_init_dev(lpss
);
416 lpss
->devid
= ida_simple_get(&intel_lpss_devid_ida
, 0, 0, GFP_KERNEL
);
420 ret
= intel_lpss_register_clock(lpss
);
422 goto err_clk_register
;
424 intel_lpss_ltr_expose(lpss
);
426 ret
= intel_lpss_debugfs_add(lpss
);
428 dev_warn(dev
, "Failed to create debugfs entries\n");
430 if (intel_lpss_has_idma(lpss
)) {
432 * Ensure the DMA driver is loaded before the host
433 * controller device appears, so that the host controller
434 * driver can request its DMA channels as early as
437 * If the DMA module is not there that's OK as well.
439 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME
);
441 ret
= mfd_add_devices(dev
, lpss
->devid
, &intel_lpss_idma64_cell
,
442 1, info
->mem
, info
->irq
, NULL
);
444 dev_warn(dev
, "Failed to add %s, fallback to PIO\n",
445 LPSS_IDMA64_DRIVER_NAME
);
448 ret
= mfd_add_devices(dev
, lpss
->devid
, lpss
->cell
,
449 1, info
->mem
, info
->irq
, NULL
);
456 intel_lpss_debugfs_remove(lpss
);
457 intel_lpss_ltr_hide(lpss
);
458 intel_lpss_unregister_clock(lpss
);
461 ida_simple_remove(&intel_lpss_devid_ida
, lpss
->devid
);
465 EXPORT_SYMBOL_GPL(intel_lpss_probe
);
467 void intel_lpss_remove(struct device
*dev
)
469 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
471 mfd_remove_devices(dev
);
472 intel_lpss_debugfs_remove(lpss
);
473 intel_lpss_ltr_hide(lpss
);
474 intel_lpss_unregister_clock(lpss
);
475 ida_simple_remove(&intel_lpss_devid_ida
, lpss
->devid
);
477 EXPORT_SYMBOL_GPL(intel_lpss_remove
);
479 static int resume_lpss_device(struct device
*dev
, void *data
)
481 pm_runtime_resume(dev
);
485 int intel_lpss_prepare(struct device
*dev
)
488 * Resume both child devices before entering system sleep. This
489 * ensures that they are in proper state before they get suspended.
491 device_for_each_child_reverse(dev
, NULL
, resume_lpss_device
);
494 EXPORT_SYMBOL_GPL(intel_lpss_prepare
);
496 int intel_lpss_suspend(struct device
*dev
)
498 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
501 /* Save device context */
502 for (i
= 0; i
< LPSS_PRIV_REG_COUNT
; i
++)
503 lpss
->priv_ctx
[i
] = readl(lpss
->priv
+ i
* 4);
506 * If the device type is not UART, then put the controller into
507 * reset. UART cannot be put into reset since S3/S0ix fail when
508 * no_console_suspend flag is enabled.
510 if (lpss
->type
!= LPSS_DEV_UART
)
511 writel(0, lpss
->priv
+ LPSS_PRIV_RESETS
);
515 EXPORT_SYMBOL_GPL(intel_lpss_suspend
);
517 int intel_lpss_resume(struct device
*dev
)
519 struct intel_lpss
*lpss
= dev_get_drvdata(dev
);
522 intel_lpss_deassert_reset(lpss
);
524 /* Restore device context */
525 for (i
= 0; i
< LPSS_PRIV_REG_COUNT
; i
++)
526 writel(lpss
->priv_ctx
[i
], lpss
->priv
+ i
* 4);
530 EXPORT_SYMBOL_GPL(intel_lpss_resume
);
532 static int __init
intel_lpss_init(void)
534 intel_lpss_debugfs
= debugfs_create_dir("intel_lpss", NULL
);
537 module_init(intel_lpss_init
);
539 static void __exit
intel_lpss_exit(void)
541 debugfs_remove(intel_lpss_debugfs
);
543 module_exit(intel_lpss_exit
);
545 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
546 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
547 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
548 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
549 MODULE_DESCRIPTION("Intel LPSS core driver");
550 MODULE_LICENSE("GPL v2");