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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / drivers / pci / host / pci-aardvark.c
blob5f3048e75becb598b14013382ed102fa59a6f5b4
1 /*
2 * Driver for the Aardvark PCIe controller, used on Marvell Armada
3 * 3700.
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/kernel.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/of_address.h>
23 #include <linux/of_pci.h>
24
25 /* PCIe core registers */
26 #define PCIE_CORE_CMD_STATUS_REG 0x4
27 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
28 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
29 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
30 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
31 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
32 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
33 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
34 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
35 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
36 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
37 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
38 #define PCIE_CORE_LINK_TRAINING BIT(5)
39 #define PCIE_CORE_LINK_WIDTH_SHIFT 20
40 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
42 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
43 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
44 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
45
46 /* PIO registers base address and register offsets */
47 #define PIO_BASE_ADDR 0x4000
48 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
49 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
50 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
51 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
52 #define PIO_COMPLETION_STATUS_SHIFT 7
53 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
54 #define PIO_COMPLETION_STATUS_OK 0
55 #define PIO_COMPLETION_STATUS_UR 1
56 #define PIO_COMPLETION_STATUS_CRS 2
57 #define PIO_COMPLETION_STATUS_CA 4
58 #define PIO_NON_POSTED_REQ BIT(0)
59 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
60 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
61 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
62 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
63 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
64 #define PIO_START (PIO_BASE_ADDR + 0x1c)
65 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
66 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
67
68 /* Aardvark Control registers */
69 #define CONTROL_BASE_ADDR 0x4800
70 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
71 #define PCIE_GEN_SEL_MSK 0x3
72 #define PCIE_GEN_SEL_SHIFT 0x0
73 #define SPEED_GEN_1 0
74 #define SPEED_GEN_2 1
75 #define SPEED_GEN_3 2
76 #define IS_RC_MSK 1
77 #define IS_RC_SHIFT 2
78 #define LANE_CNT_MSK 0x18
79 #define LANE_CNT_SHIFT 0x3
80 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
81 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
82 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
83 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
84 #define LINK_TRAINING_EN BIT(6)
85 #define LEGACY_INTA BIT(28)
86 #define LEGACY_INTB BIT(29)
87 #define LEGACY_INTC BIT(30)
88 #define LEGACY_INTD BIT(31)
89 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
90 #define HOT_RESET_GEN BIT(0)
91 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
92 #define PCIE_CORE_CTRL2_RESERVED 0x7
93 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
94 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
95 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
96 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
97 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
98 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
99 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
100 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
101 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
102 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
103 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
104 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
105 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
106 #define PCIE_ISR1_FLUSH BIT(5)
107 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
108 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
109 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
110 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
111 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
112 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
113 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
114
115 /* PCIe window configuration */
116 #define OB_WIN_BASE_ADDR 0x4c00
117 #define OB_WIN_BLOCK_SIZE 0x20
118 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
119 OB_WIN_BLOCK_SIZE * (win) + \
120 (offset))
121 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
122 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
123 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
124 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
125 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
126 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
127 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
128
129 /* PCIe window types */
130 #define OB_PCIE_MEM 0x0
131 #define OB_PCIE_IO 0x4
132
133 /* LMI registers base address and register offsets */
134 #define LMI_BASE_ADDR 0x6000
135 #define CFG_REG (LMI_BASE_ADDR + 0x0)
136 #define LTSSM_SHIFT 24
137 #define LTSSM_MASK 0x3f
138 #define LTSSM_L0 0x10
139 #define RC_BAR_CONFIG 0x300
140
141 /* PCIe core controller registers */
142 #define CTRL_CORE_BASE_ADDR 0x18000
143 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
144 #define CTRL_MODE_SHIFT 0x0
145 #define CTRL_MODE_MASK 0x1
146 #define PCIE_CORE_MODE_DIRECT 0x0
147 #define PCIE_CORE_MODE_COMMAND 0x1
148
149 /* PCIe Central Interrupts Registers */
150 #define CENTRAL_INT_BASE_ADDR 0x1b000
151 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
152 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
153 #define PCIE_IRQ_CMDQ_INT BIT(0)
154 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
155 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
156 #define PCIE_IRQ_DMA_INT BIT(4)
157 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
158 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
159 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
160 #define PCIE_IRQ_COMPQ_INT BIT(12)
161 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
162 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
163 #define PCIE_IRQ_CORE_INT BIT(16)
164 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
165 #define PCIE_IRQ_DPMU_INT BIT(18)
166 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
167 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
168 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
169 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
170 #define PCIE_IRQ_EP_STATUS BIT(23)
171 #define PCIE_IRQ_ALL_MASK 0xfff0fb
172 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
173
174 /* Transaction types */
175 #define PCIE_CONFIG_RD_TYPE0 0x8
176 #define PCIE_CONFIG_RD_TYPE1 0x9
177 #define PCIE_CONFIG_WR_TYPE0 0xa
178 #define PCIE_CONFIG_WR_TYPE1 0xb
179
180 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
181 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
182 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
183 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
184 #define PCIE_CONF_ADDR(bus, devfn, where) \
185 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
186 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
187
188 #define PIO_TIMEOUT_MS 1
189
190 #define LINK_WAIT_MAX_RETRIES 10
191 #define LINK_WAIT_USLEEP_MIN 90000
192 #define LINK_WAIT_USLEEP_MAX 100000
193
194 #define MSI_IRQ_NUM 32
195
196 struct advk_pcie {
197 struct platform_device *pdev;
198 void __iomem *base;
199 struct list_head resources;
200 struct irq_domain *irq_domain;
201 struct irq_chip irq_chip;
202 struct irq_domain *msi_domain;
203 struct irq_domain *msi_inner_domain;
204 struct irq_chip msi_bottom_irq_chip;
205 struct irq_chip msi_irq_chip;
206 struct msi_domain_info msi_domain_info;
207 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
208 struct mutex msi_used_lock;
209 u16 msi_msg;
210 int root_bus_nr;
211 };
212
213 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
214 {
215 writel(val, pcie->base + reg);
216 }
217
218 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
219 {
220 return readl(pcie->base + reg);
221 }
222
223 static int advk_pcie_link_up(struct advk_pcie *pcie)
224 {
225 u32 val, ltssm_state;
226
227 val = advk_readl(pcie, CFG_REG);
228 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
229 return ltssm_state >= LTSSM_L0;
230 }
231
232 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
233 {
234 struct device *dev = &pcie->pdev->dev;
235 int retries;
236
237 /* check if the link is up or not */
238 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
239 if (advk_pcie_link_up(pcie)) {
240 dev_info(dev, "link up\n");
241 return 0;
242 }
243
244 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
245 }
246
247 dev_err(dev, "link never came up\n");
248 return -ETIMEDOUT;
249 }
250
251 /*
252 * Set PCIe address window register which could be used for memory
253 * mapping.
254 */
255 static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
256 u32 win_num, u32 match_ms,
257 u32 match_ls, u32 mask_ms,
258 u32 mask_ls, u32 remap_ms,
259 u32 remap_ls, u32 action)
260 {
261 advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num));
262 advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num));
263 advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num));
264 advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num));
265 advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num));
266 advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num));
267 advk_writel(pcie, action, OB_WIN_ACTIONS(win_num));
268 advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
269 }
270
271 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
272 {
273 u32 reg;
274 int i;
275
276 /* Point PCIe unit MBUS decode windows to DRAM space */
277 for (i = 0; i < 8; i++)
278 advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0);
279
280 /* Set to Direct mode */
281 reg = advk_readl(pcie, CTRL_CONFIG_REG);
282 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
283 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
284 advk_writel(pcie, reg, CTRL_CONFIG_REG);
285
286 /* Set PCI global control register to RC mode */
287 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
288 reg |= (IS_RC_MSK << IS_RC_SHIFT);
289 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
290
291 /* Set Advanced Error Capabilities and Control PF0 register */
292 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
293 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
294 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
295 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
296 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
297
298 /* Set PCIe Device Control and Status 1 PF0 register */
299 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
300 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
301 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
302 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
303 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
304 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
305
306 /* Program PCIe Control 2 to disable strict ordering */
307 reg = PCIE_CORE_CTRL2_RESERVED |
308 PCIE_CORE_CTRL2_TD_ENABLE;
309 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
310
311 /* Set GEN2 */
312 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
313 reg &= ~PCIE_GEN_SEL_MSK;
314 reg |= SPEED_GEN_2;
315 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
316
317 /* Set lane X1 */
318 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
319 reg &= ~LANE_CNT_MSK;
320 reg |= LANE_COUNT_1;
321 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
322
323 /* Enable link training */
324 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
325 reg |= LINK_TRAINING_EN;
326 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
327
328 /* Enable MSI */
329 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
330 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
331 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
332
333 /* Clear all interrupts */
334 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
335 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
336 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
337
338 /* Disable All ISR0/1 Sources */
339 reg = PCIE_ISR0_ALL_MASK;
340 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
341 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
342
343 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
344
345 /* Unmask all MSI's */
346 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
347
348 /* Enable summary interrupt for GIC SPI source */
349 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
350 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
351
352 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
353 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
354 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
355
356 /* Bypass the address window mapping for PIO */
357 reg = advk_readl(pcie, PIO_CTRL);
358 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
359 advk_writel(pcie, reg, PIO_CTRL);
360
361 /* Start link training */
362 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
363 reg |= PCIE_CORE_LINK_TRAINING;
364 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
365
366 advk_pcie_wait_for_link(pcie);
367
368 reg = PCIE_CORE_LINK_L0S_ENTRY |
369 (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
370 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
371
372 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
373 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
374 PCIE_CORE_CMD_IO_ACCESS_EN |
375 PCIE_CORE_CMD_MEM_IO_REQ_EN;
376 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
377 }
378
379 static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
380 {
381 struct device *dev = &pcie->pdev->dev;
382 u32 reg;
383 unsigned int status;
384 char *strcomp_status, *str_posted;
385
386 reg = advk_readl(pcie, PIO_STAT);
387 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
388 PIO_COMPLETION_STATUS_SHIFT;
389
390 if (!status)
391 return;
392
393 switch (status) {
394 case PIO_COMPLETION_STATUS_UR:
395 strcomp_status = "UR";
396 break;
397 case PIO_COMPLETION_STATUS_CRS:
398 strcomp_status = "CRS";
399 break;
400 case PIO_COMPLETION_STATUS_CA:
401 strcomp_status = "CA";
402 break;
403 default:
404 strcomp_status = "Unknown";
405 break;
406 }
407
408 if (reg & PIO_NON_POSTED_REQ)
409 str_posted = "Non-posted";
410 else
411 str_posted = "Posted";
412
413 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
414 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
415 }
416
417 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
418 {
419 struct device *dev = &pcie->pdev->dev;
420 unsigned long timeout;
421
422 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS);
423
424 while (time_before(jiffies, timeout)) {
425 u32 start, isr;
426
427 start = advk_readl(pcie, PIO_START);
428 isr = advk_readl(pcie, PIO_ISR);
429 if (!start && isr)
430 return 0;
431 }
432
433 dev_err(dev, "config read/write timed out\n");
434 return -ETIMEDOUT;
435 }
436
437 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
438 int where, int size, u32 *val)
439 {
440 struct advk_pcie *pcie = bus->sysdata;
441 u32 reg;
442 int ret;
443
444 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) {
445 *val = 0xffffffff;
446 return PCIBIOS_DEVICE_NOT_FOUND;
447 }
448
449 /* Start PIO */
450 advk_writel(pcie, 0, PIO_START);
451 advk_writel(pcie, 1, PIO_ISR);
452
453 /* Program the control register */
454 reg = advk_readl(pcie, PIO_CTRL);
455 reg &= ~PIO_CTRL_TYPE_MASK;
456 if (bus->number == pcie->root_bus_nr)
457 reg |= PCIE_CONFIG_RD_TYPE0;
458 else
459 reg |= PCIE_CONFIG_RD_TYPE1;
460 advk_writel(pcie, reg, PIO_CTRL);
461
462 /* Program the address registers */
463 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
464 advk_writel(pcie, reg, PIO_ADDR_LS);
465 advk_writel(pcie, 0, PIO_ADDR_MS);
466
467 /* Program the data strobe */
468 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
469
470 /* Start the transfer */
471 advk_writel(pcie, 1, PIO_START);
472
473 ret = advk_pcie_wait_pio(pcie);
474 if (ret < 0)
475 return PCIBIOS_SET_FAILED;
476
477 advk_pcie_check_pio_status(pcie);
478
479 /* Get the read result */
480 *val = advk_readl(pcie, PIO_RD_DATA);
481 if (size == 1)
482 *val = (*val >> (8 * (where & 3))) & 0xff;
483 else if (size == 2)
484 *val = (*val >> (8 * (where & 3))) & 0xffff;
485
486 return PCIBIOS_SUCCESSFUL;
487 }
488
489 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
490 int where, int size, u32 val)
491 {
492 struct advk_pcie *pcie = bus->sysdata;
493 u32 reg;
494 u32 data_strobe = 0x0;
495 int offset;
496 int ret;
497
498 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
499 return PCIBIOS_DEVICE_NOT_FOUND;
500
501 if (where % size)
502 return PCIBIOS_SET_FAILED;
503
504 /* Start PIO */
505 advk_writel(pcie, 0, PIO_START);
506 advk_writel(pcie, 1, PIO_ISR);
507
508 /* Program the control register */
509 reg = advk_readl(pcie, PIO_CTRL);
510 reg &= ~PIO_CTRL_TYPE_MASK;
511 if (bus->number == pcie->root_bus_nr)
512 reg |= PCIE_CONFIG_WR_TYPE0;
513 else
514 reg |= PCIE_CONFIG_WR_TYPE1;
515 advk_writel(pcie, reg, PIO_CTRL);
516
517 /* Program the address registers */
518 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
519 advk_writel(pcie, reg, PIO_ADDR_LS);
520 advk_writel(pcie, 0, PIO_ADDR_MS);
521
522 /* Calculate the write strobe */
523 offset = where & 0x3;
524 reg = val << (8 * offset);
525 data_strobe = GENMASK(size - 1, 0) << offset;
526
527 /* Program the data register */
528 advk_writel(pcie, reg, PIO_WR_DATA);
529
530 /* Program the data strobe */
531 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
532
533 /* Start the transfer */
534 advk_writel(pcie, 1, PIO_START);
535
536 ret = advk_pcie_wait_pio(pcie);
537 if (ret < 0)
538 return PCIBIOS_SET_FAILED;
539
540 advk_pcie_check_pio_status(pcie);
541
542 return PCIBIOS_SUCCESSFUL;
543 }
544
545 static struct pci_ops advk_pcie_ops = {
546 .read = advk_pcie_rd_conf,
547 .write = advk_pcie_wr_conf,
548 };
549
550 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
551 struct msi_msg *msg)
552 {
553 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
554 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
555
556 msg->address_lo = lower_32_bits(msi_msg);
557 msg->address_hi = upper_32_bits(msi_msg);
558 msg->data = data->irq;
559 }
560
561 static int advk_msi_set_affinity(struct irq_data *irq_data,
562 const struct cpumask *mask, bool force)
563 {
564 return -EINVAL;
565 }
566
567 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
568 unsigned int virq,
569 unsigned int nr_irqs, void *args)
570 {
571 struct advk_pcie *pcie = domain->host_data;
572 int hwirq, i;
573
574 mutex_lock(&pcie->msi_used_lock);
575 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
576 0, nr_irqs, 0);
577 if (hwirq >= MSI_IRQ_NUM) {
578 mutex_unlock(&pcie->msi_used_lock);
579 return -ENOSPC;
580 }
581
582 bitmap_set(pcie->msi_used, hwirq, nr_irqs);
583 mutex_unlock(&pcie->msi_used_lock);
584
585 for (i = 0; i < nr_irqs; i++)
586 irq_domain_set_info(domain, virq + i, hwirq + i,
587 &pcie->msi_bottom_irq_chip,
588 domain->host_data, handle_simple_irq,
589 NULL, NULL);
590
591 return hwirq;
592 }
593
594 static void advk_msi_irq_domain_free(struct irq_domain *domain,
595 unsigned int virq, unsigned int nr_irqs)
596 {
597 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
598 struct advk_pcie *pcie = domain->host_data;
599
600 mutex_lock(&pcie->msi_used_lock);
601 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
602 mutex_unlock(&pcie->msi_used_lock);
603 }
604
605 static const struct irq_domain_ops advk_msi_domain_ops = {
606 .alloc = advk_msi_irq_domain_alloc,
607 .free = advk_msi_irq_domain_free,
608 };
609
610 static void advk_pcie_irq_mask(struct irq_data *d)
611 {
612 struct advk_pcie *pcie = d->domain->host_data;
613 irq_hw_number_t hwirq = irqd_to_hwirq(d);
614 u32 mask;
615
616 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
617 mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
618 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
619 }
620
621 static void advk_pcie_irq_unmask(struct irq_data *d)
622 {
623 struct advk_pcie *pcie = d->domain->host_data;
624 irq_hw_number_t hwirq = irqd_to_hwirq(d);
625 u32 mask;
626
627 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
628 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
629 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
630 }
631
632 static int advk_pcie_irq_map(struct irq_domain *h,
633 unsigned int virq, irq_hw_number_t hwirq)
634 {
635 struct advk_pcie *pcie = h->host_data;
636
637 advk_pcie_irq_mask(irq_get_irq_data(virq));
638 irq_set_status_flags(virq, IRQ_LEVEL);
639 irq_set_chip_and_handler(virq, &pcie->irq_chip,
640 handle_level_irq);
641 irq_set_chip_data(virq, pcie);
642
643 return 0;
644 }
645
646 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
647 .map = advk_pcie_irq_map,
648 .xlate = irq_domain_xlate_onecell,
649 };
650
651 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
652 {
653 struct device *dev = &pcie->pdev->dev;
654 struct device_node *node = dev->of_node;
655 struct irq_chip *bottom_ic, *msi_ic;
656 struct msi_domain_info *msi_di;
657 phys_addr_t msi_msg_phys;
658
659 mutex_init(&pcie->msi_used_lock);
660
661 bottom_ic = &pcie->msi_bottom_irq_chip;
662
663 bottom_ic->name = "MSI";
664 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
665 bottom_ic->irq_set_affinity = advk_msi_set_affinity;
666
667 msi_ic = &pcie->msi_irq_chip;
668 msi_ic->name = "advk-MSI";
669
670 msi_di = &pcie->msi_domain_info;
671 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
672 MSI_FLAG_MULTI_PCI_MSI;
673 msi_di->chip = msi_ic;
674
675 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
676
677 advk_writel(pcie, lower_32_bits(msi_msg_phys),
678 PCIE_MSI_ADDR_LOW_REG);
679 advk_writel(pcie, upper_32_bits(msi_msg_phys),
680 PCIE_MSI_ADDR_HIGH_REG);
681
682 pcie->msi_inner_domain =
683 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
684 &advk_msi_domain_ops, pcie);
685 if (!pcie->msi_inner_domain)
686 return -ENOMEM;
687
688 pcie->msi_domain =
689 pci_msi_create_irq_domain(of_node_to_fwnode(node),
690 msi_di, pcie->msi_inner_domain);
691 if (!pcie->msi_domain) {
692 irq_domain_remove(pcie->msi_inner_domain);
693 return -ENOMEM;
694 }
695
696 return 0;
697 }
698
699 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
700 {
701 irq_domain_remove(pcie->msi_domain);
702 irq_domain_remove(pcie->msi_inner_domain);
703 }
704
705 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
706 {
707 struct device *dev = &pcie->pdev->dev;
708 struct device_node *node = dev->of_node;
709 struct device_node *pcie_intc_node;
710 struct irq_chip *irq_chip;
711
712 pcie_intc_node = of_get_next_child(node, NULL);
713 if (!pcie_intc_node) {
714 dev_err(dev, "No PCIe Intc node found\n");
715 return -ENODEV;
716 }
717
718 irq_chip = &pcie->irq_chip;
719
720 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
721 dev_name(dev));
722 if (!irq_chip->name) {
723 of_node_put(pcie_intc_node);
724 return -ENOMEM;
725 }
726
727 irq_chip->irq_mask = advk_pcie_irq_mask;
728 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
729 irq_chip->irq_unmask = advk_pcie_irq_unmask;
730
731 pcie->irq_domain =
732 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
733 &advk_pcie_irq_domain_ops, pcie);
734 if (!pcie->irq_domain) {
735 dev_err(dev, "Failed to get a INTx IRQ domain\n");
736 of_node_put(pcie_intc_node);
737 return -ENOMEM;
738 }
739
740 return 0;
741 }
742
743 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
744 {
745 irq_domain_remove(pcie->irq_domain);
746 }
747
748 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
749 {
750 u32 msi_val, msi_mask, msi_status, msi_idx;
751 u16 msi_data;
752
753 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
754 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
755 msi_status = msi_val & ~msi_mask;
756
757 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
758 if (!(BIT(msi_idx) & msi_status))
759 continue;
760
761 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
762 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
763 generic_handle_irq(msi_data);
764 }
765
766 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
767 PCIE_ISR0_REG);
768 }
769
770 static void advk_pcie_handle_int(struct advk_pcie *pcie)
771 {
772 u32 isr0_val, isr0_mask, isr0_status;
773 u32 isr1_val, isr1_mask, isr1_status;
774 int i, virq;
775
776 isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
777 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
778 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
779
780 isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
781 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
782 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
783
784 if (!isr0_status && !isr1_status) {
785 advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
786 advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
787 return;
788 }
789
790 /* Process MSI interrupts */
791 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
792 advk_pcie_handle_msi(pcie);
793
794 /* Process legacy interrupts */
795 for (i = 0; i < PCI_NUM_INTX; i++) {
796 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
797 continue;
798
799 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
800 PCIE_ISR1_REG);
801
802 virq = irq_find_mapping(pcie->irq_domain, i);
803 generic_handle_irq(virq);
804 }
805 }
806
807 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
808 {
809 struct advk_pcie *pcie = arg;
810 u32 status;
811
812 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
813 if (!(status & PCIE_IRQ_CORE_INT))
814 return IRQ_NONE;
815
816 advk_pcie_handle_int(pcie);
817
818 /* Clear interrupt */
819 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
820
821 return IRQ_HANDLED;
822 }
823
824 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
825 {
826 int err, res_valid = 0;
827 struct device *dev = &pcie->pdev->dev;
828 struct device_node *np = dev->of_node;
829 struct resource_entry *win, *tmp;
830 resource_size_t iobase;
831
832 INIT_LIST_HEAD(&pcie->resources);
833
834 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
835 &iobase);
836 if (err)
837 return err;
838
839 err = devm_request_pci_bus_resources(dev, &pcie->resources);
840 if (err)
841 goto out_release_res;
842
843 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
844 struct resource *res = win->res;
845
846 switch (resource_type(res)) {
847 case IORESOURCE_IO:
848 advk_pcie_set_ob_win(pcie, 1,
849 upper_32_bits(res->start),
850 lower_32_bits(res->start),
851 0, 0xF8000000, 0,
852 lower_32_bits(res->start),
853 OB_PCIE_IO);
854 err = pci_remap_iospace(res, iobase);
855 if (err) {
856 dev_warn(dev, "error %d: failed to map resource %pR\n",
857 err, res);
858 resource_list_destroy_entry(win);
859 }
860 break;
861 case IORESOURCE_MEM:
862 advk_pcie_set_ob_win(pcie, 0,
863 upper_32_bits(res->start),
864 lower_32_bits(res->start),
865 0x0, 0xF8000000, 0,
866 lower_32_bits(res->start),
867 (2 << 20) | OB_PCIE_MEM);
868 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
869 break;
870 case IORESOURCE_BUS:
871 pcie->root_bus_nr = res->start;
872 break;
873 }
874 }
875
876 if (!res_valid) {
877 dev_err(dev, "non-prefetchable memory resource required\n");
878 err = -EINVAL;
879 goto out_release_res;
880 }
881
882 return 0;
883
884 out_release_res:
885 pci_free_resource_list(&pcie->resources);
886 return err;
887 }
888
889 static int advk_pcie_probe(struct platform_device *pdev)
890 {
891 struct device *dev = &pdev->dev;
892 struct advk_pcie *pcie;
893 struct resource *res;
894 struct pci_bus *bus, *child;
895 struct pci_host_bridge *bridge;
896 int ret, irq;
897
898 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
899 if (!bridge)
900 return -ENOMEM;
901
902 pcie = pci_host_bridge_priv(bridge);
903 pcie->pdev = pdev;
904
905 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
906 pcie->base = devm_ioremap_resource(dev, res);
907 if (IS_ERR(pcie->base))
908 return PTR_ERR(pcie->base);
909
910 irq = platform_get_irq(pdev, 0);
911 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
912 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
913 pcie);
914 if (ret) {
915 dev_err(dev, "Failed to register interrupt\n");
916 return ret;
917 }
918
919 ret = advk_pcie_parse_request_of_pci_ranges(pcie);
920 if (ret) {
921 dev_err(dev, "Failed to parse resources\n");
922 return ret;
923 }
924
925 advk_pcie_setup_hw(pcie);
926
927 ret = advk_pcie_init_irq_domain(pcie);
928 if (ret) {
929 dev_err(dev, "Failed to initialize irq\n");
930 return ret;
931 }
932
933 ret = advk_pcie_init_msi_irq_domain(pcie);
934 if (ret) {
935 dev_err(dev, "Failed to initialize irq\n");
936 advk_pcie_remove_irq_domain(pcie);
937 return ret;
938 }
939
940 list_splice_init(&pcie->resources, &bridge->windows);
941 bridge->dev.parent = dev;
942 bridge->sysdata = pcie;
943 bridge->busnr = 0;
944 bridge->ops = &advk_pcie_ops;
945 bridge->map_irq = of_irq_parse_and_map_pci;
946 bridge->swizzle_irq = pci_common_swizzle;
947
948 ret = pci_scan_root_bus_bridge(bridge);
949 if (ret < 0) {
950 advk_pcie_remove_msi_irq_domain(pcie);
951 advk_pcie_remove_irq_domain(pcie);
952 return ret;
953 }
954
955 bus = bridge->bus;
956
957 pci_bus_size_bridges(bus);
958 pci_bus_assign_resources(bus);
959
960 list_for_each_entry(child, &bus->children, node)
961 pcie_bus_configure_settings(child);
962
963 pci_bus_add_devices(bus);
964 return 0;
965 }
966
967 static const struct of_device_id advk_pcie_of_match_table[] = {
968 { .compatible = "marvell,armada-3700-pcie", },
969 {},
970 };
971
972 static struct platform_driver advk_pcie_driver = {
973 .driver = {
974 .name = "advk-pcie",
975 .of_match_table = advk_pcie_of_match_table,
976 /* Driver unloading/unbinding currently not supported */
977 .suppress_bind_attrs = true,
978 },
979 .probe = advk_pcie_probe,
980 };
981 builtin_platform_driver(advk_pcie_driver);
Linux with added FPC-III support