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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / drivers / pci / probe.c
blobe23bfd9845b12f3808e88838bbb1bdec5c4dcc81
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/irqdomain.h>
19 #include <linux/pm_runtime.h>
20 #include "pci.h"
21
22 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
23 #define CARDBUS_RESERVE_BUSNR 3
24
25 static struct resource busn_resource = {
26 .name = "PCI busn",
27 .start = 0,
28 .end = 255,
29 .flags = IORESOURCE_BUS,
30 };
31
32 /* Ugh. Need to stop exporting this to modules. */
33 LIST_HEAD(pci_root_buses);
34 EXPORT_SYMBOL(pci_root_buses);
35
36 static LIST_HEAD(pci_domain_busn_res_list);
37
38 struct pci_domain_busn_res {
39 struct list_head list;
40 struct resource res;
41 int domain_nr;
42 };
43
44 static struct resource *get_pci_domain_busn_res(int domain_nr)
45 {
46 struct pci_domain_busn_res *r;
47
48 list_for_each_entry(r, &pci_domain_busn_res_list, list)
49 if (r->domain_nr == domain_nr)
50 return &r->res;
51
52 r = kzalloc(sizeof(*r), GFP_KERNEL);
53 if (!r)
54 return NULL;
55
56 r->domain_nr = domain_nr;
57 r->res.start = 0;
58 r->res.end = 0xff;
59 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
60
61 list_add_tail(&r->list, &pci_domain_busn_res_list);
62
63 return &r->res;
64 }
65
66 static int find_anything(struct device *dev, void *data)
67 {
68 return 1;
69 }
70
71 /*
72 * Some device drivers need know if pci is initiated.
73 * Basically, we think pci is not initiated when there
74 * is no device to be found on the pci_bus_type.
75 */
76 int no_pci_devices(void)
77 {
78 struct device *dev;
79 int no_devices;
80
81 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
82 no_devices = (dev == NULL);
83 put_device(dev);
84 return no_devices;
85 }
86 EXPORT_SYMBOL(no_pci_devices);
87
88 /*
89 * PCI Bus Class
90 */
91 static void release_pcibus_dev(struct device *dev)
92 {
93 struct pci_bus *pci_bus = to_pci_bus(dev);
94
95 put_device(pci_bus->bridge);
96 pci_bus_remove_resources(pci_bus);
97 pci_release_bus_of_node(pci_bus);
98 kfree(pci_bus);
99 }
100
101 static struct class pcibus_class = {
102 .name = "pci_bus",
103 .dev_release = &release_pcibus_dev,
104 .dev_groups = pcibus_groups,
105 };
106
107 static int __init pcibus_class_init(void)
108 {
109 return class_register(&pcibus_class);
110 }
111 postcore_initcall(pcibus_class_init);
112
113 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
114 {
115 u64 size = mask & maxbase; /* Find the significant bits */
116 if (!size)
117 return 0;
118
119 /* Get the lowest of them to find the decode size, and
120 from that the extent. */
121 size = (size & ~(size-1)) - 1;
122
123 /* base == maxbase can be valid only if the BAR has
124 already been programmed with all 1s. */
125 if (base == maxbase && ((base | size) & mask) != mask)
126 return 0;
127
128 return size;
129 }
130
131 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
132 {
133 u32 mem_type;
134 unsigned long flags;
135
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
139 return flags;
140 }
141
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
146
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
148 switch (mem_type) {
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
150 break;
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152 /* 1M mem BAR treated as 32-bit BAR */
153 break;
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
156 break;
157 default:
158 /* mem unknown type treated as 32-bit BAR */
159 break;
160 }
161 return flags;
162 }
163
164 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
165
166 /**
167 * pci_read_base - read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
172 *
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
174 */
175 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
177 {
178 u32 l = 0, sz = 0, mask;
179 u64 l64, sz64, mask64;
180 u16 orig_cmd;
181 struct pci_bus_region region, inverted_region;
182
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
184
185 /* No printks while decoding is disabled! */
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
191 }
192 }
193
194 res->name = pci_name(dev);
195
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
200
201 /*
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
205 * 1 must be clear.
206 */
207 if (sz == 0xffffffff)
208 sz = 0;
209
210 /*
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
213 */
214 if (l == 0xffffffff)
215 l = 0;
216
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
224 } else {
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
228 }
229 } else {
230 if (l & PCI_ROM_ADDRESS_ENABLE)
231 res->flags |= IORESOURCE_ROM_ENABLE;
232 l64 = l & PCI_ROM_ADDRESS_MASK;
233 sz64 = sz & PCI_ROM_ADDRESS_MASK;
234 mask64 = PCI_ROM_ADDRESS_MASK;
235 }
236
237 if (res->flags & IORESOURCE_MEM_64) {
238 pci_read_config_dword(dev, pos + 4, &l);
239 pci_write_config_dword(dev, pos + 4, ~0);
240 pci_read_config_dword(dev, pos + 4, &sz);
241 pci_write_config_dword(dev, pos + 4, l);
242
243 l64 |= ((u64)l << 32);
244 sz64 |= ((u64)sz << 32);
245 mask64 |= ((u64)~0 << 32);
246 }
247
248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
250
251 if (!sz64)
252 goto fail;
253
254 sz64 = pci_size(l64, sz64, mask64);
255 if (!sz64) {
256 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
257 pos);
258 goto fail;
259 }
260
261 if (res->flags & IORESOURCE_MEM_64) {
262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
263 && sz64 > 0x100000000ULL) {
264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
265 res->start = 0;
266 res->end = 0;
267 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos, (unsigned long long)sz64);
269 goto out;
270 }
271
272 if ((sizeof(pci_bus_addr_t) < 8) && l) {
273 /* Above 32-bit boundary; try to reallocate */
274 res->flags |= IORESOURCE_UNSET;
275 res->start = 0;
276 res->end = sz64;
277 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos, (unsigned long long)l64);
279 goto out;
280 }
281 }
282
283 region.start = l64;
284 region.end = l64 + sz64;
285
286 pcibios_bus_to_resource(dev->bus, res, &region);
287 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
288
289 /*
290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
291 * the corresponding resource address (the physical address used by
292 * the CPU. Converting that resource address back to a bus address
293 * should yield the original BAR value:
294 *
295 * resource_to_bus(bus_to_resource(A)) == A
296 *
297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
298 * be claimed by the device.
299 */
300 if (inverted_region.start != region.start) {
301 res->flags |= IORESOURCE_UNSET;
302 res->start = 0;
303 res->end = region.end - region.start;
304 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos, (unsigned long long)region.start);
306 }
307
308 goto out;
309
310
311 fail:
312 res->flags = 0;
313 out:
314 if (res->flags)
315 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
316
317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
318 }
319
320 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
321 {
322 unsigned int pos, reg;
323
324 if (dev->non_compliant_bars)
325 return;
326
327 for (pos = 0; pos < howmany; pos++) {
328 struct resource *res = &dev->resource[pos];
329 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
330 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
331 }
332
333 if (rom) {
334 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
335 dev->rom_base_reg = rom;
336 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
337 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
338 __pci_read_base(dev, pci_bar_mem32, res, rom);
339 }
340 }
341
342 static void pci_read_bridge_io(struct pci_bus *child)
343 {
344 struct pci_dev *dev = child->self;
345 u8 io_base_lo, io_limit_lo;
346 unsigned long io_mask, io_granularity, base, limit;
347 struct pci_bus_region region;
348 struct resource *res;
349
350 io_mask = PCI_IO_RANGE_MASK;
351 io_granularity = 0x1000;
352 if (dev->io_window_1k) {
353 /* Support 1K I/O space granularity */
354 io_mask = PCI_IO_1K_RANGE_MASK;
355 io_granularity = 0x400;
356 }
357
358 res = child->resource[0];
359 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
360 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
361 base = (io_base_lo & io_mask) << 8;
362 limit = (io_limit_lo & io_mask) << 8;
363
364 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
365 u16 io_base_hi, io_limit_hi;
366
367 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
368 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
369 base |= ((unsigned long) io_base_hi << 16);
370 limit |= ((unsigned long) io_limit_hi << 16);
371 }
372
373 if (base <= limit) {
374 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
375 region.start = base;
376 region.end = limit + io_granularity - 1;
377 pcibios_bus_to_resource(dev->bus, res, &region);
378 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
379 }
380 }
381
382 static void pci_read_bridge_mmio(struct pci_bus *child)
383 {
384 struct pci_dev *dev = child->self;
385 u16 mem_base_lo, mem_limit_lo;
386 unsigned long base, limit;
387 struct pci_bus_region region;
388 struct resource *res;
389
390 res = child->resource[1];
391 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
392 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
393 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
395 if (base <= limit) {
396 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
397 region.start = base;
398 region.end = limit + 0xfffff;
399 pcibios_bus_to_resource(dev->bus, res, &region);
400 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
401 }
402 }
403
404 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
405 {
406 struct pci_dev *dev = child->self;
407 u16 mem_base_lo, mem_limit_lo;
408 u64 base64, limit64;
409 pci_bus_addr_t base, limit;
410 struct pci_bus_region region;
411 struct resource *res;
412
413 res = child->resource[2];
414 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
415 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
416 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
417 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
418
419 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
420 u32 mem_base_hi, mem_limit_hi;
421
422 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
423 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
424
425 /*
426 * Some bridges set the base > limit by default, and some
427 * (broken) BIOSes do not initialize them. If we find
428 * this, just assume they are not being used.
429 */
430 if (mem_base_hi <= mem_limit_hi) {
431 base64 |= (u64) mem_base_hi << 32;
432 limit64 |= (u64) mem_limit_hi << 32;
433 }
434 }
435
436 base = (pci_bus_addr_t) base64;
437 limit = (pci_bus_addr_t) limit64;
438
439 if (base != base64) {
440 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
441 (unsigned long long) base64);
442 return;
443 }
444
445 if (base <= limit) {
446 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
447 IORESOURCE_MEM | IORESOURCE_PREFETCH;
448 if (res->flags & PCI_PREF_RANGE_TYPE_64)
449 res->flags |= IORESOURCE_MEM_64;
450 region.start = base;
451 region.end = limit + 0xfffff;
452 pcibios_bus_to_resource(dev->bus, res, &region);
453 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
454 }
455 }
456
457 void pci_read_bridge_bases(struct pci_bus *child)
458 {
459 struct pci_dev *dev = child->self;
460 struct resource *res;
461 int i;
462
463 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
464 return;
465
466 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
467 &child->busn_res,
468 dev->transparent ? " (subtractive decode)" : "");
469
470 pci_bus_remove_resources(child);
471 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
472 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
473
474 pci_read_bridge_io(child);
475 pci_read_bridge_mmio(child);
476 pci_read_bridge_mmio_pref(child);
477
478 if (dev->transparent) {
479 pci_bus_for_each_resource(child->parent, res, i) {
480 if (res && res->flags) {
481 pci_bus_add_resource(child, res,
482 PCI_SUBTRACTIVE_DECODE);
483 dev_printk(KERN_DEBUG, &dev->dev,
484 " bridge window %pR (subtractive decode)\n",
485 res);
486 }
487 }
488 }
489 }
490
491 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
492 {
493 struct pci_bus *b;
494
495 b = kzalloc(sizeof(*b), GFP_KERNEL);
496 if (!b)
497 return NULL;
498
499 INIT_LIST_HEAD(&b->node);
500 INIT_LIST_HEAD(&b->children);
501 INIT_LIST_HEAD(&b->devices);
502 INIT_LIST_HEAD(&b->slots);
503 INIT_LIST_HEAD(&b->resources);
504 b->max_bus_speed = PCI_SPEED_UNKNOWN;
505 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
506 #ifdef CONFIG_PCI_DOMAINS_GENERIC
507 if (parent)
508 b->domain_nr = parent->domain_nr;
509 #endif
510 return b;
511 }
512
513 static void devm_pci_release_host_bridge_dev(struct device *dev)
514 {
515 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
516
517 if (bridge->release_fn)
518 bridge->release_fn(bridge);
519
520 pci_free_resource_list(&bridge->windows);
521 }
522
523 static void pci_release_host_bridge_dev(struct device *dev)
524 {
525 devm_pci_release_host_bridge_dev(dev);
526 kfree(to_pci_host_bridge(dev));
527 }
528
529 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
530 {
531 struct pci_host_bridge *bridge;
532
533 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
534 if (!bridge)
535 return NULL;
536
537 INIT_LIST_HEAD(&bridge->windows);
538 bridge->dev.release = pci_release_host_bridge_dev;
539
540 return bridge;
541 }
542 EXPORT_SYMBOL(pci_alloc_host_bridge);
543
544 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
545 size_t priv)
546 {
547 struct pci_host_bridge *bridge;
548
549 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
550 if (!bridge)
551 return NULL;
552
553 INIT_LIST_HEAD(&bridge->windows);
554 bridge->dev.release = devm_pci_release_host_bridge_dev;
555
556 return bridge;
557 }
558 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
559
560 void pci_free_host_bridge(struct pci_host_bridge *bridge)
561 {
562 pci_free_resource_list(&bridge->windows);
563
564 kfree(bridge);
565 }
566 EXPORT_SYMBOL(pci_free_host_bridge);
567
568 static const unsigned char pcix_bus_speed[] = {
569 PCI_SPEED_UNKNOWN, /* 0 */
570 PCI_SPEED_66MHz_PCIX, /* 1 */
571 PCI_SPEED_100MHz_PCIX, /* 2 */
572 PCI_SPEED_133MHz_PCIX, /* 3 */
573 PCI_SPEED_UNKNOWN, /* 4 */
574 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
575 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
576 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
577 PCI_SPEED_UNKNOWN, /* 8 */
578 PCI_SPEED_66MHz_PCIX_266, /* 9 */
579 PCI_SPEED_100MHz_PCIX_266, /* A */
580 PCI_SPEED_133MHz_PCIX_266, /* B */
581 PCI_SPEED_UNKNOWN, /* C */
582 PCI_SPEED_66MHz_PCIX_533, /* D */
583 PCI_SPEED_100MHz_PCIX_533, /* E */
584 PCI_SPEED_133MHz_PCIX_533 /* F */
585 };
586
587 const unsigned char pcie_link_speed[] = {
588 PCI_SPEED_UNKNOWN, /* 0 */
589 PCIE_SPEED_2_5GT, /* 1 */
590 PCIE_SPEED_5_0GT, /* 2 */
591 PCIE_SPEED_8_0GT, /* 3 */
592 PCI_SPEED_UNKNOWN, /* 4 */
593 PCI_SPEED_UNKNOWN, /* 5 */
594 PCI_SPEED_UNKNOWN, /* 6 */
595 PCI_SPEED_UNKNOWN, /* 7 */
596 PCI_SPEED_UNKNOWN, /* 8 */
597 PCI_SPEED_UNKNOWN, /* 9 */
598 PCI_SPEED_UNKNOWN, /* A */
599 PCI_SPEED_UNKNOWN, /* B */
600 PCI_SPEED_UNKNOWN, /* C */
601 PCI_SPEED_UNKNOWN, /* D */
602 PCI_SPEED_UNKNOWN, /* E */
603 PCI_SPEED_UNKNOWN /* F */
604 };
605
606 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
607 {
608 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
609 }
610 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
611
612 static unsigned char agp_speeds[] = {
613 AGP_UNKNOWN,
614 AGP_1X,
615 AGP_2X,
616 AGP_4X,
617 AGP_8X
618 };
619
620 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
621 {
622 int index = 0;
623
624 if (agpstat & 4)
625 index = 3;
626 else if (agpstat & 2)
627 index = 2;
628 else if (agpstat & 1)
629 index = 1;
630 else
631 goto out;
632
633 if (agp3) {
634 index += 2;
635 if (index == 5)
636 index = 0;
637 }
638
639 out:
640 return agp_speeds[index];
641 }
642
643 static void pci_set_bus_speed(struct pci_bus *bus)
644 {
645 struct pci_dev *bridge = bus->self;
646 int pos;
647
648 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
649 if (!pos)
650 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
651 if (pos) {
652 u32 agpstat, agpcmd;
653
654 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
655 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
656
657 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
658 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
659 }
660
661 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
662 if (pos) {
663 u16 status;
664 enum pci_bus_speed max;
665
666 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
667 &status);
668
669 if (status & PCI_X_SSTATUS_533MHZ) {
670 max = PCI_SPEED_133MHz_PCIX_533;
671 } else if (status & PCI_X_SSTATUS_266MHZ) {
672 max = PCI_SPEED_133MHz_PCIX_266;
673 } else if (status & PCI_X_SSTATUS_133MHZ) {
674 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
675 max = PCI_SPEED_133MHz_PCIX_ECC;
676 else
677 max = PCI_SPEED_133MHz_PCIX;
678 } else {
679 max = PCI_SPEED_66MHz_PCIX;
680 }
681
682 bus->max_bus_speed = max;
683 bus->cur_bus_speed = pcix_bus_speed[
684 (status & PCI_X_SSTATUS_FREQ) >> 6];
685
686 return;
687 }
688
689 if (pci_is_pcie(bridge)) {
690 u32 linkcap;
691 u16 linksta;
692
693 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
694 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
695
696 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
697 pcie_update_link_speed(bus, linksta);
698 }
699 }
700
701 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
702 {
703 struct irq_domain *d;
704
705 /*
706 * Any firmware interface that can resolve the msi_domain
707 * should be called from here.
708 */
709 d = pci_host_bridge_of_msi_domain(bus);
710 if (!d)
711 d = pci_host_bridge_acpi_msi_domain(bus);
712
713 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
714 /*
715 * If no IRQ domain was found via the OF tree, try looking it up
716 * directly through the fwnode_handle.
717 */
718 if (!d) {
719 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
720
721 if (fwnode)
722 d = irq_find_matching_fwnode(fwnode,
723 DOMAIN_BUS_PCI_MSI);
724 }
725 #endif
726
727 return d;
728 }
729
730 static void pci_set_bus_msi_domain(struct pci_bus *bus)
731 {
732 struct irq_domain *d;
733 struct pci_bus *b;
734
735 /*
736 * The bus can be a root bus, a subordinate bus, or a virtual bus
737 * created by an SR-IOV device. Walk up to the first bridge device
738 * found or derive the domain from the host bridge.
739 */
740 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
741 if (b->self)
742 d = dev_get_msi_domain(&b->self->dev);
743 }
744
745 if (!d)
746 d = pci_host_bridge_msi_domain(b);
747
748 dev_set_msi_domain(&bus->dev, d);
749 }
750
751 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
752 {
753 struct device *parent = bridge->dev.parent;
754 struct resource_entry *window, *n;
755 struct pci_bus *bus, *b;
756 resource_size_t offset;
757 LIST_HEAD(resources);
758 struct resource *res;
759 char addr[64], *fmt;
760 const char *name;
761 int err;
762
763 bus = pci_alloc_bus(NULL);
764 if (!bus)
765 return -ENOMEM;
766
767 bridge->bus = bus;
768
769 /* temporarily move resources off the list */
770 list_splice_init(&bridge->windows, &resources);
771 bus->sysdata = bridge->sysdata;
772 bus->msi = bridge->msi;
773 bus->ops = bridge->ops;
774 bus->number = bus->busn_res.start = bridge->busnr;
775 #ifdef CONFIG_PCI_DOMAINS_GENERIC
776 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
777 #endif
778
779 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
780 if (b) {
781 /* If we already got to this bus through a different bridge, ignore it */
782 dev_dbg(&b->dev, "bus already known\n");
783 err = -EEXIST;
784 goto free;
785 }
786
787 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
788 bridge->busnr);
789
790 err = pcibios_root_bridge_prepare(bridge);
791 if (err)
792 goto free;
793
794 err = device_register(&bridge->dev);
795 if (err)
796 put_device(&bridge->dev);
797
798 bus->bridge = get_device(&bridge->dev);
799 device_enable_async_suspend(bus->bridge);
800 pci_set_bus_of_node(bus);
801 pci_set_bus_msi_domain(bus);
802
803 if (!parent)
804 set_dev_node(bus->bridge, pcibus_to_node(bus));
805
806 bus->dev.class = &pcibus_class;
807 bus->dev.parent = bus->bridge;
808
809 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
810 name = dev_name(&bus->dev);
811
812 err = device_register(&bus->dev);
813 if (err)
814 goto unregister;
815
816 pcibios_add_bus(bus);
817
818 /* Create legacy_io and legacy_mem files for this bus */
819 pci_create_legacy_files(bus);
820
821 if (parent)
822 dev_info(parent, "PCI host bridge to bus %s\n", name);
823 else
824 pr_info("PCI host bridge to bus %s\n", name);
825
826 /* Add initial resources to the bus */
827 resource_list_for_each_entry_safe(window, n, &resources) {
828 list_move_tail(&window->node, &bridge->windows);
829 offset = window->offset;
830 res = window->res;
831
832 if (res->flags & IORESOURCE_BUS)
833 pci_bus_insert_busn_res(bus, bus->number, res->end);
834 else
835 pci_bus_add_resource(bus, res, 0);
836
837 if (offset) {
838 if (resource_type(res) == IORESOURCE_IO)
839 fmt = " (bus address [%#06llx-%#06llx])";
840 else
841 fmt = " (bus address [%#010llx-%#010llx])";
842
843 snprintf(addr, sizeof(addr), fmt,
844 (unsigned long long)(res->start - offset),
845 (unsigned long long)(res->end - offset));
846 } else
847 addr[0] = '\0';
848
849 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
850 }
851
852 down_write(&pci_bus_sem);
853 list_add_tail(&bus->node, &pci_root_buses);
854 up_write(&pci_bus_sem);
855
856 return 0;
857
858 unregister:
859 put_device(&bridge->dev);
860 device_unregister(&bridge->dev);
861
862 free:
863 kfree(bus);
864 return err;
865 }
866
867 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
868 struct pci_dev *bridge, int busnr)
869 {
870 struct pci_bus *child;
871 int i;
872 int ret;
873
874 /*
875 * Allocate a new bus, and inherit stuff from the parent..
876 */
877 child = pci_alloc_bus(parent);
878 if (!child)
879 return NULL;
880
881 child->parent = parent;
882 child->ops = parent->ops;
883 child->msi = parent->msi;
884 child->sysdata = parent->sysdata;
885 child->bus_flags = parent->bus_flags;
886
887 /* initialize some portions of the bus device, but don't register it
888 * now as the parent is not properly set up yet.
889 */
890 child->dev.class = &pcibus_class;
891 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
892
893 /*
894 * Set up the primary, secondary and subordinate
895 * bus numbers.
896 */
897 child->number = child->busn_res.start = busnr;
898 child->primary = parent->busn_res.start;
899 child->busn_res.end = 0xff;
900
901 if (!bridge) {
902 child->dev.parent = parent->bridge;
903 goto add_dev;
904 }
905
906 child->self = bridge;
907 child->bridge = get_device(&bridge->dev);
908 child->dev.parent = child->bridge;
909 pci_set_bus_of_node(child);
910 pci_set_bus_speed(child);
911
912 /* Set up default resource pointers and names.. */
913 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
914 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
915 child->resource[i]->name = child->name;
916 }
917 bridge->subordinate = child;
918
919 add_dev:
920 pci_set_bus_msi_domain(child);
921 ret = device_register(&child->dev);
922 WARN_ON(ret < 0);
923
924 pcibios_add_bus(child);
925
926 if (child->ops->add_bus) {
927 ret = child->ops->add_bus(child);
928 if (WARN_ON(ret < 0))
929 dev_err(&child->dev, "failed to add bus: %d\n", ret);
930 }
931
932 /* Create legacy_io and legacy_mem files for this bus */
933 pci_create_legacy_files(child);
934
935 return child;
936 }
937
938 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
939 int busnr)
940 {
941 struct pci_bus *child;
942
943 child = pci_alloc_child_bus(parent, dev, busnr);
944 if (child) {
945 down_write(&pci_bus_sem);
946 list_add_tail(&child->node, &parent->children);
947 up_write(&pci_bus_sem);
948 }
949 return child;
950 }
951 EXPORT_SYMBOL(pci_add_new_bus);
952
953 static void pci_enable_crs(struct pci_dev *pdev)
954 {
955 u16 root_cap = 0;
956
957 /* Enable CRS Software Visibility if supported */
958 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
959 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
960 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
961 PCI_EXP_RTCTL_CRSSVE);
962 }
963
964 /*
965 * If it's a bridge, configure it and scan the bus behind it.
966 * For CardBus bridges, we don't scan behind as the devices will
967 * be handled by the bridge driver itself.
968 *
969 * We need to process bridges in two passes -- first we scan those
970 * already configured by the BIOS and after we are done with all of
971 * them, we proceed to assigning numbers to the remaining buses in
972 * order to avoid overlaps between old and new bus numbers.
973 */
974 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
975 {
976 struct pci_bus *child;
977 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
978 u32 buses, i, j = 0;
979 u16 bctl;
980 u8 primary, secondary, subordinate;
981 int broken = 0;
982
983 /*
984 * Make sure the bridge is powered on to be able to access config
985 * space of devices below it.
986 */
987 pm_runtime_get_sync(&dev->dev);
988
989 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
990 primary = buses & 0xFF;
991 secondary = (buses >> 8) & 0xFF;
992 subordinate = (buses >> 16) & 0xFF;
993
994 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
995 secondary, subordinate, pass);
996
997 if (!primary && (primary != bus->number) && secondary && subordinate) {
998 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
999 primary = bus->number;
1000 }
1001
1002 /* Check if setup is sensible at all */
1003 if (!pass &&
1004 (primary != bus->number || secondary <= bus->number ||
1005 secondary > subordinate)) {
1006 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1007 secondary, subordinate);
1008 broken = 1;
1009 }
1010
1011 /* Disable MasterAbortMode during probing to avoid reporting
1012 of bus errors (in some architectures) */
1013 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1014 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1015 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1016
1017 pci_enable_crs(dev);
1018
1019 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1020 !is_cardbus && !broken) {
1021 unsigned int cmax;
1022 /*
1023 * Bus already configured by firmware, process it in the first
1024 * pass and just note the configuration.
1025 */
1026 if (pass)
1027 goto out;
1028
1029 /*
1030 * The bus might already exist for two reasons: Either we are
1031 * rescanning the bus or the bus is reachable through more than
1032 * one bridge. The second case can happen with the i450NX
1033 * chipset.
1034 */
1035 child = pci_find_bus(pci_domain_nr(bus), secondary);
1036 if (!child) {
1037 child = pci_add_new_bus(bus, dev, secondary);
1038 if (!child)
1039 goto out;
1040 child->primary = primary;
1041 pci_bus_insert_busn_res(child, secondary, subordinate);
1042 child->bridge_ctl = bctl;
1043 }
1044
1045 cmax = pci_scan_child_bus(child);
1046 if (cmax > subordinate)
1047 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
1048 subordinate, cmax);
1049 /* subordinate should equal child->busn_res.end */
1050 if (subordinate > max)
1051 max = subordinate;
1052 } else {
1053 /*
1054 * We need to assign a number to this bus which we always
1055 * do in the second pass.
1056 */
1057 if (!pass) {
1058 if (pcibios_assign_all_busses() || broken || is_cardbus)
1059 /* Temporarily disable forwarding of the
1060 configuration cycles on all bridges in
1061 this bus segment to avoid possible
1062 conflicts in the second pass between two
1063 bridges programmed with overlapping
1064 bus ranges. */
1065 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1066 buses & ~0xffffff);
1067 goto out;
1068 }
1069
1070 /* Clear errors */
1071 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1072
1073 /* Prevent assigning a bus number that already exists.
1074 * This can happen when a bridge is hot-plugged, so in
1075 * this case we only re-scan this bus. */
1076 child = pci_find_bus(pci_domain_nr(bus), max+1);
1077 if (!child) {
1078 child = pci_add_new_bus(bus, dev, max+1);
1079 if (!child)
1080 goto out;
1081 pci_bus_insert_busn_res(child, max+1,
1082 bus->busn_res.end);
1083 }
1084 max++;
1085 buses = (buses & 0xff000000)
1086 | ((unsigned int)(child->primary) << 0)
1087 | ((unsigned int)(child->busn_res.start) << 8)
1088 | ((unsigned int)(child->busn_res.end) << 16);
1089
1090 /*
1091 * yenta.c forces a secondary latency timer of 176.
1092 * Copy that behaviour here.
1093 */
1094 if (is_cardbus) {
1095 buses &= ~0xff000000;
1096 buses |= CARDBUS_LATENCY_TIMER << 24;
1097 }
1098
1099 /*
1100 * We need to blast all three values with a single write.
1101 */
1102 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1103
1104 if (!is_cardbus) {
1105 child->bridge_ctl = bctl;
1106 max = pci_scan_child_bus(child);
1107 } else {
1108 /*
1109 * For CardBus bridges, we leave 4 bus numbers
1110 * as cards with a PCI-to-PCI bridge can be
1111 * inserted later.
1112 */
1113 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1114 struct pci_bus *parent = bus;
1115 if (pci_find_bus(pci_domain_nr(bus),
1116 max+i+1))
1117 break;
1118 while (parent->parent) {
1119 if ((!pcibios_assign_all_busses()) &&
1120 (parent->busn_res.end > max) &&
1121 (parent->busn_res.end <= max+i)) {
1122 j = 1;
1123 }
1124 parent = parent->parent;
1125 }
1126 if (j) {
1127 /*
1128 * Often, there are two cardbus bridges
1129 * -- try to leave one valid bus number
1130 * for each one.
1131 */
1132 i /= 2;
1133 break;
1134 }
1135 }
1136 max += i;
1137 }
1138 /*
1139 * Set the subordinate bus number to its real value.
1140 */
1141 pci_bus_update_busn_res_end(child, max);
1142 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1143 }
1144
1145 sprintf(child->name,
1146 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1147 pci_domain_nr(bus), child->number);
1148
1149 /* Has only triggered on CardBus, fixup is in yenta_socket */
1150 while (bus->parent) {
1151 if ((child->busn_res.end > bus->busn_res.end) ||
1152 (child->number > bus->busn_res.end) ||
1153 (child->number < bus->number) ||
1154 (child->busn_res.end < bus->number)) {
1155 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1156 &child->busn_res,
1157 (bus->number > child->busn_res.end &&
1158 bus->busn_res.end < child->number) ?
1159 "wholly" : "partially",
1160 bus->self->transparent ? " transparent" : "",
1161 dev_name(&bus->dev),
1162 &bus->busn_res);
1163 }
1164 bus = bus->parent;
1165 }
1166
1167 out:
1168 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1169
1170 pm_runtime_put(&dev->dev);
1171
1172 return max;
1173 }
1174 EXPORT_SYMBOL(pci_scan_bridge);
1175
1176 /*
1177 * Read interrupt line and base address registers.
1178 * The architecture-dependent code can tweak these, of course.
1179 */
1180 static void pci_read_irq(struct pci_dev *dev)
1181 {
1182 unsigned char irq;
1183
1184 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1185 dev->pin = irq;
1186 if (irq)
1187 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1188 dev->irq = irq;
1189 }
1190
1191 void set_pcie_port_type(struct pci_dev *pdev)
1192 {
1193 int pos;
1194 u16 reg16;
1195 int type;
1196 struct pci_dev *parent;
1197
1198 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1199 if (!pos)
1200 return;
1201
1202 pdev->pcie_cap = pos;
1203 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1204 pdev->pcie_flags_reg = reg16;
1205 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1206 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1207
1208 /*
1209 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1210 * of a Link. No PCIe component has two Links. Two Links are
1211 * connected by a Switch that has a Port on each Link and internal
1212 * logic to connect the two Ports.
1213 */
1214 type = pci_pcie_type(pdev);
1215 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1216 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1217 pdev->has_secondary_link = 1;
1218 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1219 type == PCI_EXP_TYPE_DOWNSTREAM) {
1220 parent = pci_upstream_bridge(pdev);
1221
1222 /*
1223 * Usually there's an upstream device (Root Port or Switch
1224 * Downstream Port), but we can't assume one exists.
1225 */
1226 if (parent && !parent->has_secondary_link)
1227 pdev->has_secondary_link = 1;
1228 }
1229 }
1230
1231 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1232 {
1233 u32 reg32;
1234
1235 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1236 if (reg32 & PCI_EXP_SLTCAP_HPC)
1237 pdev->is_hotplug_bridge = 1;
1238 }
1239
1240 static void set_pcie_thunderbolt(struct pci_dev *dev)
1241 {
1242 int vsec = 0;
1243 u32 header;
1244
1245 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1246 PCI_EXT_CAP_ID_VNDR))) {
1247 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1248
1249 /* Is the device part of a Thunderbolt controller? */
1250 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1251 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1252 dev->is_thunderbolt = 1;
1253 return;
1254 }
1255 }
1256 }
1257
1258 /**
1259 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1260 * @dev: PCI device
1261 *
1262 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1263 * when forwarding a type1 configuration request the bridge must check that
1264 * the extended register address field is zero. The bridge is not permitted
1265 * to forward the transactions and must handle it as an Unsupported Request.
1266 * Some bridges do not follow this rule and simply drop the extended register
1267 * bits, resulting in the standard config space being aliased, every 256
1268 * bytes across the entire configuration space. Test for this condition by
1269 * comparing the first dword of each potential alias to the vendor/device ID.
1270 * Known offenders:
1271 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1272 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1273 */
1274 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1275 {
1276 #ifdef CONFIG_PCI_QUIRKS
1277 int pos;
1278 u32 header, tmp;
1279
1280 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1281
1282 for (pos = PCI_CFG_SPACE_SIZE;
1283 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1284 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1285 || header != tmp)
1286 return false;
1287 }
1288
1289 return true;
1290 #else
1291 return false;
1292 #endif
1293 }
1294
1295 /**
1296 * pci_cfg_space_size - get the configuration space size of the PCI device.
1297 * @dev: PCI device
1298 *
1299 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1300 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1301 * access it. Maybe we don't have a way to generate extended config space
1302 * accesses, or the device is behind a reverse Express bridge. So we try
1303 * reading the dword at 0x100 which must either be 0 or a valid extended
1304 * capability header.
1305 */
1306 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1307 {
1308 u32 status;
1309 int pos = PCI_CFG_SPACE_SIZE;
1310
1311 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1312 return PCI_CFG_SPACE_SIZE;
1313 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1314 return PCI_CFG_SPACE_SIZE;
1315
1316 return PCI_CFG_SPACE_EXP_SIZE;
1317 }
1318
1319 int pci_cfg_space_size(struct pci_dev *dev)
1320 {
1321 int pos;
1322 u32 status;
1323 u16 class;
1324
1325 class = dev->class >> 8;
1326 if (class == PCI_CLASS_BRIDGE_HOST)
1327 return pci_cfg_space_size_ext(dev);
1328
1329 if (pci_is_pcie(dev))
1330 return pci_cfg_space_size_ext(dev);
1331
1332 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1333 if (!pos)
1334 return PCI_CFG_SPACE_SIZE;
1335
1336 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1337 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1338 return pci_cfg_space_size_ext(dev);
1339
1340 return PCI_CFG_SPACE_SIZE;
1341 }
1342
1343 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1344
1345 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1346 {
1347 /*
1348 * Disable the MSI hardware to avoid screaming interrupts
1349 * during boot. This is the power on reset default so
1350 * usually this should be a noop.
1351 */
1352 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1353 if (dev->msi_cap)
1354 pci_msi_set_enable(dev, 0);
1355
1356 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1357 if (dev->msix_cap)
1358 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1359 }
1360
1361 /**
1362 * pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability
1363 * @dev: PCI device
1364 *
1365 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1366 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1367 */
1368 static int pci_intx_mask_broken(struct pci_dev *dev)
1369 {
1370 u16 orig, toggle, new;
1371
1372 pci_read_config_word(dev, PCI_COMMAND, &orig);
1373 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1374 pci_write_config_word(dev, PCI_COMMAND, toggle);
1375 pci_read_config_word(dev, PCI_COMMAND, &new);
1376
1377 pci_write_config_word(dev, PCI_COMMAND, orig);
1378
1379 /*
1380 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1381 * r2.3, so strictly speaking, a device is not *broken* if it's not
1382 * writable. But we'll live with the misnomer for now.
1383 */
1384 if (new != toggle)
1385 return 1;
1386 return 0;
1387 }
1388
1389 /**
1390 * pci_setup_device - fill in class and map information of a device
1391 * @dev: the device structure to fill
1392 *
1393 * Initialize the device structure with information about the device's
1394 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1395 * Called at initialisation of the PCI subsystem and by CardBus services.
1396 * Returns 0 on success and negative if unknown type of device (not normal,
1397 * bridge or CardBus).
1398 */
1399 int pci_setup_device(struct pci_dev *dev)
1400 {
1401 u32 class;
1402 u16 cmd;
1403 u8 hdr_type;
1404 int pos = 0;
1405 struct pci_bus_region region;
1406 struct resource *res;
1407
1408 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1409 return -EIO;
1410
1411 dev->sysdata = dev->bus->sysdata;
1412 dev->dev.parent = dev->bus->bridge;
1413 dev->dev.bus = &pci_bus_type;
1414 dev->hdr_type = hdr_type & 0x7f;
1415 dev->multifunction = !!(hdr_type & 0x80);
1416 dev->error_state = pci_channel_io_normal;
1417 set_pcie_port_type(dev);
1418
1419 pci_dev_assign_slot(dev);
1420 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1421 set this higher, assuming the system even supports it. */
1422 dev->dma_mask = 0xffffffff;
1423
1424 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1425 dev->bus->number, PCI_SLOT(dev->devfn),
1426 PCI_FUNC(dev->devfn));
1427
1428 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1429 dev->revision = class & 0xff;
1430 dev->class = class >> 8; /* upper 3 bytes */
1431
1432 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1433 dev->vendor, dev->device, dev->hdr_type, dev->class);
1434
1435 /* need to have dev->class ready */
1436 dev->cfg_size = pci_cfg_space_size(dev);
1437
1438 /* need to have dev->cfg_size ready */
1439 set_pcie_thunderbolt(dev);
1440
1441 /* "Unknown power state" */
1442 dev->current_state = PCI_UNKNOWN;
1443
1444 /* Early fixups, before probing the BARs */
1445 pci_fixup_device(pci_fixup_early, dev);
1446 /* device class may be changed after fixup */
1447 class = dev->class >> 8;
1448
1449 if (dev->non_compliant_bars) {
1450 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1451 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1452 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1453 cmd &= ~PCI_COMMAND_IO;
1454 cmd &= ~PCI_COMMAND_MEMORY;
1455 pci_write_config_word(dev, PCI_COMMAND, cmd);
1456 }
1457 }
1458
1459 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1460
1461 switch (dev->hdr_type) { /* header type */
1462 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1463 if (class == PCI_CLASS_BRIDGE_PCI)
1464 goto bad;
1465 pci_read_irq(dev);
1466 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1467 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1468 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1469
1470 /*
1471 * Do the ugly legacy mode stuff here rather than broken chip
1472 * quirk code. Legacy mode ATA controllers have fixed
1473 * addresses. These are not always echoed in BAR0-3, and
1474 * BAR0-3 in a few cases contain junk!
1475 */
1476 if (class == PCI_CLASS_STORAGE_IDE) {
1477 u8 progif;
1478 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1479 if ((progif & 1) == 0) {
1480 region.start = 0x1F0;
1481 region.end = 0x1F7;
1482 res = &dev->resource[0];
1483 res->flags = LEGACY_IO_RESOURCE;
1484 pcibios_bus_to_resource(dev->bus, res, &region);
1485 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1486 res);
1487 region.start = 0x3F6;
1488 region.end = 0x3F6;
1489 res = &dev->resource[1];
1490 res->flags = LEGACY_IO_RESOURCE;
1491 pcibios_bus_to_resource(dev->bus, res, &region);
1492 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1493 res);
1494 }
1495 if ((progif & 4) == 0) {
1496 region.start = 0x170;
1497 region.end = 0x177;
1498 res = &dev->resource[2];
1499 res->flags = LEGACY_IO_RESOURCE;
1500 pcibios_bus_to_resource(dev->bus, res, &region);
1501 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1502 res);
1503 region.start = 0x376;
1504 region.end = 0x376;
1505 res = &dev->resource[3];
1506 res->flags = LEGACY_IO_RESOURCE;
1507 pcibios_bus_to_resource(dev->bus, res, &region);
1508 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1509 res);
1510 }
1511 }
1512 break;
1513
1514 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1515 if (class != PCI_CLASS_BRIDGE_PCI)
1516 goto bad;
1517 /* The PCI-to-PCI bridge spec requires that subtractive
1518 decoding (i.e. transparent) bridge must have programming
1519 interface code of 0x01. */
1520 pci_read_irq(dev);
1521 dev->transparent = ((dev->class & 0xff) == 1);
1522 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1523 set_pcie_hotplug_bridge(dev);
1524 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1525 if (pos) {
1526 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1527 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1528 }
1529 break;
1530
1531 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1532 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1533 goto bad;
1534 pci_read_irq(dev);
1535 pci_read_bases(dev, 1, 0);
1536 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1537 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1538 break;
1539
1540 default: /* unknown header */
1541 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1542 dev->hdr_type);
1543 return -EIO;
1544
1545 bad:
1546 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1547 dev->class, dev->hdr_type);
1548 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1549 }
1550
1551 /* We found a fine healthy device, go go go... */
1552 return 0;
1553 }
1554
1555 static void pci_configure_mps(struct pci_dev *dev)
1556 {
1557 struct pci_dev *bridge = pci_upstream_bridge(dev);
1558 int mps, p_mps, rc;
1559
1560 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1561 return;
1562
1563 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1564 if (dev->is_virtfn)
1565 return;
1566
1567 mps = pcie_get_mps(dev);
1568 p_mps = pcie_get_mps(bridge);
1569
1570 if (mps == p_mps)
1571 return;
1572
1573 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1574 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1575 mps, pci_name(bridge), p_mps);
1576 return;
1577 }
1578
1579 /*
1580 * Fancier MPS configuration is done later by
1581 * pcie_bus_configure_settings()
1582 */
1583 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1584 return;
1585
1586 rc = pcie_set_mps(dev, p_mps);
1587 if (rc) {
1588 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1589 p_mps);
1590 return;
1591 }
1592
1593 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1594 p_mps, mps, 128 << dev->pcie_mpss);
1595 }
1596
1597 static struct hpp_type0 pci_default_type0 = {
1598 .revision = 1,
1599 .cache_line_size = 8,
1600 .latency_timer = 0x40,
1601 .enable_serr = 0,
1602 .enable_perr = 0,
1603 };
1604
1605 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1606 {
1607 u16 pci_cmd, pci_bctl;
1608
1609 if (!hpp)
1610 hpp = &pci_default_type0;
1611
1612 if (hpp->revision > 1) {
1613 dev_warn(&dev->dev,
1614 "PCI settings rev %d not supported; using defaults\n",
1615 hpp->revision);
1616 hpp = &pci_default_type0;
1617 }
1618
1619 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1620 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1621 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1622 if (hpp->enable_serr)
1623 pci_cmd |= PCI_COMMAND_SERR;
1624 if (hpp->enable_perr)
1625 pci_cmd |= PCI_COMMAND_PARITY;
1626 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1627
1628 /* Program bridge control value */
1629 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1630 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1631 hpp->latency_timer);
1632 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1633 if (hpp->enable_serr)
1634 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1635 if (hpp->enable_perr)
1636 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1637 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1638 }
1639 }
1640
1641 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1642 {
1643 int pos;
1644
1645 if (!hpp)
1646 return;
1647
1648 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1649 if (!pos)
1650 return;
1651
1652 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1653 }
1654
1655 static bool pcie_root_rcb_set(struct pci_dev *dev)
1656 {
1657 struct pci_dev *rp = pcie_find_root_port(dev);
1658 u16 lnkctl;
1659
1660 if (!rp)
1661 return false;
1662
1663 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1664 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1665 return true;
1666
1667 return false;
1668 }
1669
1670 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1671 {
1672 int pos;
1673 u32 reg32;
1674
1675 if (!hpp)
1676 return;
1677
1678 if (!pci_is_pcie(dev))
1679 return;
1680
1681 if (hpp->revision > 1) {
1682 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1683 hpp->revision);
1684 return;
1685 }
1686
1687 /*
1688 * Don't allow _HPX to change MPS or MRRS settings. We manage
1689 * those to make sure they're consistent with the rest of the
1690 * platform.
1691 */
1692 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1693 PCI_EXP_DEVCTL_READRQ;
1694 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1695 PCI_EXP_DEVCTL_READRQ);
1696
1697 /* Initialize Device Control Register */
1698 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1699 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1700
1701 /* Initialize Link Control Register */
1702 if (pcie_cap_has_lnkctl(dev)) {
1703
1704 /*
1705 * If the Root Port supports Read Completion Boundary of
1706 * 128, set RCB to 128. Otherwise, clear it.
1707 */
1708 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1709 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1710 if (pcie_root_rcb_set(dev))
1711 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1712
1713 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1714 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1715 }
1716
1717 /* Find Advanced Error Reporting Enhanced Capability */
1718 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1719 if (!pos)
1720 return;
1721
1722 /* Initialize Uncorrectable Error Mask Register */
1723 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1724 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1725 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1726
1727 /* Initialize Uncorrectable Error Severity Register */
1728 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1729 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1730 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1731
1732 /* Initialize Correctable Error Mask Register */
1733 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1734 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1735 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1736
1737 /* Initialize Advanced Error Capabilities and Control Register */
1738 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1739 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1740 /* Don't enable ECRC generation or checking if unsupported */
1741 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
1742 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
1743 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
1744 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
1745 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1746
1747 /*
1748 * FIXME: The following two registers are not supported yet.
1749 *
1750 * o Secondary Uncorrectable Error Severity Register
1751 * o Secondary Uncorrectable Error Mask Register
1752 */
1753 }
1754
1755 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1756 {
1757 struct pci_host_bridge *host;
1758 u32 cap;
1759 u16 ctl;
1760 int ret;
1761
1762 if (!pci_is_pcie(dev))
1763 return 0;
1764
1765 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1766 if (ret)
1767 return 0;
1768
1769 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1770 return 0;
1771
1772 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
1773 if (ret)
1774 return 0;
1775
1776 host = pci_find_host_bridge(dev->bus);
1777 if (!host)
1778 return 0;
1779
1780 /*
1781 * If some device in the hierarchy doesn't handle Extended Tags
1782 * correctly, make sure they're disabled.
1783 */
1784 if (host->no_ext_tags) {
1785 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
1786 dev_info(&dev->dev, "disabling Extended Tags\n");
1787 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1788 PCI_EXP_DEVCTL_EXT_TAG);
1789 }
1790 return 0;
1791 }
1792
1793 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
1794 dev_info(&dev->dev, "enabling Extended Tags\n");
1795 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1796 PCI_EXP_DEVCTL_EXT_TAG);
1797 }
1798 return 0;
1799 }
1800
1801 /**
1802 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
1803 * @dev: PCI device to query
1804 *
1805 * Returns true if the device has enabled relaxed ordering attribute.
1806 */
1807 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
1808 {
1809 u16 v;
1810
1811 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
1812
1813 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
1814 }
1815 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
1816
1817 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
1818 {
1819 struct pci_dev *root;
1820
1821 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
1822 if (dev->is_virtfn)
1823 return;
1824
1825 if (!pcie_relaxed_ordering_enabled(dev))
1826 return;
1827
1828 /*
1829 * For now, we only deal with Relaxed Ordering issues with Root
1830 * Ports. Peer-to-Peer DMA is another can of worms.
1831 */
1832 root = pci_find_pcie_root_port(dev);
1833 if (!root)
1834 return;
1835
1836 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
1837 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1838 PCI_EXP_DEVCTL_RELAX_EN);
1839 dev_info(&dev->dev, "Disable Relaxed Ordering because the Root Port didn't support it\n");
1840 }
1841 }
1842
1843 static void pci_configure_device(struct pci_dev *dev)
1844 {
1845 struct hotplug_params hpp;
1846 int ret;
1847
1848 pci_configure_mps(dev);
1849 pci_configure_extended_tags(dev, NULL);
1850 pci_configure_relaxed_ordering(dev);
1851
1852 memset(&hpp, 0, sizeof(hpp));
1853 ret = pci_get_hp_params(dev, &hpp);
1854 if (ret)
1855 return;
1856
1857 program_hpp_type2(dev, hpp.t2);
1858 program_hpp_type1(dev, hpp.t1);
1859 program_hpp_type0(dev, hpp.t0);
1860 }
1861
1862 static void pci_release_capabilities(struct pci_dev *dev)
1863 {
1864 pci_vpd_release(dev);
1865 pci_iov_release(dev);
1866 pci_free_cap_save_buffers(dev);
1867 }
1868
1869 /**
1870 * pci_release_dev - free a pci device structure when all users of it are finished.
1871 * @dev: device that's been disconnected
1872 *
1873 * Will be called only by the device core when all users of this pci device are
1874 * done.
1875 */
1876 static void pci_release_dev(struct device *dev)
1877 {
1878 struct pci_dev *pci_dev;
1879
1880 pci_dev = to_pci_dev(dev);
1881 pci_release_capabilities(pci_dev);
1882 pci_release_of_node(pci_dev);
1883 pcibios_release_device(pci_dev);
1884 pci_bus_put(pci_dev->bus);
1885 kfree(pci_dev->driver_override);
1886 kfree(pci_dev->dma_alias_mask);
1887 kfree(pci_dev);
1888 }
1889
1890 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1891 {
1892 struct pci_dev *dev;
1893
1894 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1895 if (!dev)
1896 return NULL;
1897
1898 INIT_LIST_HEAD(&dev->bus_list);
1899 dev->dev.type = &pci_dev_type;
1900 dev->bus = pci_bus_get(bus);
1901
1902 return dev;
1903 }
1904 EXPORT_SYMBOL(pci_alloc_dev);
1905
1906 static bool pci_bus_crs_vendor_id(u32 l)
1907 {
1908 return (l & 0xffff) == 0x0001;
1909 }
1910
1911 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
1912 int timeout)
1913 {
1914 int delay = 1;
1915
1916 if (!pci_bus_crs_vendor_id(*l))
1917 return true; /* not a CRS completion */
1918
1919 if (!timeout)
1920 return false; /* CRS, but caller doesn't want to wait */
1921
1922 /*
1923 * We got the reserved Vendor ID that indicates a completion with
1924 * Configuration Request Retry Status (CRS). Retry until we get a
1925 * valid Vendor ID or we time out.
1926 */
1927 while (pci_bus_crs_vendor_id(*l)) {
1928 if (delay > timeout) {
1929 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
1930 pci_domain_nr(bus), bus->number,
1931 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
1932
1933 return false;
1934 }
1935 if (delay >= 1000)
1936 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
1937 pci_domain_nr(bus), bus->number,
1938 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
1939
1940 msleep(delay);
1941 delay *= 2;
1942
1943 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1944 return false;
1945 }
1946
1947 if (delay >= 1000)
1948 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
1949 pci_domain_nr(bus), bus->number,
1950 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
1951
1952 return true;
1953 }
1954
1955 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1956 int timeout)
1957 {
1958 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1959 return false;
1960
1961 /* some broken boards return 0 or ~0 if a slot is empty: */
1962 if (*l == 0xffffffff || *l == 0x00000000 ||
1963 *l == 0x0000ffff || *l == 0xffff0000)
1964 return false;
1965
1966 if (pci_bus_crs_vendor_id(*l))
1967 return pci_bus_wait_crs(bus, devfn, l, timeout);
1968
1969 return true;
1970 }
1971 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1972
1973 /*
1974 * Read the config data for a PCI device, sanity-check it
1975 * and fill in the dev structure...
1976 */
1977 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1978 {
1979 struct pci_dev *dev;
1980 u32 l;
1981
1982 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1983 return NULL;
1984
1985 dev = pci_alloc_dev(bus);
1986 if (!dev)
1987 return NULL;
1988
1989 dev->devfn = devfn;
1990 dev->vendor = l & 0xffff;
1991 dev->device = (l >> 16) & 0xffff;
1992
1993 pci_set_of_node(dev);
1994
1995 if (pci_setup_device(dev)) {
1996 pci_bus_put(dev->bus);
1997 kfree(dev);
1998 return NULL;
1999 }
2000
2001 return dev;
2002 }
2003
2004 static void pci_init_capabilities(struct pci_dev *dev)
2005 {
2006 /* Enhanced Allocation */
2007 pci_ea_init(dev);
2008
2009 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2010 pci_msi_setup_pci_dev(dev);
2011
2012 /* Buffers for saving PCIe and PCI-X capabilities */
2013 pci_allocate_cap_save_buffers(dev);
2014
2015 /* Power Management */
2016 pci_pm_init(dev);
2017
2018 /* Vital Product Data */
2019 pci_vpd_init(dev);
2020
2021 /* Alternative Routing-ID Forwarding */
2022 pci_configure_ari(dev);
2023
2024 /* Single Root I/O Virtualization */
2025 pci_iov_init(dev);
2026
2027 /* Address Translation Services */
2028 pci_ats_init(dev);
2029
2030 /* Enable ACS P2P upstream forwarding */
2031 pci_enable_acs(dev);
2032
2033 /* Precision Time Measurement */
2034 pci_ptm_init(dev);
2035
2036 /* Advanced Error Reporting */
2037 pci_aer_init(dev);
2038 }
2039
2040 /*
2041 * This is the equivalent of pci_host_bridge_msi_domain that acts on
2042 * devices. Firmware interfaces that can select the MSI domain on a
2043 * per-device basis should be called from here.
2044 */
2045 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2046 {
2047 struct irq_domain *d;
2048
2049 /*
2050 * If a domain has been set through the pcibios_add_device
2051 * callback, then this is the one (platform code knows best).
2052 */
2053 d = dev_get_msi_domain(&dev->dev);
2054 if (d)
2055 return d;
2056
2057 /*
2058 * Let's see if we have a firmware interface able to provide
2059 * the domain.
2060 */
2061 d = pci_msi_get_device_domain(dev);
2062 if (d)
2063 return d;
2064
2065 return NULL;
2066 }
2067
2068 static void pci_set_msi_domain(struct pci_dev *dev)
2069 {
2070 struct irq_domain *d;
2071
2072 /*
2073 * If the platform or firmware interfaces cannot supply a
2074 * device-specific MSI domain, then inherit the default domain
2075 * from the host bridge itself.
2076 */
2077 d = pci_dev_msi_domain(dev);
2078 if (!d)
2079 d = dev_get_msi_domain(&dev->bus->dev);
2080
2081 dev_set_msi_domain(&dev->dev, d);
2082 }
2083
2084 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2085 {
2086 int ret;
2087
2088 pci_configure_device(dev);
2089
2090 device_initialize(&dev->dev);
2091 dev->dev.release = pci_release_dev;
2092
2093 set_dev_node(&dev->dev, pcibus_to_node(bus));
2094 dev->dev.dma_mask = &dev->dma_mask;
2095 dev->dev.dma_parms = &dev->dma_parms;
2096 dev->dev.coherent_dma_mask = 0xffffffffull;
2097
2098 pci_set_dma_max_seg_size(dev, 65536);
2099 pci_set_dma_seg_boundary(dev, 0xffffffff);
2100
2101 /* Fix up broken headers */
2102 pci_fixup_device(pci_fixup_header, dev);
2103
2104 /* moved out from quirk header fixup code */
2105 pci_reassigndev_resource_alignment(dev);
2106
2107 /* Clear the state_saved flag. */
2108 dev->state_saved = false;
2109
2110 /* Initialize various capabilities */
2111 pci_init_capabilities(dev);
2112
2113 /*
2114 * Add the device to our list of discovered devices
2115 * and the bus list for fixup functions, etc.
2116 */
2117 down_write(&pci_bus_sem);
2118 list_add_tail(&dev->bus_list, &bus->devices);
2119 up_write(&pci_bus_sem);
2120
2121 ret = pcibios_add_device(dev);
2122 WARN_ON(ret < 0);
2123
2124 /* Setup MSI irq domain */
2125 pci_set_msi_domain(dev);
2126
2127 /* Notifier could use PCI capabilities */
2128 dev->match_driver = false;
2129 ret = device_add(&dev->dev);
2130 WARN_ON(ret < 0);
2131 }
2132
2133 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2134 {
2135 struct pci_dev *dev;
2136
2137 dev = pci_get_slot(bus, devfn);
2138 if (dev) {
2139 pci_dev_put(dev);
2140 return dev;
2141 }
2142
2143 dev = pci_scan_device(bus, devfn);
2144 if (!dev)
2145 return NULL;
2146
2147 pci_device_add(dev, bus);
2148
2149 return dev;
2150 }
2151 EXPORT_SYMBOL(pci_scan_single_device);
2152
2153 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2154 {
2155 int pos;
2156 u16 cap = 0;
2157 unsigned next_fn;
2158
2159 if (pci_ari_enabled(bus)) {
2160 if (!dev)
2161 return 0;
2162 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2163 if (!pos)
2164 return 0;
2165
2166 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2167 next_fn = PCI_ARI_CAP_NFN(cap);
2168 if (next_fn <= fn)
2169 return 0; /* protect against malformed list */
2170
2171 return next_fn;
2172 }
2173
2174 /* dev may be NULL for non-contiguous multifunction devices */
2175 if (!dev || dev->multifunction)
2176 return (fn + 1) % 8;
2177
2178 return 0;
2179 }
2180
2181 static int only_one_child(struct pci_bus *bus)
2182 {
2183 struct pci_dev *parent = bus->self;
2184
2185 if (!parent || !pci_is_pcie(parent))
2186 return 0;
2187 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
2188 return 1;
2189
2190 /*
2191 * PCIe downstream ports are bridges that normally lead to only a
2192 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
2193 * possible devices, not just device 0. See PCIe spec r3.0,
2194 * sec 7.3.1.
2195 */
2196 if (parent->has_secondary_link &&
2197 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2198 return 1;
2199 return 0;
2200 }
2201
2202 /**
2203 * pci_scan_slot - scan a PCI slot on a bus for devices.
2204 * @bus: PCI bus to scan
2205 * @devfn: slot number to scan (must have zero function.)
2206 *
2207 * Scan a PCI slot on the specified PCI bus for devices, adding
2208 * discovered devices to the @bus->devices list. New devices
2209 * will not have is_added set.
2210 *
2211 * Returns the number of new devices found.
2212 */
2213 int pci_scan_slot(struct pci_bus *bus, int devfn)
2214 {
2215 unsigned fn, nr = 0;
2216 struct pci_dev *dev;
2217
2218 if (only_one_child(bus) && (devfn > 0))
2219 return 0; /* Already scanned the entire slot */
2220
2221 dev = pci_scan_single_device(bus, devfn);
2222 if (!dev)
2223 return 0;
2224 if (!dev->is_added)
2225 nr++;
2226
2227 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2228 dev = pci_scan_single_device(bus, devfn + fn);
2229 if (dev) {
2230 if (!dev->is_added)
2231 nr++;
2232 dev->multifunction = 1;
2233 }
2234 }
2235
2236 /* only one slot has pcie device */
2237 if (bus->self && nr)
2238 pcie_aspm_init_link_state(bus->self);
2239
2240 return nr;
2241 }
2242 EXPORT_SYMBOL(pci_scan_slot);
2243
2244 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2245 {
2246 u8 *smpss = data;
2247
2248 if (!pci_is_pcie(dev))
2249 return 0;
2250
2251 /*
2252 * We don't have a way to change MPS settings on devices that have
2253 * drivers attached. A hot-added device might support only the minimum
2254 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2255 * where devices may be hot-added, we limit the fabric MPS to 128 so
2256 * hot-added devices will work correctly.
2257 *
2258 * However, if we hot-add a device to a slot directly below a Root
2259 * Port, it's impossible for there to be other existing devices below
2260 * the port. We don't limit the MPS in this case because we can
2261 * reconfigure MPS on both the Root Port and the hot-added device,
2262 * and there are no other devices involved.
2263 *
2264 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2265 */
2266 if (dev->is_hotplug_bridge &&
2267 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2268 *smpss = 0;
2269
2270 if (*smpss > dev->pcie_mpss)
2271 *smpss = dev->pcie_mpss;
2272
2273 return 0;
2274 }
2275
2276 static void pcie_write_mps(struct pci_dev *dev, int mps)
2277 {
2278 int rc;
2279
2280 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2281 mps = 128 << dev->pcie_mpss;
2282
2283 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2284 dev->bus->self)
2285 /* For "Performance", the assumption is made that
2286 * downstream communication will never be larger than
2287 * the MRRS. So, the MPS only needs to be configured
2288 * for the upstream communication. This being the case,
2289 * walk from the top down and set the MPS of the child
2290 * to that of the parent bus.
2291 *
2292 * Configure the device MPS with the smaller of the
2293 * device MPSS or the bridge MPS (which is assumed to be
2294 * properly configured at this point to the largest
2295 * allowable MPS based on its parent bus).
2296 */
2297 mps = min(mps, pcie_get_mps(dev->bus->self));
2298 }
2299
2300 rc = pcie_set_mps(dev, mps);
2301 if (rc)
2302 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
2303 }
2304
2305 static void pcie_write_mrrs(struct pci_dev *dev)
2306 {
2307 int rc, mrrs;
2308
2309 /* In the "safe" case, do not configure the MRRS. There appear to be
2310 * issues with setting MRRS to 0 on a number of devices.
2311 */
2312 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2313 return;
2314
2315 /* For Max performance, the MRRS must be set to the largest supported
2316 * value. However, it cannot be configured larger than the MPS the
2317 * device or the bus can support. This should already be properly
2318 * configured by a prior call to pcie_write_mps.
2319 */
2320 mrrs = pcie_get_mps(dev);
2321
2322 /* MRRS is a R/W register. Invalid values can be written, but a
2323 * subsequent read will verify if the value is acceptable or not.
2324 * If the MRRS value provided is not acceptable (e.g., too large),
2325 * shrink the value until it is acceptable to the HW.
2326 */
2327 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2328 rc = pcie_set_readrq(dev, mrrs);
2329 if (!rc)
2330 break;
2331
2332 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
2333 mrrs /= 2;
2334 }
2335
2336 if (mrrs < 128)
2337 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2338 }
2339
2340 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2341 {
2342 int mps, orig_mps;
2343
2344 if (!pci_is_pcie(dev))
2345 return 0;
2346
2347 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2348 pcie_bus_config == PCIE_BUS_DEFAULT)
2349 return 0;
2350
2351 mps = 128 << *(u8 *)data;
2352 orig_mps = pcie_get_mps(dev);
2353
2354 pcie_write_mps(dev, mps);
2355 pcie_write_mrrs(dev);
2356
2357 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2358 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2359 orig_mps, pcie_get_readrq(dev));
2360
2361 return 0;
2362 }
2363
2364 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2365 * parents then children fashion. If this changes, then this code will not
2366 * work as designed.
2367 */
2368 void pcie_bus_configure_settings(struct pci_bus *bus)
2369 {
2370 u8 smpss = 0;
2371
2372 if (!bus->self)
2373 return;
2374
2375 if (!pci_is_pcie(bus->self))
2376 return;
2377
2378 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2379 * to be aware of the MPS of the destination. To work around this,
2380 * simply force the MPS of the entire system to the smallest possible.
2381 */
2382 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2383 smpss = 0;
2384
2385 if (pcie_bus_config == PCIE_BUS_SAFE) {
2386 smpss = bus->self->pcie_mpss;
2387
2388 pcie_find_smpss(bus->self, &smpss);
2389 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2390 }
2391
2392 pcie_bus_configure_set(bus->self, &smpss);
2393 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2394 }
2395 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2396
2397 /*
2398 * Called after each bus is probed, but before its children are examined. This
2399 * is marked as __weak because multiple architectures define it.
2400 */
2401 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2402 {
2403 /* nothing to do, expected to be removed in the future */
2404 }
2405
2406 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2407 {
2408 unsigned int devfn, pass, max = bus->busn_res.start;
2409 struct pci_dev *dev;
2410
2411 dev_dbg(&bus->dev, "scanning bus\n");
2412
2413 /* Go find them, Rover! */
2414 for (devfn = 0; devfn < 0x100; devfn += 8)
2415 pci_scan_slot(bus, devfn);
2416
2417 /* Reserve buses for SR-IOV capability. */
2418 max += pci_iov_bus_range(bus);
2419
2420 /*
2421 * After performing arch-dependent fixup of the bus, look behind
2422 * all PCI-to-PCI bridges on this bus.
2423 */
2424 if (!bus->is_added) {
2425 dev_dbg(&bus->dev, "fixups for bus\n");
2426 pcibios_fixup_bus(bus);
2427 bus->is_added = 1;
2428 }
2429
2430 for (pass = 0; pass < 2; pass++)
2431 list_for_each_entry(dev, &bus->devices, bus_list) {
2432 if (pci_is_bridge(dev))
2433 max = pci_scan_bridge(bus, dev, max, pass);
2434 }
2435
2436 /*
2437 * Make sure a hotplug bridge has at least the minimum requested
2438 * number of buses.
2439 */
2440 if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
2441 if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
2442 max = bus->busn_res.start + pci_hotplug_bus_size - 1;
2443
2444 /* Do not allocate more buses than we have room left */
2445 if (max > bus->busn_res.end)
2446 max = bus->busn_res.end;
2447 }
2448
2449 /*
2450 * We've scanned the bus and so we know all about what's on
2451 * the other side of any bridges that may be on this bus plus
2452 * any devices.
2453 *
2454 * Return how far we've got finding sub-buses.
2455 */
2456 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2457 return max;
2458 }
2459 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2460
2461 /**
2462 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2463 * @bridge: Host bridge to set up.
2464 *
2465 * Default empty implementation. Replace with an architecture-specific setup
2466 * routine, if necessary.
2467 */
2468 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2469 {
2470 return 0;
2471 }
2472
2473 void __weak pcibios_add_bus(struct pci_bus *bus)
2474 {
2475 }
2476
2477 void __weak pcibios_remove_bus(struct pci_bus *bus)
2478 {
2479 }
2480
2481 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2482 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2483 {
2484 int error;
2485 struct pci_host_bridge *bridge;
2486
2487 bridge = pci_alloc_host_bridge(0);
2488 if (!bridge)
2489 return NULL;
2490
2491 bridge->dev.parent = parent;
2492
2493 list_splice_init(resources, &bridge->windows);
2494 bridge->sysdata = sysdata;
2495 bridge->busnr = bus;
2496 bridge->ops = ops;
2497
2498 error = pci_register_host_bridge(bridge);
2499 if (error < 0)
2500 goto err_out;
2501
2502 return bridge->bus;
2503
2504 err_out:
2505 kfree(bridge);
2506 return NULL;
2507 }
2508 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2509
2510 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2511 {
2512 struct resource *res = &b->busn_res;
2513 struct resource *parent_res, *conflict;
2514
2515 res->start = bus;
2516 res->end = bus_max;
2517 res->flags = IORESOURCE_BUS;
2518
2519 if (!pci_is_root_bus(b))
2520 parent_res = &b->parent->busn_res;
2521 else {
2522 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2523 res->flags |= IORESOURCE_PCI_FIXED;
2524 }
2525
2526 conflict = request_resource_conflict(parent_res, res);
2527
2528 if (conflict)
2529 dev_printk(KERN_DEBUG, &b->dev,
2530 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2531 res, pci_is_root_bus(b) ? "domain " : "",
2532 parent_res, conflict->name, conflict);
2533
2534 return conflict == NULL;
2535 }
2536
2537 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2538 {
2539 struct resource *res = &b->busn_res;
2540 struct resource old_res = *res;
2541 resource_size_t size;
2542 int ret;
2543
2544 if (res->start > bus_max)
2545 return -EINVAL;
2546
2547 size = bus_max - res->start + 1;
2548 ret = adjust_resource(res, res->start, size);
2549 dev_printk(KERN_DEBUG, &b->dev,
2550 "busn_res: %pR end %s updated to %02x\n",
2551 &old_res, ret ? "can not be" : "is", bus_max);
2552
2553 if (!ret && !res->parent)
2554 pci_bus_insert_busn_res(b, res->start, res->end);
2555
2556 return ret;
2557 }
2558
2559 void pci_bus_release_busn_res(struct pci_bus *b)
2560 {
2561 struct resource *res = &b->busn_res;
2562 int ret;
2563
2564 if (!res->flags || !res->parent)
2565 return;
2566
2567 ret = release_resource(res);
2568 dev_printk(KERN_DEBUG, &b->dev,
2569 "busn_res: %pR %s released\n",
2570 res, ret ? "can not be" : "is");
2571 }
2572
2573 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
2574 {
2575 struct resource_entry *window;
2576 bool found = false;
2577 struct pci_bus *b;
2578 int max, bus, ret;
2579
2580 if (!bridge)
2581 return -EINVAL;
2582
2583 resource_list_for_each_entry(window, &bridge->windows)
2584 if (window->res->flags & IORESOURCE_BUS) {
2585 found = true;
2586 break;
2587 }
2588
2589 ret = pci_register_host_bridge(bridge);
2590 if (ret < 0)
2591 return ret;
2592
2593 b = bridge->bus;
2594 bus = bridge->busnr;
2595
2596 if (!found) {
2597 dev_info(&b->dev,
2598 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2599 bus);
2600 pci_bus_insert_busn_res(b, bus, 255);
2601 }
2602
2603 max = pci_scan_child_bus(b);
2604
2605 if (!found)
2606 pci_bus_update_busn_res_end(b, max);
2607
2608 return 0;
2609 }
2610 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
2611
2612 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2613 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2614 {
2615 struct resource_entry *window;
2616 bool found = false;
2617 struct pci_bus *b;
2618 int max;
2619
2620 resource_list_for_each_entry(window, resources)
2621 if (window->res->flags & IORESOURCE_BUS) {
2622 found = true;
2623 break;
2624 }
2625
2626 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2627 if (!b)
2628 return NULL;
2629
2630 if (!found) {
2631 dev_info(&b->dev,
2632 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2633 bus);
2634 pci_bus_insert_busn_res(b, bus, 255);
2635 }
2636
2637 max = pci_scan_child_bus(b);
2638
2639 if (!found)
2640 pci_bus_update_busn_res_end(b, max);
2641
2642 return b;
2643 }
2644 EXPORT_SYMBOL(pci_scan_root_bus);
2645
2646 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2647 void *sysdata)
2648 {
2649 LIST_HEAD(resources);
2650 struct pci_bus *b;
2651
2652 pci_add_resource(&resources, &ioport_resource);
2653 pci_add_resource(&resources, &iomem_resource);
2654 pci_add_resource(&resources, &busn_resource);
2655 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2656 if (b) {
2657 pci_scan_child_bus(b);
2658 } else {
2659 pci_free_resource_list(&resources);
2660 }
2661 return b;
2662 }
2663 EXPORT_SYMBOL(pci_scan_bus);
2664
2665 /**
2666 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2667 * @bridge: PCI bridge for the bus to scan
2668 *
2669 * Scan a PCI bus and child buses for new devices, add them,
2670 * and enable them, resizing bridge mmio/io resource if necessary
2671 * and possible. The caller must ensure the child devices are already
2672 * removed for resizing to occur.
2673 *
2674 * Returns the max number of subordinate bus discovered.
2675 */
2676 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2677 {
2678 unsigned int max;
2679 struct pci_bus *bus = bridge->subordinate;
2680
2681 max = pci_scan_child_bus(bus);
2682
2683 pci_assign_unassigned_bridge_resources(bridge);
2684
2685 pci_bus_add_devices(bus);
2686
2687 return max;
2688 }
2689
2690 /**
2691 * pci_rescan_bus - scan a PCI bus for devices.
2692 * @bus: PCI bus to scan
2693 *
2694 * Scan a PCI bus and child buses for new devices, adds them,
2695 * and enables them.
2696 *
2697 * Returns the max number of subordinate bus discovered.
2698 */
2699 unsigned int pci_rescan_bus(struct pci_bus *bus)
2700 {
2701 unsigned int max;
2702
2703 max = pci_scan_child_bus(bus);
2704 pci_assign_unassigned_bus_resources(bus);
2705 pci_bus_add_devices(bus);
2706
2707 return max;
2708 }
2709 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2710
2711 /*
2712 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2713 * routines should always be executed under this mutex.
2714 */
2715 static DEFINE_MUTEX(pci_rescan_remove_lock);
2716
2717 void pci_lock_rescan_remove(void)
2718 {
2719 mutex_lock(&pci_rescan_remove_lock);
2720 }
2721 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2722
2723 void pci_unlock_rescan_remove(void)
2724 {
2725 mutex_unlock(&pci_rescan_remove_lock);
2726 }
2727 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2728
2729 static int __init pci_sort_bf_cmp(const struct device *d_a,
2730 const struct device *d_b)
2731 {
2732 const struct pci_dev *a = to_pci_dev(d_a);
2733 const struct pci_dev *b = to_pci_dev(d_b);
2734
2735 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2736 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2737
2738 if (a->bus->number < b->bus->number) return -1;
2739 else if (a->bus->number > b->bus->number) return 1;
2740
2741 if (a->devfn < b->devfn) return -1;
2742 else if (a->devfn > b->devfn) return 1;
2743
2744 return 0;
2745 }
2746
2747 void __init pci_sort_breadthfirst(void)
2748 {
2749 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2750 }
Linux with added FPC-III support