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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / drivers / pinctrl / mvebu / pinctrl-armada-37xx.c
blobc5fe7d4a9065919112768eb651b5cf15d2283681
1 /*
2 * Marvell 37xx SoC pinctrl driver
3 *
4 * Copyright (C) 2017 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26
27 #include "../pinctrl-utils.h"
28
29 #define OUTPUT_EN 0x0
30 #define INPUT_VAL 0x10
31 #define OUTPUT_VAL 0x18
32 #define OUTPUT_CTL 0x20
33 #define SELECTION 0x30
34
35 #define IRQ_EN 0x0
36 #define IRQ_POL 0x08
37 #define IRQ_STATUS 0x10
38 #define IRQ_WKUP 0x18
39
40 #define NB_FUNCS 3
41 #define GPIO_PER_REG 32
42
43 /**
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
46 * pins.
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
49 * the group
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
57 */
58 struct armada_37xx_pin_group {
59 const char *name;
60 unsigned int start_pin;
61 unsigned int npins;
62 u32 reg_mask;
63 u32 val[NB_FUNCS];
64 unsigned int extra_pin;
65 unsigned int extra_npins;
66 const char *funcs[NB_FUNCS];
67 unsigned int *pins;
68 };
69
70 struct armada_37xx_pin_data {
71 u8 nr_pins;
72 char *name;
73 struct armada_37xx_pin_group *groups;
74 int ngroups;
75 };
76
77 struct armada_37xx_pmx_func {
78 const char *name;
79 const char **groups;
80 unsigned int ngroups;
81 };
82
83 struct armada_37xx_pinctrl {
84 struct regmap *regmap;
85 void __iomem *base;
86 const struct armada_37xx_pin_data *data;
87 struct device *dev;
88 struct gpio_chip gpio_chip;
89 struct irq_chip irq_chip;
90 spinlock_t irq_lock;
91 struct pinctrl_desc pctl;
92 struct pinctrl_dev *pctl_dev;
93 struct armada_37xx_pin_group *groups;
94 unsigned int ngroups;
95 struct armada_37xx_pmx_func *funcs;
96 unsigned int nfuncs;
97 };
98
99 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
100 { \
101 .name = _name, \
102 .start_pin = _start, \
103 .npins = _nr, \
104 .reg_mask = _mask, \
105 .val = {0, _mask}, \
106 .funcs = {_func1, _func2} \
107 }
108
109 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
110 { \
111 .name = _name, \
112 .start_pin = _start, \
113 .npins = _nr, \
114 .reg_mask = _mask, \
115 .val = {0, _mask}, \
116 .funcs = {_func1, "gpio"} \
117 }
118
119 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
120 { \
121 .name = _name, \
122 .start_pin = _start, \
123 .npins = _nr, \
124 .reg_mask = _mask, \
125 .val = {_val1, _val2}, \
126 .funcs = {_func1, "gpio"} \
127 }
128
129 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
130 { \
131 .name = _name, \
132 .start_pin = _start, \
133 .npins = _nr, \
134 .reg_mask = _mask, \
135 .val = {_v1, _v2, _v3}, \
136 .funcs = {_f1, _f2, "gpio"} \
137 }
138
139 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
140 _f1, _f2) \
141 { \
142 .name = _name, \
143 .start_pin = _start, \
144 .npins = _nr, \
145 .reg_mask = _mask, \
146 .val = {_v1, _v2}, \
147 .extra_pin = _start2, \
148 .extra_npins = _nr2, \
149 .funcs = {_f1, _f2} \
150 }
151
152 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
153 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
154 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
155 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
156 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
157 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
158 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
159 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
160 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
161 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
162 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
163 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
164 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
165 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
166 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
167 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
168 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
169 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
170 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
171 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
172 18, 2, "gpio", "uart"),
173 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
174 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
175 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
176 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
177
178 };
179
180 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
181 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
182 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
183 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
184 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
185 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
186 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
187 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
188 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
189 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
190 "mii", "mii_err"),
191 };
192
193 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
194 .nr_pins = 36,
195 .name = "GPIO1",
196 .groups = armada_37xx_nb_groups,
197 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
198 };
199
200 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
201 .nr_pins = 30,
202 .name = "GPIO2",
203 .groups = armada_37xx_sb_groups,
204 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
205 };
206
207 static inline void armada_37xx_update_reg(unsigned int *reg,
208 unsigned int offset)
209 {
210 /* We never have more than 2 registers */
211 if (offset >= GPIO_PER_REG) {
212 offset -= GPIO_PER_REG;
213 *reg += sizeof(u32);
214 }
215 }
216
217 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
218 const char *func)
219 {
220 int f;
221
222 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
223 if (!strcmp(grp->funcs[f], func))
224 return f;
225
226 return -ENOTSUPP;
227 }
228
229 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
230 struct armada_37xx_pinctrl *info, int pin, int *grp)
231 {
232 while (*grp < info->ngroups) {
233 struct armada_37xx_pin_group *group = &info->groups[*grp];
234 int j;
235
236 *grp = *grp + 1;
237 for (j = 0; j < (group->npins + group->extra_npins); j++)
238 if (group->pins[j] == pin)
239 return group;
240 }
241 return NULL;
242 }
243
244 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
245 unsigned int selector, unsigned long *config)
246 {
247 return -ENOTSUPP;
248 }
249
250 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
251 unsigned int selector, unsigned long *configs,
252 unsigned int num_configs)
253 {
254 return -ENOTSUPP;
255 }
256
257 static const struct pinconf_ops armada_37xx_pinconf_ops = {
258 .is_generic = true,
259 .pin_config_group_get = armada_37xx_pin_config_group_get,
260 .pin_config_group_set = armada_37xx_pin_config_group_set,
261 };
262
263 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
264 {
265 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
266
267 return info->ngroups;
268 }
269
270 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
271 unsigned int group)
272 {
273 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
274
275 return info->groups[group].name;
276 }
277
278 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
279 unsigned int selector,
280 const unsigned int **pins,
281 unsigned int *npins)
282 {
283 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
284
285 if (selector >= info->ngroups)
286 return -EINVAL;
287
288 *pins = info->groups[selector].pins;
289 *npins = info->groups[selector].npins +
290 info->groups[selector].extra_npins;
291
292 return 0;
293 }
294
295 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
296 .get_groups_count = armada_37xx_get_groups_count,
297 .get_group_name = armada_37xx_get_group_name,
298 .get_group_pins = armada_37xx_get_group_pins,
299 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
300 .dt_free_map = pinctrl_utils_free_map,
301 };
302
303 /*
304 * Pinmux_ops handling
305 */
306
307 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
308 {
309 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
310
311 return info->nfuncs;
312 }
313
314 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
315 unsigned int selector)
316 {
317 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
318
319 return info->funcs[selector].name;
320 }
321
322 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
323 unsigned int selector,
324 const char * const **groups,
325 unsigned int * const num_groups)
326 {
327 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
328
329 *groups = info->funcs[selector].groups;
330 *num_groups = info->funcs[selector].ngroups;
331
332 return 0;
333 }
334
335 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
336 const char *name,
337 struct armada_37xx_pin_group *grp)
338 {
339 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
340 unsigned int reg = SELECTION;
341 unsigned int mask = grp->reg_mask;
342 int func, val;
343
344 dev_dbg(info->dev, "enable function %s group %s\n",
345 name, grp->name);
346
347 func = armada_37xx_get_func_reg(grp, name);
348
349 if (func < 0)
350 return func;
351
352 val = grp->val[func];
353
354 regmap_update_bits(info->regmap, reg, mask, val);
355
356 return 0;
357 }
358
359 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
360 unsigned int selector,
361 unsigned int group)
362 {
363
364 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
365 struct armada_37xx_pin_group *grp = &info->groups[group];
366 const char *name = info->funcs[selector].name;
367
368 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
369 }
370
371 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
372 struct irq_data *d)
373 {
374 int offset = irqd_to_hwirq(d);
375
376 armada_37xx_update_reg(reg, offset);
377 }
378
379 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
380 unsigned int offset)
381 {
382 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
383 unsigned int reg = OUTPUT_EN;
384 unsigned int mask;
385
386 armada_37xx_update_reg(&reg, offset);
387 mask = BIT(offset);
388
389 return regmap_update_bits(info->regmap, reg, mask, 0);
390 }
391
392 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
393 unsigned int offset)
394 {
395 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
396 unsigned int reg = OUTPUT_EN;
397 unsigned int val, mask;
398
399 armada_37xx_update_reg(&reg, offset);
400 mask = BIT(offset);
401 regmap_read(info->regmap, reg, &val);
402
403 return !(val & mask);
404 }
405
406 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
407 unsigned int offset, int value)
408 {
409 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
410 unsigned int reg = OUTPUT_EN;
411 unsigned int mask, val, ret;
412
413 armada_37xx_update_reg(&reg, offset);
414 mask = BIT(offset);
415
416 ret = regmap_update_bits(info->regmap, reg, mask, mask);
417
418 if (ret)
419 return ret;
420
421 reg = OUTPUT_VAL;
422 val = value ? mask : 0;
423 regmap_update_bits(info->regmap, reg, mask, val);
424
425 return 0;
426 }
427
428 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
429 {
430 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
431 unsigned int reg = INPUT_VAL;
432 unsigned int val, mask;
433
434 armada_37xx_update_reg(&reg, offset);
435 mask = BIT(offset);
436
437 regmap_read(info->regmap, reg, &val);
438
439 return (val & mask) != 0;
440 }
441
442 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
443 int value)
444 {
445 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
446 unsigned int reg = OUTPUT_VAL;
447 unsigned int mask, val;
448
449 armada_37xx_update_reg(&reg, offset);
450 mask = BIT(offset);
451 val = value ? mask : 0;
452
453 regmap_update_bits(info->regmap, reg, mask, val);
454 }
455
456 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
457 struct pinctrl_gpio_range *range,
458 unsigned int offset, bool input)
459 {
460 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
461 struct gpio_chip *chip = range->gc;
462
463 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
464 offset, range->name, offset, input ? "input" : "output");
465
466 if (input)
467 armada_37xx_gpio_direction_input(chip, offset);
468 else
469 armada_37xx_gpio_direction_output(chip, offset, 0);
470
471 return 0;
472 }
473
474 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
475 struct pinctrl_gpio_range *range,
476 unsigned int offset)
477 {
478 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
479 struct armada_37xx_pin_group *group;
480 int grp = 0;
481
482 dev_dbg(info->dev, "requesting gpio %d\n", offset);
483
484 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
485 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
486
487 return 0;
488 }
489
490 static const struct pinmux_ops armada_37xx_pmx_ops = {
491 .get_functions_count = armada_37xx_pmx_get_funcs_count,
492 .get_function_name = armada_37xx_pmx_get_func_name,
493 .get_function_groups = armada_37xx_pmx_get_groups,
494 .set_mux = armada_37xx_pmx_set,
495 .gpio_request_enable = armada_37xx_gpio_request_enable,
496 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
497 };
498
499 static const struct gpio_chip armada_37xx_gpiolib_chip = {
500 .request = gpiochip_generic_request,
501 .free = gpiochip_generic_free,
502 .set = armada_37xx_gpio_set,
503 .get = armada_37xx_gpio_get,
504 .get_direction = armada_37xx_gpio_get_direction,
505 .direction_input = armada_37xx_gpio_direction_input,
506 .direction_output = armada_37xx_gpio_direction_output,
507 .owner = THIS_MODULE,
508 };
509
510 static void armada_37xx_irq_ack(struct irq_data *d)
511 {
512 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
513 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
514 u32 reg = IRQ_STATUS;
515 unsigned long flags;
516
517 armada_37xx_irq_update_reg(&reg, d);
518 spin_lock_irqsave(&info->irq_lock, flags);
519 writel(d->mask, info->base + reg);
520 spin_unlock_irqrestore(&info->irq_lock, flags);
521 }
522
523 static void armada_37xx_irq_mask(struct irq_data *d)
524 {
525 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
526 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
527 u32 val, reg = IRQ_EN;
528 unsigned long flags;
529
530 armada_37xx_irq_update_reg(&reg, d);
531 spin_lock_irqsave(&info->irq_lock, flags);
532 val = readl(info->base + reg);
533 writel(val & ~d->mask, info->base + reg);
534 spin_unlock_irqrestore(&info->irq_lock, flags);
535 }
536
537 static void armada_37xx_irq_unmask(struct irq_data *d)
538 {
539 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
540 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
541 u32 val, reg = IRQ_EN;
542 unsigned long flags;
543
544 armada_37xx_irq_update_reg(&reg, d);
545 spin_lock_irqsave(&info->irq_lock, flags);
546 val = readl(info->base + reg);
547 writel(val | d->mask, info->base + reg);
548 spin_unlock_irqrestore(&info->irq_lock, flags);
549 }
550
551 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
552 {
553 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
554 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
555 u32 val, reg = IRQ_WKUP;
556 unsigned long flags;
557
558 armada_37xx_irq_update_reg(&reg, d);
559 spin_lock_irqsave(&info->irq_lock, flags);
560 val = readl(info->base + reg);
561 if (on)
562 val |= (BIT(d->hwirq % GPIO_PER_REG));
563 else
564 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
565 writel(val, info->base + reg);
566 spin_unlock_irqrestore(&info->irq_lock, flags);
567
568 return 0;
569 }
570
571 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
572 {
573 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
574 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
575 u32 val, reg = IRQ_POL;
576 unsigned long flags;
577
578 spin_lock_irqsave(&info->irq_lock, flags);
579 armada_37xx_irq_update_reg(&reg, d);
580 val = readl(info->base + reg);
581 switch (type) {
582 case IRQ_TYPE_EDGE_RISING:
583 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
584 break;
585 case IRQ_TYPE_EDGE_FALLING:
586 val |= (BIT(d->hwirq % GPIO_PER_REG));
587 break;
588 default:
589 spin_unlock_irqrestore(&info->irq_lock, flags);
590 return -EINVAL;
591 }
592 writel(val, info->base + reg);
593 spin_unlock_irqrestore(&info->irq_lock, flags);
594
595 return 0;
596 }
597
598
599 static void armada_37xx_irq_handler(struct irq_desc *desc)
600 {
601 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
602 struct irq_chip *chip = irq_desc_get_chip(desc);
603 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
604 struct irq_domain *d = gc->irqdomain;
605 int i;
606
607 chained_irq_enter(chip, desc);
608 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
609 u32 status;
610 unsigned long flags;
611
612 spin_lock_irqsave(&info->irq_lock, flags);
613 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
614 /* Manage only the interrupt that was enabled */
615 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
616 spin_unlock_irqrestore(&info->irq_lock, flags);
617 while (status) {
618 u32 hwirq = ffs(status) - 1;
619 u32 virq = irq_find_mapping(d, hwirq +
620 i * GPIO_PER_REG);
621
622 generic_handle_irq(virq);
623
624 /* Update status in case a new IRQ appears */
625 spin_lock_irqsave(&info->irq_lock, flags);
626 status = readl_relaxed(info->base +
627 IRQ_STATUS + 4 * i);
628 /* Manage only the interrupt that was enabled */
629 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
630 spin_unlock_irqrestore(&info->irq_lock, flags);
631 }
632 }
633 chained_irq_exit(chip, desc);
634 }
635
636 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
637 {
638 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
639 int irq = d->hwirq - chip->irq_base;
640 /*
641 * The mask field is a "precomputed bitmask for accessing the
642 * chip registers" which was introduced for the generic
643 * irqchip framework. As we don't use this framework, we can
644 * reuse this field for our own usage.
645 */
646 d->mask = BIT(irq % GPIO_PER_REG);
647
648 armada_37xx_irq_unmask(d);
649
650 return 0;
651 }
652
653 static int armada_37xx_irqchip_register(struct platform_device *pdev,
654 struct armada_37xx_pinctrl *info)
655 {
656 struct device_node *np = info->dev->of_node;
657 struct gpio_chip *gc = &info->gpio_chip;
658 struct irq_chip *irqchip = &info->irq_chip;
659 struct resource res;
660 int ret = -ENODEV, i, nr_irq_parent;
661
662 /* Check if we have at least one gpio-controller child node */
663 for_each_child_of_node(info->dev->of_node, np) {
664 if (of_property_read_bool(np, "gpio-controller")) {
665 ret = 0;
666 break;
667 }
668 };
669 if (ret)
670 return ret;
671
672 nr_irq_parent = of_irq_count(np);
673 spin_lock_init(&info->irq_lock);
674
675 if (!nr_irq_parent) {
676 dev_err(&pdev->dev, "Invalid or no IRQ\n");
677 return 0;
678 }
679
680 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
681 dev_err(info->dev, "cannot find IO resource\n");
682 return -ENOENT;
683 }
684
685 info->base = devm_ioremap_resource(info->dev, &res);
686 if (IS_ERR(info->base))
687 return PTR_ERR(info->base);
688
689 irqchip->irq_ack = armada_37xx_irq_ack;
690 irqchip->irq_mask = armada_37xx_irq_mask;
691 irqchip->irq_unmask = armada_37xx_irq_unmask;
692 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
693 irqchip->irq_set_type = armada_37xx_irq_set_type;
694 irqchip->irq_startup = armada_37xx_irq_startup;
695 irqchip->name = info->data->name;
696 ret = gpiochip_irqchip_add(gc, irqchip, 0,
697 handle_edge_irq, IRQ_TYPE_NONE);
698 if (ret) {
699 dev_info(&pdev->dev, "could not add irqchip\n");
700 return ret;
701 }
702
703 /*
704 * Many interrupts are connected to the parent interrupt
705 * controller. But we do not take advantage of this and use
706 * the chained irq with all of them.
707 */
708 for (i = 0; i < nr_irq_parent; i++) {
709 int irq = irq_of_parse_and_map(np, i);
710
711 if (irq < 0)
712 continue;
713
714 gpiochip_set_chained_irqchip(gc, irqchip, irq,
715 armada_37xx_irq_handler);
716 }
717
718 return 0;
719 }
720
721 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
722 struct armada_37xx_pinctrl *info)
723 {
724 struct device_node *np;
725 struct gpio_chip *gc;
726 int ret = -ENODEV;
727
728 for_each_child_of_node(info->dev->of_node, np) {
729 if (of_find_property(np, "gpio-controller", NULL)) {
730 ret = 0;
731 break;
732 }
733 };
734 if (ret)
735 return ret;
736
737 info->gpio_chip = armada_37xx_gpiolib_chip;
738
739 gc = &info->gpio_chip;
740 gc->ngpio = info->data->nr_pins;
741 gc->parent = &pdev->dev;
742 gc->base = -1;
743 gc->of_node = np;
744 gc->label = info->data->name;
745
746 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
747 if (ret)
748 return ret;
749 ret = armada_37xx_irqchip_register(pdev, info);
750 if (ret)
751 return ret;
752
753 return 0;
754 }
755
756 /**
757 * armada_37xx_add_function() - Add a new function to the list
758 * @funcs: array of function to add the new one
759 * @funcsize: size of the remaining space for the function
760 * @name: name of the function to add
761 *
762 * If it is a new function then create it by adding its name else
763 * increment the number of group associated to this function.
764 */
765 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
766 int *funcsize, const char *name)
767 {
768 int i = 0;
769
770 if (*funcsize <= 0)
771 return -EOVERFLOW;
772
773 while (funcs->ngroups) {
774 /* function already there */
775 if (strcmp(funcs->name, name) == 0) {
776 funcs->ngroups++;
777
778 return -EEXIST;
779 }
780 funcs++;
781 i++;
782 }
783
784 /* append new unique function */
785 funcs->name = name;
786 funcs->ngroups = 1;
787 (*funcsize)--;
788
789 return 0;
790 }
791
792 /**
793 * armada_37xx_fill_group() - complete the group array
794 * @info: info driver instance
795 *
796 * Based on the data available from the armada_37xx_pin_group array
797 * completes the last member of the struct for each function: the list
798 * of the groups associated to this function.
799 *
800 */
801 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
802 {
803 int n, num = 0, funcsize = info->data->nr_pins;
804
805 for (n = 0; n < info->ngroups; n++) {
806 struct armada_37xx_pin_group *grp = &info->groups[n];
807 int i, j, f;
808
809 grp->pins = devm_kzalloc(info->dev,
810 (grp->npins + grp->extra_npins) *
811 sizeof(*grp->pins), GFP_KERNEL);
812 if (!grp->pins)
813 return -ENOMEM;
814
815 for (i = 0; i < grp->npins; i++)
816 grp->pins[i] = grp->start_pin + i;
817
818 for (j = 0; j < grp->extra_npins; j++)
819 grp->pins[i+j] = grp->extra_pin + j;
820
821 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
822 int ret;
823 /* check for unique functions and count groups */
824 ret = armada_37xx_add_function(info->funcs, &funcsize,
825 grp->funcs[f]);
826 if (ret == -EOVERFLOW)
827 dev_err(info->dev,
828 "More functions than pins(%d)\n",
829 info->data->nr_pins);
830 if (ret < 0)
831 continue;
832 num++;
833 }
834 }
835
836 info->nfuncs = num;
837
838 return 0;
839 }
840
841 /**
842 * armada_37xx_fill_funcs() - complete the funcs array
843 * @info: info driver instance
844 *
845 * Based on the data available from the armada_37xx_pin_group array
846 * completes the last two member of the struct for each group:
847 * - the list of the pins included in the group
848 * - the list of pinmux functions that can be selected for this group
849 *
850 */
851 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
852 {
853 struct armada_37xx_pmx_func *funcs = info->funcs;
854 int n;
855
856 for (n = 0; n < info->nfuncs; n++) {
857 const char *name = funcs[n].name;
858 const char **groups;
859 int g;
860
861 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
862 sizeof(*(funcs[n].groups)),
863 GFP_KERNEL);
864 if (!funcs[n].groups)
865 return -ENOMEM;
866
867 groups = funcs[n].groups;
868
869 for (g = 0; g < info->ngroups; g++) {
870 struct armada_37xx_pin_group *gp = &info->groups[g];
871 int f;
872
873 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
874 if (strcmp(gp->funcs[f], name) == 0) {
875 *groups = gp->name;
876 groups++;
877 }
878 }
879 }
880 }
881 return 0;
882 }
883
884 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
885 struct armada_37xx_pinctrl *info)
886 {
887 const struct armada_37xx_pin_data *pin_data = info->data;
888 struct pinctrl_desc *ctrldesc = &info->pctl;
889 struct pinctrl_pin_desc *pindesc, *pdesc;
890 int pin, ret;
891
892 info->groups = pin_data->groups;
893 info->ngroups = pin_data->ngroups;
894
895 ctrldesc->name = "armada_37xx-pinctrl";
896 ctrldesc->owner = THIS_MODULE;
897 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
898 ctrldesc->pmxops = &armada_37xx_pmx_ops;
899 ctrldesc->confops = &armada_37xx_pinconf_ops;
900
901 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
902 pin_data->nr_pins, GFP_KERNEL);
903 if (!pindesc)
904 return -ENOMEM;
905
906 ctrldesc->pins = pindesc;
907 ctrldesc->npins = pin_data->nr_pins;
908
909 pdesc = pindesc;
910 for (pin = 0; pin < pin_data->nr_pins; pin++) {
911 pdesc->number = pin;
912 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
913 pin_data->name, pin);
914 pdesc++;
915 }
916
917 /*
918 * we allocate functions for number of pins and hope there are
919 * fewer unique functions than pins available
920 */
921 info->funcs = devm_kzalloc(&pdev->dev, pin_data->nr_pins *
922 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
923 if (!info->funcs)
924 return -ENOMEM;
925
926
927 ret = armada_37xx_fill_group(info);
928 if (ret)
929 return ret;
930
931 ret = armada_37xx_fill_func(info);
932 if (ret)
933 return ret;
934
935 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
936 if (IS_ERR(info->pctl_dev)) {
937 dev_err(&pdev->dev, "could not register pinctrl driver\n");
938 return PTR_ERR(info->pctl_dev);
939 }
940
941 return 0;
942 }
943
944 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
945 {
946 .compatible = "marvell,armada3710-sb-pinctrl",
947 .data = (void *)&armada_37xx_pin_sb,
948 },
949 {
950 .compatible = "marvell,armada3710-nb-pinctrl",
951 .data = (void *)&armada_37xx_pin_nb,
952 },
953 { },
954 };
955
956 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
957 {
958 struct armada_37xx_pinctrl *info;
959 struct device *dev = &pdev->dev;
960 struct device_node *np = dev->of_node;
961 struct regmap *regmap;
962 int ret;
963
964 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
965 GFP_KERNEL);
966 if (!info)
967 return -ENOMEM;
968
969 info->dev = dev;
970
971 regmap = syscon_node_to_regmap(np);
972 if (IS_ERR(regmap)) {
973 dev_err(&pdev->dev, "cannot get regmap\n");
974 return PTR_ERR(regmap);
975 }
976 info->regmap = regmap;
977
978 info->data = of_device_get_match_data(dev);
979
980 ret = armada_37xx_pinctrl_register(pdev, info);
981 if (ret)
982 return ret;
983
984 ret = armada_37xx_gpiochip_register(pdev, info);
985 if (ret)
986 return ret;
987
988 platform_set_drvdata(pdev, info);
989
990 return 0;
991 }
992
993 static struct platform_driver armada_37xx_pinctrl_driver = {
994 .driver = {
995 .name = "armada-37xx-pinctrl",
996 .of_match_table = armada_37xx_pinctrl_of_match,
997 },
998 };
999
1000 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1001 armada_37xx_pinctrl_probe);
Linux with added FPC-III support