drivers/pinctrl/samsung/pinctrl-exynos-arm.c

   1 /*
   2  * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2012 Linaro Ltd
   7  *              http://www.linaro.org
   8  *
   9  * Author: Thomas Abraham <thomas.ab@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This file contains the Samsung Exynos specific information required by the
  17  * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  18  * external gpio and wakeup interrupt support.
  19  */
  20
  21 #include <linux/device.h>
  22 #include <linux/of_address.h>
  23 #include <linux/slab.h>
  24 #include <linux/err.h>
  25 #include <linux/soc/samsung/exynos-regs-pmu.h>
  26
  27 #include "pinctrl-samsung.h"
  28 #include "pinctrl-exynos.h"
  29
  30 static const struct samsung_pin_bank_type bank_type_off = {
  31         .fld_width = { 4, 1, 2, 2, 2, 2, },
  32         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  33 };
  34
  35 static const struct samsung_pin_bank_type bank_type_alive = {
  36         .fld_width = { 4, 1, 2, 2, },
  37         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  38 };
  39
  40 /* Retention control for S5PV210 are located at the end of clock controller */
  41 #define S5P_OTHERS 0xE000
  42
  43 #define S5P_OTHERS_RET_IO               (1 << 31)
  44 #define S5P_OTHERS_RET_CF               (1 << 30)
  45 #define S5P_OTHERS_RET_MMC              (1 << 29)
  46 #define S5P_OTHERS_RET_UART             (1 << 28)
  47
  48 static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
  49 {
  50         void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
  51         u32 tmp;
  52
  53         tmp = __raw_readl(clk_base + S5P_OTHERS);
  54         tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |
  55                 S5P_OTHERS_RET_UART);
  56         __raw_writel(tmp, clk_base + S5P_OTHERS);
  57 }
  58
  59 static struct samsung_retention_ctrl *
  60 s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
  61                        const struct samsung_retention_data *data)
  62 {
  63         struct samsung_retention_ctrl *ctrl;
  64         struct device_node *np;
  65         void __iomem *clk_base;
  66
  67         ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
  68         if (!ctrl)
  69                 return ERR_PTR(-ENOMEM);
  70
  71         np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
  72         if (!np) {
  73                 pr_err("%s: failed to find clock controller DT node\n",
  74                         __func__);
  75                 return ERR_PTR(-ENODEV);
  76         }
  77
  78         clk_base = of_iomap(np, 0);
  79         if (!clk_base) {
  80                 pr_err("%s: failed to map clock registers\n", __func__);
  81                 return ERR_PTR(-EINVAL);
  82         }
  83
  84         ctrl->priv = (void __force *)clk_base;
  85         ctrl->disable = s5pv210_retention_disable;
  86
  87         return ctrl;
  88 }
  89
  90 static const struct samsung_retention_data s5pv210_retention_data __initconst = {
  91         .init    = s5pv210_retention_init,
  92 };
  93
  94 /* pin banks of s5pv210 pin-controller */
  95 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
  96         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
  97         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
  98         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
  99         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 100         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 101         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 102         EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
 103         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
 104         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
 105         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
 106         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
 107         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
 108         EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
 109         EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
 110         EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
 111         EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
 112         EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
 113         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
 114         EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
 115         EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
 116         EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
 117         EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
 118         EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
 119         EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
 120         EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
 121         EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
 122         EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
 123         EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
 124         EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
 125         EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
 126         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
 127         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
 128         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
 129         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
 130 };
 131
 132 static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
 133         {
 134                 /* pin-controller instance 0 data */
 135                 .pin_banks      = s5pv210_pin_bank,
 136                 .nr_banks       = ARRAY_SIZE(s5pv210_pin_bank),
 137                 .eint_gpio_init = exynos_eint_gpio_init,
 138                 .eint_wkup_init = exynos_eint_wkup_init,
 139                 .suspend        = exynos_pinctrl_suspend,
 140                 .resume         = exynos_pinctrl_resume,
 141                 .retention_data = &s5pv210_retention_data,
 142         },
 143 };
 144
 145 const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = {
 146         .ctrl           = s5pv210_pin_ctrl,
 147         .num_ctrl       = ARRAY_SIZE(s5pv210_pin_ctrl),
 148 };
 149
 150 /* Pad retention control code for accessing PMU regmap */
 151 static atomic_t exynos_shared_retention_refcnt;
 152
 153 /* pin banks of exynos3250 pin-controller 0 */
 154 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
 155         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 156         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 157         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb",  0x08),
 158         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 159         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 160         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 161         EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
 162 };
 163
 164 /* pin banks of exynos3250 pin-controller 1 */
 165 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
 166         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
 167         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
 168         EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
 169         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
 170         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 171         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 172         EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
 173         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 174         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 175         EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
 176         EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
 177         EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
 178         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
 179         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
 180         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
 181         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
 182 };
 183
 184 /*
 185  * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle
 186  * them all together
 187  */
 188 static const u32 exynos3250_retention_regs[] = {
 189         S5P_PAD_RET_MAUDIO_OPTION,
 190         S5P_PAD_RET_GPIO_OPTION,
 191         S5P_PAD_RET_UART_OPTION,
 192         S5P_PAD_RET_MMCA_OPTION,
 193         S5P_PAD_RET_MMCB_OPTION,
 194         S5P_PAD_RET_EBIA_OPTION,
 195         S5P_PAD_RET_EBIB_OPTION,
 196         S5P_PAD_RET_MMC2_OPTION,
 197         S5P_PAD_RET_SPI_OPTION,
 198 };
 199
 200 static const struct samsung_retention_data exynos3250_retention_data __initconst = {
 201         .regs    = exynos3250_retention_regs,
 202         .nr_regs = ARRAY_SIZE(exynos3250_retention_regs),
 203         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 204         .refcnt  = &exynos_shared_retention_refcnt,
 205         .init    = exynos_retention_init,
 206 };
 207
 208 /*
 209  * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
 210  * two gpio/pin-mux/pinconfig controllers.
 211  */
 212 static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
 213         {
 214                 /* pin-controller instance 0 data */
 215                 .pin_banks      = exynos3250_pin_banks0,
 216                 .nr_banks       = ARRAY_SIZE(exynos3250_pin_banks0),
 217                 .eint_gpio_init = exynos_eint_gpio_init,
 218                 .suspend        = exynos_pinctrl_suspend,
 219                 .resume         = exynos_pinctrl_resume,
 220                 .retention_data = &exynos3250_retention_data,
 221         }, {
 222                 /* pin-controller instance 1 data */
 223                 .pin_banks      = exynos3250_pin_banks1,
 224                 .nr_banks       = ARRAY_SIZE(exynos3250_pin_banks1),
 225                 .eint_gpio_init = exynos_eint_gpio_init,
 226                 .eint_wkup_init = exynos_eint_wkup_init,
 227                 .suspend        = exynos_pinctrl_suspend,
 228                 .resume         = exynos_pinctrl_resume,
 229                 .retention_data = &exynos3250_retention_data,
 230         },
 231 };
 232
 233 const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {
 234         .ctrl           = exynos3250_pin_ctrl,
 235         .num_ctrl       = ARRAY_SIZE(exynos3250_pin_ctrl),
 236 };
 237
 238 /* pin banks of exynos4210 pin-controller 0 */
 239 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
 240         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 241         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 242         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 243         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 244         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 245         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 246         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 247         EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
 248         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
 249         EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
 250         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
 251         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
 252         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 253         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 254         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 255         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 256 };
 257
 258 /* pin banks of exynos4210 pin-controller 1 */
 259 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
 260         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
 261         EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
 262         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 263         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 264         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 265         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 266         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
 267         EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
 268         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 269         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 270         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 271         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 272         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 273         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 274         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 275         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 276         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 277         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 278         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 279         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 280 };
 281
 282 /* pin banks of exynos4210 pin-controller 2 */
 283 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
 284         EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
 285 };
 286
 287 /* PMU pad retention groups registers for Exynos4 (without audio) */
 288 static const u32 exynos4_retention_regs[] = {
 289         S5P_PAD_RET_GPIO_OPTION,
 290         S5P_PAD_RET_UART_OPTION,
 291         S5P_PAD_RET_MMCA_OPTION,
 292         S5P_PAD_RET_MMCB_OPTION,
 293         S5P_PAD_RET_EBIA_OPTION,
 294         S5P_PAD_RET_EBIB_OPTION,
 295 };
 296
 297 static const struct samsung_retention_data exynos4_retention_data __initconst = {
 298         .regs    = exynos4_retention_regs,
 299         .nr_regs = ARRAY_SIZE(exynos4_retention_regs),
 300         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 301         .refcnt  = &exynos_shared_retention_refcnt,
 302         .init    = exynos_retention_init,
 303 };
 304
 305 /* PMU retention control for audio pins can be tied to audio pin bank */
 306 static const u32 exynos4_audio_retention_regs[] = {
 307         S5P_PAD_RET_MAUDIO_OPTION,
 308 };
 309
 310 static const struct samsung_retention_data exynos4_audio_retention_data __initconst = {
 311         .regs    = exynos4_audio_retention_regs,
 312         .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs),
 313         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 314         .init    = exynos_retention_init,
 315 };
 316
 317 /*
 318  * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
 319  * three gpio/pin-mux/pinconfig controllers.
 320  */
 321 static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
 322         {
 323                 /* pin-controller instance 0 data */
 324                 .pin_banks      = exynos4210_pin_banks0,
 325                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks0),
 326                 .eint_gpio_init = exynos_eint_gpio_init,
 327                 .suspend        = exynos_pinctrl_suspend,
 328                 .resume         = exynos_pinctrl_resume,
 329                 .retention_data = &exynos4_retention_data,
 330         }, {
 331                 /* pin-controller instance 1 data */
 332                 .pin_banks      = exynos4210_pin_banks1,
 333                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks1),
 334                 .eint_gpio_init = exynos_eint_gpio_init,
 335                 .eint_wkup_init = exynos_eint_wkup_init,
 336                 .suspend        = exynos_pinctrl_suspend,
 337                 .resume         = exynos_pinctrl_resume,
 338                 .retention_data = &exynos4_retention_data,
 339         }, {
 340                 /* pin-controller instance 2 data */
 341                 .pin_banks      = exynos4210_pin_banks2,
 342                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks2),
 343                 .retention_data = &exynos4_audio_retention_data,
 344         },
 345 };
 346
 347 const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {
 348         .ctrl           = exynos4210_pin_ctrl,
 349         .num_ctrl       = ARRAY_SIZE(exynos4210_pin_ctrl),
 350 };
 351
 352 /* pin banks of exynos4x12 pin-controller 0 */
 353 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
 354         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 355         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 356         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 357         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 358         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 359         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 360         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 361         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 362         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 363         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 364         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 365         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
 366         EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
 367 };
 368
 369 /* pin banks of exynos4x12 pin-controller 1 */
 370 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
 371         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 372         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 373         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 374         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 375         EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
 376         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
 377         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 378         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 379         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 380         EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
 381         EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
 382         EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
 383         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 384         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 385         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 386         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 387         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 388         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 389         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 390         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 391         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 392         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 393         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 394 };
 395
 396 /* pin banks of exynos4x12 pin-controller 2 */
 397 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
 398         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 399 };
 400
 401 /* pin banks of exynos4x12 pin-controller 3 */
 402 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
 403         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 404         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 405         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
 406         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
 407         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
 408 };
 409
 410 /*
 411  * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
 412  * four gpio/pin-mux/pinconfig controllers.
 413  */
 414 static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
 415         {
 416                 /* pin-controller instance 0 data */
 417                 .pin_banks      = exynos4x12_pin_banks0,
 418                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks0),
 419                 .eint_gpio_init = exynos_eint_gpio_init,
 420                 .suspend        = exynos_pinctrl_suspend,
 421                 .resume         = exynos_pinctrl_resume,
 422                 .retention_data = &exynos4_retention_data,
 423         }, {
 424                 /* pin-controller instance 1 data */
 425                 .pin_banks      = exynos4x12_pin_banks1,
 426                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks1),
 427                 .eint_gpio_init = exynos_eint_gpio_init,
 428                 .eint_wkup_init = exynos_eint_wkup_init,
 429                 .suspend        = exynos_pinctrl_suspend,
 430                 .resume         = exynos_pinctrl_resume,
 431                 .retention_data = &exynos4_retention_data,
 432         }, {
 433                 /* pin-controller instance 2 data */
 434                 .pin_banks      = exynos4x12_pin_banks2,
 435                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks2),
 436                 .eint_gpio_init = exynos_eint_gpio_init,
 437                 .suspend        = exynos_pinctrl_suspend,
 438                 .resume         = exynos_pinctrl_resume,
 439                 .retention_data = &exynos4_audio_retention_data,
 440         }, {
 441                 /* pin-controller instance 3 data */
 442                 .pin_banks      = exynos4x12_pin_banks3,
 443                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks3),
 444                 .eint_gpio_init = exynos_eint_gpio_init,
 445                 .suspend        = exynos_pinctrl_suspend,
 446                 .resume         = exynos_pinctrl_resume,
 447         },
 448 };
 449
 450 const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {
 451         .ctrl           = exynos4x12_pin_ctrl,
 452         .num_ctrl       = ARRAY_SIZE(exynos4x12_pin_ctrl),
 453 };
 454
 455 /* pin banks of exynos5250 pin-controller 0 */
 456 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
 457         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 458         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 459         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 460         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 461         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
 462         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
 463         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
 464         EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
 465         EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
 466         EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
 467         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
 468         EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
 469         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
 470         EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
 471         EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
 472         EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
 473         EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
 474         EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
 475         EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
 476         EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
 477         EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
 478         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 479         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 480         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 481         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 482 };
 483
 484 /* pin banks of exynos5250 pin-controller 1 */
 485 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
 486         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
 487         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
 488         EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
 489         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
 490         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
 491         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
 492         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
 493         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
 494         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
 495 };
 496
 497 /* pin banks of exynos5250 pin-controller 2 */
 498 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
 499         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 500         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 501         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
 502         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
 503         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
 504 };
 505
 506 /* pin banks of exynos5250 pin-controller 3 */
 507 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
 508         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 509 };
 510
 511 /*
 512  * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
 513  * four gpio/pin-mux/pinconfig controllers.
 514  */
 515 static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
 516         {
 517                 /* pin-controller instance 0 data */
 518                 .pin_banks      = exynos5250_pin_banks0,
 519                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks0),
 520                 .eint_gpio_init = exynos_eint_gpio_init,
 521                 .eint_wkup_init = exynos_eint_wkup_init,
 522                 .suspend        = exynos_pinctrl_suspend,
 523                 .resume         = exynos_pinctrl_resume,
 524                 .retention_data = &exynos4_retention_data,
 525         }, {
 526                 /* pin-controller instance 1 data */
 527                 .pin_banks      = exynos5250_pin_banks1,
 528                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks1),
 529                 .eint_gpio_init = exynos_eint_gpio_init,
 530                 .suspend        = exynos_pinctrl_suspend,
 531                 .resume         = exynos_pinctrl_resume,
 532                 .retention_data = &exynos4_retention_data,
 533         }, {
 534                 /* pin-controller instance 2 data */
 535                 .pin_banks      = exynos5250_pin_banks2,
 536                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks2),
 537                 .eint_gpio_init = exynos_eint_gpio_init,
 538                 .suspend        = exynos_pinctrl_suspend,
 539                 .resume         = exynos_pinctrl_resume,
 540         }, {
 541                 /* pin-controller instance 3 data */
 542                 .pin_banks      = exynos5250_pin_banks3,
 543                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks3),
 544                 .eint_gpio_init = exynos_eint_gpio_init,
 545                 .suspend        = exynos_pinctrl_suspend,
 546                 .resume         = exynos_pinctrl_resume,
 547                 .retention_data = &exynos4_audio_retention_data,
 548         },
 549 };
 550
 551 const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {
 552         .ctrl           = exynos5250_pin_ctrl,
 553         .num_ctrl       = ARRAY_SIZE(exynos5250_pin_ctrl),
 554 };
 555
 556 /* pin banks of exynos5260 pin-controller 0 */
 557 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
 558         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
 559         EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
 560         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 561         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 562         EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
 563         EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
 564         EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
 565         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
 566         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
 567         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
 568         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
 569         EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
 570         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
 571         EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
 572         EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
 573         EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
 574         EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
 575         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
 576         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
 577         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
 578         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
 579 };
 580
 581 /* pin banks of exynos5260 pin-controller 1 */
 582 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
 583         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
 584         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
 585         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
 586         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
 587         EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
 588 };
 589
 590 /* pin banks of exynos5260 pin-controller 2 */
 591 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
 592         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
 593         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
 594 };
 595
 596 /*
 597  * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
 598  * three gpio/pin-mux/pinconfig controllers.
 599  */
 600 static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
 601         {
 602                 /* pin-controller instance 0 data */
 603                 .pin_banks      = exynos5260_pin_banks0,
 604                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks0),
 605                 .eint_gpio_init = exynos_eint_gpio_init,
 606                 .eint_wkup_init = exynos_eint_wkup_init,
 607         }, {
 608                 /* pin-controller instance 1 data */
 609                 .pin_banks      = exynos5260_pin_banks1,
 610                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks1),
 611                 .eint_gpio_init = exynos_eint_gpio_init,
 612         }, {
 613                 /* pin-controller instance 2 data */
 614                 .pin_banks      = exynos5260_pin_banks2,
 615                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks2),
 616                 .eint_gpio_init = exynos_eint_gpio_init,
 617         },
 618 };
 619
 620 const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {
 621         .ctrl           = exynos5260_pin_ctrl,
 622         .num_ctrl       = ARRAY_SIZE(exynos5260_pin_ctrl),
 623 };
 624
 625 /* pin banks of exynos5410 pin-controller 0 */
 626 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
 627         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 628         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 629         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 630         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 631         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
 632         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
 633         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
 634         EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
 635         EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
 636         EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
 637         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
 638         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
 639         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
 640         EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
 641         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
 642         EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
 643         EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
 644         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
 645         EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
 646         EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
 647         EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
 648         EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
 649         EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
 650         EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
 651         EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
 652         EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
 653         EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
 654         EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
 655         EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
 656         EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
 657         EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
 658         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 659         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 660         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 661         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 662 };
 663
 664 /* pin banks of exynos5410 pin-controller 1 */
 665 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
 666         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
 667         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
 668         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
 669         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
 670         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
 671         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
 672         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
 673         EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
 674         EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
 675 };
 676
 677 /* pin banks of exynos5410 pin-controller 2 */
 678 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
 679         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 680         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 681         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
 682         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
 683         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
 684 };
 685
 686 /* pin banks of exynos5410 pin-controller 3 */
 687 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
 688         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 689 };
 690
 691 /*
 692  * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
 693  * four gpio/pin-mux/pinconfig controllers.
 694  */
 695 static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
 696         {
 697                 /* pin-controller instance 0 data */
 698                 .pin_banks      = exynos5410_pin_banks0,
 699                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks0),
 700                 .eint_gpio_init = exynos_eint_gpio_init,
 701                 .eint_wkup_init = exynos_eint_wkup_init,
 702                 .suspend        = exynos_pinctrl_suspend,
 703                 .resume         = exynos_pinctrl_resume,
 704         }, {
 705                 /* pin-controller instance 1 data */
 706                 .pin_banks      = exynos5410_pin_banks1,
 707                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks1),
 708                 .eint_gpio_init = exynos_eint_gpio_init,
 709                 .suspend        = exynos_pinctrl_suspend,
 710                 .resume         = exynos_pinctrl_resume,
 711         }, {
 712                 /* pin-controller instance 2 data */
 713                 .pin_banks      = exynos5410_pin_banks2,
 714                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks2),
 715                 .eint_gpio_init = exynos_eint_gpio_init,
 716                 .suspend        = exynos_pinctrl_suspend,
 717                 .resume         = exynos_pinctrl_resume,
 718         }, {
 719                 /* pin-controller instance 3 data */
 720                 .pin_banks      = exynos5410_pin_banks3,
 721                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks3),
 722                 .eint_gpio_init = exynos_eint_gpio_init,
 723                 .suspend        = exynos_pinctrl_suspend,
 724                 .resume         = exynos_pinctrl_resume,
 725         },
 726 };
 727
 728 const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {
 729         .ctrl           = exynos5410_pin_ctrl,
 730         .num_ctrl       = ARRAY_SIZE(exynos5410_pin_ctrl),
 731 };
 732
 733 /* pin banks of exynos5420 pin-controller 0 */
 734 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
 735         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
 736         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 737         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 738         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 739         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 740 };
 741
 742 /* pin banks of exynos5420 pin-controller 1 */
 743 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
 744         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
 745         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
 746         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
 747         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
 748         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
 749         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
 750         EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
 751         EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
 752         EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
 753         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
 754         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
 755         EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
 756         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
 757 };
 758
 759 /* pin banks of exynos5420 pin-controller 2 */
 760 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
 761         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
 762         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
 763         EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
 764         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
 765         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
 766         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
 767         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
 768         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
 769 };
 770
 771 /* pin banks of exynos5420 pin-controller 3 */
 772 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
 773         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 774         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 775         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 776         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 777         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
 778         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
 779         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
 780         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
 781         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
 782 };
 783
 784 /* pin banks of exynos5420 pin-controller 4 */
 785 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
 786         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 787 };
 788
 789 /* PMU pad retention groups registers for Exynos5420 (without audio) */
 790 static const u32 exynos5420_retention_regs[] = {
 791         EXYNOS_PAD_RET_DRAM_OPTION,
 792         EXYNOS_PAD_RET_JTAG_OPTION,
 793         EXYNOS5420_PAD_RET_GPIO_OPTION,
 794         EXYNOS5420_PAD_RET_UART_OPTION,
 795         EXYNOS5420_PAD_RET_MMCA_OPTION,
 796         EXYNOS5420_PAD_RET_MMCB_OPTION,
 797         EXYNOS5420_PAD_RET_MMCC_OPTION,
 798         EXYNOS5420_PAD_RET_HSI_OPTION,
 799         EXYNOS_PAD_RET_EBIA_OPTION,
 800         EXYNOS_PAD_RET_EBIB_OPTION,
 801         EXYNOS5420_PAD_RET_SPI_OPTION,
 802         EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
 803 };
 804
 805 static const struct samsung_retention_data exynos5420_retention_data __initconst = {
 806         .regs    = exynos5420_retention_regs,
 807         .nr_regs = ARRAY_SIZE(exynos5420_retention_regs),
 808         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 809         .refcnt  = &exynos_shared_retention_refcnt,
 810         .init    = exynos_retention_init,
 811 };
 812
 813 /*
 814  * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
 815  * four gpio/pin-mux/pinconfig controllers.
 816  */
 817 static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
 818         {
 819                 /* pin-controller instance 0 data */
 820                 .pin_banks      = exynos5420_pin_banks0,
 821                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks0),
 822                 .eint_gpio_init = exynos_eint_gpio_init,
 823                 .eint_wkup_init = exynos_eint_wkup_init,
 824                 .retention_data = &exynos5420_retention_data,
 825         }, {
 826                 /* pin-controller instance 1 data */
 827                 .pin_banks      = exynos5420_pin_banks1,
 828                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks1),
 829                 .eint_gpio_init = exynos_eint_gpio_init,
 830                 .retention_data = &exynos5420_retention_data,
 831         }, {
 832                 /* pin-controller instance 2 data */
 833                 .pin_banks      = exynos5420_pin_banks2,
 834                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks2),
 835                 .eint_gpio_init = exynos_eint_gpio_init,
 836                 .retention_data = &exynos5420_retention_data,
 837         }, {
 838                 /* pin-controller instance 3 data */
 839                 .pin_banks      = exynos5420_pin_banks3,
 840                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks3),
 841                 .eint_gpio_init = exynos_eint_gpio_init,
 842                 .retention_data = &exynos5420_retention_data,
 843         }, {
 844                 /* pin-controller instance 4 data */
 845                 .pin_banks      = exynos5420_pin_banks4,
 846                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks4),
 847                 .eint_gpio_init = exynos_eint_gpio_init,
 848                 .retention_data = &exynos4_audio_retention_data,
 849         },
 850 };
 851
 852 const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = {
 853         .ctrl           = exynos5420_pin_ctrl,
 854         .num_ctrl       = ARRAY_SIZE(exynos5420_pin_ctrl),
 855 };