drivers/staging/rtlwifi/wifi.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __RTL_WIFI_H__
  27 #define __RTL_WIFI_H__
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sched.h>
  32 #include <linux/firmware.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/usb.h>
  36 #include <net/mac80211.h>
  37 #include <linux/completion.h>
  38 #include "debug.h"
  39
  40 #define MASKBYTE0                               0xff
  41 #define MASKBYTE1                               0xff00
  42 #define MASKBYTE2                               0xff0000
  43 #define MASKBYTE3                               0xff000000
  44 #define MASKHWORD                               0xffff0000
  45 #define MASKLWORD                               0x0000ffff
  46 #define MASKDWORD                               0xffffffff
  47 #define MASK12BITS                              0xfff
  48 #define MASKH4BITS                              0xf0000000
  49 #define MASKOFDM_D                              0xffc00000
  50 #define MASKCCK                                 0x3f3f3f3f
  51
  52 #define MASK4BITS                               0x0f
  53 #define MASK20BITS                              0xfffff
  54 #define RFREG_OFFSET_MASK                       0xfffff
  55
  56 #define MASKBYTE0                               0xff
  57 #define MASKBYTE1                               0xff00
  58 #define MASKBYTE2                               0xff0000
  59 #define MASKBYTE3                               0xff000000
  60 #define MASKHWORD                               0xffff0000
  61 #define MASKLWORD                               0x0000ffff
  62 #define MASKDWORD                               0xffffffff
  63 #define MASK12BITS                              0xfff
  64 #define MASKH4BITS                              0xf0000000
  65 #define MASKOFDM_D                              0xffc00000
  66 #define MASKCCK                                 0x3f3f3f3f
  67
  68 #define MASK4BITS                               0x0f
  69 #define MASK20BITS                              0xfffff
  70 #define RFREG_OFFSET_MASK                       0xfffff
  71
  72 #define RF_CHANGE_BY_INIT                       0
  73 #define RF_CHANGE_BY_IPS                        BIT(28)
  74 #define RF_CHANGE_BY_PS                         BIT(29)
  75 #define RF_CHANGE_BY_HW                         BIT(30)
  76 #define RF_CHANGE_BY_SW                         BIT(31)
  77
  78 #define IQK_ADDA_REG_NUM                        16
  79 #define IQK_MAC_REG_NUM                         4
  80 #define IQK_THRESHOLD                           8
  81
  82 #define MAX_KEY_LEN                             61
  83 #define KEY_BUF_SIZE                            5
  84
  85 /* QoS related. */
  86 /*aci: 0x00     Best Effort*/
  87 /*aci: 0x01     Background*/
  88 /*aci: 0x10     Video*/
  89 /*aci: 0x11     Voice*/
  90 /*Max: define total number.*/
  91 #define AC0_BE                                  0
  92 #define AC1_BK                                  1
  93 #define AC2_VI                                  2
  94 #define AC3_VO                                  3
  95 #define AC_MAX                                  4
  96 #define QOS_QUEUE_NUM                           4
  97 #define RTL_MAC80211_NUM_QUEUE                  5
  98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE          254
  99 #define RTL_USB_MAX_RX_COUNT                    100
 100 #define QBSS_LOAD_SIZE                          5
 101 #define MAX_WMMELE_LENGTH                       64
 102 #define ASPM_L1_LATENCY                         7
 103
 104 #define TOTAL_CAM_ENTRY                         32
 105
 106 /*slot time for 11g. */
 107 #define RTL_SLOT_TIME_9                         9
 108 #define RTL_SLOT_TIME_20                        20
 109
 110 /*related to tcp/ip. */
 111 #define SNAP_SIZE               6
 112 #define PROTOC_TYPE_SIZE        2
 113
 114 /*related with 802.11 frame*/
 115 #define MAC80211_3ADDR_LEN                      24
 116 #define MAC80211_4ADDR_LEN                      30
 117
 118 #define CHANNEL_MAX_NUMBER      (14 + 24 + 21)  /* 14 is the max channel no */
 119 #define CHANNEL_MAX_NUMBER_2G           14
 120 #define CHANNEL_MAX_NUMBER_5G           49 /* Please refer to
 121                                             *"phy_GetChnlGroup8812A" and
 122                                             * "Hal_ReadTxPowerInfo8812A"
 123                                             */
 124 #define CHANNEL_MAX_NUMBER_5G_80M       7
 125 #define CHANNEL_GROUP_MAX       (3 + 9) /*  ch1~3, 4~9, 10~14 = three groups */
 126 #define MAX_PG_GROUP                    13
 127 #define CHANNEL_GROUP_MAX_2G            3
 128 #define CHANNEL_GROUP_IDX_5GL           3
 129 #define CHANNEL_GROUP_IDX_5GM           6
 130 #define CHANNEL_GROUP_IDX_5GH           9
 131 #define CHANNEL_GROUP_MAX_5G            9
 132 #define CHANNEL_MAX_NUMBER_2G           14
 133 #define AVG_THERMAL_NUM                 8
 134 #define AVG_THERMAL_NUM_88E             4
 135 #define AVG_THERMAL_NUM_8723BE          4
 136 #define MAX_TID_COUNT                   9
 137
 138 /* for early mode */
 139 #define FCS_LEN                         4
 140 #define EM_HDR_LEN                      8
 141
 142 enum rtl8192c_h2c_cmd {
 143         H2C_AP_OFFLOAD = 0,
 144         H2C_SETPWRMODE = 1,
 145         H2C_JOINBSSRPT = 2,
 146         H2C_RSVDPAGE = 3,
 147         H2C_RSSI_REPORT = 5,
 148         H2C_RA_MASK = 6,
 149         H2C_MACID_PS_MODE = 7,
 150         H2C_P2P_PS_OFFLOAD = 8,
 151         H2C_MAC_MODE_SEL = 9,
 152         H2C_PWRM = 15,
 153         H2C_P2P_PS_CTW_CMD = 24,
 154         MAX_H2CCMD
 155 };
 156
 157 #define MAX_TX_COUNT                    4
 158 #define MAX_REGULATION_NUM              4
 159 #define MAX_RF_PATH_NUM                 4
 160 #define MAX_RATE_SECTION_NUM            6       /* = MAX_RATE_SECTION */
 161 #define MAX_2_4G_BANDWIDTH_NUM          4
 162 #define MAX_5G_BANDWIDTH_NUM            4
 163 #define MAX_RF_PATH                     4
 164 #define MAX_CHNL_GROUP_24G              6
 165 #define MAX_CHNL_GROUP_5G               14
 166
 167 #define TX_PWR_BY_RATE_NUM_BAND         2
 168 #define TX_PWR_BY_RATE_NUM_RF           4
 169 #define TX_PWR_BY_RATE_NUM_SECTION      12
 170 /* compatible with TX_PWR_BY_RATE_NUM_SECTION */
 171 #define TX_PWR_BY_RATE_NUM_RATE         84
 172 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G  6       /* MAX_RATE_SECTION */
 173 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G   5       /* MAX_RATE_SECTION -1 */
 174
 175 #define BUFDESC_SEG_NUM         1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
 176
 177 #define DEL_SW_IDX_SZ           30
 178
 179 /* For now, it's just for 8192ee
 180  * but not OK yet, keep it 0
 181  */
 182 #define RTL8192EE_SEG_NUM               BUFDESC_SEG_NUM
 183 #define RTL8822BE_SEG_NUM               BUFDESC_SEG_NUM
 184
 185 enum rf_tx_num {
 186         RF_1TX = 0,
 187         RF_2TX,
 188         RF_MAX_TX_NUM,
 189         RF_TX_NUM_NONIMPLEMENT,
 190 };
 191
 192 #define PACKET_NORMAL                   0
 193 #define PACKET_DHCP                     1
 194 #define PACKET_ARP                      2
 195 #define PACKET_EAPOL                    3
 196
 197 #define MAX_SUPPORT_WOL_PATTERN_NUM     16
 198 #define RSVD_WOL_PATTERN_NUM            1
 199 #define WKFMCAM_ADDR_NUM                6
 200 #define WKFMCAM_SIZE                    24
 201
 202 #define MAX_WOL_BIT_MASK_SIZE           16
 203 /* MIN LEN keeps 13 here */
 204 #define MIN_WOL_PATTERN_SIZE            13
 205 #define MAX_WOL_PATTERN_SIZE            128
 206
 207 #define WAKE_ON_MAGIC_PACKET            BIT(0)
 208 #define WAKE_ON_PATTERN_MATCH           BIT(1)
 209
 210 #define WOL_REASON_PTK_UPDATE           BIT(0)
 211 #define WOL_REASON_GTK_UPDATE           BIT(1)
 212 #define WOL_REASON_DISASSOC             BIT(2)
 213 #define WOL_REASON_DEAUTH               BIT(3)
 214 #define WOL_REASON_AP_LOST              BIT(4)
 215 #define WOL_REASON_MAGIC_PKT            BIT(5)
 216 #define WOL_REASON_UNICAST_PKT          BIT(6)
 217 #define WOL_REASON_PATTERN_PKT          BIT(7)
 218 #define WOL_REASON_RTD3_SSID_MATCH      BIT(8)
 219 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
 220 #define WOL_REASON_REALWOW_V2_ACKLOST   BIT(10)
 221
 222 struct rtlwifi_firmware_header {
 223         __le16 signature;
 224         u8 category;
 225         u8 function;
 226         __le16 version;
 227         u8 subversion;
 228         u8 rsvd1;
 229         u8 month;
 230         u8 date;
 231         u8 hour;
 232         u8 minute;
 233         __le16 ramcodesize;
 234         __le16 rsvd2;
 235         __le32 svnindex;
 236         __le32 rsvd3;
 237         __le32 rsvd4;
 238         __le32 rsvd5;
 239 };
 240
 241 struct txpower_info_2g {
 242         u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 243         u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 244         /*If only one tx, only BW20 and OFDM are used.*/
 245         u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
 246         u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
 247         u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
 248         u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
 249         u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
 250         u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
 251 };
 252
 253 struct txpower_info_5g {
 254         u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
 255         /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
 256         u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
 257         u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
 258         u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
 259         u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
 260         u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
 261 };
 262
 263 enum rate_section {
 264         CCK = 0,
 265         OFDM,
 266         HT_MCS0_MCS7,
 267         HT_MCS8_MCS15,
 268         VHT_1SSMCS0_1SSMCS9,
 269         VHT_2SSMCS0_2SSMCS9,
 270         MAX_RATE_SECTION,
 271 };
 272
 273 enum intf_type {
 274         INTF_PCI = 0,
 275         INTF_USB = 1,
 276 };
 277
 278 enum radio_path {
 279         RF90_PATH_A = 0,
 280         RF90_PATH_B = 1,
 281         RF90_PATH_C = 2,
 282         RF90_PATH_D = 3,
 283 };
 284
 285 enum radio_mask {
 286         RF_MASK_A = BIT(0),
 287         RF_MASK_B = BIT(1),
 288         RF_MASK_C = BIT(2),
 289         RF_MASK_D = BIT(3),
 290 };
 291
 292 enum regulation_txpwr_lmt {
 293         TXPWR_LMT_FCC = 0,
 294         TXPWR_LMT_MKK = 1,
 295         TXPWR_LMT_ETSI = 2,
 296         TXPWR_LMT_WW = 3,
 297
 298         TXPWR_LMT_MAX_REGULATION_NUM = 4
 299 };
 300
 301 enum rt_eeprom_type {
 302         EEPROM_93C46,
 303         EEPROM_93C56,
 304         EEPROM_BOOT_EFUSE,
 305 };
 306
 307 enum ttl_status {
 308         RTL_STATUS_INTERFACE_START = 0,
 309 };
 310
 311 enum hardware_type {
 312         HARDWARE_TYPE_RTL8192E,
 313         HARDWARE_TYPE_RTL8192U,
 314         HARDWARE_TYPE_RTL8192SE,
 315         HARDWARE_TYPE_RTL8192SU,
 316         HARDWARE_TYPE_RTL8192CE,
 317         HARDWARE_TYPE_RTL8192CU,
 318         HARDWARE_TYPE_RTL8192DE,
 319         HARDWARE_TYPE_RTL8192DU,
 320         HARDWARE_TYPE_RTL8723AE,
 321         HARDWARE_TYPE_RTL8723U,
 322         HARDWARE_TYPE_RTL8188EE,
 323         HARDWARE_TYPE_RTL8723BE,
 324         HARDWARE_TYPE_RTL8192EE,
 325         HARDWARE_TYPE_RTL8821AE,
 326         HARDWARE_TYPE_RTL8812AE,
 327         HARDWARE_TYPE_RTL8822BE,
 328
 329         /* keep it last */
 330         HARDWARE_TYPE_NUM
 331 };
 332
 333 #define RTL_HW_TYPE(rtlpriv)    (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
 334 #define IS_NEW_GENERATION_IC(rtlpriv)                   \
 335                         (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
 336 #define IS_HARDWARE_TYPE_8192CE(rtlpriv)                \
 337                         (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
 338 #define IS_HARDWARE_TYPE_8812(rtlpriv)                  \
 339                         (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
 340 #define IS_HARDWARE_TYPE_8821(rtlpriv)                  \
 341                         (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
 342 #define IS_HARDWARE_TYPE_8723A(rtlpriv)                 \
 343                         (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
 344 #define IS_HARDWARE_TYPE_8723B(rtlpriv)                 \
 345                         (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
 346 #define IS_HARDWARE_TYPE_8192E(rtlpriv)                 \
 347                         (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
 348 #define IS_HARDWARE_TYPE_8822B(rtlpriv)                 \
 349                         (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
 350
 351 #define RX_HAL_IS_CCK_RATE(rxmcs)                       \
 352         ((rxmcs) == DESC_RATE1M ||                      \
 353          (rxmcs) == DESC_RATE2M ||                      \
 354          (rxmcs) == DESC_RATE5_5M ||                    \
 355          (rxmcs) == DESC_RATE11M)
 356
 357 enum scan_operation_backup_opt {
 358         SCAN_OPT_BACKUP = 0,
 359         SCAN_OPT_BACKUP_BAND0 = 0,
 360         SCAN_OPT_BACKUP_BAND1,
 361         SCAN_OPT_RESTORE,
 362         SCAN_OPT_MAX
 363 };
 364
 365 /*RF state.*/
 366 enum rf_pwrstate {
 367         ERFON,
 368         ERFSLEEP,
 369         ERFOFF
 370 };
 371
 372 struct bb_reg_def {
 373         u32 rfintfs;
 374         u32 rfintfi;
 375         u32 rfintfo;
 376         u32 rfintfe;
 377         u32 rf3wire_offset;
 378         u32 rflssi_select;
 379         u32 rftxgain_stage;
 380         u32 rfhssi_para1;
 381         u32 rfhssi_para2;
 382         u32 rfsw_ctrl;
 383         u32 rfagc_control1;
 384         u32 rfagc_control2;
 385         u32 rfrxiq_imbal;
 386         u32 rfrx_afe;
 387         u32 rftxiq_imbal;
 388         u32 rftx_afe;
 389         u32 rf_rb;              /* rflssi_readback */
 390         u32 rf_rbpi;            /* rflssi_readbackpi */
 391 };
 392
 393 enum io_type {
 394         IO_CMD_PAUSE_DM_BY_SCAN = 0,
 395         IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
 396         IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
 397         IO_CMD_RESUME_DM_BY_SCAN = 2,
 398 };
 399
 400 enum hw_variables {
 401         HW_VAR_ETHER_ADDR = 0x0,
 402         HW_VAR_MULTICAST_REG = 0x1,
 403         HW_VAR_BASIC_RATE = 0x2,
 404         HW_VAR_BSSID = 0x3,
 405         HW_VAR_MEDIA_STATUS = 0x4,
 406         HW_VAR_SECURITY_CONF = 0x5,
 407         HW_VAR_BEACON_INTERVAL = 0x6,
 408         HW_VAR_ATIM_WINDOW = 0x7,
 409         HW_VAR_LISTEN_INTERVAL = 0x8,
 410         HW_VAR_CS_COUNTER = 0x9,
 411         HW_VAR_DEFAULTKEY0 = 0xa,
 412         HW_VAR_DEFAULTKEY1 = 0xb,
 413         HW_VAR_DEFAULTKEY2 = 0xc,
 414         HW_VAR_DEFAULTKEY3 = 0xd,
 415         HW_VAR_SIFS = 0xe,
 416         HW_VAR_R2T_SIFS = 0xf,
 417         HW_VAR_DIFS = 0x10,
 418         HW_VAR_EIFS = 0x11,
 419         HW_VAR_SLOT_TIME = 0x12,
 420         HW_VAR_ACK_PREAMBLE = 0x13,
 421         HW_VAR_CW_CONFIG = 0x14,
 422         HW_VAR_CW_VALUES = 0x15,
 423         HW_VAR_RATE_FALLBACK_CONTROL = 0x16,
 424         HW_VAR_CONTENTION_WINDOW = 0x17,
 425         HW_VAR_RETRY_COUNT = 0x18,
 426         HW_VAR_TR_SWITCH = 0x19,
 427         HW_VAR_COMMAND = 0x1a,
 428         HW_VAR_WPA_CONFIG = 0x1b,
 429         HW_VAR_AMPDU_MIN_SPACE = 0x1c,
 430         HW_VAR_SHORTGI_DENSITY = 0x1d,
 431         HW_VAR_AMPDU_FACTOR = 0x1e,
 432         HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
 433         HW_VAR_AC_PARAM = 0x20,
 434         HW_VAR_ACM_CTRL = 0x21,
 435         HW_VAR_DIS_REQ_QSIZE = 0x22,
 436         HW_VAR_CCX_CHNL_LOAD = 0x23,
 437         HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
 438         HW_VAR_CCX_CLM_NHM = 0x25,
 439         HW_VAR_TXOPLIMIT = 0x26,
 440         HW_VAR_TURBO_MODE = 0x27,
 441         HW_VAR_RF_STATE = 0x28,
 442         HW_VAR_RF_OFF_BY_HW = 0x29,
 443         HW_VAR_BUS_SPEED = 0x2a,
 444         HW_VAR_SET_DEV_POWER = 0x2b,
 445
 446         HW_VAR_RCR = 0x2c,
 447         HW_VAR_RATR_0 = 0x2d,
 448         HW_VAR_RRSR = 0x2e,
 449         HW_VAR_CPU_RST = 0x2f,
 450         HW_VAR_CHECK_BSSID = 0x30,
 451         HW_VAR_LBK_MODE = 0x31,
 452         HW_VAR_AES_11N_FIX = 0x32,
 453         HW_VAR_USB_RX_AGGR = 0x33,
 454         HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
 455         HW_VAR_RETRY_LIMIT = 0x35,
 456         HW_VAR_INIT_TX_RATE = 0x36,
 457         HW_VAR_TX_RATE_REG = 0x37,
 458         HW_VAR_EFUSE_USAGE = 0x38,
 459         HW_VAR_EFUSE_BYTES = 0x39,
 460         HW_VAR_AUTOLOAD_STATUS = 0x3a,
 461         HW_VAR_RF_2R_DISABLE = 0x3b,
 462         HW_VAR_SET_RPWM = 0x3c,
 463         HW_VAR_H2C_FW_PWRMODE = 0x3d,
 464         HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
 465         HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
 466         HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
 467         HW_VAR_FW_PSMODE_STATUS = 0x41,
 468         HW_VAR_INIT_RTS_RATE = 0x42,
 469         HW_VAR_RESUME_CLK_ON = 0x43,
 470         HW_VAR_FW_LPS_ACTION = 0x44,
 471         HW_VAR_1X1_RECV_COMBINE = 0x45,
 472         HW_VAR_STOP_SEND_BEACON = 0x46,
 473         HW_VAR_TSF_TIMER = 0x47,
 474         HW_VAR_IO_CMD = 0x48,
 475
 476         HW_VAR_RF_RECOVERY = 0x49,
 477         HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
 478         HW_VAR_WF_MASK = 0x4b,
 479         HW_VAR_WF_CRC = 0x4c,
 480         HW_VAR_WF_IS_MAC_ADDR = 0x4d,
 481         HW_VAR_H2C_FW_OFFLOAD = 0x4e,
 482         HW_VAR_RESET_WFCRC = 0x4f,
 483
 484         HW_VAR_HANDLE_FW_C2H = 0x50,
 485         HW_VAR_DL_FW_RSVD_PAGE = 0x51,
 486         HW_VAR_AID = 0x52,
 487         HW_VAR_HW_SEQ_ENABLE = 0x53,
 488         HW_VAR_CORRECT_TSF = 0x54,
 489         HW_VAR_BCN_VALID = 0x55,
 490         HW_VAR_FWLPS_RF_ON = 0x56,
 491         HW_VAR_DUAL_TSF_RST = 0x57,
 492         HW_VAR_SWITCH_EPHY_WOWLAN = 0x58,
 493         HW_VAR_INT_MIGRATION = 0x59,
 494         HW_VAR_INT_AC = 0x5a,
 495         HW_VAR_RF_TIMING = 0x5b,
 496
 497         HAL_DEF_WOWLAN = 0x5c,
 498         HW_VAR_MRC = 0x5d,
 499         HW_VAR_KEEP_ALIVE = 0x5e,
 500         HW_VAR_NAV_UPPER = 0x5f,
 501
 502         HW_VAR_MGT_FILTER = 0x60,
 503         HW_VAR_CTRL_FILTER = 0x61,
 504         HW_VAR_DATA_FILTER = 0x62,
 505 };
 506
 507 enum rt_media_status {
 508         RT_MEDIA_DISCONNECT = 0,
 509         RT_MEDIA_CONNECT = 1
 510 };
 511
 512 enum rt_oem_id {
 513         RT_CID_DEFAULT = 0,
 514         RT_CID_8187_ALPHA0 = 1,
 515         RT_CID_8187_SERCOMM_PS = 2,
 516         RT_CID_8187_HW_LED = 3,
 517         RT_CID_8187_NETGEAR = 4,
 518         RT_CID_WHQL = 5,
 519         RT_CID_819X_CAMEO = 6,
 520         RT_CID_819X_RUNTOP = 7,
 521         RT_CID_819X_SENAO = 8,
 522         RT_CID_TOSHIBA = 9,
 523         RT_CID_819X_NETCORE = 10,
 524         RT_CID_NETTRONIX = 11,
 525         RT_CID_DLINK = 12,
 526         RT_CID_PRONET = 13,
 527         RT_CID_COREGA = 14,
 528         RT_CID_819X_ALPHA = 15,
 529         RT_CID_819X_SITECOM = 16,
 530         RT_CID_CCX = 17,
 531         RT_CID_819X_LENOVO = 18,
 532         RT_CID_819X_QMI = 19,
 533         RT_CID_819X_EDIMAX_BELKIN = 20,
 534         RT_CID_819X_SERCOMM_BELKIN = 21,
 535         RT_CID_819X_CAMEO1 = 22,
 536         RT_CID_819X_MSI = 23,
 537         RT_CID_819X_ACER = 24,
 538         RT_CID_819X_HP = 27,
 539         RT_CID_819X_CLEVO = 28,
 540         RT_CID_819X_ARCADYAN_BELKIN = 29,
 541         RT_CID_819X_SAMSUNG = 30,
 542         RT_CID_819X_WNC_COREGA = 31,
 543         RT_CID_819X_FOXCOON = 32,
 544         RT_CID_819X_DELL = 33,
 545         RT_CID_819X_PRONETS = 34,
 546         RT_CID_819X_EDIMAX_ASUS = 35,
 547         RT_CID_NETGEAR = 36,
 548         RT_CID_PLANEX = 37,
 549         RT_CID_CC_C = 38,
 550 };
 551
 552 enum hw_descs {
 553         HW_DESC_OWN,
 554         HW_DESC_RXOWN,
 555         HW_DESC_TX_NEXTDESC_ADDR,
 556         HW_DESC_TXBUFF_ADDR,
 557         HW_DESC_RXBUFF_ADDR,
 558         HW_DESC_RXPKT_LEN,
 559         HW_DESC_RXERO,
 560         HW_DESC_RX_PREPARE,
 561 };
 562
 563 enum prime_sc {
 564         PRIME_CHNL_OFFSET_DONT_CARE = 0,
 565         PRIME_CHNL_OFFSET_LOWER = 1,
 566         PRIME_CHNL_OFFSET_UPPER = 2,
 567 };
 568
 569 enum rf_type {
 570         RF_1T1R = 0,
 571         RF_1T2R = 1,
 572         RF_2T2R = 2,
 573         RF_2T2R_GREEN = 3,
 574         RF_2T3R = 4,
 575         RF_2T4R = 5,
 576         RF_3T3R = 6,
 577         RF_3T4R = 7,
 578         RF_4T4R = 8,
 579 };
 580
 581 enum ht_channel_width {
 582         HT_CHANNEL_WIDTH_20 = 0,
 583         HT_CHANNEL_WIDTH_20_40 = 1,
 584         HT_CHANNEL_WIDTH_80 = 2,
 585         HT_CHANNEL_WIDTH_MAX,
 586 };
 587
 588 /* Ref: 802.11i spec D10.0 7.3.2.25.1
 589  * Cipher Suites Encryption Algorithms
 590  */
 591 enum rt_enc_alg {
 592         NO_ENCRYPTION = 0,
 593         WEP40_ENCRYPTION = 1,
 594         TKIP_ENCRYPTION = 2,
 595         RSERVED_ENCRYPTION = 3,
 596         AESCCMP_ENCRYPTION = 4,
 597         WEP104_ENCRYPTION = 5,
 598         AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
 599 };
 600
 601 enum rtl_hal_state {
 602         _HAL_STATE_STOP = 0,
 603         _HAL_STATE_START = 1,
 604 };
 605
 606 enum rtl_desc_rate {
 607         DESC_RATE1M = 0x00,
 608         DESC_RATE2M = 0x01,
 609         DESC_RATE5_5M = 0x02,
 610         DESC_RATE11M = 0x03,
 611
 612         DESC_RATE6M = 0x04,
 613         DESC_RATE9M = 0x05,
 614         DESC_RATE12M = 0x06,
 615         DESC_RATE18M = 0x07,
 616         DESC_RATE24M = 0x08,
 617         DESC_RATE36M = 0x09,
 618         DESC_RATE48M = 0x0a,
 619         DESC_RATE54M = 0x0b,
 620
 621         DESC_RATEMCS0 = 0x0c,
 622         DESC_RATEMCS1 = 0x0d,
 623         DESC_RATEMCS2 = 0x0e,
 624         DESC_RATEMCS3 = 0x0f,
 625         DESC_RATEMCS4 = 0x10,
 626         DESC_RATEMCS5 = 0x11,
 627         DESC_RATEMCS6 = 0x12,
 628         DESC_RATEMCS7 = 0x13,
 629         DESC_RATEMCS8 = 0x14,
 630         DESC_RATEMCS9 = 0x15,
 631         DESC_RATEMCS10 = 0x16,
 632         DESC_RATEMCS11 = 0x17,
 633         DESC_RATEMCS12 = 0x18,
 634         DESC_RATEMCS13 = 0x19,
 635         DESC_RATEMCS14 = 0x1a,
 636         DESC_RATEMCS15 = 0x1b,
 637         DESC_RATEMCS15_SG = 0x1c,
 638         DESC_RATEMCS32 = 0x20,
 639
 640         DESC_RATEVHT1SS_MCS0 = 0x2c,
 641         DESC_RATEVHT1SS_MCS1 = 0x2d,
 642         DESC_RATEVHT1SS_MCS2 = 0x2e,
 643         DESC_RATEVHT1SS_MCS3 = 0x2f,
 644         DESC_RATEVHT1SS_MCS4 = 0x30,
 645         DESC_RATEVHT1SS_MCS5 = 0x31,
 646         DESC_RATEVHT1SS_MCS6 = 0x32,
 647         DESC_RATEVHT1SS_MCS7 = 0x33,
 648         DESC_RATEVHT1SS_MCS8 = 0x34,
 649         DESC_RATEVHT1SS_MCS9 = 0x35,
 650         DESC_RATEVHT2SS_MCS0 = 0x36,
 651         DESC_RATEVHT2SS_MCS1 = 0x37,
 652         DESC_RATEVHT2SS_MCS2 = 0x38,
 653         DESC_RATEVHT2SS_MCS3 = 0x39,
 654         DESC_RATEVHT2SS_MCS4 = 0x3a,
 655         DESC_RATEVHT2SS_MCS5 = 0x3b,
 656         DESC_RATEVHT2SS_MCS6 = 0x3c,
 657         DESC_RATEVHT2SS_MCS7 = 0x3d,
 658         DESC_RATEVHT2SS_MCS8 = 0x3e,
 659         DESC_RATEVHT2SS_MCS9 = 0x3f,
 660 };
 661
 662 enum rtl_var_map {
 663         /*reg map */
 664         SYS_ISO_CTRL = 0,
 665         SYS_FUNC_EN,
 666         SYS_CLK,
 667         MAC_RCR_AM,
 668         MAC_RCR_AB,
 669         MAC_RCR_ACRC32,
 670         MAC_RCR_ACF,
 671         MAC_RCR_AAP,
 672         MAC_HIMR,
 673         MAC_HIMRE,
 674         MAC_HSISR,
 675
 676         /*efuse map */
 677         EFUSE_TEST,
 678         EFUSE_CTRL,
 679         EFUSE_CLK,
 680         EFUSE_CLK_CTRL,
 681         EFUSE_PWC_EV12V,
 682         EFUSE_FEN_ELDR,
 683         EFUSE_LOADER_CLK_EN,
 684         EFUSE_ANA8M,
 685         EFUSE_HWSET_MAX_SIZE,
 686         EFUSE_MAX_SECTION_MAP,
 687         EFUSE_REAL_CONTENT_SIZE,
 688         EFUSE_OOB_PROTECT_BYTES_LEN,
 689         EFUSE_ACCESS,
 690
 691         /*CAM map */
 692         RWCAM,
 693         WCAMI,
 694         RCAMO,
 695         CAMDBG,
 696         SECR,
 697         SEC_CAM_NONE,
 698         SEC_CAM_WEP40,
 699         SEC_CAM_TKIP,
 700         SEC_CAM_AES,
 701         SEC_CAM_WEP104,
 702
 703         /*IMR map */
 704         RTL_IMR_BCNDMAINT6,     /*Beacon DMA Interrupt 6 */
 705         RTL_IMR_BCNDMAINT5,     /*Beacon DMA Interrupt 5 */
 706         RTL_IMR_BCNDMAINT4,     /*Beacon DMA Interrupt 4 */
 707         RTL_IMR_BCNDMAINT3,     /*Beacon DMA Interrupt 3 */
 708         RTL_IMR_BCNDMAINT2,     /*Beacon DMA Interrupt 2 */
 709         RTL_IMR_BCNDMAINT1,     /*Beacon DMA Interrupt 1 */
 710         RTL_IMR_BCNDOK8,        /*Beacon Queue DMA OK Interrupt 8 */
 711         RTL_IMR_BCNDOK7,        /*Beacon Queue DMA OK Interrupt 7 */
 712         RTL_IMR_BCNDOK6,        /*Beacon Queue DMA OK Interrupt 6 */
 713         RTL_IMR_BCNDOK5,        /*Beacon Queue DMA OK Interrupt 5 */
 714         RTL_IMR_BCNDOK4,        /*Beacon Queue DMA OK Interrupt 4 */
 715         RTL_IMR_BCNDOK3,        /*Beacon Queue DMA OK Interrupt 3 */
 716         RTL_IMR_BCNDOK2,        /*Beacon Queue DMA OK Interrupt 2 */
 717         RTL_IMR_BCNDOK1,        /*Beacon Queue DMA OK Interrupt 1 */
 718         RTL_IMR_TIMEOUT2,       /*Timeout interrupt 2 */
 719         RTL_IMR_TIMEOUT1,       /*Timeout interrupt 1 */
 720         RTL_IMR_TXFOVW,         /*Transmit FIFO Overflow */
 721         RTL_IMR_PSTIMEOUT,      /*Power save time out interrupt */
 722         RTL_IMR_BCNINT,         /*Beacon DMA Interrupt 0 */
 723         RTL_IMR_RXFOVW,         /*Receive FIFO Overflow */
 724         RTL_IMR_RDU,            /*Receive Descriptor Unavailable */
 725         RTL_IMR_ATIMEND,        /*For 92C,ATIM Window End Interrupt */
 726         RTL_IMR_H2CDOK,         /*H2C Queue DMA OK Interrupt */
 727         RTL_IMR_BDOK,           /*Beacon Queue DMA OK Interrupt */
 728         RTL_IMR_HIGHDOK,        /*High Queue DMA OK Interrupt */
 729         RTL_IMR_COMDOK,         /*Command Queue DMA OK Interrupt*/
 730         RTL_IMR_TBDOK,          /*Transmit Beacon OK interrupt */
 731         RTL_IMR_MGNTDOK,        /*Management Queue DMA OK Interrupt */
 732         RTL_IMR_TBDER,          /*For 92C,Transmit Beacon Error Interrupt */
 733         RTL_IMR_BKDOK,          /*AC_BK DMA OK Interrupt */
 734         RTL_IMR_BEDOK,          /*AC_BE DMA OK Interrupt */
 735         RTL_IMR_VIDOK,          /*AC_VI DMA OK Interrupt */
 736         RTL_IMR_VODOK,          /*AC_VO DMA Interrupt */
 737         RTL_IMR_ROK,            /*Receive DMA OK Interrupt */
 738         RTL_IMR_HSISR_IND,      /*HSISR Interrupt*/
 739         RTL_IBSS_INT_MASKS,     /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
 740                                  * RTL_IMR_TBDER)
 741                                  */
 742         RTL_IMR_C2HCMD,         /*fw interrupt*/
 743
 744         /*CCK Rates, TxHT = 0 */
 745         RTL_RC_CCK_RATE1M,
 746         RTL_RC_CCK_RATE2M,
 747         RTL_RC_CCK_RATE5_5M,
 748         RTL_RC_CCK_RATE11M,
 749
 750         /*OFDM Rates, TxHT = 0 */
 751         RTL_RC_OFDM_RATE6M,
 752         RTL_RC_OFDM_RATE9M,
 753         RTL_RC_OFDM_RATE12M,
 754         RTL_RC_OFDM_RATE18M,
 755         RTL_RC_OFDM_RATE24M,
 756         RTL_RC_OFDM_RATE36M,
 757         RTL_RC_OFDM_RATE48M,
 758         RTL_RC_OFDM_RATE54M,
 759
 760         RTL_RC_HT_RATEMCS7,
 761         RTL_RC_HT_RATEMCS15,
 762
 763         RTL_RC_VHT_RATE_1SS_MCS7,
 764         RTL_RC_VHT_RATE_1SS_MCS8,
 765         RTL_RC_VHT_RATE_1SS_MCS9,
 766         RTL_RC_VHT_RATE_2SS_MCS7,
 767         RTL_RC_VHT_RATE_2SS_MCS8,
 768         RTL_RC_VHT_RATE_2SS_MCS9,
 769
 770         /*keep it last */
 771         RTL_VAR_MAP_MAX,
 772 };
 773
 774 /*Firmware PS mode for control LPS.*/
 775 enum _fw_ps_mode {
 776         FW_PS_ACTIVE_MODE = 0,
 777         FW_PS_MIN_MODE = 1,
 778         FW_PS_MAX_MODE = 2,
 779         FW_PS_DTIM_MODE = 3,
 780         FW_PS_VOIP_MODE = 4,
 781         FW_PS_UAPSD_WMM_MODE = 5,
 782         FW_PS_UAPSD_MODE = 6,
 783         FW_PS_IBSS_MODE = 7,
 784         FW_PS_WWLAN_MODE = 8,
 785         FW_PS_PM_RADIO_OFF = 9,
 786         FW_PS_PM_CARD_DISABLE = 10,
 787 };
 788
 789 enum rt_psmode {
 790         EACTIVE,                /*Active/Continuous access. */
 791         EMAXPS,                 /*Max power save mode. */
 792         EFASTPS,                /*Fast power save mode. */
 793         EAUTOPS,                /*Auto power save mode. */
 794 };
 795
 796 /*LED related.*/
 797 enum led_ctl_mode {
 798         LED_CTL_POWER_ON = 1,
 799         LED_CTL_LINK = 2,
 800         LED_CTL_NO_LINK = 3,
 801         LED_CTL_TX = 4,
 802         LED_CTL_RX = 5,
 803         LED_CTL_SITE_SURVEY = 6,
 804         LED_CTL_POWER_OFF = 7,
 805         LED_CTL_START_TO_LINK = 8,
 806         LED_CTL_START_WPS = 9,
 807         LED_CTL_STOP_WPS = 10,
 808 };
 809
 810 enum rtl_led_pin {
 811         LED_PIN_GPIO0,
 812         LED_PIN_LED0,
 813         LED_PIN_LED1,
 814         LED_PIN_LED2
 815 };
 816
 817 /* QoS related.*/
 818 /* acm implementation method.*/
 819 enum acm_method {
 820         EACMWAY0_SWANDHW = 0,
 821         EACMWAY1_HW = 1,
 822         EACMWAY2_SW = 2,
 823 };
 824
 825 enum macphy_mode {
 826         SINGLEMAC_SINGLEPHY = 0,
 827         DUALMAC_DUALPHY,
 828         DUALMAC_SINGLEPHY,
 829 };
 830
 831 enum band_type {
 832         BAND_ON_2_4G = 0,
 833         BAND_ON_5G,
 834         BAND_ON_BOTH,
 835         BANDMAX
 836 };
 837
 838 /* aci/aifsn Field.
 839  * Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
 840  */
 841 union aci_aifsn {
 842         u8 char_data;
 843
 844         struct {
 845                 u8 aifsn:4;
 846                 u8 acm:1;
 847                 u8 aci:2;
 848                 u8 reserved:1;
 849         } f;                    /* Field */
 850 };
 851
 852 /*mlme related.*/
 853 enum wireless_mode {
 854         WIRELESS_MODE_UNKNOWN = 0x00,
 855         WIRELESS_MODE_A = 0x01,
 856         WIRELESS_MODE_B = 0x02,
 857         WIRELESS_MODE_G = 0x04,
 858         WIRELESS_MODE_AUTO = 0x08,
 859         WIRELESS_MODE_N_24G = 0x10,
 860         WIRELESS_MODE_N_5G = 0x20,
 861         WIRELESS_MODE_AC_5G = 0x40,
 862         WIRELESS_MODE_AC_24G  = 0x80,
 863         WIRELESS_MODE_AC_ONLY = 0x100,
 864         WIRELESS_MODE_MAX = 0x800
 865 };
 866
 867 #define IS_WIRELESS_MODE_A(wirelessmode)        \
 868         (wirelessmode == WIRELESS_MODE_A)
 869 #define IS_WIRELESS_MODE_B(wirelessmode)        \
 870         (wirelessmode == WIRELESS_MODE_B)
 871 #define IS_WIRELESS_MODE_G(wirelessmode)        \
 872         (wirelessmode == WIRELESS_MODE_G)
 873 #define IS_WIRELESS_MODE_N_24G(wirelessmode)    \
 874         (wirelessmode == WIRELESS_MODE_N_24G)
 875 #define IS_WIRELESS_MODE_N_5G(wirelessmode)     \
 876         (wirelessmode == WIRELESS_MODE_N_5G)
 877
 878 enum ratr_table_mode {
 879         RATR_INX_WIRELESS_NGB = 0,
 880         RATR_INX_WIRELESS_NG = 1,
 881         RATR_INX_WIRELESS_NB = 2,
 882         RATR_INX_WIRELESS_N = 3,
 883         RATR_INX_WIRELESS_GB = 4,
 884         RATR_INX_WIRELESS_G = 5,
 885         RATR_INX_WIRELESS_B = 6,
 886         RATR_INX_WIRELESS_MC = 7,
 887         RATR_INX_WIRELESS_A = 8,
 888         RATR_INX_WIRELESS_AC_5N = 8,
 889         RATR_INX_WIRELESS_AC_24N = 9,
 890 };
 891
 892 enum ratr_table_mode_new {
 893         RATEID_IDX_BGN_40M_2SS = 0,
 894         RATEID_IDX_BGN_40M_1SS = 1,
 895         RATEID_IDX_BGN_20M_2SS_BN = 2,
 896         RATEID_IDX_BGN_20M_1SS_BN = 3,
 897         RATEID_IDX_GN_N2SS = 4,
 898         RATEID_IDX_GN_N1SS = 5,
 899         RATEID_IDX_BG = 6,
 900         RATEID_IDX_G = 7,
 901         RATEID_IDX_B = 8,
 902         RATEID_IDX_VHT_2SS = 9,
 903         RATEID_IDX_VHT_1SS = 10,
 904         RATEID_IDX_MIX1 = 11,
 905         RATEID_IDX_MIX2 = 12,
 906         RATEID_IDX_VHT_3SS = 13,
 907         RATEID_IDX_BGN_3SS = 14,
 908 };
 909
 910 enum rtl_link_state {
 911         MAC80211_NOLINK = 0,
 912         MAC80211_LINKING = 1,
 913         MAC80211_LINKED = 2,
 914         MAC80211_LINKED_SCANNING = 3,
 915 };
 916
 917 enum act_category {
 918         ACT_CAT_QOS = 1,
 919         ACT_CAT_DLS = 2,
 920         ACT_CAT_BA = 3,
 921         ACT_CAT_HT = 7,
 922         ACT_CAT_WMM = 17,
 923 };
 924
 925 enum ba_action {
 926         ACT_ADDBAREQ = 0,
 927         ACT_ADDBARSP = 1,
 928         ACT_DELBA = 2,
 929 };
 930
 931 enum rt_polarity_ctl {
 932         RT_POLARITY_LOW_ACT = 0,
 933         RT_POLARITY_HIGH_ACT = 1,
 934 };
 935
 936 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
 937 enum fw_wow_reason_v2 {
 938         FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
 939         FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
 940         FW_WOW_V2_DISASSOC_EVENT = 0x04,
 941         FW_WOW_V2_DEAUTH_EVENT = 0x08,
 942         FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
 943         FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
 944         FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
 945         FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
 946         FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
 947         FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
 948         FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
 949         FW_WOW_V2_REASON_MAX = 0xff,
 950 };
 951
 952 enum wolpattern_type {
 953         UNICAST_PATTERN = 0,
 954         MULTICAST_PATTERN = 1,
 955         BROADCAST_PATTERN = 2,
 956         DONT_CARE_DA = 3,
 957         UNKNOWN_TYPE = 4,
 958 };
 959
 960 enum package_type {
 961         PACKAGE_DEFAULT,
 962         PACKAGE_QFN68,
 963         PACKAGE_TFBGA90,
 964         PACKAGE_TFBGA80,
 965         PACKAGE_TFBGA79
 966 };
 967
 968 enum rtl_spec_ver {
 969         RTL_SPEC_NEW_RATEID = BIT(0),   /* use ratr_table_mode_new */
 970         RTL_SPEC_SUPPORT_VHT = BIT(1),  /* support VHT */
 971         RTL_SPEC_NEW_FW_C2H = BIT(2),   /* new FW C2H (e.g. TX REPORT) */
 972 };
 973
 974 struct octet_string {
 975         u8 *octet;
 976         u16 length;
 977 };
 978
 979 struct rtl_hdr_3addr {
 980         __le16 frame_ctl;
 981         __le16 duration_id;
 982         u8 addr1[ETH_ALEN];
 983         u8 addr2[ETH_ALEN];
 984         u8 addr3[ETH_ALEN];
 985         __le16 seq_ctl;
 986         u8 payload[0];
 987 } __packed;
 988
 989 struct rtl_info_element {
 990         u8 id;
 991         u8 len;
 992         u8 data[0];
 993 } __packed;
 994
 995 struct rtl_probe_rsp {
 996         struct rtl_hdr_3addr header;
 997         u32 time_stamp[2];
 998         __le16 beacon_interval;
 999         __le16 capability;
1000         /* SSID, supported rates, FH params, DS params,
1001          * CF params, IBSS params, TIM (if beacon), RSN
1002          */
1003         struct rtl_info_element info_element[0];
1004 } __packed;
1005
1006 struct rtl_beacon_keys {
1007         /*u8 ssid[32];*/
1008         /*u32 ssid_len;*/
1009         u8 bcn_channel;
1010         __le16 ht_cap_info;
1011         u8 ht_info_infos_0_sco; /* bit0 & bit1 in infos[0] is 2nd ch offset */
1012         bool valid;
1013 };
1014
1015 /*LED related.*/
1016 /*ledpin Identify how to implement this SW led.*/
1017 struct rtl_led {
1018         void *hw;
1019         enum rtl_led_pin ledpin;
1020         bool ledon;
1021 };
1022
1023 struct rtl_led_ctl {
1024         bool led_opendrain;
1025         struct rtl_led sw_led0;
1026         struct rtl_led sw_led1;
1027 };
1028
1029 struct rtl_qos_parameters {
1030         __le16 cw_min;
1031         __le16 cw_max;
1032         u8 aifs;
1033         u8 flag;
1034         __le16 tx_op;
1035 } __packed;
1036
1037 struct rt_smooth_data {
1038         u32 elements[100];      /*array to store values */
1039         u32 index;              /*index to current array to store */
1040         u32 total_num;          /*num of valid elements */
1041         u32 total_val;          /*sum of valid elements */
1042 };
1043
1044 struct false_alarm_statistics {
1045         u32 cnt_parity_fail;
1046         u32 cnt_rate_illegal;
1047         u32 cnt_crc8_fail;
1048         u32 cnt_mcs_fail;
1049         u32 cnt_fast_fsync_fail;
1050         u32 cnt_sb_search_fail;
1051         u32 cnt_ofdm_fail;
1052         u32 cnt_cck_fail;
1053         u32 cnt_all;
1054         u32 cnt_ofdm_cca;
1055         u32 cnt_cck_cca;
1056         u32 cnt_cca_all;
1057         u32 cnt_bw_usc;
1058         u32 cnt_bw_lsc;
1059 };
1060
1061 struct init_gain {
1062         u8 xaagccore1;
1063         u8 xbagccore1;
1064         u8 xcagccore1;
1065         u8 xdagccore1;
1066         u8 cca;
1067
1068 };
1069
1070 struct wireless_stats {
1071         u64 txbytesunicast;
1072         u64 txbytesmulticast;
1073         u64 txbytesbroadcast;
1074         u64 rxbytesunicast;
1075
1076         u64 txbytesunicast_inperiod;
1077         u64 rxbytesunicast_inperiod;
1078         u32 txbytesunicast_inperiod_tp;
1079         u32 rxbytesunicast_inperiod_tp;
1080         u64 txbytesunicast_last;
1081         u64 rxbytesunicast_last;
1082
1083         long rx_snr_db[4];
1084         /* Correct smoothed ss in Dbm, only used
1085          * in driver to report real power now.
1086          */
1087         long recv_signal_power;
1088         long signal_quality;
1089         long last_sigstrength_inpercent;
1090
1091         u32 rssi_calculate_cnt;
1092         u32 pwdb_all_cnt;
1093
1094         /* Transformed, in dbm. Beautified signal
1095          * strength for UI, not correct.
1096          */
1097         long signal_strength;
1098
1099         u8 rx_rssi_percentage[4];
1100         u8 rx_evm_dbm[4];
1101         u8 rx_evm_percentage[2];
1102
1103         u16 rx_cfo_short[4];
1104         u16 rx_cfo_tail[4];
1105
1106         struct rt_smooth_data ui_rssi;
1107         struct rt_smooth_data ui_link_quality;
1108 };
1109
1110 struct rate_adaptive {
1111         u8 rate_adaptive_disabled;
1112         u8 ratr_state;
1113         u16 reserve;
1114
1115         u32 high_rssi_thresh_for_ra;
1116         u32 high2low_rssi_thresh_for_ra;
1117         u8 low2high_rssi_thresh_for_ra40m;
1118         u32 low_rssi_thresh_for_ra40m;
1119         u8 low2high_rssi_thresh_for_ra20m;
1120         u32 low_rssi_thresh_for_ra20m;
1121         u32 upper_rssi_threshold_ratr;
1122         u32 middleupper_rssi_threshold_ratr;
1123         u32 middle_rssi_threshold_ratr;
1124         u32 middlelow_rssi_threshold_ratr;
1125         u32 low_rssi_threshold_ratr;
1126         u32 ultralow_rssi_threshold_ratr;
1127         u32 low_rssi_threshold_ratr_40m;
1128         u32 low_rssi_threshold_ratr_20m;
1129         u8 ping_rssi_enable;
1130         u32 ping_rssi_ratr;
1131         u32 ping_rssi_thresh_for_ra;
1132         u32 last_ratr;
1133         u8 pre_ratr_state;
1134         u8 ldpc_thres;
1135         bool use_ldpc;
1136         bool lower_rts_rate;
1137         bool is_special_data;
1138 };
1139
1140 struct regd_pair_mapping {
1141         u16 reg_dmnenum;
1142         u16 reg_5ghz_ctl;
1143         u16 reg_2ghz_ctl;
1144 };
1145
1146 struct dynamic_primary_cca {
1147         u8 pricca_flag;
1148         u8 intf_flag;
1149         u8 intf_type;
1150         u8 dup_rts_flag;
1151         u8 monitor_flag;
1152         u8 ch_offset;
1153         u8 mf_state;
1154 };
1155
1156 struct rtl_regulatory {
1157         s8 alpha2[2];
1158         u16 country_code;
1159         u16 max_power_level;
1160         u32 tp_scale;
1161         u16 current_rd;
1162         u16 current_rd_ext;
1163         s16 power_limit;
1164         struct regd_pair_mapping *regpair;
1165 };
1166
1167 struct rtl_rfkill {
1168         bool rfkill_state;      /*0 is off, 1 is on */
1169 };
1170
1171 /*for P2P PS**/
1172 #define P2P_MAX_NOA_NUM         2
1173
1174 enum p2p_role {
1175         P2P_ROLE_DISABLE = 0,
1176         P2P_ROLE_DEVICE = 1,
1177         P2P_ROLE_CLIENT = 2,
1178         P2P_ROLE_GO = 3
1179 };
1180
1181 enum p2p_ps_state {
1182         P2P_PS_DISABLE = 0,
1183         P2P_PS_ENABLE = 1,
1184         P2P_PS_SCAN = 2,
1185         P2P_PS_SCAN_DONE = 3,
1186         P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1187 };
1188
1189 enum p2p_ps_mode {
1190         P2P_PS_NONE = 0,
1191         P2P_PS_CTWINDOW = 1,
1192         P2P_PS_NOA       = 2,
1193         P2P_PS_MIX = 3, /* CTWindow and NoA */
1194 };
1195
1196 struct rtl_p2p_ps_info {
1197         enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1198         enum p2p_ps_state p2p_ps_state; /*  indicate p2p ps state */
1199         u8 noa_index; /*  Identifies instance of Notice of Absence timing. */
1200         /*  Client traffic window. A period of time in TU after TBTT. */
1201         u8 ctwindow;
1202         u8 opp_ps; /*  opportunistic power save. */
1203         u8 noa_num; /*  number of NoA descriptor in P2P IE. */
1204         /*  Count for owner, Type of client. */
1205         u8 noa_count_type[P2P_MAX_NOA_NUM];
1206         /*  Max duration for owner, preferred or min acceptable duration
1207          * for client.
1208          */
1209         u32 noa_duration[P2P_MAX_NOA_NUM];
1210         /*  Length of interval for owner, preferred or max acceptable intervali
1211          * of client.
1212          */
1213         u32 noa_interval[P2P_MAX_NOA_NUM];
1214         /*  schedule in terms of the lower 4 bytes of the TSF timer. */
1215         u32 noa_start_time[P2P_MAX_NOA_NUM];
1216 };
1217
1218 struct p2p_ps_offload_t {
1219         u8 offload_en:1;
1220         u8 role:1; /* 1: Owner, 0: Client */
1221         u8 ctwindow_en:1;
1222         u8 noa0_en:1;
1223         u8 noa1_en:1;
1224         u8 allstasleep:1;
1225         u8 discovery:1;
1226         u8 reserved:1;
1227 };
1228
1229 #define IQK_MATRIX_REG_NUM      8
1230 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1231
1232 struct iqk_matrix_regs {
1233         bool iqk_done;
1234         long value[1][IQK_MATRIX_REG_NUM];
1235 };
1236
1237 struct phy_parameters {
1238         u16 length;
1239         u32 *pdata;
1240 };
1241
1242 enum hw_param_tab_index {
1243         PHY_REG_2T,
1244         PHY_REG_1T,
1245         PHY_REG_PG,
1246         RADIOA_2T,
1247         RADIOB_2T,
1248         RADIOA_1T,
1249         RADIOB_1T,
1250         MAC_REG,
1251         AGCTAB_2T,
1252         AGCTAB_1T,
1253         MAX_TAB
1254 };
1255
1256 struct rtl_phy {
1257         struct bb_reg_def phyreg_def[4];        /*Radio A/B/C/D */
1258         struct init_gain initgain_backup;
1259         enum io_type current_io_type;
1260
1261         u8 rf_mode;
1262         u8 rf_type;
1263         u8 current_chan_bw;
1264         u8 max_ht_chan_bw;
1265         u8 max_vht_chan_bw;
1266         u8 set_bwmode_inprogress;
1267         u8 sw_chnl_inprogress;
1268         u8 sw_chnl_stage;
1269         u8 sw_chnl_step;
1270         u8 current_channel;
1271         u8 h2c_box_num;
1272         u8 set_io_inprogress;
1273         u8 lck_inprogress;
1274
1275         /* record for power tracking */
1276         s32 reg_e94;
1277         s32 reg_e9c;
1278         s32 reg_ea4;
1279         s32 reg_eac;
1280         s32 reg_eb4;
1281         s32 reg_ebc;
1282         s32 reg_ec4;
1283         s32 reg_ecc;
1284         u8 rfpienable;
1285         u8 reserve_0;
1286         u16 reserve_1;
1287         u32 reg_c04, reg_c08, reg_874;
1288         u32 adda_backup[16];
1289         u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1290         u32 iqk_bb_backup[10];
1291         bool iqk_initialized;
1292
1293         bool rfpath_rx_enable[MAX_RF_PATH];
1294         u8 reg_837;
1295         /* Dual mac */
1296         bool need_iqk;
1297         struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1298
1299         bool rfpi_enable;
1300         bool iqk_in_progress;
1301
1302         u8 pwrgroup_cnt;
1303         u8 cck_high_power;
1304         /* this is for 88E & 8723A */
1305         u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1306         /* MAX_PG_GROUP groups of pwr diff by rates */
1307         u32 mcs_offset[MAX_PG_GROUP][16];
1308         u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1309                                    [TX_PWR_BY_RATE_NUM_RF]
1310                                    [TX_PWR_BY_RATE_NUM_RF]
1311                                    [TX_PWR_BY_RATE_NUM_RATE];
1312         /* compatible with TX_PWR_BY_RATE_NUM_SECTION*/
1313         u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1314                                  [TX_PWR_BY_RATE_NUM_RF]
1315                                  [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1316         u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1317                                 [TX_PWR_BY_RATE_NUM_RF]
1318                                 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1319         u8 default_initialgain[4];
1320
1321         /* the current Tx power level */
1322         u8 cur_cck_txpwridx;
1323         u8 cur_ofdm24g_txpwridx;
1324         u8 cur_bw20_txpwridx;
1325         u8 cur_bw40_txpwridx;
1326
1327         s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1328                            [MAX_2_4G_BANDWIDTH_NUM]
1329                            [MAX_RATE_SECTION_NUM]
1330                            [CHANNEL_MAX_NUMBER_2G]
1331                            [MAX_RF_PATH_NUM];
1332         s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1333                          [MAX_5G_BANDWIDTH_NUM]
1334                          [MAX_RATE_SECTION_NUM]
1335                          [CHANNEL_MAX_NUMBER_5G]
1336                          [MAX_RF_PATH_NUM];
1337
1338         u32 rfreg_chnlval[2];
1339         bool apk_done;
1340         u32 reg_rf3c[2];        /* pathA / pathB  */
1341
1342         u32 backup_rf_0x1a;/*92ee*/
1343         /* bfsync */
1344         u8 framesync;
1345         u32 framesync_c34;
1346
1347         u8 num_total_rfpath;
1348         struct phy_parameters hwparam_tables[MAX_TAB];
1349         u16 rf_pathmap;
1350
1351         u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1352         enum rt_polarity_ctl polarity_ctl;
1353 };
1354
1355 #define MAX_TID_COUNT                           9
1356 #define RTL_AGG_STOP                            0
1357 #define RTL_AGG_PROGRESS                        1
1358 #define RTL_AGG_START                           2
1359 #define RTL_AGG_OPERATIONAL                     3
1360 #define RTL_AGG_OFF                             0
1361 #define RTL_AGG_ON                              1
1362 #define RTL_RX_AGG_START                        1
1363 #define RTL_RX_AGG_STOP                         0
1364 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA         2
1365 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA         3
1366
1367 struct rtl_ht_agg {
1368         u16 txq_id;
1369         u16 wait_for_ba;
1370         u16 start_idx;
1371         u64 bitmap;
1372         u32 rate_n_flags;
1373         u8 agg_state;
1374         u8 rx_agg_state;
1375 };
1376
1377 struct rssi_sta {
1378         /* for old dm */
1379         long undec_sm_pwdb;
1380         long undec_sm_cck;
1381
1382         /* for new phydm_mod */
1383         s32 undecorated_smoothed_pwdb;
1384         s32 undecorated_smoothed_cck;
1385         s32 undecorated_smoothed_ofdm;
1386         u8 ofdm_pkt;
1387         u8 cck_pkt;
1388         u16 cck_sum_power;
1389         u8 is_send_rssi;
1390         u64 packet_map;
1391         u8 valid_bit;
1392 };
1393
1394 struct rtl_tid_data {
1395         u16 seq_number;
1396         struct rtl_ht_agg agg;
1397 };
1398
1399 struct rtl_sta_info {
1400         struct list_head list;
1401         struct rtl_tid_data tids[MAX_TID_COUNT];
1402         /* just used for ap adhoc or mesh*/
1403         struct rssi_sta rssi_stat;
1404         u8 rssi_level;
1405         u16 wireless_mode;
1406         u8 ratr_index;
1407         u8 mimo_ps;
1408         u8 mac_addr[ETH_ALEN];
1409 } __packed;
1410
1411 struct rtl_priv;
1412 struct rtl_io {
1413         struct device *dev;
1414         struct mutex bb_mutex;
1415
1416         /*PCI MEM map */
1417         unsigned long pci_mem_end;      /*shared mem end        */
1418         unsigned long pci_mem_start;    /*shared mem start */
1419
1420         /*PCI IO map */
1421         unsigned long pci_base_addr;    /*device I/O address */
1422
1423         void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
1424         void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
1425         void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
1426         void (*writeN_sync)(struct rtl_priv *rtlpriv, u32 addr, void *buf,
1427                             u16 len);
1428
1429         u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr);
1430         u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr);
1431         u32 (*read32_sync)(struct rtl_priv *rtlpriv, u32 addr);
1432
1433 };
1434
1435 struct rtl_mac {
1436         u8 mac_addr[ETH_ALEN];
1437         u8 mac80211_registered;
1438         u8 beacon_enabled;
1439
1440         u32 tx_ss_num;
1441         u32 rx_ss_num;
1442
1443         struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1444         struct ieee80211_hw *hw;
1445         struct ieee80211_vif *vif;
1446         enum nl80211_iftype opmode;
1447
1448         /*Probe Beacon management */
1449         struct rtl_tid_data tids[MAX_TID_COUNT];
1450         enum rtl_link_state link_state;
1451         struct rtl_beacon_keys cur_beacon_keys;
1452         u8 new_beacon_cnt;
1453
1454         int n_channels;
1455         int n_bitrates;
1456
1457         bool offchan_delay;
1458         u8 p2p; /*using p2p role*/
1459         bool p2p_in_use;
1460
1461         /*filters */
1462         u32 rx_conf;
1463         u16 rx_mgt_filter;
1464         u16 rx_ctrl_filter;
1465         u16 rx_data_filter;
1466
1467         bool act_scanning;
1468         u8 cnt_after_linked;
1469         bool skip_scan;
1470
1471         /* early mode */
1472         /* skb wait queue */
1473         struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1474
1475         u8 ht_stbc_cap;
1476         u8 ht_cur_stbc;
1477
1478         /*vht support*/
1479         u8 vht_enable;
1480         u8 bw_80;
1481         u8 vht_cur_ldpc;
1482         u8 vht_cur_stbc;
1483         u8 vht_stbc_cap;
1484         u8 vht_ldpc_cap;
1485
1486         /*RDG*/
1487         bool rdg_en;
1488
1489         /*AP*/
1490         u8 bssid[ETH_ALEN] __aligned(2);
1491         u32 vendor;
1492         u8 mcs[16];     /* 16 bytes mcs for HT rates. */
1493         u32 basic_rates; /* b/g rates */
1494         u8 ht_enable;
1495         u8 sgi_40;
1496         u8 sgi_20;
1497         u8 bw_40;
1498         u16 mode;               /* wireless mode */
1499         u8 slot_time;
1500         u8 short_preamble;
1501         u8 use_cts_protect;
1502         u8 cur_40_prime_sc;
1503         u8 cur_40_prime_sc_bk;
1504         u8 cur_80_prime_sc;
1505         u64 tsf;
1506         u8 retry_short;
1507         u8 retry_long;
1508         u16 assoc_id;
1509         bool hiddenssid;
1510
1511         /*IBSS*/
1512         int beacon_interval;
1513
1514         /*AMPDU*/
1515         u8 min_space_cfg;       /*For Min spacing configurations */
1516         u8 max_mss_density;
1517         u8 current_ampdu_factor;
1518         u8 current_ampdu_density;
1519
1520         /*QOS & EDCA */
1521         struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1522         struct rtl_qos_parameters ac[AC_MAX];
1523
1524         /* counters */
1525         u64 last_txok_cnt;
1526         u64 last_rxok_cnt;
1527         u32 last_bt_edca_ul;
1528         u32 last_bt_edca_dl;
1529 };
1530
1531 struct btdm_8723 {
1532         bool all_off;
1533         bool agc_table_en;
1534         bool adc_back_off_on;
1535         bool b2_ant_hid_en;
1536         bool low_penalty_rate_adaptive;
1537         bool rf_rx_lpf_shrink;
1538         bool reject_aggre_pkt;
1539         bool tra_tdma_on;
1540         u8 tra_tdma_nav;
1541         u8 tra_tdma_ant;
1542         bool tdma_on;
1543         u8 tdma_ant;
1544         u8 tdma_nav;
1545         u8 tdma_dac_swing;
1546         u8 fw_dac_swing_lvl;
1547         bool ps_tdma_on;
1548         u8 ps_tdma_byte[5];
1549         bool pta_on;
1550         u32 val_0x6c0;
1551         u32 val_0x6c8;
1552         u32 val_0x6cc;
1553         bool sw_dac_swing_on;
1554         u32 sw_dac_swing_lvl;
1555         u32 wlan_act_hi;
1556         u32 wlan_act_lo;
1557         u32 bt_retry_index;
1558         bool dec_bt_pwr;
1559         bool ignore_wlan_act;
1560 };
1561
1562 struct bt_coexist_8723 {
1563         u32 high_priority_tx;
1564         u32 high_priority_rx;
1565         u32 low_priority_tx;
1566         u32 low_priority_rx;
1567         u8 c2h_bt_info;
1568         bool c2h_bt_info_req_sent;
1569         bool c2h_bt_inquiry_page;
1570         u32 bt_inq_page_start_time;
1571         u8 bt_retry_cnt;
1572         u8 c2h_bt_info_original;
1573         u8 bt_inquiry_page_cnt;
1574         struct btdm_8723 btdm;
1575 };
1576
1577 struct rtl_hal {
1578         struct ieee80211_hw *hw;
1579         bool driver_is_goingto_unload;
1580         bool up_first_time;
1581         bool first_init;
1582         bool being_init_adapter;
1583         bool bbrf_ready;
1584         bool mac_func_enable;
1585         bool pre_edcca_enable;
1586         struct bt_coexist_8723 hal_coex_8723;
1587
1588         enum intf_type interface;
1589         u16 hw_type;            /*92c or 92d or 92s and so on */
1590         u8 ic_class;
1591         u8 oem_id;
1592         u32 version;            /*version of chip */
1593         u8 state;               /*stop 0, start 1 */
1594         u8 board_type;
1595         u8 package_type;
1596         u8 external_pa;
1597
1598         u8 pa_mode;
1599         u8 pa_type_2g;
1600         u8 pa_type_5g;
1601         u8 lna_type_2g;
1602         u8 lna_type_5g;
1603         u8 external_pa_2g;
1604         u8 external_lna_2g;
1605         u8 external_pa_5g;
1606         u8 external_lna_5g;
1607         u8 type_glna;
1608         u8 type_gpa;
1609         u8 type_alna;
1610         u8 type_apa;
1611         u8 rfe_type;
1612
1613         /*firmware */
1614         u32 fwsize;
1615         u8 *pfirmware;
1616         u16 fw_version;
1617         u16 fw_subversion;
1618         bool h2c_setinprogress;
1619         u8 last_hmeboxnum;
1620         bool fw_ready;
1621         /*Reserve page start offset except beacon in TxQ. */
1622         u8 fw_rsvdpage_startoffset;
1623         u8 h2c_txcmd_seq;
1624         u8 current_ra_rate;
1625
1626         /* FW Cmd IO related */
1627         u16 fwcmd_iomap;
1628         u32 fwcmd_ioparam;
1629         bool set_fwcmd_inprogress;
1630         u8 current_fwcmd_io;
1631
1632         struct p2p_ps_offload_t p2p_ps_offload;
1633         bool fw_clk_change_in_progress;
1634         bool allow_sw_to_change_hwclc;
1635         u8 fw_ps_state;
1636         /**/
1637         bool driver_going2unload;
1638
1639         /*AMPDU init min space*/
1640         u8 minspace_cfg;        /*For Min spacing configurations */
1641
1642         /* Dual mac */
1643         enum macphy_mode macphymode;
1644         enum band_type current_bandtype;        /* 0:2.4G, 1:5G */
1645         enum band_type current_bandtypebackup;
1646         enum band_type bandset;
1647         /* dual MAC 0--Mac0 1--Mac1 */
1648         u32 interfaceindex;
1649         /* just for DualMac S3S4 */
1650         u8 macphyctl_reg;
1651         bool earlymode_enable;
1652         u8 max_earlymode_num;
1653         /* Dual mac*/
1654         bool during_mac0init_radiob;
1655         bool during_mac1init_radioa;
1656         bool reloadtxpowerindex;
1657         /* True if IMR or IQK  have done
1658          * for 2.4G in scan progress
1659          */
1660         bool load_imrandiqk_setting_for2g;
1661
1662         bool disable_amsdu_8k;
1663         bool master_of_dmsp;
1664         bool slave_of_dmsp;
1665
1666         u16 rx_tag;/*for 92ee*/
1667         u8 rts_en;
1668
1669         /*for wowlan*/
1670         bool wow_enable;
1671         bool enter_pnp_sleep;
1672         bool wake_from_pnp_sleep;
1673         bool wow_enabled;
1674         __kernel_time_t last_suspend_sec;
1675         u32 wowlan_fwsize;
1676         u8 *wowlan_firmware;
1677
1678         u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1679
1680         bool real_wow_v2_enable;
1681         bool re_init_llt_table;
1682 };
1683
1684 struct rtl_security {
1685         /*default 0 */
1686         bool use_sw_sec;
1687
1688         bool being_setkey;
1689         bool use_defaultkey;
1690         /*Encryption Algorithm for Unicast Packet */
1691         enum rt_enc_alg pairwise_enc_algorithm;
1692         /*Encryption Algorithm for Brocast/Multicast */
1693         enum rt_enc_alg group_enc_algorithm;
1694         /*Cam Entry Bitmap */
1695         u32 hwsec_cam_bitmap;
1696         u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1697         /* local Key buffer, indx 0 is for
1698          * pairwise key 1-4 is for agoup key.
1699          */
1700         u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1701         u8 key_len[KEY_BUF_SIZE];
1702
1703         /* The pointer of Pairwise Key,
1704          * it always points to KeyBuf[4]
1705          */
1706         u8 *pairwise_key;
1707 };
1708
1709 #define ASSOCIATE_ENTRY_NUM     33
1710
1711 struct fast_ant_training {
1712         u8      bssid[6];
1713         u8      antsel_rx_keep_0;
1714         u8      antsel_rx_keep_1;
1715         u8      antsel_rx_keep_2;
1716         u32     ant_sum[7];
1717         u32     ant_cnt[7];
1718         u32     ant_ave[7];
1719         u8      fat_state;
1720         u32     train_idx;
1721         u8      antsel_a[ASSOCIATE_ENTRY_NUM];
1722         u8      antsel_b[ASSOCIATE_ENTRY_NUM];
1723         u8      antsel_c[ASSOCIATE_ENTRY_NUM];
1724         u32     main_ant_sum[ASSOCIATE_ENTRY_NUM];
1725         u32     aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1726         u32     main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1727         u32     aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1728         u8      rx_idle_ant;
1729         bool    becomelinked;
1730 };
1731
1732 struct dm_phy_dbg_info {
1733         s8 rx_snrdb[4];
1734         u64 num_qry_phy_status;
1735         u64 num_qry_phy_status_cck;
1736         u64 num_qry_phy_status_ofdm;
1737         u16 num_qry_beacon_pkt;
1738         u16 num_non_be_pkt;
1739         s32 rx_evm[4];
1740 };
1741
1742 struct rtl_dm {
1743         /*PHY status for Dynamic Management */
1744         long entry_min_undec_sm_pwdb;
1745         long undec_sm_cck;
1746         long undec_sm_pwdb;     /*out dm */
1747         long entry_max_undec_sm_pwdb;
1748         s32 ofdm_pkt_cnt;
1749         bool dm_initialgain_enable;
1750         bool dynamic_txpower_enable;
1751         bool current_turbo_edca;
1752         bool is_any_nonbepkts;  /*out dm */
1753         bool is_cur_rdlstate;
1754         bool txpower_trackinginit;
1755         bool disable_framebursting;
1756         bool cck_inch14;
1757         bool txpower_tracking;
1758         bool useramask;
1759         bool rfpath_rxenable[4];
1760         bool inform_fw_driverctrldm;
1761         bool current_mrc_switch;
1762         u8 txpowercount;
1763         u8 powerindex_backup[6];
1764
1765         u8 thermalvalue_rxgain;
1766         u8 thermalvalue_iqk;
1767         u8 thermalvalue_lck;
1768         u8 thermalvalue;
1769         u8 last_dtp_lvl;
1770         u8 thermalvalue_avg[AVG_THERMAL_NUM];
1771         u8 thermalvalue_avg_index;
1772         u8 tm_trigger;
1773         bool done_txpower;
1774         u8 dynamic_txhighpower_lvl;     /*Tx high power level */
1775         u8 dm_flag;             /*Indicate each dynamic mechanism's status. */
1776         u8 dm_flag_tmp;
1777         u8 dm_type;
1778         u8 dm_rssi_sel;
1779         u8 txpower_track_control;
1780         bool interrupt_migration;
1781         bool disable_tx_int;
1782         s8 ofdm_index[MAX_RF_PATH];
1783         u8 default_ofdm_index;
1784         u8 default_cck_index;
1785         s8 cck_index;
1786         s8 delta_power_index[MAX_RF_PATH];
1787         s8 delta_power_index_last[MAX_RF_PATH];
1788         s8 power_index_offset[MAX_RF_PATH];
1789         s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1790         s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1791         s8 remnant_cck_idx;
1792         bool modify_txagc_flag_path_a;
1793         bool modify_txagc_flag_path_b;
1794
1795         bool one_entry_only;
1796         struct dm_phy_dbg_info dbginfo;
1797
1798         /* Dynamic ATC switch */
1799         bool atc_status;
1800         bool large_cfo_hit;
1801         bool is_freeze;
1802         int cfo_tail[2];
1803         int cfo_ave_pre;
1804         int crystal_cap;
1805         u8 cfo_threshold;
1806         u32 packet_count;
1807         u32 packet_count_pre;
1808         u8 tx_rate;
1809
1810         /*88e tx power tracking*/
1811         u8      swing_idx_ofdm[MAX_RF_PATH];
1812         u8      swing_idx_ofdm_cur;
1813         u8      swing_idx_ofdm_base[MAX_RF_PATH];
1814         bool    swing_flag_ofdm;
1815         u8      swing_idx_cck;
1816         u8      swing_idx_cck_cur;
1817         u8      swing_idx_cck_base;
1818         bool    swing_flag_cck;
1819
1820         s8      swing_diff_2g;
1821         s8      swing_diff_5g;
1822
1823         /* DMSP */
1824         bool supp_phymode_switch;
1825
1826         /* DulMac */
1827         struct fast_ant_training fat_table;
1828
1829         u8      resp_tx_path;
1830         u8      path_sel;
1831         u32     patha_sum;
1832         u32     pathb_sum;
1833         u32     patha_cnt;
1834         u32     pathb_cnt;
1835
1836         u8 pre_channel;
1837         u8 *p_channel;
1838         u8 linked_interval;
1839
1840         u64 last_tx_ok_cnt;
1841         u64 last_rx_ok_cnt;
1842 };
1843
1844 #define EFUSE_MAX_LOGICAL_SIZE                  512
1845
1846 struct rtl_efuse {
1847         bool autoload_ok;
1848         bool bootfromefuse;
1849         u16 max_physical_size;
1850
1851         u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1852         u16 efuse_usedbytes;
1853         u8 efuse_usedpercentage;
1854 #ifdef EFUSE_REPG_WORKAROUND
1855         bool efuse_re_pg_sec1flag;
1856         u8 efuse_re_pg_data[8];
1857 #endif
1858
1859         u8 autoload_failflag;
1860         u8 autoload_status;
1861
1862         short epromtype;
1863         u16 eeprom_vid;
1864         u16 eeprom_did;
1865         u16 eeprom_svid;
1866         u16 eeprom_smid;
1867         u8 eeprom_oemid;
1868         u16 eeprom_channelplan;
1869         u8 eeprom_version;
1870         u8 board_type;
1871         u8 external_pa;
1872
1873         u8 dev_addr[6];
1874         u8 wowlan_enable;
1875         u8 antenna_div_cfg;
1876         u8 antenna_div_type;
1877
1878         bool txpwr_fromeprom;
1879         u8 eeprom_crystalcap;
1880         u8 eeprom_tssi[2];
1881         u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1882         u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1883         u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1884         u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1885         u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1886         u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1887
1888         u8 internal_pa_5g[2];   /* pathA / pathB */
1889         u8 eeprom_c9;
1890         u8 eeprom_cc;
1891
1892         /*For power group */
1893         u8 eeprom_pwrgroup[2][3];
1894         u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1895         u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1896
1897         u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1898         /*For HT 40MHZ pwr */
1899         u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1900         /*For HT 40MHZ pwr */
1901         u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1902
1903         /*--------------------------------------------------------*
1904          * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1905          * other ICs (8188EE\8723BE\8192EE\8812AE...)
1906          * define new arrays in Windows code.
1907          * BUT, in linux code, we use the same array for all ICs.
1908          *
1909          * The Correspondance relation between two arrays is:
1910          * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1911          * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1912          * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1913          * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1914          *
1915          * Sizes of these arrays are decided by the larger ones.
1916          */
1917         s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1918         s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1919         s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1920         s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1921
1922         u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1923         u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1924         s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1925         s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1926         s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1927         s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1928
1929         u8 txpwr_safetyflag;                    /* Band edge enable flag */
1930         u16 eeprom_txpowerdiff;
1931         u8 legacy_httxpowerdiff;        /* Legacy to HT rate power diff */
1932         u8 antenna_txpwdiff[3];
1933
1934         u8 eeprom_regulatory;
1935         u8 eeprom_thermalmeter;
1936         u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1937         u16 tssi_13dbm;
1938         u8 crystalcap;          /* CrystalCap. */
1939         u8 delta_iqk;
1940         u8 delta_lck;
1941
1942         u8 legacy_ht_txpowerdiff;       /*Legacy to HT rate power diff */
1943         bool apk_thermalmeterignore;
1944
1945         bool b1x1_recvcombine;
1946         bool b1ss_support;
1947
1948         /*channel plan */
1949         u8 channel_plan;
1950 };
1951
1952 struct rtl_tx_report {
1953         atomic_t sn;
1954         u16 last_sent_sn;
1955         unsigned long last_sent_time;
1956         u16 last_recv_sn;
1957 };
1958
1959 struct rtl_ps_ctl {
1960         bool pwrdomain_protect;
1961         bool in_powersavemode;
1962         bool rfchange_inprogress;
1963         bool swrf_processing;
1964         bool hwradiooff;
1965         /* just for PCIE ASPM
1966          * If it supports ASPM, Offset[560h] = 0x40,
1967          * otherwise Offset[560h] = 0x00.
1968          */
1969         bool support_aspm;
1970         bool support_backdoor;
1971
1972         /*for LPS */
1973         enum rt_psmode dot11_psmode;    /*Power save mode configured. */
1974         bool swctrl_lps;
1975         bool leisure_ps;
1976         bool fwctrl_lps;
1977         u8 fwctrl_psmode;
1978         /*For Fw control LPS mode */
1979         u8 reg_fwctrl_lps;
1980         /*Record Fw PS mode status. */
1981         bool fw_current_inpsmode;
1982         u8 reg_max_lps_awakeintvl;
1983         bool report_linked;
1984         bool low_power_enable;/*for 32k*/
1985
1986         /*for IPS */
1987         bool inactiveps;
1988
1989         u32 rfoff_reason;
1990
1991         /*RF OFF Level */
1992         u32 cur_ps_level;
1993         u32 reg_rfps_level;
1994
1995         /*just for PCIE ASPM */
1996         u8 const_amdpci_aspm;
1997         bool pwrdown_mode;
1998
1999         enum rf_pwrstate inactive_pwrstate;
2000         enum rf_pwrstate rfpwr_state;   /*cur power state */
2001
2002         /* for SW LPS*/
2003         bool sw_ps_enabled;
2004         bool state;
2005         bool state_inap;
2006         bool multi_buffered;
2007         u16 nullfunc_seq;
2008         unsigned int dtim_counter;
2009         unsigned int sleep_ms;
2010         unsigned long last_sleep_jiffies;
2011         unsigned long last_awake_jiffies;
2012         unsigned long last_delaylps_stamp_jiffies;
2013         unsigned long last_dtim;
2014         unsigned long last_beacon;
2015         unsigned long last_action;
2016         unsigned long last_slept;
2017
2018         /*For P2P PS */
2019         struct rtl_p2p_ps_info p2p_ps_info;
2020         u8 pwr_mode;
2021         u8 smart_ps;
2022
2023         /* wake up on line */
2024         u8 wo_wlan_mode;
2025         u8 arp_offload_enable;
2026         u8 gtk_offload_enable;
2027         /* Used for WOL, indicates the reason for waking event.*/
2028         u32 wakeup_reason;
2029         /* Record the last waking time for comparison with setting key. */
2030         u64 last_wakeup_time;
2031 };
2032
2033 struct rtl_stats {
2034         u8 psaddr[ETH_ALEN];
2035         u32 mac_time[2];
2036         s8 rssi;
2037         u8 signal;
2038         u8 noise;
2039         u8 rate;                /* hw desc rate */
2040         u8 received_channel;
2041         u8 control;
2042         u8 mask;
2043         u8 freq;
2044         u16 len;
2045         u64 tsf;
2046         u32 beacon_time;
2047         u8 nic_type;
2048         u16 length;
2049         u8 signalquality;       /*in 0-100 index. */
2050         /*
2051          * Real power in dBm for this packet,
2052          * no beautification and aggregation.
2053          */
2054         s32 recvsignalpower;
2055         s8 rxpower;             /*in dBm Translate from PWdB */
2056         u8 signalstrength;      /*in 0-100 index. */
2057         u16 hwerror:1;
2058         u16 crc:1;
2059         u16 icv:1;
2060         u16 shortpreamble:1;
2061         u16 antenna:1;
2062         u16 decrypted:1;
2063         u16 wakeup:1;
2064         u32 timestamp_low;
2065         u32 timestamp_high;
2066         bool shift;
2067
2068         u8 rx_drvinfo_size;
2069         u8 rx_bufshift;
2070         bool isampdu;
2071         bool isfirst_ampdu;
2072         bool rx_is40mhzpacket;
2073         u8 rx_packet_bw;
2074         u32 rx_pwdb_all;
2075         u8 rx_mimo_signalstrength[4];   /*in 0~100 index */
2076         s8 rx_mimo_signalquality[4];
2077         u8 rx_mimo_evm_dbm[4];
2078         u16 cfo_short[4];               /* per-path's Cfo_short */
2079         u16 cfo_tail[4];
2080
2081         s8 rx_mimo_sig_qual[4];
2082         u8 rx_pwr[4]; /* per-path's pwdb */
2083         u8 rx_snr[4]; /* per-path's SNR */
2084         u8 bandwidth;
2085         u8 bt_coex_pwr_adjust;
2086         bool packet_matchbssid;
2087         bool is_cck;
2088         bool is_ht;
2089         bool packet_toself;
2090         bool packet_beacon;     /*for rssi */
2091         s8 cck_adc_pwdb[4];     /*for rx path selection */
2092
2093         bool is_vht;
2094         bool is_short_gi;
2095         u8 vht_nss;
2096
2097         u8 packet_report_type;
2098
2099         u32 macid;
2100         u8 wake_match;
2101         u32 bt_rx_rssi_percentage;
2102         u32 macid_valid_entry[2];
2103 };
2104
2105 struct rt_link_detect {
2106         /* count for roaming */
2107         u32 bcn_rx_inperiod;
2108         u32 roam_times;
2109
2110         u32 num_tx_in4period[4];
2111         u32 num_rx_in4period[4];
2112
2113         u32 num_tx_inperiod;
2114         u32 num_rx_inperiod;
2115
2116         bool busytraffic;
2117         bool tx_busy_traffic;
2118         bool rx_busy_traffic;
2119         bool higher_busytraffic;
2120         bool higher_busyrxtraffic;
2121
2122         u32 tidtx_in4period[MAX_TID_COUNT][4];
2123         u32 tidtx_inperiod[MAX_TID_COUNT];
2124         bool higher_busytxtraffic[MAX_TID_COUNT];
2125 };
2126
2127 struct rtl_tcb_desc {
2128         u8 packet_bw:2;
2129         u8 multicast:1;
2130         u8 broadcast:1;
2131
2132         u8 rts_stbc:1;
2133         u8 rts_enable:1;
2134         u8 cts_enable:1;
2135         u8 rts_use_shortpreamble:1;
2136         u8 rts_use_shortgi:1;
2137         u8 rts_sc:1;
2138         u8 rts_bw:1;
2139         u8 rts_rate;
2140
2141         u8 use_shortgi:1;
2142         u8 use_shortpreamble:1;
2143         u8 use_driver_rate:1;
2144         u8 disable_ratefallback:1;
2145
2146         u8 use_spe_rpt:1;
2147
2148         u8 ratr_index;
2149         u8 mac_id;
2150         u8 hw_rate;
2151
2152         u8 last_inipkt:1;
2153         u8 cmd_or_init:1;
2154         u8 queue_index;
2155
2156         /* early mode */
2157         u8 empkt_num;
2158         /* The max value by HW */
2159         u32 empkt_len[10];
2160         bool tx_enable_sw_calc_duration;
2161 };
2162
2163 struct rtl_wow_pattern {
2164         u8 type;
2165         u16 crc;
2166         u32 mask[4];
2167 };
2168
2169 struct rtl_hal_ops {
2170         int (*init_sw_vars)(struct ieee80211_hw *hw);
2171         void (*deinit_sw_vars)(struct ieee80211_hw *hw);
2172         void (*read_chip_version)(struct ieee80211_hw *hw);
2173         void (*read_eeprom_info)(struct ieee80211_hw *hw);
2174         void (*interrupt_recognized)(struct ieee80211_hw *hw,
2175                                      u32 *p_inta, u32 *p_intb,
2176                                      u32 *p_intc, u32 *p_intd);
2177         int (*hw_init)(struct ieee80211_hw *hw);
2178         void (*hw_disable)(struct ieee80211_hw *hw);
2179         void (*hw_suspend)(struct ieee80211_hw *hw);
2180         void (*hw_resume)(struct ieee80211_hw *hw);
2181         void (*enable_interrupt)(struct ieee80211_hw *hw);
2182         void (*disable_interrupt)(struct ieee80211_hw *hw);
2183         int (*set_network_type)(struct ieee80211_hw *hw,
2184                                 enum nl80211_iftype type);
2185         void (*set_chk_bssid)(struct ieee80211_hw *hw,
2186                               bool check_bssid);
2187         void (*set_bw_mode)(struct ieee80211_hw *hw,
2188                             enum nl80211_channel_type ch_type);
2189          u8 (*switch_channel)(struct ieee80211_hw *hw);
2190         void (*set_qos)(struct ieee80211_hw *hw, int aci);
2191         void (*set_bcn_reg)(struct ieee80211_hw *hw);
2192         void (*set_bcn_intv)(struct ieee80211_hw *hw);
2193         void (*update_interrupt_mask)(struct ieee80211_hw *hw,
2194                                       u32 add_msr, u32 rm_msr);
2195         void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2196         void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2197         void (*update_rate_tbl)(struct ieee80211_hw *hw,
2198                                 struct ieee80211_sta *sta, u8 rssi_leve,
2199                                 bool update_bw);
2200         void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2201                                     u8 *desc, u8 queue_index,
2202                                     struct sk_buff *skb, dma_addr_t addr);
2203         void (*update_rate_mask)(struct ieee80211_hw *hw, u8 rssi_level);
2204         u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2205                                          u8 queue_index);
2206         void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2207                                 u8 queue_index);
2208         void (*fill_tx_desc)(struct ieee80211_hw *hw,
2209                              struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2210                              u8 *pbd_desc_tx,
2211                              struct ieee80211_tx_info *info,
2212                              struct ieee80211_sta *sta,
2213                              struct sk_buff *skb, u8 hw_queue,
2214                              struct rtl_tcb_desc *ptcb_desc);
2215         void (*fill_fake_txdesc)(struct ieee80211_hw *hw, u8 *pdesc,
2216                                  u32 buffer_len, bool bispspoll);
2217         void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc,
2218                                 bool firstseg, bool lastseg,
2219                                 struct sk_buff *skb);
2220         void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
2221                                      u8 *pdesc, u8 *pbd_desc,
2222                                      struct sk_buff *skb, u8 hw_queue);
2223         bool (*query_rx_desc)(struct ieee80211_hw *hw,
2224                               struct rtl_stats *stats,
2225                               struct ieee80211_rx_status *rx_status,
2226                               u8 *pdesc, struct sk_buff *skb);
2227         void (*set_channel_access)(struct ieee80211_hw *hw);
2228         bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid);
2229         void (*dm_watchdog)(struct ieee80211_hw *hw);
2230         void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation);
2231         bool (*set_rf_power_state)(struct ieee80211_hw *hw,
2232                                    enum rf_pwrstate rfpwr_state);
2233         void (*led_control)(struct ieee80211_hw *hw,
2234                             enum led_ctl_mode ledaction);
2235         void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2236                          u8 desc_name, u8 *val);
2237         u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2238                         u8 desc_name);
2239         bool (*is_tx_desc_closed)(struct ieee80211_hw *hw,
2240                                   u8 hw_queue, u16 index);
2241         void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue);
2242         void (*enable_hw_sec)(struct ieee80211_hw *hw);
2243         void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
2244                         u8 *macaddr, bool is_group, u8 enc_algo,
2245                         bool is_wepkey, bool clear_all);
2246         void (*init_sw_leds)(struct ieee80211_hw *hw);
2247         void (*deinit_sw_leds)(struct ieee80211_hw *hw);
2248         u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2249         void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2250                           u32 data);
2251         u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2252                          u32 regaddr, u32 bitmask);
2253         void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2254                           u32 regaddr, u32 bitmask, u32 data);
2255         void (*linked_set_reg)(struct ieee80211_hw *hw);
2256         void (*chk_switch_dmdp)(struct ieee80211_hw *hw);
2257         void (*dualmac_easy_concurrent)(struct ieee80211_hw *hw);
2258         void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
2259         bool (*phy_rf6052_config)(struct ieee80211_hw *hw);
2260         void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw,
2261                                            u8 *powerlevel);
2262         void (*phy_rf6052_set_ofdm_txpower)(struct ieee80211_hw *hw,
2263                                             u8 *ppowerlevel, u8 channel);
2264         bool (*config_bb_with_headerfile)(struct ieee80211_hw *hw,
2265                                           u8 configtype);
2266         bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw,
2267                                             u8 configtype);
2268         void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t);
2269         void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw);
2270         void (*dm_dynamic_txpower)(struct ieee80211_hw *hw);
2271         void (*c2h_command_handle)(struct ieee80211_hw *hw);
2272         void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw,
2273                                             bool mstate);
2274         void (*bt_coex_off_before_lps)(struct ieee80211_hw *hw);
2275         void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id,
2276                              u32 cmd_len, u8 *p_cmdbuffer);
2277         void (*set_default_port_id_cmd)(struct ieee80211_hw *hw);
2278         bool (*get_btc_status)(void);
2279         bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2280         u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2281                                  const struct rtl_stats *status,
2282                                  struct sk_buff *skb);
2283         void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2284                                    struct rtl_wow_pattern *rtl_pattern,
2285                                    u8 index);
2286         u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2287         void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len,
2288                                     u8 *val);
2289         /* ops for halmac cb */
2290         bool (*halmac_cb_init_mac_register)(struct rtl_priv *rtlpriv);
2291         bool (*halmac_cb_init_bb_rf_register)(struct rtl_priv *rtlpriv);
2292         bool (*halmac_cb_write_data_rsvd_page)(struct rtl_priv *rtlpriv,
2293                                                u8 *buf, u32 size);
2294         bool (*halmac_cb_write_data_h2c)(struct rtl_priv *rtlpriv, u8 *buf,
2295                                          u32 size);
2296         /* ops for phydm cb */
2297         u8 (*get_txpower_index)(struct ieee80211_hw *hw, u8 path,
2298                                 u8 rate, u8 bandwidth, u8 channel);
2299         void (*set_tx_power_index_by_rs)(struct ieee80211_hw *hw,
2300                                          u8 channel, u8 path,
2301                                          enum rate_section rs);
2302         void (*store_tx_power_by_rate)(struct ieee80211_hw *hw,
2303                                        u32 band, u32 rfpath,
2304                                        u32 txnum, u32 regaddr,
2305                                        u32 bitmask, u32 data);
2306         void (*phy_set_txpower_limit)(struct ieee80211_hw *hw, u8 *pregulation,
2307                                       u8 *pband, u8 *pbandwidth,
2308                                       u8 *prate_section, u8 *prf_path,
2309                                       u8 *pchannel, u8 *ppower_limit);
2310 };
2311
2312 struct rtl_intf_ops {
2313         /*com */
2314         void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2315         int (*adapter_start)(struct ieee80211_hw *hw);
2316         void (*adapter_stop)(struct ieee80211_hw *hw);
2317         bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2318                                  struct rtl_priv **buddy_priv);
2319
2320         int (*adapter_tx)(struct ieee80211_hw *hw,
2321                           struct ieee80211_sta *sta,
2322                           struct sk_buff *skb,
2323                           struct rtl_tcb_desc *ptcb_desc);
2324         void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2325         int (*reset_trx_ring)(struct ieee80211_hw *hw);
2326         bool (*waitq_insert)(struct ieee80211_hw *hw,
2327                              struct ieee80211_sta *sta,
2328                              struct sk_buff *skb);
2329
2330         /*pci */
2331         void (*disable_aspm)(struct ieee80211_hw *hw);
2332         void (*enable_aspm)(struct ieee80211_hw *hw);
2333
2334         /*usb */
2335 };
2336
2337 struct rtl_mod_params {
2338         /* default: 0,0 */
2339         u64 debug_mask;
2340         /* default: 0 = using hardware encryption */
2341         bool sw_crypto;
2342
2343         /* default: 0 = DBG_EMERG (0)*/
2344         int debug_level;
2345
2346         /* default: 1 = using no linked power save */
2347         bool inactiveps;
2348
2349         /* default: 1 = using linked sw power save */
2350         bool swctrl_lps;
2351
2352         /* default: 1 = using linked fw power save */
2353         bool fwctrl_lps;
2354
2355         /* default: 0 = not using MSI interrupts mode
2356          * submodules should set their own default value
2357          */
2358         bool msi_support;
2359
2360         /* default: 0 = dma 32 */
2361         bool dma64;
2362
2363         /* default: 1 = enable aspm */
2364         int aspm_support;
2365
2366         /* default 0: 1 means disable */
2367         bool disable_watchdog;
2368
2369         /* default 0: 1 means do not disable interrupts */
2370         bool int_clear;
2371
2372         /* select antenna */
2373         int ant_sel;
2374 };
2375
2376 struct rtl_hal_usbint_cfg {
2377         /* data - rx */
2378         u32 in_ep_num;
2379         u32 rx_urb_num;
2380         u32 rx_max_size;
2381
2382         /* op - rx */
2383         void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2384         void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2385                                      struct sk_buff_head *);
2386
2387         /* tx */
2388         void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2389         int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2390                                struct sk_buff *);
2391         struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2392                                                 struct sk_buff_head *);
2393
2394         /* endpoint mapping */
2395         int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2396         u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2397 };
2398
2399 struct rtl_hal_cfg {
2400         u8 bar_id;
2401         bool write_readback;
2402         char *name;
2403         char *alt_fw_name;
2404         struct rtl_hal_ops *ops;
2405         struct rtl_mod_params *mod_params;
2406         struct rtl_hal_usbint_cfg *usb_interface_cfg;
2407         enum rtl_spec_ver spec_ver;
2408
2409         /* this map used for some registers or vars
2410          * defined int HAL but used in MAIN
2411          */
2412         u32 maps[RTL_VAR_MAP_MAX];
2413
2414 };
2415
2416 struct rtl_locks {
2417         /* mutex */
2418         struct mutex conf_mutex;
2419         struct mutex ips_mutex; /* mutex for enter/leave IPS */
2420         struct mutex lps_mutex; /* mutex for enter/leave LPS */
2421
2422         /*spin lock */
2423         spinlock_t irq_th_lock;
2424         spinlock_t h2c_lock;
2425         spinlock_t rf_ps_lock;
2426         spinlock_t rf_lock;
2427         spinlock_t waitq_lock;
2428         spinlock_t entry_list_lock;
2429         spinlock_t usb_lock;
2430         spinlock_t c2hcmd_lock;
2431         spinlock_t scan_list_lock; /* lock for the scan list */
2432
2433         /*FW clock change */
2434         spinlock_t fw_ps_lock;
2435
2436         /*Dual mac*/
2437         spinlock_t cck_and_rw_pagea_lock;
2438
2439         spinlock_t iqk_lock;
2440 };
2441
2442 struct rtl_works {
2443         struct ieee80211_hw *hw;
2444
2445         /*timer */
2446         struct timer_list watchdog_timer;
2447         struct timer_list dualmac_easyconcurrent_retrytimer;
2448         struct timer_list fw_clockoff_timer;
2449         struct timer_list fast_antenna_training_timer;
2450         /*task */
2451         struct tasklet_struct irq_tasklet;
2452         struct tasklet_struct irq_prepare_bcn_tasklet;
2453
2454         /*work queue */
2455         struct workqueue_struct *rtl_wq;
2456         struct delayed_work watchdog_wq;
2457         struct delayed_work ips_nic_off_wq;
2458         struct delayed_work c2hcmd_wq;
2459
2460         /* For SW LPS */
2461         struct delayed_work ps_work;
2462         struct delayed_work ps_rfon_wq;
2463         struct delayed_work fwevt_wq;
2464
2465         struct work_struct lps_change_work;
2466         struct work_struct fill_h2c_cmd;
2467 };
2468
2469 struct rtl_debug {
2470         /* add for debug */
2471         struct dentry *debugfs_dir;
2472         char debugfs_name[20];
2473
2474         char *msg_buf;
2475 };
2476
2477 #define MIMO_PS_STATIC                  0
2478 #define MIMO_PS_DYNAMIC                 1
2479 #define MIMO_PS_NOLIMIT                 3
2480
2481 struct rtl_dualmac_easy_concurrent_ctl {
2482         enum band_type currentbandtype_backfordmdp;
2483         bool close_bbandrf_for_dmsp;
2484         bool change_to_dmdp;
2485         bool change_to_dmsp;
2486         bool switch_in_process;
2487 };
2488
2489 struct rtl_dmsp_ctl {
2490         bool activescan_for_slaveofdmsp;
2491         bool scan_for_anothermac_fordmsp;
2492         bool scan_for_itself_fordmsp;
2493         bool writedig_for_anothermacofdmsp;
2494         u32 curdigvalue_for_anothermacofdmsp;
2495         bool changecckpdstate_for_anothermacofdmsp;
2496         u8 curcckpdstate_for_anothermacofdmsp;
2497         bool changetxhighpowerlvl_for_anothermacofdmsp;
2498         u8 curtxhighlvl_for_anothermacofdmsp;
2499         long rssivalmin_for_anothermacofdmsp;
2500 };
2501
2502 struct ps_t {
2503         u8 pre_ccastate;
2504         u8 cur_ccasate;
2505         u8 pre_rfstate;
2506         u8 cur_rfstate;
2507         u8 initialize;
2508         long rssi_val_min;
2509 };
2510
2511 struct dig_t {
2512         u32 rssi_lowthresh;
2513         u32 rssi_highthresh;
2514         u32 fa_lowthresh;
2515         u32 fa_highthresh;
2516         long last_min_undec_pwdb_for_dm;
2517         long rssi_highpower_lowthresh;
2518         long rssi_highpower_highthresh;
2519         u32 recover_cnt;
2520         u32 pre_igvalue;
2521         u32 cur_igvalue;
2522         long rssi_val;
2523         u8 dig_enable_flag;
2524         u8 dig_ext_port_stage;
2525         u8 dig_algorithm;
2526         u8 dig_twoport_algorithm;
2527         u8 dig_dbgmode;
2528         u8 dig_slgorithm_switch;
2529         u8 cursta_cstate;
2530         u8 presta_cstate;
2531         u8 curmultista_cstate;
2532         u8 stop_dig;
2533         s8 back_val;
2534         s8 back_range_max;
2535         s8 back_range_min;
2536         u8 rx_gain_max;
2537         u8 rx_gain_min;
2538         u8 min_undec_pwdb_for_dm;
2539         u8 rssi_val_min;
2540         u8 pre_cck_cca_thres;
2541         u8 cur_cck_cca_thres;
2542         u8 pre_cck_pd_state;
2543         u8 cur_cck_pd_state;
2544         u8 pre_cck_fa_state;
2545         u8 cur_cck_fa_state;
2546         u8 pre_ccastate;
2547         u8 cur_ccasate;
2548         u8 large_fa_hit;
2549         u8 forbidden_igi;
2550         u8 dig_state;
2551         u8 dig_highpwrstate;
2552         u8 cur_sta_cstate;
2553         u8 pre_sta_cstate;
2554         u8 cur_ap_cstate;
2555         u8 pre_ap_cstate;
2556         u8 cur_pd_thstate;
2557         u8 pre_pd_thstate;
2558         u8 cur_cs_ratiostate;
2559         u8 pre_cs_ratiostate;
2560         u8 backoff_enable_flag;
2561         s8 backoffval_range_max;
2562         s8 backoffval_range_min;
2563         u8 dig_min_0;
2564         u8 dig_min_1;
2565         u8 bt30_cur_igi;
2566         bool media_connect_0;
2567         bool media_connect_1;
2568
2569         u32 antdiv_rssi_max;
2570         u32 rssi_max;
2571 };
2572
2573 struct rtl_global_var {
2574         /* from this list we can get
2575          * other adapter's rtl_priv
2576          */
2577         struct list_head glb_priv_list;
2578         spinlock_t glb_list_lock;
2579 };
2580
2581 #define IN_4WAY_TIMEOUT_TIME    (30 * MSEC_PER_SEC)     /* 30 seconds */
2582
2583 struct rtl_btc_info {
2584         u8 bt_type;
2585         u8 btcoexist;
2586         u8 ant_num;
2587         u8 single_ant_path;
2588
2589         u8 ap_num;
2590         bool in_4way;
2591         unsigned long in_4way_ts;
2592 };
2593
2594 struct bt_coexist_info {
2595         struct rtl_btc_ops *btc_ops;
2596         struct rtl_btc_info btc_info;
2597         /* btc context */
2598         void *btc_context;
2599         void *wifi_only_context;
2600         /* EEPROM BT info. */
2601         u8 eeprom_bt_coexist;
2602         u8 eeprom_bt_type;
2603         u8 eeprom_bt_ant_num;
2604         u8 eeprom_bt_ant_isol;
2605         u8 eeprom_bt_radio_shared;
2606
2607         u8 bt_coexistence;
2608         u8 bt_ant_num;
2609         u8 bt_coexist_type;
2610         u8 bt_state;
2611         u8 bt_cur_state;        /* 0:on, 1:off */
2612         u8 bt_ant_isolation;    /* 0:good, 1:bad */
2613         u8 bt_pape_ctrl;        /* 0:SW, 1:SW/HW dynamic */
2614         u8 bt_service;
2615         u8 bt_radio_shared_type;
2616         u8 bt_rfreg_origin_1e;
2617         u8 bt_rfreg_origin_1f;
2618         u8 bt_rssi_state;
2619         u32 ratio_tx;
2620         u32 ratio_pri;
2621         u32 bt_edca_ul;
2622         u32 bt_edca_dl;
2623
2624         bool init_set;
2625         bool bt_busy_traffic;
2626         bool bt_traffic_mode_set;
2627         bool bt_non_traffic_mode_set;
2628
2629         bool fw_coexist_all_off;
2630         bool sw_coexist_all_off;
2631         bool hw_coexist_all_off;
2632         u32 cstate;
2633         u32 previous_state;
2634         u32 cstate_h;
2635         u32 previous_state_h;
2636
2637         u8 bt_pre_rssi_state;
2638         u8 bt_pre_rssi_state1;
2639
2640         u8 reg_bt_iso;
2641         u8 reg_bt_sco;
2642         bool balance_on;
2643         u8 bt_active_zero_cnt;
2644         bool cur_bt_disabled;
2645         bool pre_bt_disabled;
2646
2647         u8 bt_profile_case;
2648         u8 bt_profile_action;
2649         bool bt_busy;
2650         bool hold_for_bt_operation;
2651         u8 lps_counter;
2652 };
2653
2654 struct rtl_btc_ops {
2655         void (*btc_init_variables)(struct rtl_priv *rtlpriv);
2656         void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
2657         void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
2658         void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv);
2659         void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2660         void (*btc_init_hw_config)(struct rtl_priv *rtlpriv);
2661         void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
2662         void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type);
2663         void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2664         void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype);
2665         void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
2666                                           u8 scantype);
2667         void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action);
2668         void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv,
2669                                        enum rt_media_status mstatus);
2670         void (*btc_periodical)(struct rtl_priv *rtlpriv);
2671         void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
2672         void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv,
2673                                   u8 *tmp_buf, u8 length);
2674         void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2675                                     u8 *tmp_buf, u8 length);
2676         bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv);
2677         bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv);
2678         bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv);
2679         void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2680                                           u8 pkt_type);
2681         void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
2682                                        bool scanning);
2683         void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
2684                                                  u8 type, bool scanning);
2685         void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
2686                                          struct seq_file *m);
2687         void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2688         u8   (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2689         u8   (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2690         bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2691         void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2692                                   u8 *ctrl_agg_size, u8 *agg_size);
2693         bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2694 };
2695
2696 struct rtl_halmac_ops {
2697         int (*halmac_init_adapter)(struct rtl_priv *);
2698         int (*halmac_deinit_adapter)(struct rtl_priv *);
2699         int (*halmac_init_hal)(struct rtl_priv *);
2700         int (*halmac_deinit_hal)(struct rtl_priv *);
2701         int (*halmac_poweron)(struct rtl_priv *);
2702         int (*halmac_poweroff)(struct rtl_priv *);
2703
2704         int (*halmac_phy_power_switch)(struct rtl_priv *rtlpriv, u8 enable);
2705         int (*halmac_set_mac_address)(struct rtl_priv *rtlpriv, u8 hwport,
2706                                       u8 *addr);
2707         int (*halmac_set_bssid)(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr);
2708
2709         int (*halmac_get_physical_efuse_size)(struct rtl_priv *rtlpriv,
2710                                               u32 *size);
2711         int (*halmac_read_physical_efuse_map)(struct rtl_priv *rtlpriv,
2712                                               u8 *map, u32 size);
2713         int (*halmac_get_logical_efuse_size)(struct rtl_priv *rtlpriv,
2714                                              u32 *size);
2715         int (*halmac_read_logical_efuse_map)(struct rtl_priv *rtlpriv, u8 *map,
2716                                              u32 size);
2717
2718         int (*halmac_set_bandwidth)(struct rtl_priv *rtlpriv, u8 channel,
2719                                     u8 pri_ch_idx, u8 bw);
2720
2721         int (*halmac_c2h_handle)(struct rtl_priv *rtlpriv, u8 *c2h, u32 size);
2722
2723         int (*halmac_chk_txdesc)(struct rtl_priv *rtlpriv, u8 *txdesc,
2724                                  u32 size);
2725 };
2726
2727 struct rtl_halmac_indicator {
2728         struct completion *comp;
2729         u32 wait_ms;
2730
2731         u8 *buffer;
2732         u32 buf_size;
2733         u32 ret_size;
2734         u32 status;
2735 };
2736
2737 struct rtl_halmac {
2738         struct rtl_halmac_ops *ops; /* halmac ops (halmac.ko own this object) */
2739         void *internal; /* internal context of halmac, i.e. PHALMAC_ADAPTER */
2740         struct rtl_halmac_indicator *indicator; /* size=10 */
2741
2742         /* flags */
2743         /*
2744          * send_general_info
2745          *      0: no need to call halmac_send_general_info()
2746          *      1: need to call halmac_send_general_info()
2747          */
2748         u8 send_general_info;
2749 };
2750
2751 struct rtl_phydm_params {
2752         u8 mp_chip;     /* 1: MP chip, 0: test chip */
2753         u8 fab_ver;     /* 0: TSMC, 1: UMC, ...*/
2754         u8 cut_ver;     /* 0: A, 1: B, ..., 10: K */
2755         u8 efuse0x3d7;  /* default: 0xff */
2756         u8 efuse0x3d8;  /* default: 0xff */
2757 };
2758
2759 struct rtl_phydm_ops {
2760         /* init/deinit priv */
2761         int (*phydm_init_priv)(struct rtl_priv *rtlpriv,
2762                                struct rtl_phydm_params *params);
2763         int (*phydm_deinit_priv)(struct rtl_priv *rtlpriv);
2764         bool (*phydm_load_txpower_by_rate)(struct rtl_priv *rtlpriv);
2765         bool (*phydm_load_txpower_limit)(struct rtl_priv *rtlpriv);
2766
2767         /* init hw */
2768         int  (*phydm_init_dm)(struct rtl_priv *rtlpriv);
2769         int  (*phydm_deinit_dm)(struct rtl_priv *rtlpriv);
2770         int  (*phydm_reset_dm)(struct rtl_priv *rtlpriv);
2771         bool (*phydm_parameter_init)(struct rtl_priv *rtlpriv, bool post);
2772         bool (*phydm_phy_bb_config)(struct rtl_priv *rtlpriv);
2773         bool (*phydm_phy_rf_config)(struct rtl_priv *rtlpriv);
2774         bool (*phydm_phy_mac_config)(struct rtl_priv *rtlpriv);
2775         bool (*phydm_trx_mode)(struct rtl_priv *rtlpriv,
2776                                enum radio_mask tx_path, enum radio_mask rx_path,
2777                                bool is_tx2_path);
2778         /* watchdog */
2779         bool (*phydm_watchdog)(struct rtl_priv *rtlpriv);
2780
2781         /* channel */
2782         bool (*phydm_switch_band)(struct rtl_priv *rtlpriv, u8 central_ch);
2783         bool (*phydm_switch_channel)(struct rtl_priv *rtlpriv, u8 central_ch);
2784         bool (*phydm_switch_bandwidth)(struct rtl_priv *rtlpriv,
2785                                        u8 primary_ch_idx,
2786                                        enum ht_channel_width width);
2787         bool (*phydm_iq_calibrate)(struct rtl_priv *rtlpriv);
2788         bool (*phydm_clear_txpowertracking_state)(struct rtl_priv *rtlpriv);
2789         bool (*phydm_pause_dig)(struct rtl_priv *rtlpriv, bool pause);
2790
2791         /* read/write reg */
2792         u32  (*phydm_read_rf_reg)(struct rtl_priv *rtlpriv,
2793                                   enum radio_path rfpath,
2794                                   u32 addr, u32 mask);
2795         bool (*phydm_write_rf_reg)(struct rtl_priv *rtlpriv,
2796                                    enum radio_path rfpath,
2797                                    u32 addr, u32 mask, u32 data);
2798         u8   (*phydm_read_txagc)(struct rtl_priv *rtlpriv,
2799                                  enum radio_path rfpath, u8 hw_rate);
2800         bool (*phydm_write_txagc)(struct rtl_priv *rtlpriv, u32 power_index,
2801                                   enum radio_path rfpath, u8 hw_rate);
2802
2803         /* RX */
2804         bool (*phydm_c2h_content_parsing)(struct rtl_priv *rtlpriv, u8 cmd_id,
2805                                           u8 cmd_len, u8 *content);
2806         bool (*phydm_query_phy_status)(struct rtl_priv *rtlpriv, u8 *phystrpt,
2807                                        struct ieee80211_hdr *hdr,
2808                                        struct rtl_stats *pstatus);
2809
2810         /* TX */
2811         u8 (*phydm_rate_id_mapping)(struct rtl_priv *rtlpriv,
2812                                     enum wireless_mode wireless_mode,
2813                                     enum rf_type rf_type,
2814                                     enum ht_channel_width bw);
2815         bool (*phydm_get_ra_bitmap)(struct rtl_priv *rtlpriv,
2816                                     enum wireless_mode wireless_mode,
2817                                     enum rf_type rf_type,
2818                                     enum ht_channel_width bw,
2819                                     u8 tx_rate_level, /* 0~6 */
2820                                     u32 *tx_bitmap_msb,
2821                                     u32 *tx_bitmap_lsb);
2822
2823         /* STA */
2824         bool (*phydm_add_sta)(struct rtl_priv *rtlpriv,
2825                               struct ieee80211_sta *sta);
2826         bool (*phydm_del_sta)(struct rtl_priv *rtlpriv,
2827                               struct ieee80211_sta *sta);
2828
2829         /* BTC */
2830         u32  (*phydm_get_version)(struct rtl_priv *rtlpriv);
2831         bool (*phydm_modify_ra_pcr_threshold)(struct rtl_priv *rtlpriv,
2832                                               u8 ra_offset_direction,
2833                                               u8 ra_threshold_offset);
2834         u32  (*phydm_query_counter)(struct rtl_priv *rtlpriv,
2835                                     const char *info_type);
2836
2837         /* debug */
2838         bool (*phydm_debug_cmd)(struct rtl_priv *rtlpriv, char *in, u32 in_len,
2839                                 char *out, u32 out_len);
2840
2841 };
2842
2843 struct rtl_phydm {
2844         struct rtl_phydm_ops *ops;/* phydm ops (phydm_mod.ko own this object) */
2845         void *internal; /* internal context of phydm, i.e. PHY_DM_STRUCT */
2846
2847         u8 adaptivity_en;
2848         /* debug */
2849         u16 forced_data_rate;
2850         u8 forced_igi_lb;
2851         u8 antenna_test;
2852 };
2853
2854 struct proxim {
2855         bool proxim_on;
2856
2857         void *proximity_priv;
2858         int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2859                          struct sk_buff *skb);
2860         u8  (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2861 };
2862
2863 struct rtl_c2hcmd {
2864         struct list_head list;
2865         u8 tag;
2866         u8 len;
2867         u8 *val;
2868 };
2869
2870 struct rtl_bssid_entry {
2871         struct list_head list;
2872         u8 bssid[ETH_ALEN];
2873         u32 age;
2874 };
2875
2876 struct rtl_scan_list {
2877         int num;
2878         struct list_head list;  /* sort by age */
2879 };
2880
2881 struct rtl_priv {
2882         struct ieee80211_hw *hw;
2883         struct completion firmware_loading_complete;
2884         struct list_head list;
2885         struct rtl_priv *buddy_priv;
2886         struct rtl_global_var *glb_var;
2887         struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2888         struct rtl_dmsp_ctl dmsp_ctl;
2889         struct rtl_locks locks;
2890         struct rtl_works works;
2891         struct rtl_mac mac80211;
2892         struct rtl_hal rtlhal;
2893         struct rtl_regulatory regd;
2894         struct rtl_rfkill rfkill;
2895         struct rtl_io io;
2896         struct rtl_phy phy;
2897         struct rtl_dm dm;
2898         struct rtl_security sec;
2899         struct rtl_efuse efuse;
2900         struct rtl_led_ctl ledctl;
2901         struct rtl_tx_report tx_report;
2902         struct rtl_scan_list scan_list;
2903         struct rtl_ps_ctl psc;
2904         struct rate_adaptive ra;
2905         struct dynamic_primary_cca primarycca;
2906         struct wireless_stats stats;
2907         struct rt_link_detect link_info;
2908         struct false_alarm_statistics falsealm_cnt;
2909         struct rtl_rate_priv *rate_priv;
2910         /* sta entry list for ap adhoc or mesh */
2911         struct list_head entry_list;
2912         /* c2hcmd list for kthread level access */
2913         struct list_head c2hcmd_list;
2914         struct rtl_debug dbg;
2915         int max_fw_size;
2916
2917         /*hal_cfg : for diff cards
2918          *intf_ops : for diff interface usb/pcie
2919          */
2920         struct rtl_hal_cfg *cfg;
2921         const struct rtl_intf_ops *intf_ops;
2922
2923         /* this var will be set by set_bit,
2924          * and was used to indicate status of
2925          * interface or hardware
2926          */
2927         unsigned long status;
2928
2929         /* tables for dm */
2930         struct dig_t dm_digtable;
2931         struct ps_t dm_pstable;
2932
2933         u32 reg_874;
2934         u32 reg_c70;
2935         u32 reg_85c;
2936         u32 reg_a74;
2937         bool reg_init;  /* true if regs saved */
2938         bool bt_operation_on;
2939         __le32 *usb_data;
2940         int usb_data_index;
2941         bool initialized;
2942         bool enter_ps;  /* true when entering PS */
2943         u8 rate_mask[5];
2944
2945         /* intel Proximity, should be alloc mem
2946          * in intel Proximity module and can only
2947          * be used in intel Proximity mode
2948          */
2949         struct proxim proximity;
2950
2951         /*for bt coexist use*/
2952         struct bt_coexist_info btcoexist;
2953
2954         /* halmac for newer IC. (e.g. 8822B) */
2955         struct rtl_halmac halmac;
2956
2957         /* phydm for newer IC. (e.g. 8822B) */
2958         struct rtl_phydm phydm;
2959
2960         /* separate 92ee from other ICs,
2961          * 92ee use new trx flow.
2962          */
2963         bool use_new_trx_flow;
2964
2965 #ifdef CONFIG_PM
2966         struct wiphy_wowlan_support wowlan;
2967 #endif
2968         /* This must be the last item so
2969          * that it points to the data allocated
2970          * beyond  this structure like:
2971          * rtl_pci_priv or rtl_usb_priv
2972          */
2973         u8 priv[0] __aligned(sizeof(void *));
2974 };
2975
2976 #define rtl_priv(hw)            (((struct rtl_priv *)(hw)->priv))
2977 #define rtl_mac(rtlpriv)        (&((rtlpriv)->mac80211))
2978 #define rtl_hal(rtlpriv)        (&((rtlpriv)->rtlhal))
2979 #define rtl_efuse(rtlpriv)      (&((rtlpriv)->efuse))
2980 #define rtl_psc(rtlpriv)        (&((rtlpriv)->psc))
2981
2982 /***************************************
2983  *    Bluetooth Co-existence Related
2984  ***************************************/
2985
2986 enum bt_ant_num {
2987         ANT_X2 = 0,
2988         ANT_X1 = 1,
2989 };
2990
2991 enum bt_co_type {
2992         BT_2WIRE = 0,
2993         BT_ISSC_3WIRE = 1,
2994         BT_ACCEL = 2,
2995         BT_CSR_BC4 = 3,
2996         BT_CSR_BC8 = 4,
2997         BT_RTL8756 = 5,
2998         BT_RTL8723A = 6,
2999         BT_RTL8821A = 7,
3000         BT_RTL8723B = 8,
3001         BT_RTL8192E = 9,
3002         BT_RTL8812A = 11,
3003         BT_RTL8822B = 12,
3004 };
3005
3006 enum bt_total_ant_num {
3007         ANT_TOTAL_X2 = 0,
3008         ANT_TOTAL_X1 = 1
3009 };
3010
3011 enum bt_cur_state {
3012         BT_OFF = 0,
3013         BT_ON = 1,
3014 };
3015
3016 enum bt_service_type {
3017         BT_SCO = 0,
3018         BT_A2DP = 1,
3019         BT_HID = 2,
3020         BT_HID_IDLE = 3,
3021         BT_SCAN = 4,
3022         BT_IDLE = 5,
3023         BT_OTHER_ACTION = 6,
3024         BT_BUSY = 7,
3025         BT_OTHERBUSY = 8,
3026         BT_PAN = 9,
3027 };
3028
3029 enum bt_radio_shared {
3030         BT_RADIO_SHARED = 0,
3031         BT_RADIO_INDIVIDUAL = 1,
3032 };
3033
3034 /****************************************
3035  *      mem access macro define start
3036  *      Call endian free function when
3037  *      1. Read/write packet content.
3038  *      2. Before write integer to IO.
3039  *      3. After read integer from IO.
3040  ***************************************/
3041 /* Convert little data endian to host ordering */
3042 #define EF1BYTE(_val)           \
3043         ((u8)(_val))
3044 #define EF2BYTE(_val)           \
3045         (le16_to_cpu(_val))
3046 #define EF4BYTE(_val)           \
3047         (le32_to_cpu(_val))
3048
3049 /* Read data from memory */
3050 #define READEF1BYTE(_ptr)      \
3051         EF1BYTE(*((u8 *)(_ptr)))
3052 /* Read le16 data from memory and convert to host ordering */
3053 #define READEF2BYTE(_ptr)      \
3054         EF2BYTE(*(_ptr))
3055 #define READEF4BYTE(_ptr)      \
3056         EF4BYTE(*(_ptr))
3057
3058 /* Create a bit mask
3059  * Examples:
3060  * BIT_LEN_MASK_32(0) => 0x00000000
3061  * BIT_LEN_MASK_32(1) => 0x00000001
3062  * BIT_LEN_MASK_32(2) => 0x00000003
3063  * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
3064  */
3065 #define BIT_LEN_MASK_32(__bitlen)        \
3066         (0xFFFFFFFF >> (32 - (__bitlen)))
3067 #define BIT_LEN_MASK_16(__bitlen)        \
3068         (0xFFFF >> (16 - (__bitlen)))
3069 #define BIT_LEN_MASK_8(__bitlen) \
3070         (0xFF >> (8 - (__bitlen)))
3071
3072 /* Create an offset bit mask
3073  * Examples:
3074  * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
3075  * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
3076  */
3077 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
3078         (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
3079 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
3080         (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
3081 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
3082         (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
3083
3084 /*Description:
3085  * Return 4-byte value in host byte ordering from
3086  * 4-byte pointer in little-endian system.
3087  */
3088 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
3089         (EF4BYTE(*((__le32 *)(__pstart))))
3090 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
3091         (EF2BYTE(*((__le16 *)(__pstart))))
3092 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
3093         (EF1BYTE(*((u8 *)(__pstart))))
3094
3095 /* Description:
3096  * Translate subfield (continuous bits in little-endian) of 4-byte
3097  * value to host byte ordering.
3098  */
3099 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
3100         ( \
3101                 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
3102                 BIT_LEN_MASK_32(__bitlen) \
3103         )
3104 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
3105         ( \
3106                 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
3107                 BIT_LEN_MASK_16(__bitlen) \
3108         )
3109 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
3110         ( \
3111                 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
3112                 BIT_LEN_MASK_8(__bitlen) \
3113         )
3114
3115 /* Description:
3116  * Mask subfield (continuous bits in little-endian) of 4-byte value
3117  * and return the result in 4-byte value in host byte ordering.
3118  */
3119 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
3120         ( \
3121                 LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
3122                 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
3123         )
3124 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
3125         ( \
3126                 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
3127                 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
3128         )
3129 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
3130         ( \
3131                 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
3132                 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
3133         )
3134
3135 /* Description:
3136  * Set subfield of little-endian 4-byte value to specified value.
3137  */
3138 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
3139         (*((__le32 *)(__pstart)) = \
3140         cpu_to_le32( \
3141                 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
3142                 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
3143         ))
3144 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
3145         (*((__le16 *)(__pstart)) = \
3146         cpu_to_le16( \
3147                 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
3148                 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
3149         ))
3150 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
3151         (*((u8 *)(__pstart)) = EF1BYTE \
3152         ( \
3153                 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
3154                 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
3155         ))
3156
3157 #define N_BYTE_ALIGNMENT(__value, __alignment) ((__alignment == 1) ? \
3158         (__value) : (((__value + __alignment - 1) /                 \
3159          __alignment) * __alignment))
3160
3161 /****************************************
3162  *      mem access macro define end
3163  ****************************************/
3164
3165 #define byte(x, n) ((x >> (8 * n)) & 0xff)
3166
3167 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
3168 #define RTL_WATCH_DOG_TIME      2000
3169 #define MSECS(t)                msecs_to_jiffies(t)
3170 #define WLAN_FC_GET_VERS(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
3171 #define WLAN_FC_GET_TYPE(fc)    (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
3172 #define WLAN_FC_GET_STYPE(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
3173 #define WLAN_FC_MORE_DATA(fc)   (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
3174 #define rtl_dm(rtlpriv)         (&((rtlpriv)->dm))
3175
3176 #define RT_RF_OFF_LEVL_ASPM             BIT(0)  /*PCI ASPM */
3177 #define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /*PCI clock request */
3178 #define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /*PCI D3 mode */
3179 /*NIC halt, re-initialize hw parameters*/
3180 #define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)
3181 #define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /*FW free, re-download the FW */
3182 #define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /*FW in 32k */
3183 /*Always enable ASPM and Clock Req in initialization.*/
3184 #define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)
3185 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
3186 #define RT_PS_LEVEL_ASPM                BIT(7)
3187 /*When LPS is on, disable 2R if no packet is received or transmitted.*/
3188 #define RT_RF_LPS_DISALBE_2R            BIT(30)
3189 #define RT_RF_LPS_LEVEL_ASPM            BIT(31) /*LPS with ASPM */
3190 #define RT_IN_PS_LEVEL(ppsc, _ps_flg)           \
3191         ((ppsc->cur_ps_level & _ps_flg) ? true : false)
3192 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)        \
3193         (ppsc->cur_ps_level &= (~(_ps_flg)))
3194 #define RT_SET_PS_LEVEL(ppsc, _ps_flg)          \
3195         (ppsc->cur_ps_level |= _ps_flg)
3196
3197 #define container_of_dwork_rtl(x, y, z) \
3198         container_of(to_delayed_work(x), y, z)
3199
3200 #define FILL_OCTET_STRING(_os, _octet, _len)    \
3201                 (_os).octet = (u8 *)(_octet);           \
3202                 (_os).length = (_len)
3203
3204 #define CP_MACADDR(des, src)    \
3205         ((des)[0] = (src)[0], (des)[1] = (src)[1],\
3206         (des)[2] = (src)[2], (des)[3] = (src)[3],\
3207         (des)[4] = (src)[4], (des)[5] = (src)[5])
3208
3209 #define LDPC_HT_ENABLE_RX                       BIT(0)
3210 #define LDPC_HT_ENABLE_TX                       BIT(1)
3211 #define LDPC_HT_TEST_TX_ENABLE                  BIT(2)
3212 #define LDPC_HT_CAP_TX                          BIT(3)
3213
3214 #define STBC_HT_ENABLE_RX                       BIT(0)
3215 #define STBC_HT_ENABLE_TX                       BIT(1)
3216 #define STBC_HT_TEST_TX_ENABLE                  BIT(2)
3217 #define STBC_HT_CAP_TX                          BIT(3)
3218
3219 #define LDPC_VHT_ENABLE_RX                      BIT(0)
3220 #define LDPC_VHT_ENABLE_TX                      BIT(1)
3221 #define LDPC_VHT_TEST_TX_ENABLE                 BIT(2)
3222 #define LDPC_VHT_CAP_TX                         BIT(3)
3223
3224 #define STBC_VHT_ENABLE_RX                      BIT(0)
3225 #define STBC_VHT_ENABLE_TX                      BIT(1)
3226 #define STBC_VHT_TEST_TX_ENABLE                 BIT(2)
3227 #define STBC_VHT_CAP_TX                         BIT(3)
3228
3229 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
3230
3231 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
3232
3233 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
3234 {
3235         return rtlpriv->io.read8_sync(rtlpriv, addr);
3236 }
3237
3238 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
3239 {
3240         return rtlpriv->io.read16_sync(rtlpriv, addr);
3241 }
3242
3243 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
3244 {
3245         return rtlpriv->io.read32_sync(rtlpriv, addr);
3246 }
3247
3248 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
3249 {
3250         rtlpriv->io.write8_async(rtlpriv, addr, val8);
3251
3252         if (rtlpriv->cfg->write_readback)
3253                 rtlpriv->io.read8_sync(rtlpriv, addr);
3254 }
3255
3256 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
3257                                              u32 addr, u32 val8)
3258 {
3259         struct rtl_priv *rtlpriv = rtl_priv(hw);
3260
3261         rtl_write_byte(rtlpriv, addr, (u8)val8);
3262 }
3263
3264 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
3265 {
3266         rtlpriv->io.write16_async(rtlpriv, addr, val16);
3267
3268         if (rtlpriv->cfg->write_readback)
3269                 rtlpriv->io.read16_sync(rtlpriv, addr);
3270 }
3271
3272 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
3273                                    u32 addr, u32 val32)
3274 {
3275         rtlpriv->io.write32_async(rtlpriv, addr, val32);
3276
3277         if (rtlpriv->cfg->write_readback)
3278                 rtlpriv->io.read32_sync(rtlpriv, addr);
3279 }
3280
3281 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
3282                                 u32 regaddr, u32 bitmask)
3283 {
3284         struct rtl_priv *rtlpriv = hw->priv;
3285
3286         return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
3287 }
3288
3289 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
3290                                  u32 bitmask, u32 data)
3291 {
3292         struct rtl_priv *rtlpriv = hw->priv;
3293
3294         rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
3295 }
3296
3297 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
3298                                              u32 regaddr, u32 data)
3299 {
3300         rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
3301 }
3302
3303 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
3304                                 enum radio_path rfpath, u32 regaddr,
3305                                 u32 bitmask)
3306 {
3307         struct rtl_priv *rtlpriv = hw->priv;
3308
3309         return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
3310 }
3311
3312 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
3313                                  enum radio_path rfpath, u32 regaddr,
3314                                  u32 bitmask, u32 data)
3315 {
3316         struct rtl_priv *rtlpriv = hw->priv;
3317
3318         rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
3319 }
3320
3321 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
3322 {
3323         return (rtlhal->state == _HAL_STATE_STOP);
3324 }
3325
3326 static inline void set_hal_start(struct rtl_hal *rtlhal)
3327 {
3328         rtlhal->state = _HAL_STATE_START;
3329 }
3330
3331 static inline void set_hal_stop(struct rtl_hal *rtlhal)
3332 {
3333         rtlhal->state = _HAL_STATE_STOP;
3334 }
3335
3336 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3337 {
3338         return rtlphy->rf_type;
3339 }
3340
3341 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3342 {
3343         return (struct ieee80211_hdr *)(skb->data);
3344 }
3345
3346 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3347 {
3348         return rtl_get_hdr(skb)->frame_control;
3349 }
3350
3351 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3352 {
3353         return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3354 }
3355
3356 static inline u16 rtl_get_tid(struct sk_buff *skb)
3357 {
3358         return rtl_get_tid_h(rtl_get_hdr(skb));
3359 }
3360
3361 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3362                                             struct ieee80211_vif *vif,
3363                                             const u8 *bssid)
3364 {
3365         return ieee80211_find_sta(vif, bssid);
3366 }
3367
3368 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3369                                                  u8 *mac_addr)
3370 {
3371         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3372
3373         return ieee80211_find_sta(mac->vif, mac_addr);
3374 }
3375
3376 #endif