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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / drivers / usb / dwc2 / hcd.c
blobfa20ec43a187673e7461d408d55b725bcfc611eb
1 /*
2 * hcd.c - DesignWare HS OTG Controller host-mode routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 /*
38 * This file contains the core HCD code, and implements the Linux hc_driver
39 * API
40 */
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/platform_device.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/delay.h>
48 #include <linux/io.h>
49 #include <linux/slab.h>
50 #include <linux/usb.h>
51
52 #include <linux/usb/hcd.h>
53 #include <linux/usb/ch11.h>
54
55 #include "core.h"
56 #include "hcd.h"
57
58 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
59
60 /*
61 * =========================================================================
62 * Host Core Layer Functions
63 * =========================================================================
64 */
65
66 /**
67 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
68 * used in both device and host modes
69 *
70 * @hsotg: Programming view of the DWC_otg controller
71 */
72 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
73 {
74 u32 intmsk;
75
76 /* Clear any pending OTG Interrupts */
77 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
78
79 /* Clear any pending interrupts */
80 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
81
82 /* Enable the interrupts in the GINTMSK */
83 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
84
85 if (!hsotg->params.host_dma)
86 intmsk |= GINTSTS_RXFLVL;
87 if (!hsotg->params.external_id_pin_ctl)
88 intmsk |= GINTSTS_CONIDSTSCHNG;
89
90 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
91 GINTSTS_SESSREQINT;
92
93 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
94 }
95
96 /*
97 * Initializes the FSLSPClkSel field of the HCFG register depending on the
98 * PHY type
99 */
100 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
101 {
102 u32 hcfg, val;
103
104 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
105 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
106 hsotg->params.ulpi_fs_ls) ||
107 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
108 /* Full speed PHY */
109 val = HCFG_FSLSPCLKSEL_48_MHZ;
110 } else {
111 /* High speed PHY running at full speed or high speed */
112 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
113 }
114
115 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
116 hcfg = dwc2_readl(hsotg->regs + HCFG);
117 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
118 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
119 dwc2_writel(hcfg, hsotg->regs + HCFG);
120 }
121
122 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
123 {
124 u32 usbcfg, ggpio, i2cctl;
125 int retval = 0;
126
127 /*
128 * core_init() is now called on every switch so only call the
129 * following for the first time through
130 */
131 if (select_phy) {
132 dev_dbg(hsotg->dev, "FS PHY selected\n");
133
134 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
135 if (!(usbcfg & GUSBCFG_PHYSEL)) {
136 usbcfg |= GUSBCFG_PHYSEL;
137 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
138
139 /* Reset after a PHY select */
140 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
141
142 if (retval) {
143 dev_err(hsotg->dev,
144 "%s: Reset failed, aborting", __func__);
145 return retval;
146 }
147 }
148
149 if (hsotg->params.activate_stm_fs_transceiver) {
150 ggpio = dwc2_readl(hsotg->regs + GGPIO);
151 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
152 dev_dbg(hsotg->dev, "Activating transceiver\n");
153 /*
154 * STM32F4x9 uses the GGPIO register as general
155 * core configuration register.
156 */
157 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
158 dwc2_writel(ggpio, hsotg->regs + GGPIO);
159 }
160 }
161 }
162
163 /*
164 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
165 * do this on HNP Dev/Host mode switches (done in dev_init and
166 * host_init).
167 */
168 if (dwc2_is_host_mode(hsotg))
169 dwc2_init_fs_ls_pclk_sel(hsotg);
170
171 if (hsotg->params.i2c_enable) {
172 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
173
174 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
175 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
176 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
177 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
178
179 /* Program GI2CCTL.I2CEn */
180 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
181 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
182 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
183 i2cctl &= ~GI2CCTL_I2CEN;
184 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
185 i2cctl |= GI2CCTL_I2CEN;
186 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
187 }
188
189 return retval;
190 }
191
192 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
193 {
194 u32 usbcfg, usbcfg_old;
195 int retval = 0;
196
197 if (!select_phy)
198 return 0;
199
200 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
201 usbcfg_old = usbcfg;
202
203 /*
204 * HS PHY parameters. These parameters are preserved during soft reset
205 * so only program the first time. Do a soft reset immediately after
206 * setting phyif.
207 */
208 switch (hsotg->params.phy_type) {
209 case DWC2_PHY_TYPE_PARAM_ULPI:
210 /* ULPI interface */
211 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
212 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
213 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
214 if (hsotg->params.phy_ulpi_ddr)
215 usbcfg |= GUSBCFG_DDRSEL;
216 break;
217 case DWC2_PHY_TYPE_PARAM_UTMI:
218 /* UTMI+ interface */
219 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
220 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
221 if (hsotg->params.phy_utmi_width == 16)
222 usbcfg |= GUSBCFG_PHYIF16;
223 break;
224 default:
225 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
226 break;
227 }
228
229 if (usbcfg != usbcfg_old) {
230 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
231
232 /* Reset after setting the PHY parameters */
233 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
234 if (retval) {
235 dev_err(hsotg->dev,
236 "%s: Reset failed, aborting", __func__);
237 return retval;
238 }
239 }
240
241 return retval;
242 }
243
244 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
245 {
246 u32 usbcfg;
247 int retval = 0;
248
249 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
250 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
251 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
252 /* If FS/LS mode with FS/LS PHY */
253 retval = dwc2_fs_phy_init(hsotg, select_phy);
254 if (retval)
255 return retval;
256 } else {
257 /* High speed PHY */
258 retval = dwc2_hs_phy_init(hsotg, select_phy);
259 if (retval)
260 return retval;
261 }
262
263 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
264 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
265 hsotg->params.ulpi_fs_ls) {
266 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
267 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
268 usbcfg |= GUSBCFG_ULPI_FS_LS;
269 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
270 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
271 } else {
272 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
273 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
274 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
275 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
276 }
277
278 return retval;
279 }
280
281 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
282 {
283 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
284
285 switch (hsotg->hw_params.arch) {
286 case GHWCFG2_EXT_DMA_ARCH:
287 dev_err(hsotg->dev, "External DMA Mode not supported\n");
288 return -EINVAL;
289
290 case GHWCFG2_INT_DMA_ARCH:
291 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
292 if (hsotg->params.ahbcfg != -1) {
293 ahbcfg &= GAHBCFG_CTRL_MASK;
294 ahbcfg |= hsotg->params.ahbcfg &
295 ~GAHBCFG_CTRL_MASK;
296 }
297 break;
298
299 case GHWCFG2_SLAVE_ONLY_ARCH:
300 default:
301 dev_dbg(hsotg->dev, "Slave Only Mode\n");
302 break;
303 }
304
305 dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n",
306 hsotg->params.host_dma,
307 hsotg->params.dma_desc_enable);
308
309 if (hsotg->params.host_dma) {
310 if (hsotg->params.dma_desc_enable)
311 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
312 else
313 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
314 } else {
315 dev_dbg(hsotg->dev, "Using Slave mode\n");
316 hsotg->params.dma_desc_enable = false;
317 }
318
319 if (hsotg->params.host_dma)
320 ahbcfg |= GAHBCFG_DMA_EN;
321
322 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
323
324 return 0;
325 }
326
327 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
328 {
329 u32 usbcfg;
330
331 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
332 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
333
334 switch (hsotg->hw_params.op_mode) {
335 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
336 if (hsotg->params.otg_cap ==
337 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
338 usbcfg |= GUSBCFG_HNPCAP;
339 if (hsotg->params.otg_cap !=
340 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
341 usbcfg |= GUSBCFG_SRPCAP;
342 break;
343
344 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
345 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
346 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
347 if (hsotg->params.otg_cap !=
348 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
349 usbcfg |= GUSBCFG_SRPCAP;
350 break;
351
352 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
353 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
354 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
355 default:
356 break;
357 }
358
359 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
360 }
361
362 /**
363 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
364 *
365 * @hsotg: Programming view of DWC_otg controller
366 */
367 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
368 {
369 u32 intmsk;
370
371 dev_dbg(hsotg->dev, "%s()\n", __func__);
372
373 /* Disable all interrupts */
374 dwc2_writel(0, hsotg->regs + GINTMSK);
375 dwc2_writel(0, hsotg->regs + HAINTMSK);
376
377 /* Enable the common interrupts */
378 dwc2_enable_common_interrupts(hsotg);
379
380 /* Enable host mode interrupts without disturbing common interrupts */
381 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
382 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
383 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
384 }
385
386 /**
387 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
388 *
389 * @hsotg: Programming view of DWC_otg controller
390 */
391 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
392 {
393 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
394
395 /* Disable host mode interrupts without disturbing common interrupts */
396 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
397 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
398 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
399 }
400
401 /*
402 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
403 * For system that have a total fifo depth that is smaller than the default
404 * RX + TX fifo size.
405 *
406 * @hsotg: Programming view of DWC_otg controller
407 */
408 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
409 {
410 struct dwc2_core_params *params = &hsotg->params;
411 struct dwc2_hw_params *hw = &hsotg->hw_params;
412 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
413
414 total_fifo_size = hw->total_fifo_size;
415 rxfsiz = params->host_rx_fifo_size;
416 nptxfsiz = params->host_nperio_tx_fifo_size;
417 ptxfsiz = params->host_perio_tx_fifo_size;
418
419 /*
420 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
421 * allocation with support for high bandwidth endpoints. Synopsys
422 * defines MPS(Max Packet size) for a periodic EP=1024, and for
423 * non-periodic as 512.
424 */
425 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
426 /*
427 * For Buffer DMA mode/Scatter Gather DMA mode
428 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
429 * with n = number of host channel.
430 * 2 * ((1024/4) + 2) = 516
431 */
432 rxfsiz = 516 + hw->host_channels;
433
434 /*
435 * min non-periodic tx fifo depth
436 * 2 * (largest non-periodic USB packet used / 4)
437 * 2 * (512/4) = 256
438 */
439 nptxfsiz = 256;
440
441 /*
442 * min periodic tx fifo depth
443 * (largest packet size*MC)/4
444 * (1024 * 3)/4 = 768
445 */
446 ptxfsiz = 768;
447
448 params->host_rx_fifo_size = rxfsiz;
449 params->host_nperio_tx_fifo_size = nptxfsiz;
450 params->host_perio_tx_fifo_size = ptxfsiz;
451 }
452
453 /*
454 * If the summation of RX, NPTX and PTX fifo sizes is still
455 * bigger than the total_fifo_size, then we have a problem.
456 *
457 * We won't be able to allocate as many endpoints. Right now,
458 * we're just printing an error message, but ideally this FIFO
459 * allocation algorithm would be improved in the future.
460 *
461 * FIXME improve this FIFO allocation algorithm.
462 */
463 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
464 dev_err(hsotg->dev, "invalid fifo sizes\n");
465 }
466
467 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
468 {
469 struct dwc2_core_params *params = &hsotg->params;
470 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
471
472 if (!params->enable_dynamic_fifo)
473 return;
474
475 dwc2_calculate_dynamic_fifo(hsotg);
476
477 /* Rx FIFO */
478 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
479 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
480 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
481 grxfsiz |= params->host_rx_fifo_size <<
482 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
483 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
484 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
485 dwc2_readl(hsotg->regs + GRXFSIZ));
486
487 /* Non-periodic Tx FIFO */
488 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
489 dwc2_readl(hsotg->regs + GNPTXFSIZ));
490 nptxfsiz = params->host_nperio_tx_fifo_size <<
491 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
492 nptxfsiz |= params->host_rx_fifo_size <<
493 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
494 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
495 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
496 dwc2_readl(hsotg->regs + GNPTXFSIZ));
497
498 /* Periodic Tx FIFO */
499 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
500 dwc2_readl(hsotg->regs + HPTXFSIZ));
501 hptxfsiz = params->host_perio_tx_fifo_size <<
502 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
503 hptxfsiz |= (params->host_rx_fifo_size +
504 params->host_nperio_tx_fifo_size) <<
505 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
506 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
507 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
508 dwc2_readl(hsotg->regs + HPTXFSIZ));
509
510 if (hsotg->params.en_multiple_tx_fifo &&
511 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
512 /*
513 * This feature was implemented in 2.91a version
514 * Global DFIFOCFG calculation for Host mode -
515 * include RxFIFO, NPTXFIFO and HPTXFIFO
516 */
517 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
518 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
519 dfifocfg |= (params->host_rx_fifo_size +
520 params->host_nperio_tx_fifo_size +
521 params->host_perio_tx_fifo_size) <<
522 GDFIFOCFG_EPINFOBASE_SHIFT &
523 GDFIFOCFG_EPINFOBASE_MASK;
524 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
525 }
526 }
527
528 /**
529 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
530 * the HFIR register according to PHY type and speed
531 *
532 * @hsotg: Programming view of DWC_otg controller
533 *
534 * NOTE: The caller can modify the value of the HFIR register only after the
535 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
536 * has been set
537 */
538 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
539 {
540 u32 usbcfg;
541 u32 hprt0;
542 int clock = 60; /* default value */
543
544 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
545 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
546
547 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
548 !(usbcfg & GUSBCFG_PHYIF16))
549 clock = 60;
550 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
551 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
552 clock = 48;
553 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
554 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
555 clock = 30;
556 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
557 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
558 clock = 60;
559 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
560 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
561 clock = 48;
562 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
563 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
564 clock = 48;
565 if ((usbcfg & GUSBCFG_PHYSEL) &&
566 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
567 clock = 48;
568
569 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
570 /* High speed case */
571 return 125 * clock - 1;
572
573 /* FS/LS case */
574 return 1000 * clock - 1;
575 }
576
577 /**
578 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
579 * buffer
580 *
581 * @core_if: Programming view of DWC_otg controller
582 * @dest: Destination buffer for the packet
583 * @bytes: Number of bytes to copy to the destination
584 */
585 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
586 {
587 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
588 u32 *data_buf = (u32 *)dest;
589 int word_count = (bytes + 3) / 4;
590 int i;
591
592 /*
593 * Todo: Account for the case where dest is not dword aligned. This
594 * requires reading data from the FIFO into a u32 temp buffer, then
595 * moving it into the data buffer.
596 */
597
598 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
599
600 for (i = 0; i < word_count; i++, data_buf++)
601 *data_buf = dwc2_readl(fifo);
602 }
603
604 /**
605 * dwc2_dump_channel_info() - Prints the state of a host channel
606 *
607 * @hsotg: Programming view of DWC_otg controller
608 * @chan: Pointer to the channel to dump
609 *
610 * Must be called with interrupt disabled and spinlock held
611 *
612 * NOTE: This function will be removed once the peripheral controller code
613 * is integrated and the driver is stable
614 */
615 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
616 struct dwc2_host_chan *chan)
617 {
618 #ifdef VERBOSE_DEBUG
619 int num_channels = hsotg->params.host_channels;
620 struct dwc2_qh *qh;
621 u32 hcchar;
622 u32 hcsplt;
623 u32 hctsiz;
624 u32 hc_dma;
625 int i;
626
627 if (!chan)
628 return;
629
630 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
631 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
632 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
633 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
634
635 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
636 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
637 hcchar, hcsplt);
638 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
639 hctsiz, hc_dma);
640 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
641 chan->dev_addr, chan->ep_num, chan->ep_is_in);
642 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
643 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
644 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
645 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
646 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
647 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
648 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
649 (unsigned long)chan->xfer_dma);
650 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
651 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
652 dev_dbg(hsotg->dev, " NP inactive sched:\n");
653 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
654 qh_list_entry)
655 dev_dbg(hsotg->dev, " %p\n", qh);
656 dev_dbg(hsotg->dev, " NP active sched:\n");
657 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
658 qh_list_entry)
659 dev_dbg(hsotg->dev, " %p\n", qh);
660 dev_dbg(hsotg->dev, " Channels:\n");
661 for (i = 0; i < num_channels; i++) {
662 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
663
664 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
665 }
666 #endif /* VERBOSE_DEBUG */
667 }
668
669 static int _dwc2_hcd_start(struct usb_hcd *hcd);
670
671 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
672 {
673 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
674
675 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
676 _dwc2_hcd_start(hcd);
677 }
678
679 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
680 {
681 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
682
683 hcd->self.is_b_host = 0;
684 }
685
686 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
687 int *hub_addr, int *hub_port)
688 {
689 struct urb *urb = context;
690
691 if (urb->dev->tt)
692 *hub_addr = urb->dev->tt->hub->devnum;
693 else
694 *hub_addr = 0;
695 *hub_port = urb->dev->ttport;
696 }
697
698 /*
699 * =========================================================================
700 * Low Level Host Channel Access Functions
701 * =========================================================================
702 */
703
704 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
705 struct dwc2_host_chan *chan)
706 {
707 u32 hcintmsk = HCINTMSK_CHHLTD;
708
709 switch (chan->ep_type) {
710 case USB_ENDPOINT_XFER_CONTROL:
711 case USB_ENDPOINT_XFER_BULK:
712 dev_vdbg(hsotg->dev, "control/bulk\n");
713 hcintmsk |= HCINTMSK_XFERCOMPL;
714 hcintmsk |= HCINTMSK_STALL;
715 hcintmsk |= HCINTMSK_XACTERR;
716 hcintmsk |= HCINTMSK_DATATGLERR;
717 if (chan->ep_is_in) {
718 hcintmsk |= HCINTMSK_BBLERR;
719 } else {
720 hcintmsk |= HCINTMSK_NAK;
721 hcintmsk |= HCINTMSK_NYET;
722 if (chan->do_ping)
723 hcintmsk |= HCINTMSK_ACK;
724 }
725
726 if (chan->do_split) {
727 hcintmsk |= HCINTMSK_NAK;
728 if (chan->complete_split)
729 hcintmsk |= HCINTMSK_NYET;
730 else
731 hcintmsk |= HCINTMSK_ACK;
732 }
733
734 if (chan->error_state)
735 hcintmsk |= HCINTMSK_ACK;
736 break;
737
738 case USB_ENDPOINT_XFER_INT:
739 if (dbg_perio())
740 dev_vdbg(hsotg->dev, "intr\n");
741 hcintmsk |= HCINTMSK_XFERCOMPL;
742 hcintmsk |= HCINTMSK_NAK;
743 hcintmsk |= HCINTMSK_STALL;
744 hcintmsk |= HCINTMSK_XACTERR;
745 hcintmsk |= HCINTMSK_DATATGLERR;
746 hcintmsk |= HCINTMSK_FRMOVRUN;
747
748 if (chan->ep_is_in)
749 hcintmsk |= HCINTMSK_BBLERR;
750 if (chan->error_state)
751 hcintmsk |= HCINTMSK_ACK;
752 if (chan->do_split) {
753 if (chan->complete_split)
754 hcintmsk |= HCINTMSK_NYET;
755 else
756 hcintmsk |= HCINTMSK_ACK;
757 }
758 break;
759
760 case USB_ENDPOINT_XFER_ISOC:
761 if (dbg_perio())
762 dev_vdbg(hsotg->dev, "isoc\n");
763 hcintmsk |= HCINTMSK_XFERCOMPL;
764 hcintmsk |= HCINTMSK_FRMOVRUN;
765 hcintmsk |= HCINTMSK_ACK;
766
767 if (chan->ep_is_in) {
768 hcintmsk |= HCINTMSK_XACTERR;
769 hcintmsk |= HCINTMSK_BBLERR;
770 }
771 break;
772 default:
773 dev_err(hsotg->dev, "## Unknown EP type ##\n");
774 break;
775 }
776
777 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
778 if (dbg_hc(chan))
779 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
780 }
781
782 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
783 struct dwc2_host_chan *chan)
784 {
785 u32 hcintmsk = HCINTMSK_CHHLTD;
786
787 /*
788 * For Descriptor DMA mode core halts the channel on AHB error.
789 * Interrupt is not required.
790 */
791 if (!hsotg->params.dma_desc_enable) {
792 if (dbg_hc(chan))
793 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
794 hcintmsk |= HCINTMSK_AHBERR;
795 } else {
796 if (dbg_hc(chan))
797 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
798 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
799 hcintmsk |= HCINTMSK_XFERCOMPL;
800 }
801
802 if (chan->error_state && !chan->do_split &&
803 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
804 if (dbg_hc(chan))
805 dev_vdbg(hsotg->dev, "setting ACK\n");
806 hcintmsk |= HCINTMSK_ACK;
807 if (chan->ep_is_in) {
808 hcintmsk |= HCINTMSK_DATATGLERR;
809 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
810 hcintmsk |= HCINTMSK_NAK;
811 }
812 }
813
814 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
815 if (dbg_hc(chan))
816 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
817 }
818
819 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
820 struct dwc2_host_chan *chan)
821 {
822 u32 intmsk;
823
824 if (hsotg->params.host_dma) {
825 if (dbg_hc(chan))
826 dev_vdbg(hsotg->dev, "DMA enabled\n");
827 dwc2_hc_enable_dma_ints(hsotg, chan);
828 } else {
829 if (dbg_hc(chan))
830 dev_vdbg(hsotg->dev, "DMA disabled\n");
831 dwc2_hc_enable_slave_ints(hsotg, chan);
832 }
833
834 /* Enable the top level host channel interrupt */
835 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
836 intmsk |= 1 << chan->hc_num;
837 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
838 if (dbg_hc(chan))
839 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
840
841 /* Make sure host channel interrupts are enabled */
842 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
843 intmsk |= GINTSTS_HCHINT;
844 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
845 if (dbg_hc(chan))
846 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
847 }
848
849 /**
850 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
851 * a specific endpoint
852 *
853 * @hsotg: Programming view of DWC_otg controller
854 * @chan: Information needed to initialize the host channel
855 *
856 * The HCCHARn register is set up with the characteristics specified in chan.
857 * Host channel interrupts that may need to be serviced while this transfer is
858 * in progress are enabled.
859 */
860 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
861 {
862 u8 hc_num = chan->hc_num;
863 u32 hcintmsk;
864 u32 hcchar;
865 u32 hcsplt = 0;
866
867 if (dbg_hc(chan))
868 dev_vdbg(hsotg->dev, "%s()\n", __func__);
869
870 /* Clear old interrupt conditions for this host channel */
871 hcintmsk = 0xffffffff;
872 hcintmsk &= ~HCINTMSK_RESERVED14_31;
873 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
874
875 /* Enable channel interrupts required for this transfer */
876 dwc2_hc_enable_ints(hsotg, chan);
877
878 /*
879 * Program the HCCHARn register with the endpoint characteristics for
880 * the current transfer
881 */
882 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
883 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
884 if (chan->ep_is_in)
885 hcchar |= HCCHAR_EPDIR;
886 if (chan->speed == USB_SPEED_LOW)
887 hcchar |= HCCHAR_LSPDDEV;
888 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
889 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
890 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
891 if (dbg_hc(chan)) {
892 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
893 hc_num, hcchar);
894
895 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
896 __func__, hc_num);
897 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
898 chan->dev_addr);
899 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
900 chan->ep_num);
901 dev_vdbg(hsotg->dev, " Is In: %d\n",
902 chan->ep_is_in);
903 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
904 chan->speed == USB_SPEED_LOW);
905 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
906 chan->ep_type);
907 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
908 chan->max_packet);
909 }
910
911 /* Program the HCSPLT register for SPLITs */
912 if (chan->do_split) {
913 if (dbg_hc(chan))
914 dev_vdbg(hsotg->dev,
915 "Programming HC %d with split --> %s\n",
916 hc_num,
917 chan->complete_split ? "CSPLIT" : "SSPLIT");
918 if (chan->complete_split)
919 hcsplt |= HCSPLT_COMPSPLT;
920 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
921 HCSPLT_XACTPOS_MASK;
922 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
923 HCSPLT_HUBADDR_MASK;
924 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
925 HCSPLT_PRTADDR_MASK;
926 if (dbg_hc(chan)) {
927 dev_vdbg(hsotg->dev, " comp split %d\n",
928 chan->complete_split);
929 dev_vdbg(hsotg->dev, " xact pos %d\n",
930 chan->xact_pos);
931 dev_vdbg(hsotg->dev, " hub addr %d\n",
932 chan->hub_addr);
933 dev_vdbg(hsotg->dev, " hub port %d\n",
934 chan->hub_port);
935 dev_vdbg(hsotg->dev, " is_in %d\n",
936 chan->ep_is_in);
937 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
938 chan->max_packet);
939 dev_vdbg(hsotg->dev, " xferlen %d\n",
940 chan->xfer_len);
941 }
942 }
943
944 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
945 }
946
947 /**
948 * dwc2_hc_halt() - Attempts to halt a host channel
949 *
950 * @hsotg: Controller register interface
951 * @chan: Host channel to halt
952 * @halt_status: Reason for halting the channel
953 *
954 * This function should only be called in Slave mode or to abort a transfer in
955 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
956 * controller halts the channel when the transfer is complete or a condition
957 * occurs that requires application intervention.
958 *
959 * In slave mode, checks for a free request queue entry, then sets the Channel
960 * Enable and Channel Disable bits of the Host Channel Characteristics
961 * register of the specified channel to intiate the halt. If there is no free
962 * request queue entry, sets only the Channel Disable bit of the HCCHARn
963 * register to flush requests for this channel. In the latter case, sets a
964 * flag to indicate that the host channel needs to be halted when a request
965 * queue slot is open.
966 *
967 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
968 * HCCHARn register. The controller ensures there is space in the request
969 * queue before submitting the halt request.
970 *
971 * Some time may elapse before the core flushes any posted requests for this
972 * host channel and halts. The Channel Halted interrupt handler completes the
973 * deactivation of the host channel.
974 */
975 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
976 enum dwc2_halt_status halt_status)
977 {
978 u32 nptxsts, hptxsts, hcchar;
979
980 if (dbg_hc(chan))
981 dev_vdbg(hsotg->dev, "%s()\n", __func__);
982
983 /*
984 * In buffer DMA or external DMA mode channel can't be halted
985 * for non-split periodic channels. At the end of the next
986 * uframe/frame (in the worst case), the core generates a channel
987 * halted and disables the channel automatically.
988 */
989 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
990 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
991 if (!chan->do_split &&
992 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
993 chan->ep_type == USB_ENDPOINT_XFER_INT)) {
994 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
995 __func__);
996 return;
997 }
998 }
999
1000 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1001 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1002
1003 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1004 halt_status == DWC2_HC_XFER_AHB_ERR) {
1005 /*
1006 * Disable all channel interrupts except Ch Halted. The QTD
1007 * and QH state associated with this transfer has been cleared
1008 * (in the case of URB_DEQUEUE), so the channel needs to be
1009 * shut down carefully to prevent crashes.
1010 */
1011 u32 hcintmsk = HCINTMSK_CHHLTD;
1012
1013 dev_vdbg(hsotg->dev, "dequeue/error\n");
1014 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1015
1016 /*
1017 * Make sure no other interrupts besides halt are currently
1018 * pending. Handling another interrupt could cause a crash due
1019 * to the QTD and QH state.
1020 */
1021 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1022
1023 /*
1024 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1025 * even if the channel was already halted for some other
1026 * reason
1027 */
1028 chan->halt_status = halt_status;
1029
1030 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1031 if (!(hcchar & HCCHAR_CHENA)) {
1032 /*
1033 * The channel is either already halted or it hasn't
1034 * started yet. In DMA mode, the transfer may halt if
1035 * it finishes normally or a condition occurs that
1036 * requires driver intervention. Don't want to halt
1037 * the channel again. In either Slave or DMA mode,
1038 * it's possible that the transfer has been assigned
1039 * to a channel, but not started yet when an URB is
1040 * dequeued. Don't want to halt a channel that hasn't
1041 * started yet.
1042 */
1043 return;
1044 }
1045 }
1046 if (chan->halt_pending) {
1047 /*
1048 * A halt has already been issued for this channel. This might
1049 * happen when a transfer is aborted by a higher level in
1050 * the stack.
1051 */
1052 dev_vdbg(hsotg->dev,
1053 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1054 __func__, chan->hc_num);
1055 return;
1056 }
1057
1058 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1059
1060 /* No need to set the bit in DDMA for disabling the channel */
1061 /* TODO check it everywhere channel is disabled */
1062 if (!hsotg->params.dma_desc_enable) {
1063 if (dbg_hc(chan))
1064 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1065 hcchar |= HCCHAR_CHENA;
1066 } else {
1067 if (dbg_hc(chan))
1068 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1069 }
1070 hcchar |= HCCHAR_CHDIS;
1071
1072 if (!hsotg->params.host_dma) {
1073 if (dbg_hc(chan))
1074 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1075 hcchar |= HCCHAR_CHENA;
1076
1077 /* Check for space in the request queue to issue the halt */
1078 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1079 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1080 dev_vdbg(hsotg->dev, "control/bulk\n");
1081 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1082 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1083 dev_vdbg(hsotg->dev, "Disabling channel\n");
1084 hcchar &= ~HCCHAR_CHENA;
1085 }
1086 } else {
1087 if (dbg_perio())
1088 dev_vdbg(hsotg->dev, "isoc/intr\n");
1089 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1090 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1091 hsotg->queuing_high_bandwidth) {
1092 if (dbg_perio())
1093 dev_vdbg(hsotg->dev, "Disabling channel\n");
1094 hcchar &= ~HCCHAR_CHENA;
1095 }
1096 }
1097 } else {
1098 if (dbg_hc(chan))
1099 dev_vdbg(hsotg->dev, "DMA enabled\n");
1100 }
1101
1102 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1103 chan->halt_status = halt_status;
1104
1105 if (hcchar & HCCHAR_CHENA) {
1106 if (dbg_hc(chan))
1107 dev_vdbg(hsotg->dev, "Channel enabled\n");
1108 chan->halt_pending = 1;
1109 chan->halt_on_queue = 0;
1110 } else {
1111 if (dbg_hc(chan))
1112 dev_vdbg(hsotg->dev, "Channel disabled\n");
1113 chan->halt_on_queue = 1;
1114 }
1115
1116 if (dbg_hc(chan)) {
1117 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1118 chan->hc_num);
1119 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1120 hcchar);
1121 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1122 chan->halt_pending);
1123 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1124 chan->halt_on_queue);
1125 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1126 chan->halt_status);
1127 }
1128 }
1129
1130 /**
1131 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1132 *
1133 * @hsotg: Programming view of DWC_otg controller
1134 * @chan: Identifies the host channel to clean up
1135 *
1136 * This function is normally called after a transfer is done and the host
1137 * channel is being released
1138 */
1139 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1140 {
1141 u32 hcintmsk;
1142
1143 chan->xfer_started = 0;
1144
1145 list_del_init(&chan->split_order_list_entry);
1146
1147 /*
1148 * Clear channel interrupt enables and any unhandled channel interrupt
1149 * conditions
1150 */
1151 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1152 hcintmsk = 0xffffffff;
1153 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1154 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1155 }
1156
1157 /**
1158 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1159 * which frame a periodic transfer should occur
1160 *
1161 * @hsotg: Programming view of DWC_otg controller
1162 * @chan: Identifies the host channel to set up and its properties
1163 * @hcchar: Current value of the HCCHAR register for the specified host channel
1164 *
1165 * This function has no effect on non-periodic transfers
1166 */
1167 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1168 struct dwc2_host_chan *chan, u32 *hcchar)
1169 {
1170 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1171 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1172 int host_speed;
1173 int xfer_ns;
1174 int xfer_us;
1175 int bytes_in_fifo;
1176 u16 fifo_space;
1177 u16 frame_number;
1178 u16 wire_frame;
1179
1180 /*
1181 * Try to figure out if we're an even or odd frame. If we set
1182 * even and the current frame number is even the the transfer
1183 * will happen immediately. Similar if both are odd. If one is
1184 * even and the other is odd then the transfer will happen when
1185 * the frame number ticks.
1186 *
1187 * There's a bit of a balancing act to get this right.
1188 * Sometimes we may want to send data in the current frame (AK
1189 * right away). We might want to do this if the frame number
1190 * _just_ ticked, but we might also want to do this in order
1191 * to continue a split transaction that happened late in a
1192 * microframe (so we didn't know to queue the next transfer
1193 * until the frame number had ticked). The problem is that we
1194 * need a lot of knowledge to know if there's actually still
1195 * time to send things or if it would be better to wait until
1196 * the next frame.
1197 *
1198 * We can look at how much time is left in the current frame
1199 * and make a guess about whether we'll have time to transfer.
1200 * We'll do that.
1201 */
1202
1203 /* Get speed host is running at */
1204 host_speed = (chan->speed != USB_SPEED_HIGH &&
1205 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1206
1207 /* See how many bytes are in the periodic FIFO right now */
1208 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1209 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1210 bytes_in_fifo = sizeof(u32) *
1211 (hsotg->params.host_perio_tx_fifo_size -
1212 fifo_space);
1213
1214 /*
1215 * Roughly estimate bus time for everything in the periodic
1216 * queue + our new transfer. This is "rough" because we're
1217 * using a function that makes takes into account IN/OUT
1218 * and INT/ISO and we're just slamming in one value for all
1219 * transfers. This should be an over-estimate and that should
1220 * be OK, but we can probably tighten it.
1221 */
1222 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1223 chan->xfer_len + bytes_in_fifo);
1224 xfer_us = NS_TO_US(xfer_ns);
1225
1226 /* See what frame number we'll be at by the time we finish */
1227 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1228
1229 /* This is when we were scheduled to be on the wire */
1230 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1231
1232 /*
1233 * If we'd finish _after_ the frame we're scheduled in then
1234 * it's hopeless. Just schedule right away and hope for the
1235 * best. Note that it _might_ be wise to call back into the
1236 * scheduler to pick a better frame, but this is better than
1237 * nothing.
1238 */
1239 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1240 dwc2_sch_vdbg(hsotg,
1241 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1242 chan->qh, wire_frame, frame_number,
1243 dwc2_frame_num_dec(frame_number,
1244 wire_frame));
1245 wire_frame = frame_number;
1246
1247 /*
1248 * We picked a different frame number; communicate this
1249 * back to the scheduler so it doesn't try to schedule
1250 * another in the same frame.
1251 *
1252 * Remember that next_active_frame is 1 before the wire
1253 * frame.
1254 */
1255 chan->qh->next_active_frame =
1256 dwc2_frame_num_dec(frame_number, 1);
1257 }
1258
1259 if (wire_frame & 1)
1260 *hcchar |= HCCHAR_ODDFRM;
1261 else
1262 *hcchar &= ~HCCHAR_ODDFRM;
1263 }
1264 }
1265
1266 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1267 {
1268 /* Set up the initial PID for the transfer */
1269 if (chan->speed == USB_SPEED_HIGH) {
1270 if (chan->ep_is_in) {
1271 if (chan->multi_count == 1)
1272 chan->data_pid_start = DWC2_HC_PID_DATA0;
1273 else if (chan->multi_count == 2)
1274 chan->data_pid_start = DWC2_HC_PID_DATA1;
1275 else
1276 chan->data_pid_start = DWC2_HC_PID_DATA2;
1277 } else {
1278 if (chan->multi_count == 1)
1279 chan->data_pid_start = DWC2_HC_PID_DATA0;
1280 else
1281 chan->data_pid_start = DWC2_HC_PID_MDATA;
1282 }
1283 } else {
1284 chan->data_pid_start = DWC2_HC_PID_DATA0;
1285 }
1286 }
1287
1288 /**
1289 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1290 * the Host Channel
1291 *
1292 * @hsotg: Programming view of DWC_otg controller
1293 * @chan: Information needed to initialize the host channel
1294 *
1295 * This function should only be called in Slave mode. For a channel associated
1296 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1297 * associated with a periodic EP, the periodic Tx FIFO is written.
1298 *
1299 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1300 * the number of bytes written to the Tx FIFO.
1301 */
1302 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1303 struct dwc2_host_chan *chan)
1304 {
1305 u32 i;
1306 u32 remaining_count;
1307 u32 byte_count;
1308 u32 dword_count;
1309 u32 __iomem *data_fifo;
1310 u32 *data_buf = (u32 *)chan->xfer_buf;
1311
1312 if (dbg_hc(chan))
1313 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1314
1315 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1316
1317 remaining_count = chan->xfer_len - chan->xfer_count;
1318 if (remaining_count > chan->max_packet)
1319 byte_count = chan->max_packet;
1320 else
1321 byte_count = remaining_count;
1322
1323 dword_count = (byte_count + 3) / 4;
1324
1325 if (((unsigned long)data_buf & 0x3) == 0) {
1326 /* xfer_buf is DWORD aligned */
1327 for (i = 0; i < dword_count; i++, data_buf++)
1328 dwc2_writel(*data_buf, data_fifo);
1329 } else {
1330 /* xfer_buf is not DWORD aligned */
1331 for (i = 0; i < dword_count; i++, data_buf++) {
1332 u32 data = data_buf[0] | data_buf[1] << 8 |
1333 data_buf[2] << 16 | data_buf[3] << 24;
1334 dwc2_writel(data, data_fifo);
1335 }
1336 }
1337
1338 chan->xfer_count += byte_count;
1339 chan->xfer_buf += byte_count;
1340 }
1341
1342 /**
1343 * dwc2_hc_do_ping() - Starts a PING transfer
1344 *
1345 * @hsotg: Programming view of DWC_otg controller
1346 * @chan: Information needed to initialize the host channel
1347 *
1348 * This function should only be called in Slave mode. The Do Ping bit is set in
1349 * the HCTSIZ register, then the channel is enabled.
1350 */
1351 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1352 struct dwc2_host_chan *chan)
1353 {
1354 u32 hcchar;
1355 u32 hctsiz;
1356
1357 if (dbg_hc(chan))
1358 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1359 chan->hc_num);
1360
1361 hctsiz = TSIZ_DOPNG;
1362 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1363 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1364
1365 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1366 hcchar |= HCCHAR_CHENA;
1367 hcchar &= ~HCCHAR_CHDIS;
1368 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1369 }
1370
1371 /**
1372 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1373 * channel and starts the transfer
1374 *
1375 * @hsotg: Programming view of DWC_otg controller
1376 * @chan: Information needed to initialize the host channel. The xfer_len value
1377 * may be reduced to accommodate the max widths of the XferSize and
1378 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1379 * changed to reflect the final xfer_len value.
1380 *
1381 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1382 * the caller must ensure that there is sufficient space in the request queue
1383 * and Tx Data FIFO.
1384 *
1385 * For an OUT transfer in Slave mode, it loads a data packet into the
1386 * appropriate FIFO. If necessary, additional data packets are loaded in the
1387 * Host ISR.
1388 *
1389 * For an IN transfer in Slave mode, a data packet is requested. The data
1390 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1391 * additional data packets are requested in the Host ISR.
1392 *
1393 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1394 * register along with a packet count of 1 and the channel is enabled. This
1395 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1396 * simply set to 0 since no data transfer occurs in this case.
1397 *
1398 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1399 * all the information required to perform the subsequent data transfer. In
1400 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1401 * controller performs the entire PING protocol, then starts the data
1402 * transfer.
1403 */
1404 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1405 struct dwc2_host_chan *chan)
1406 {
1407 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1408 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1409 u32 hcchar;
1410 u32 hctsiz = 0;
1411 u16 num_packets;
1412 u32 ec_mc;
1413
1414 if (dbg_hc(chan))
1415 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1416
1417 if (chan->do_ping) {
1418 if (!hsotg->params.host_dma) {
1419 if (dbg_hc(chan))
1420 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1421 dwc2_hc_do_ping(hsotg, chan);
1422 chan->xfer_started = 1;
1423 return;
1424 }
1425
1426 if (dbg_hc(chan))
1427 dev_vdbg(hsotg->dev, "ping, DMA\n");
1428
1429 hctsiz |= TSIZ_DOPNG;
1430 }
1431
1432 if (chan->do_split) {
1433 if (dbg_hc(chan))
1434 dev_vdbg(hsotg->dev, "split\n");
1435 num_packets = 1;
1436
1437 if (chan->complete_split && !chan->ep_is_in)
1438 /*
1439 * For CSPLIT OUT Transfer, set the size to 0 so the
1440 * core doesn't expect any data written to the FIFO
1441 */
1442 chan->xfer_len = 0;
1443 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1444 chan->xfer_len = chan->max_packet;
1445 else if (!chan->ep_is_in && chan->xfer_len > 188)
1446 chan->xfer_len = 188;
1447
1448 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1449 TSIZ_XFERSIZE_MASK;
1450
1451 /* For split set ec_mc for immediate retries */
1452 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1453 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1454 ec_mc = 3;
1455 else
1456 ec_mc = 1;
1457 } else {
1458 if (dbg_hc(chan))
1459 dev_vdbg(hsotg->dev, "no split\n");
1460 /*
1461 * Ensure that the transfer length and packet count will fit
1462 * in the widths allocated for them in the HCTSIZn register
1463 */
1464 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1465 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1466 /*
1467 * Make sure the transfer size is no larger than one
1468 * (micro)frame's worth of data. (A check was done
1469 * when the periodic transfer was accepted to ensure
1470 * that a (micro)frame's worth of data can be
1471 * programmed into a channel.)
1472 */
1473 u32 max_periodic_len =
1474 chan->multi_count * chan->max_packet;
1475
1476 if (chan->xfer_len > max_periodic_len)
1477 chan->xfer_len = max_periodic_len;
1478 } else if (chan->xfer_len > max_hc_xfer_size) {
1479 /*
1480 * Make sure that xfer_len is a multiple of max packet
1481 * size
1482 */
1483 chan->xfer_len =
1484 max_hc_xfer_size - chan->max_packet + 1;
1485 }
1486
1487 if (chan->xfer_len > 0) {
1488 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1489 chan->max_packet;
1490 if (num_packets > max_hc_pkt_count) {
1491 num_packets = max_hc_pkt_count;
1492 chan->xfer_len = num_packets * chan->max_packet;
1493 }
1494 } else {
1495 /* Need 1 packet for transfer length of 0 */
1496 num_packets = 1;
1497 }
1498
1499 if (chan->ep_is_in)
1500 /*
1501 * Always program an integral # of max packets for IN
1502 * transfers
1503 */
1504 chan->xfer_len = num_packets * chan->max_packet;
1505
1506 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1507 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1508 /*
1509 * Make sure that the multi_count field matches the
1510 * actual transfer length
1511 */
1512 chan->multi_count = num_packets;
1513
1514 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1515 dwc2_set_pid_isoc(chan);
1516
1517 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1518 TSIZ_XFERSIZE_MASK;
1519
1520 /* The ec_mc gets the multi_count for non-split */
1521 ec_mc = chan->multi_count;
1522 }
1523
1524 chan->start_pkt_count = num_packets;
1525 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1526 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1527 TSIZ_SC_MC_PID_MASK;
1528 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1529 if (dbg_hc(chan)) {
1530 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1531 hctsiz, chan->hc_num);
1532
1533 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1534 chan->hc_num);
1535 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1536 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1537 TSIZ_XFERSIZE_SHIFT);
1538 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1539 (hctsiz & TSIZ_PKTCNT_MASK) >>
1540 TSIZ_PKTCNT_SHIFT);
1541 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1542 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1543 TSIZ_SC_MC_PID_SHIFT);
1544 }
1545
1546 if (hsotg->params.host_dma) {
1547 dma_addr_t dma_addr;
1548
1549 if (chan->align_buf) {
1550 if (dbg_hc(chan))
1551 dev_vdbg(hsotg->dev, "align_buf\n");
1552 dma_addr = chan->align_buf;
1553 } else {
1554 dma_addr = chan->xfer_dma;
1555 }
1556 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1557
1558 if (dbg_hc(chan))
1559 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1560 (unsigned long)dma_addr, chan->hc_num);
1561 }
1562
1563 /* Start the split */
1564 if (chan->do_split) {
1565 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1566
1567 hcsplt |= HCSPLT_SPLTENA;
1568 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1569 }
1570
1571 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1572 hcchar &= ~HCCHAR_MULTICNT_MASK;
1573 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1574 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1575
1576 if (hcchar & HCCHAR_CHDIS)
1577 dev_warn(hsotg->dev,
1578 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1579 __func__, chan->hc_num, hcchar);
1580
1581 /* Set host channel enable after all other setup is complete */
1582 hcchar |= HCCHAR_CHENA;
1583 hcchar &= ~HCCHAR_CHDIS;
1584
1585 if (dbg_hc(chan))
1586 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1587 (hcchar & HCCHAR_MULTICNT_MASK) >>
1588 HCCHAR_MULTICNT_SHIFT);
1589
1590 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1591 if (dbg_hc(chan))
1592 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1593 chan->hc_num);
1594
1595 chan->xfer_started = 1;
1596 chan->requests++;
1597
1598 if (!hsotg->params.host_dma &&
1599 !chan->ep_is_in && chan->xfer_len > 0)
1600 /* Load OUT packet into the appropriate Tx FIFO */
1601 dwc2_hc_write_packet(hsotg, chan);
1602 }
1603
1604 /**
1605 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1606 * host channel and starts the transfer in Descriptor DMA mode
1607 *
1608 * @hsotg: Programming view of DWC_otg controller
1609 * @chan: Information needed to initialize the host channel
1610 *
1611 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1612 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1613 * with micro-frame bitmap.
1614 *
1615 * Initializes HCDMA register with descriptor list address and CTD value then
1616 * starts the transfer via enabling the channel.
1617 */
1618 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1619 struct dwc2_host_chan *chan)
1620 {
1621 u32 hcchar;
1622 u32 hctsiz = 0;
1623
1624 if (chan->do_ping)
1625 hctsiz |= TSIZ_DOPNG;
1626
1627 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1628 dwc2_set_pid_isoc(chan);
1629
1630 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1631 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1632 TSIZ_SC_MC_PID_MASK;
1633
1634 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1635 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1636
1637 /* Non-zero only for high-speed interrupt endpoints */
1638 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1639
1640 if (dbg_hc(chan)) {
1641 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1642 chan->hc_num);
1643 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1644 chan->data_pid_start);
1645 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1646 }
1647
1648 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1649
1650 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1651 chan->desc_list_sz, DMA_TO_DEVICE);
1652
1653 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1654
1655 if (dbg_hc(chan))
1656 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1657 &chan->desc_list_addr, chan->hc_num);
1658
1659 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1660 hcchar &= ~HCCHAR_MULTICNT_MASK;
1661 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1662 HCCHAR_MULTICNT_MASK;
1663
1664 if (hcchar & HCCHAR_CHDIS)
1665 dev_warn(hsotg->dev,
1666 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1667 __func__, chan->hc_num, hcchar);
1668
1669 /* Set host channel enable after all other setup is complete */
1670 hcchar |= HCCHAR_CHENA;
1671 hcchar &= ~HCCHAR_CHDIS;
1672
1673 if (dbg_hc(chan))
1674 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1675 (hcchar & HCCHAR_MULTICNT_MASK) >>
1676 HCCHAR_MULTICNT_SHIFT);
1677
1678 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1679 if (dbg_hc(chan))
1680 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1681 chan->hc_num);
1682
1683 chan->xfer_started = 1;
1684 chan->requests++;
1685 }
1686
1687 /**
1688 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1689 * a previous call to dwc2_hc_start_transfer()
1690 *
1691 * @hsotg: Programming view of DWC_otg controller
1692 * @chan: Information needed to initialize the host channel
1693 *
1694 * The caller must ensure there is sufficient space in the request queue and Tx
1695 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1696 * the controller acts autonomously to complete transfers programmed to a host
1697 * channel.
1698 *
1699 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1700 * if there is any data remaining to be queued. For an IN transfer, another
1701 * data packet is always requested. For the SETUP phase of a control transfer,
1702 * this function does nothing.
1703 *
1704 * Return: 1 if a new request is queued, 0 if no more requests are required
1705 * for this transfer
1706 */
1707 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1708 struct dwc2_host_chan *chan)
1709 {
1710 if (dbg_hc(chan))
1711 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1712 chan->hc_num);
1713
1714 if (chan->do_split)
1715 /* SPLITs always queue just once per channel */
1716 return 0;
1717
1718 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1719 /* SETUPs are queued only once since they can't be NAK'd */
1720 return 0;
1721
1722 if (chan->ep_is_in) {
1723 /*
1724 * Always queue another request for other IN transfers. If
1725 * back-to-back INs are issued and NAKs are received for both,
1726 * the driver may still be processing the first NAK when the
1727 * second NAK is received. When the interrupt handler clears
1728 * the NAK interrupt for the first NAK, the second NAK will
1729 * not be seen. So we can't depend on the NAK interrupt
1730 * handler to requeue a NAK'd request. Instead, IN requests
1731 * are issued each time this function is called. When the
1732 * transfer completes, the extra requests for the channel will
1733 * be flushed.
1734 */
1735 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1736
1737 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1738 hcchar |= HCCHAR_CHENA;
1739 hcchar &= ~HCCHAR_CHDIS;
1740 if (dbg_hc(chan))
1741 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1742 hcchar);
1743 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1744 chan->requests++;
1745 return 1;
1746 }
1747
1748 /* OUT transfers */
1749
1750 if (chan->xfer_count < chan->xfer_len) {
1751 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1752 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1753 u32 hcchar = dwc2_readl(hsotg->regs +
1754 HCCHAR(chan->hc_num));
1755
1756 dwc2_hc_set_even_odd_frame(hsotg, chan,
1757 &hcchar);
1758 }
1759
1760 /* Load OUT packet into the appropriate Tx FIFO */
1761 dwc2_hc_write_packet(hsotg, chan);
1762 chan->requests++;
1763 return 1;
1764 }
1765
1766 return 0;
1767 }
1768
1769 /*
1770 * =========================================================================
1771 * HCD
1772 * =========================================================================
1773 */
1774
1775 /*
1776 * Processes all the URBs in a single list of QHs. Completes them with
1777 * -ETIMEDOUT and frees the QTD.
1778 *
1779 * Must be called with interrupt disabled and spinlock held
1780 */
1781 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1782 struct list_head *qh_list)
1783 {
1784 struct dwc2_qh *qh, *qh_tmp;
1785 struct dwc2_qtd *qtd, *qtd_tmp;
1786
1787 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1788 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1789 qtd_list_entry) {
1790 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1791 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1792 }
1793 }
1794 }
1795
1796 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1797 struct list_head *qh_list)
1798 {
1799 struct dwc2_qtd *qtd, *qtd_tmp;
1800 struct dwc2_qh *qh, *qh_tmp;
1801 unsigned long flags;
1802
1803 if (!qh_list->next)
1804 /* The list hasn't been initialized yet */
1805 return;
1806
1807 spin_lock_irqsave(&hsotg->lock, flags);
1808
1809 /* Ensure there are no QTDs or URBs left */
1810 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1811
1812 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1813 dwc2_hcd_qh_unlink(hsotg, qh);
1814
1815 /* Free each QTD in the QH's QTD list */
1816 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1817 qtd_list_entry)
1818 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1819
1820 if (qh->channel && qh->channel->qh == qh)
1821 qh->channel->qh = NULL;
1822
1823 spin_unlock_irqrestore(&hsotg->lock, flags);
1824 dwc2_hcd_qh_free(hsotg, qh);
1825 spin_lock_irqsave(&hsotg->lock, flags);
1826 }
1827
1828 spin_unlock_irqrestore(&hsotg->lock, flags);
1829 }
1830
1831 /*
1832 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1833 * and periodic schedules. The QTD associated with each URB is removed from
1834 * the schedule and freed. This function may be called when a disconnect is
1835 * detected or when the HCD is being stopped.
1836 *
1837 * Must be called with interrupt disabled and spinlock held
1838 */
1839 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1840 {
1841 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1842 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1843 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1844 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1845 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1846 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1847 }
1848
1849 /**
1850 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1851 *
1852 * @hsotg: Pointer to struct dwc2_hsotg
1853 */
1854 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1855 {
1856 u32 hprt0;
1857
1858 if (hsotg->op_state == OTG_STATE_B_HOST) {
1859 /*
1860 * Reset the port. During a HNP mode switch the reset
1861 * needs to occur within 1ms and have a duration of at
1862 * least 50ms.
1863 */
1864 hprt0 = dwc2_read_hprt0(hsotg);
1865 hprt0 |= HPRT0_RST;
1866 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1867 }
1868
1869 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1870 msecs_to_jiffies(50));
1871 }
1872
1873 /* Must be called with interrupt disabled and spinlock held */
1874 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1875 {
1876 int num_channels = hsotg->params.host_channels;
1877 struct dwc2_host_chan *channel;
1878 u32 hcchar;
1879 int i;
1880
1881 if (!hsotg->params.host_dma) {
1882 /* Flush out any channel requests in slave mode */
1883 for (i = 0; i < num_channels; i++) {
1884 channel = hsotg->hc_ptr_array[i];
1885 if (!list_empty(&channel->hc_list_entry))
1886 continue;
1887 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1888 if (hcchar & HCCHAR_CHENA) {
1889 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1890 hcchar |= HCCHAR_CHDIS;
1891 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1892 }
1893 }
1894 }
1895
1896 for (i = 0; i < num_channels; i++) {
1897 channel = hsotg->hc_ptr_array[i];
1898 if (!list_empty(&channel->hc_list_entry))
1899 continue;
1900 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1901 if (hcchar & HCCHAR_CHENA) {
1902 /* Halt the channel */
1903 hcchar |= HCCHAR_CHDIS;
1904 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1905 }
1906
1907 dwc2_hc_cleanup(hsotg, channel);
1908 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1909 /*
1910 * Added for Descriptor DMA to prevent channel double cleanup in
1911 * release_channel_ddma(), which is called from ep_disable when
1912 * device disconnects
1913 */
1914 channel->qh = NULL;
1915 }
1916 /* All channels have been freed, mark them available */
1917 if (hsotg->params.uframe_sched) {
1918 hsotg->available_host_channels =
1919 hsotg->params.host_channels;
1920 } else {
1921 hsotg->non_periodic_channels = 0;
1922 hsotg->periodic_channels = 0;
1923 }
1924 }
1925
1926 /**
1927 * dwc2_hcd_connect() - Handles connect of the HCD
1928 *
1929 * @hsotg: Pointer to struct dwc2_hsotg
1930 *
1931 * Must be called with interrupt disabled and spinlock held
1932 */
1933 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1934 {
1935 if (hsotg->lx_state != DWC2_L0)
1936 usb_hcd_resume_root_hub(hsotg->priv);
1937
1938 hsotg->flags.b.port_connect_status_change = 1;
1939 hsotg->flags.b.port_connect_status = 1;
1940 }
1941
1942 /**
1943 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1944 *
1945 * @hsotg: Pointer to struct dwc2_hsotg
1946 * @force: If true, we won't try to reconnect even if we see device connected.
1947 *
1948 * Must be called with interrupt disabled and spinlock held
1949 */
1950 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1951 {
1952 u32 intr;
1953 u32 hprt0;
1954
1955 /* Set status flags for the hub driver */
1956 hsotg->flags.b.port_connect_status_change = 1;
1957 hsotg->flags.b.port_connect_status = 0;
1958
1959 /*
1960 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1961 * interrupt mask and status bits and disabling subsequent host
1962 * channel interrupts.
1963 */
1964 intr = dwc2_readl(hsotg->regs + GINTMSK);
1965 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1966 dwc2_writel(intr, hsotg->regs + GINTMSK);
1967 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1968 dwc2_writel(intr, hsotg->regs + GINTSTS);
1969
1970 /*
1971 * Turn off the vbus power only if the core has transitioned to device
1972 * mode. If still in host mode, need to keep power on to detect a
1973 * reconnection.
1974 */
1975 if (dwc2_is_device_mode(hsotg)) {
1976 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1977 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1978 dwc2_writel(0, hsotg->regs + HPRT0);
1979 }
1980
1981 dwc2_disable_host_interrupts(hsotg);
1982 }
1983
1984 /* Respond with an error status to all URBs in the schedule */
1985 dwc2_kill_all_urbs(hsotg);
1986
1987 if (dwc2_is_host_mode(hsotg))
1988 /* Clean up any host channels that were in use */
1989 dwc2_hcd_cleanup_channels(hsotg);
1990
1991 dwc2_host_disconnect(hsotg);
1992
1993 /*
1994 * Add an extra check here to see if we're actually connected but
1995 * we don't have a detection interrupt pending. This can happen if:
1996 * 1. hardware sees connect
1997 * 2. hardware sees disconnect
1998 * 3. hardware sees connect
1999 * 4. dwc2_port_intr() - clears connect interrupt
2000 * 5. dwc2_handle_common_intr() - calls here
2001 *
2002 * Without the extra check here we will end calling disconnect
2003 * and won't get any future interrupts to handle the connect.
2004 */
2005 if (!force) {
2006 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2007 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2008 dwc2_hcd_connect(hsotg);
2009 }
2010 }
2011
2012 /**
2013 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
2014 *
2015 * @hsotg: Pointer to struct dwc2_hsotg
2016 */
2017 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
2018 {
2019 if (hsotg->bus_suspended) {
2020 hsotg->flags.b.port_suspend_change = 1;
2021 usb_hcd_resume_root_hub(hsotg->priv);
2022 }
2023
2024 if (hsotg->lx_state == DWC2_L1)
2025 hsotg->flags.b.port_l1_change = 1;
2026 }
2027
2028 /**
2029 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2030 *
2031 * @hsotg: Pointer to struct dwc2_hsotg
2032 *
2033 * Must be called with interrupt disabled and spinlock held
2034 */
2035 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2036 {
2037 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
2038
2039 /*
2040 * The root hub should be disconnected before this function is called.
2041 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2042 * and the QH lists (via ..._hcd_endpoint_disable).
2043 */
2044
2045 /* Turn off all host-specific interrupts */
2046 dwc2_disable_host_interrupts(hsotg);
2047
2048 /* Turn off the vbus power */
2049 dev_dbg(hsotg->dev, "PortPower off\n");
2050 dwc2_writel(0, hsotg->regs + HPRT0);
2051 }
2052
2053 /* Caller must hold driver lock */
2054 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2055 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2056 struct dwc2_qtd *qtd)
2057 {
2058 u32 intr_mask;
2059 int retval;
2060 int dev_speed;
2061
2062 if (!hsotg->flags.b.port_connect_status) {
2063 /* No longer connected */
2064 dev_err(hsotg->dev, "Not connected\n");
2065 return -ENODEV;
2066 }
2067
2068 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2069
2070 /* Some configurations cannot support LS traffic on a FS root port */
2071 if ((dev_speed == USB_SPEED_LOW) &&
2072 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2073 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2074 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2075 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2076
2077 if (prtspd == HPRT0_SPD_FULL_SPEED)
2078 return -ENODEV;
2079 }
2080
2081 if (!qtd)
2082 return -EINVAL;
2083
2084 dwc2_hcd_qtd_init(qtd, urb);
2085 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2086 if (retval) {
2087 dev_err(hsotg->dev,
2088 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2089 retval);
2090 return retval;
2091 }
2092
2093 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2094 if (!(intr_mask & GINTSTS_SOF)) {
2095 enum dwc2_transaction_type tr_type;
2096
2097 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2098 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2099 /*
2100 * Do not schedule SG transactions until qtd has
2101 * URB_GIVEBACK_ASAP set
2102 */
2103 return 0;
2104
2105 tr_type = dwc2_hcd_select_transactions(hsotg);
2106 if (tr_type != DWC2_TRANSACTION_NONE)
2107 dwc2_hcd_queue_transactions(hsotg, tr_type);
2108 }
2109
2110 return 0;
2111 }
2112
2113 /* Must be called with interrupt disabled and spinlock held */
2114 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2115 struct dwc2_hcd_urb *urb)
2116 {
2117 struct dwc2_qh *qh;
2118 struct dwc2_qtd *urb_qtd;
2119
2120 urb_qtd = urb->qtd;
2121 if (!urb_qtd) {
2122 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2123 return -EINVAL;
2124 }
2125
2126 qh = urb_qtd->qh;
2127 if (!qh) {
2128 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2129 return -EINVAL;
2130 }
2131
2132 urb->priv = NULL;
2133
2134 if (urb_qtd->in_process && qh->channel) {
2135 dwc2_dump_channel_info(hsotg, qh->channel);
2136
2137 /* The QTD is in process (it has been assigned to a channel) */
2138 if (hsotg->flags.b.port_connect_status)
2139 /*
2140 * If still connected (i.e. in host mode), halt the
2141 * channel so it can be used for other transfers. If
2142 * no longer connected, the host registers can't be
2143 * written to halt the channel since the core is in
2144 * device mode.
2145 */
2146 dwc2_hc_halt(hsotg, qh->channel,
2147 DWC2_HC_XFER_URB_DEQUEUE);
2148 }
2149
2150 /*
2151 * Free the QTD and clean up the associated QH. Leave the QH in the
2152 * schedule if it has any remaining QTDs.
2153 */
2154 if (!hsotg->params.dma_desc_enable) {
2155 u8 in_process = urb_qtd->in_process;
2156
2157 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2158 if (in_process) {
2159 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2160 qh->channel = NULL;
2161 } else if (list_empty(&qh->qtd_list)) {
2162 dwc2_hcd_qh_unlink(hsotg, qh);
2163 }
2164 } else {
2165 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2166 }
2167
2168 return 0;
2169 }
2170
2171 /* Must NOT be called with interrupt disabled or spinlock held */
2172 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2173 struct usb_host_endpoint *ep, int retry)
2174 {
2175 struct dwc2_qtd *qtd, *qtd_tmp;
2176 struct dwc2_qh *qh;
2177 unsigned long flags;
2178 int rc;
2179
2180 spin_lock_irqsave(&hsotg->lock, flags);
2181
2182 qh = ep->hcpriv;
2183 if (!qh) {
2184 rc = -EINVAL;
2185 goto err;
2186 }
2187
2188 while (!list_empty(&qh->qtd_list) && retry--) {
2189 if (retry == 0) {
2190 dev_err(hsotg->dev,
2191 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2192 rc = -EBUSY;
2193 goto err;
2194 }
2195
2196 spin_unlock_irqrestore(&hsotg->lock, flags);
2197 msleep(20);
2198 spin_lock_irqsave(&hsotg->lock, flags);
2199 qh = ep->hcpriv;
2200 if (!qh) {
2201 rc = -EINVAL;
2202 goto err;
2203 }
2204 }
2205
2206 dwc2_hcd_qh_unlink(hsotg, qh);
2207
2208 /* Free each QTD in the QH's QTD list */
2209 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2210 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2211
2212 ep->hcpriv = NULL;
2213
2214 if (qh->channel && qh->channel->qh == qh)
2215 qh->channel->qh = NULL;
2216
2217 spin_unlock_irqrestore(&hsotg->lock, flags);
2218
2219 dwc2_hcd_qh_free(hsotg, qh);
2220
2221 return 0;
2222
2223 err:
2224 ep->hcpriv = NULL;
2225 spin_unlock_irqrestore(&hsotg->lock, flags);
2226
2227 return rc;
2228 }
2229
2230 /* Must be called with interrupt disabled and spinlock held */
2231 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2232 struct usb_host_endpoint *ep)
2233 {
2234 struct dwc2_qh *qh = ep->hcpriv;
2235
2236 if (!qh)
2237 return -EINVAL;
2238
2239 qh->data_toggle = DWC2_HC_PID_DATA0;
2240
2241 return 0;
2242 }
2243
2244 /**
2245 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2246 * prepares the core for device mode or host mode operation
2247 *
2248 * @hsotg: Programming view of the DWC_otg controller
2249 * @initial_setup: If true then this is the first init for this instance.
2250 */
2251 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2252 {
2253 u32 usbcfg, otgctl;
2254 int retval;
2255
2256 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2257
2258 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2259
2260 /* Set ULPI External VBUS bit if needed */
2261 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2262 if (hsotg->params.phy_ulpi_ext_vbus)
2263 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2264
2265 /* Set external TS Dline pulsing bit if needed */
2266 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2267 if (hsotg->params.ts_dline)
2268 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2269
2270 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2271
2272 /*
2273 * Reset the Controller
2274 *
2275 * We only need to reset the controller if this is a re-init.
2276 * For the first init we know for sure that earlier code reset us (it
2277 * needed to in order to properly detect various parameters).
2278 */
2279 if (!initial_setup) {
2280 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
2281 if (retval) {
2282 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2283 __func__);
2284 return retval;
2285 }
2286 }
2287
2288 /*
2289 * This needs to happen in FS mode before any other programming occurs
2290 */
2291 retval = dwc2_phy_init(hsotg, initial_setup);
2292 if (retval)
2293 return retval;
2294
2295 /* Program the GAHBCFG Register */
2296 retval = dwc2_gahbcfg_init(hsotg);
2297 if (retval)
2298 return retval;
2299
2300 /* Program the GUSBCFG register */
2301 dwc2_gusbcfg_init(hsotg);
2302
2303 /* Program the GOTGCTL register */
2304 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2305 otgctl &= ~GOTGCTL_OTGVER;
2306 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2307
2308 /* Clear the SRP success bit for FS-I2c */
2309 hsotg->srp_success = 0;
2310
2311 /* Enable common interrupts */
2312 dwc2_enable_common_interrupts(hsotg);
2313
2314 /*
2315 * Do device or host initialization based on mode during PCD and
2316 * HCD initialization
2317 */
2318 if (dwc2_is_host_mode(hsotg)) {
2319 dev_dbg(hsotg->dev, "Host Mode\n");
2320 hsotg->op_state = OTG_STATE_A_HOST;
2321 } else {
2322 dev_dbg(hsotg->dev, "Device Mode\n");
2323 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2324 }
2325
2326 return 0;
2327 }
2328
2329 /**
2330 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2331 * Host mode
2332 *
2333 * @hsotg: Programming view of DWC_otg controller
2334 *
2335 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2336 * request queues. Host channels are reset to ensure that they are ready for
2337 * performing transfers.
2338 */
2339 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2340 {
2341 u32 hcfg, hfir, otgctl, usbcfg;
2342
2343 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2344
2345 /* Set HS/FS Timeout Calibration to 7 (max available value).
2346 * The number of PHY clocks that the application programs in
2347 * this field is added to the high/full speed interpacket timeout
2348 * duration in the core to account for any additional delays
2349 * introduced by the PHY. This can be required, because the delay
2350 * introduced by the PHY in generating the linestate condition
2351 * can vary from one PHY to another.
2352 */
2353 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2354 usbcfg |= GUSBCFG_TOUTCAL(7);
2355 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2356
2357 /* Restart the Phy Clock */
2358 dwc2_writel(0, hsotg->regs + PCGCTL);
2359
2360 /* Initialize Host Configuration Register */
2361 dwc2_init_fs_ls_pclk_sel(hsotg);
2362 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2363 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2364 hcfg = dwc2_readl(hsotg->regs + HCFG);
2365 hcfg |= HCFG_FSLSSUPP;
2366 dwc2_writel(hcfg, hsotg->regs + HCFG);
2367 }
2368
2369 /*
2370 * This bit allows dynamic reloading of the HFIR register during
2371 * runtime. This bit needs to be programmed during initial configuration
2372 * and its value must not be changed during runtime.
2373 */
2374 if (hsotg->params.reload_ctl) {
2375 hfir = dwc2_readl(hsotg->regs + HFIR);
2376 hfir |= HFIR_RLDCTRL;
2377 dwc2_writel(hfir, hsotg->regs + HFIR);
2378 }
2379
2380 if (hsotg->params.dma_desc_enable) {
2381 u32 op_mode = hsotg->hw_params.op_mode;
2382
2383 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2384 !hsotg->hw_params.dma_desc_enable ||
2385 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2386 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2387 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2388 dev_err(hsotg->dev,
2389 "Hardware does not support descriptor DMA mode -\n");
2390 dev_err(hsotg->dev,
2391 "falling back to buffer DMA mode.\n");
2392 hsotg->params.dma_desc_enable = false;
2393 } else {
2394 hcfg = dwc2_readl(hsotg->regs + HCFG);
2395 hcfg |= HCFG_DESCDMA;
2396 dwc2_writel(hcfg, hsotg->regs + HCFG);
2397 }
2398 }
2399
2400 /* Configure data FIFO sizes */
2401 dwc2_config_fifos(hsotg);
2402
2403 /* TODO - check this */
2404 /* Clear Host Set HNP Enable in the OTG Control Register */
2405 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2406 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2407 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2408
2409 /* Make sure the FIFOs are flushed */
2410 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2411 dwc2_flush_rx_fifo(hsotg);
2412
2413 /* Clear Host Set HNP Enable in the OTG Control Register */
2414 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2415 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2416 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2417
2418 if (!hsotg->params.dma_desc_enable) {
2419 int num_channels, i;
2420 u32 hcchar;
2421
2422 /* Flush out any leftover queued requests */
2423 num_channels = hsotg->params.host_channels;
2424 for (i = 0; i < num_channels; i++) {
2425 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2426 hcchar &= ~HCCHAR_CHENA;
2427 hcchar |= HCCHAR_CHDIS;
2428 hcchar &= ~HCCHAR_EPDIR;
2429 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2430 }
2431
2432 /* Halt all channels to put them into a known state */
2433 for (i = 0; i < num_channels; i++) {
2434 int count = 0;
2435
2436 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2437 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2438 hcchar &= ~HCCHAR_EPDIR;
2439 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2440 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2441 __func__, i);
2442 do {
2443 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2444 if (++count > 1000) {
2445 dev_err(hsotg->dev,
2446 "Unable to clear enable on channel %d\n",
2447 i);
2448 break;
2449 }
2450 udelay(1);
2451 } while (hcchar & HCCHAR_CHENA);
2452 }
2453 }
2454
2455 /* Turn on the vbus power */
2456 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2457 if (hsotg->op_state == OTG_STATE_A_HOST) {
2458 u32 hprt0 = dwc2_read_hprt0(hsotg);
2459
2460 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2461 !!(hprt0 & HPRT0_PWR));
2462 if (!(hprt0 & HPRT0_PWR)) {
2463 hprt0 |= HPRT0_PWR;
2464 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2465 }
2466 }
2467
2468 dwc2_enable_host_interrupts(hsotg);
2469 }
2470
2471 /*
2472 * Initializes dynamic portions of the DWC_otg HCD state
2473 *
2474 * Must be called with interrupt disabled and spinlock held
2475 */
2476 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2477 {
2478 struct dwc2_host_chan *chan, *chan_tmp;
2479 int num_channels;
2480 int i;
2481
2482 hsotg->flags.d32 = 0;
2483 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2484
2485 if (hsotg->params.uframe_sched) {
2486 hsotg->available_host_channels =
2487 hsotg->params.host_channels;
2488 } else {
2489 hsotg->non_periodic_channels = 0;
2490 hsotg->periodic_channels = 0;
2491 }
2492
2493 /*
2494 * Put all channels in the free channel list and clean up channel
2495 * states
2496 */
2497 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2498 hc_list_entry)
2499 list_del_init(&chan->hc_list_entry);
2500
2501 num_channels = hsotg->params.host_channels;
2502 for (i = 0; i < num_channels; i++) {
2503 chan = hsotg->hc_ptr_array[i];
2504 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2505 dwc2_hc_cleanup(hsotg, chan);
2506 }
2507
2508 /* Initialize the DWC core for host mode operation */
2509 dwc2_core_host_init(hsotg);
2510 }
2511
2512 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2513 struct dwc2_host_chan *chan,
2514 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2515 {
2516 int hub_addr, hub_port;
2517
2518 chan->do_split = 1;
2519 chan->xact_pos = qtd->isoc_split_pos;
2520 chan->complete_split = qtd->complete_split;
2521 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2522 chan->hub_addr = (u8)hub_addr;
2523 chan->hub_port = (u8)hub_port;
2524 }
2525
2526 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2527 struct dwc2_host_chan *chan,
2528 struct dwc2_qtd *qtd)
2529 {
2530 struct dwc2_hcd_urb *urb = qtd->urb;
2531 struct dwc2_hcd_iso_packet_desc *frame_desc;
2532
2533 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2534 case USB_ENDPOINT_XFER_CONTROL:
2535 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2536
2537 switch (qtd->control_phase) {
2538 case DWC2_CONTROL_SETUP:
2539 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2540 chan->do_ping = 0;
2541 chan->ep_is_in = 0;
2542 chan->data_pid_start = DWC2_HC_PID_SETUP;
2543 if (hsotg->params.host_dma)
2544 chan->xfer_dma = urb->setup_dma;
2545 else
2546 chan->xfer_buf = urb->setup_packet;
2547 chan->xfer_len = 8;
2548 break;
2549
2550 case DWC2_CONTROL_DATA:
2551 dev_vdbg(hsotg->dev, " Control data transaction\n");
2552 chan->data_pid_start = qtd->data_toggle;
2553 break;
2554
2555 case DWC2_CONTROL_STATUS:
2556 /*
2557 * Direction is opposite of data direction or IN if no
2558 * data
2559 */
2560 dev_vdbg(hsotg->dev, " Control status transaction\n");
2561 if (urb->length == 0)
2562 chan->ep_is_in = 1;
2563 else
2564 chan->ep_is_in =
2565 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2566 if (chan->ep_is_in)
2567 chan->do_ping = 0;
2568 chan->data_pid_start = DWC2_HC_PID_DATA1;
2569 chan->xfer_len = 0;
2570 if (hsotg->params.host_dma)
2571 chan->xfer_dma = hsotg->status_buf_dma;
2572 else
2573 chan->xfer_buf = hsotg->status_buf;
2574 break;
2575 }
2576 break;
2577
2578 case USB_ENDPOINT_XFER_BULK:
2579 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2580 break;
2581
2582 case USB_ENDPOINT_XFER_INT:
2583 chan->ep_type = USB_ENDPOINT_XFER_INT;
2584 break;
2585
2586 case USB_ENDPOINT_XFER_ISOC:
2587 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2588 if (hsotg->params.dma_desc_enable)
2589 break;
2590
2591 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2592 frame_desc->status = 0;
2593
2594 if (hsotg->params.host_dma) {
2595 chan->xfer_dma = urb->dma;
2596 chan->xfer_dma += frame_desc->offset +
2597 qtd->isoc_split_offset;
2598 } else {
2599 chan->xfer_buf = urb->buf;
2600 chan->xfer_buf += frame_desc->offset +
2601 qtd->isoc_split_offset;
2602 }
2603
2604 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2605
2606 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2607 if (chan->xfer_len <= 188)
2608 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2609 else
2610 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2611 }
2612 break;
2613 }
2614 }
2615
2616 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2617 struct dwc2_qh *qh,
2618 struct dwc2_host_chan *chan)
2619 {
2620 if (!hsotg->unaligned_cache ||
2621 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2622 return -ENOMEM;
2623
2624 if (!qh->dw_align_buf) {
2625 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2626 GFP_ATOMIC | GFP_DMA);
2627 if (!qh->dw_align_buf)
2628 return -ENOMEM;
2629 }
2630
2631 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2632 DWC2_KMEM_UNALIGNED_BUF_SIZE,
2633 DMA_FROM_DEVICE);
2634
2635 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2636 dev_err(hsotg->dev, "can't map align_buf\n");
2637 chan->align_buf = 0;
2638 return -EINVAL;
2639 }
2640
2641 chan->align_buf = qh->dw_align_buf_dma;
2642 return 0;
2643 }
2644
2645 #define DWC2_USB_DMA_ALIGN 4
2646
2647 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2648 {
2649 void *stored_xfer_buffer;
2650
2651 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2652 return;
2653
2654 /* Restore urb->transfer_buffer from the end of the allocated area */
2655 memcpy(&stored_xfer_buffer, urb->transfer_buffer +
2656 urb->transfer_buffer_length, sizeof(urb->transfer_buffer));
2657
2658 if (usb_urb_dir_in(urb))
2659 memcpy(stored_xfer_buffer, urb->transfer_buffer,
2660 urb->transfer_buffer_length);
2661 kfree(urb->transfer_buffer);
2662 urb->transfer_buffer = stored_xfer_buffer;
2663
2664 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2665 }
2666
2667 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2668 {
2669 void *kmalloc_ptr;
2670 size_t kmalloc_size;
2671
2672 if (urb->num_sgs || urb->sg ||
2673 urb->transfer_buffer_length == 0 ||
2674 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2675 return 0;
2676
2677 /*
2678 * Allocate a buffer with enough padding for original transfer_buffer
2679 * pointer. This allocation is guaranteed to be aligned properly for
2680 * DMA
2681 */
2682 kmalloc_size = urb->transfer_buffer_length +
2683 sizeof(urb->transfer_buffer);
2684
2685 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2686 if (!kmalloc_ptr)
2687 return -ENOMEM;
2688
2689 /*
2690 * Position value of original urb->transfer_buffer pointer to the end
2691 * of allocation for later referencing
2692 */
2693 memcpy(kmalloc_ptr + urb->transfer_buffer_length,
2694 &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2695
2696 if (usb_urb_dir_out(urb))
2697 memcpy(kmalloc_ptr, urb->transfer_buffer,
2698 urb->transfer_buffer_length);
2699 urb->transfer_buffer = kmalloc_ptr;
2700
2701 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2702
2703 return 0;
2704 }
2705
2706 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2707 gfp_t mem_flags)
2708 {
2709 int ret;
2710
2711 /* We assume setup_dma is always aligned; warn if not */
2712 WARN_ON_ONCE(urb->setup_dma &&
2713 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2714
2715 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2716 if (ret)
2717 return ret;
2718
2719 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2720 if (ret)
2721 dwc2_free_dma_aligned_buffer(urb);
2722
2723 return ret;
2724 }
2725
2726 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2727 {
2728 usb_hcd_unmap_urb_for_dma(hcd, urb);
2729 dwc2_free_dma_aligned_buffer(urb);
2730 }
2731
2732 /**
2733 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2734 * channel and initializes the host channel to perform the transactions. The
2735 * host channel is removed from the free list.
2736 *
2737 * @hsotg: The HCD state structure
2738 * @qh: Transactions from the first QTD for this QH are selected and assigned
2739 * to a free host channel
2740 */
2741 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2742 {
2743 struct dwc2_host_chan *chan;
2744 struct dwc2_hcd_urb *urb;
2745 struct dwc2_qtd *qtd;
2746
2747 if (dbg_qh(qh))
2748 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2749
2750 if (list_empty(&qh->qtd_list)) {
2751 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2752 return -ENOMEM;
2753 }
2754
2755 if (list_empty(&hsotg->free_hc_list)) {
2756 dev_dbg(hsotg->dev, "No free channel to assign\n");
2757 return -ENOMEM;
2758 }
2759
2760 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2761 hc_list_entry);
2762
2763 /* Remove host channel from free list */
2764 list_del_init(&chan->hc_list_entry);
2765
2766 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2767 urb = qtd->urb;
2768 qh->channel = chan;
2769 qtd->in_process = 1;
2770
2771 /*
2772 * Use usb_pipedevice to determine device address. This address is
2773 * 0 before the SET_ADDRESS command and the correct address afterward.
2774 */
2775 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2776 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2777 chan->speed = qh->dev_speed;
2778 chan->max_packet = dwc2_max_packet(qh->maxp);
2779
2780 chan->xfer_started = 0;
2781 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2782 chan->error_state = (qtd->error_count > 0);
2783 chan->halt_on_queue = 0;
2784 chan->halt_pending = 0;
2785 chan->requests = 0;
2786
2787 /*
2788 * The following values may be modified in the transfer type section
2789 * below. The xfer_len value may be reduced when the transfer is
2790 * started to accommodate the max widths of the XferSize and PktCnt
2791 * fields in the HCTSIZn register.
2792 */
2793
2794 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2795 if (chan->ep_is_in)
2796 chan->do_ping = 0;
2797 else
2798 chan->do_ping = qh->ping_state;
2799
2800 chan->data_pid_start = qh->data_toggle;
2801 chan->multi_count = 1;
2802
2803 if (urb->actual_length > urb->length &&
2804 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2805 urb->actual_length = urb->length;
2806
2807 if (hsotg->params.host_dma)
2808 chan->xfer_dma = urb->dma + urb->actual_length;
2809 else
2810 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2811
2812 chan->xfer_len = urb->length - urb->actual_length;
2813 chan->xfer_count = 0;
2814
2815 /* Set the split attributes if required */
2816 if (qh->do_split)
2817 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2818 else
2819 chan->do_split = 0;
2820
2821 /* Set the transfer attributes */
2822 dwc2_hc_init_xfer(hsotg, chan, qtd);
2823
2824 /* For non-dword aligned buffers */
2825 if (hsotg->params.host_dma && qh->do_split &&
2826 chan->ep_is_in && (chan->xfer_dma & 0x3)) {
2827 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2828 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2829 dev_err(hsotg->dev,
2830 "Failed to allocate memory to handle non-aligned buffer\n");
2831 /* Add channel back to free list */
2832 chan->align_buf = 0;
2833 chan->multi_count = 0;
2834 list_add_tail(&chan->hc_list_entry,
2835 &hsotg->free_hc_list);
2836 qtd->in_process = 0;
2837 qh->channel = NULL;
2838 return -ENOMEM;
2839 }
2840 } else {
2841 /*
2842 * We assume that DMA is always aligned in non-split
2843 * case or split out case. Warn if not.
2844 */
2845 WARN_ON_ONCE(hsotg->params.host_dma &&
2846 (chan->xfer_dma & 0x3));
2847 chan->align_buf = 0;
2848 }
2849
2850 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2851 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2852 /*
2853 * This value may be modified when the transfer is started
2854 * to reflect the actual transfer length
2855 */
2856 chan->multi_count = dwc2_hb_mult(qh->maxp);
2857
2858 if (hsotg->params.dma_desc_enable) {
2859 chan->desc_list_addr = qh->desc_list_dma;
2860 chan->desc_list_sz = qh->desc_list_sz;
2861 }
2862
2863 dwc2_hc_init(hsotg, chan);
2864 chan->qh = qh;
2865
2866 return 0;
2867 }
2868
2869 /**
2870 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2871 * schedule and assigns them to available host channels. Called from the HCD
2872 * interrupt handler functions.
2873 *
2874 * @hsotg: The HCD state structure
2875 *
2876 * Return: The types of new transactions that were assigned to host channels
2877 */
2878 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2879 struct dwc2_hsotg *hsotg)
2880 {
2881 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2882 struct list_head *qh_ptr;
2883 struct dwc2_qh *qh;
2884 int num_channels;
2885
2886 #ifdef DWC2_DEBUG_SOF
2887 dev_vdbg(hsotg->dev, " Select Transactions\n");
2888 #endif
2889
2890 /* Process entries in the periodic ready list */
2891 qh_ptr = hsotg->periodic_sched_ready.next;
2892 while (qh_ptr != &hsotg->periodic_sched_ready) {
2893 if (list_empty(&hsotg->free_hc_list))
2894 break;
2895 if (hsotg->params.uframe_sched) {
2896 if (hsotg->available_host_channels <= 1)
2897 break;
2898 hsotg->available_host_channels--;
2899 }
2900 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2901 if (dwc2_assign_and_init_hc(hsotg, qh))
2902 break;
2903
2904 /*
2905 * Move the QH from the periodic ready schedule to the
2906 * periodic assigned schedule
2907 */
2908 qh_ptr = qh_ptr->next;
2909 list_move_tail(&qh->qh_list_entry,
2910 &hsotg->periodic_sched_assigned);
2911 ret_val = DWC2_TRANSACTION_PERIODIC;
2912 }
2913
2914 /*
2915 * Process entries in the inactive portion of the non-periodic
2916 * schedule. Some free host channels may not be used if they are
2917 * reserved for periodic transfers.
2918 */
2919 num_channels = hsotg->params.host_channels;
2920 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2921 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2922 if (!hsotg->params.uframe_sched &&
2923 hsotg->non_periodic_channels >= num_channels -
2924 hsotg->periodic_channels)
2925 break;
2926 if (list_empty(&hsotg->free_hc_list))
2927 break;
2928 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2929 if (hsotg->params.uframe_sched) {
2930 if (hsotg->available_host_channels < 1)
2931 break;
2932 hsotg->available_host_channels--;
2933 }
2934
2935 if (dwc2_assign_and_init_hc(hsotg, qh))
2936 break;
2937
2938 /*
2939 * Move the QH from the non-periodic inactive schedule to the
2940 * non-periodic active schedule
2941 */
2942 qh_ptr = qh_ptr->next;
2943 list_move_tail(&qh->qh_list_entry,
2944 &hsotg->non_periodic_sched_active);
2945
2946 if (ret_val == DWC2_TRANSACTION_NONE)
2947 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2948 else
2949 ret_val = DWC2_TRANSACTION_ALL;
2950
2951 if (!hsotg->params.uframe_sched)
2952 hsotg->non_periodic_channels++;
2953 }
2954
2955 return ret_val;
2956 }
2957
2958 /**
2959 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2960 * a host channel associated with either a periodic or non-periodic transfer
2961 *
2962 * @hsotg: The HCD state structure
2963 * @chan: Host channel descriptor associated with either a periodic or
2964 * non-periodic transfer
2965 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2966 * for periodic transfers or the non-periodic Tx FIFO
2967 * for non-periodic transfers
2968 *
2969 * Return: 1 if a request is queued and more requests may be needed to
2970 * complete the transfer, 0 if no more requests are required for this
2971 * transfer, -1 if there is insufficient space in the Tx FIFO
2972 *
2973 * This function assumes that there is space available in the appropriate
2974 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2975 * it checks whether space is available in the appropriate Tx FIFO.
2976 *
2977 * Must be called with interrupt disabled and spinlock held
2978 */
2979 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2980 struct dwc2_host_chan *chan,
2981 u16 fifo_dwords_avail)
2982 {
2983 int retval = 0;
2984
2985 if (chan->do_split)
2986 /* Put ourselves on the list to keep order straight */
2987 list_move_tail(&chan->split_order_list_entry,
2988 &hsotg->split_order);
2989
2990 if (hsotg->params.host_dma) {
2991 if (hsotg->params.dma_desc_enable) {
2992 if (!chan->xfer_started ||
2993 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2994 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2995 chan->qh->ping_state = 0;
2996 }
2997 } else if (!chan->xfer_started) {
2998 dwc2_hc_start_transfer(hsotg, chan);
2999 chan->qh->ping_state = 0;
3000 }
3001 } else if (chan->halt_pending) {
3002 /* Don't queue a request if the channel has been halted */
3003 } else if (chan->halt_on_queue) {
3004 dwc2_hc_halt(hsotg, chan, chan->halt_status);
3005 } else if (chan->do_ping) {
3006 if (!chan->xfer_started)
3007 dwc2_hc_start_transfer(hsotg, chan);
3008 } else if (!chan->ep_is_in ||
3009 chan->data_pid_start == DWC2_HC_PID_SETUP) {
3010 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
3011 if (!chan->xfer_started) {
3012 dwc2_hc_start_transfer(hsotg, chan);
3013 retval = 1;
3014 } else {
3015 retval = dwc2_hc_continue_transfer(hsotg, chan);
3016 }
3017 } else {
3018 retval = -1;
3019 }
3020 } else {
3021 if (!chan->xfer_started) {
3022 dwc2_hc_start_transfer(hsotg, chan);
3023 retval = 1;
3024 } else {
3025 retval = dwc2_hc_continue_transfer(hsotg, chan);
3026 }
3027 }
3028
3029 return retval;
3030 }
3031
3032 /*
3033 * Processes periodic channels for the next frame and queues transactions for
3034 * these channels to the DWC_otg controller. After queueing transactions, the
3035 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3036 * to queue as Periodic Tx FIFO or request queue space becomes available.
3037 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3038 *
3039 * Must be called with interrupt disabled and spinlock held
3040 */
3041 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3042 {
3043 struct list_head *qh_ptr;
3044 struct dwc2_qh *qh;
3045 u32 tx_status;
3046 u32 fspcavail;
3047 u32 gintmsk;
3048 int status;
3049 bool no_queue_space = false;
3050 bool no_fifo_space = false;
3051 u32 qspcavail;
3052
3053 /* If empty list then just adjust interrupt enables */
3054 if (list_empty(&hsotg->periodic_sched_assigned))
3055 goto exit;
3056
3057 if (dbg_perio())
3058 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3059
3060 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3061 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3062 TXSTS_QSPCAVAIL_SHIFT;
3063 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3064 TXSTS_FSPCAVAIL_SHIFT;
3065
3066 if (dbg_perio()) {
3067 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
3068 qspcavail);
3069 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
3070 fspcavail);
3071 }
3072
3073 qh_ptr = hsotg->periodic_sched_assigned.next;
3074 while (qh_ptr != &hsotg->periodic_sched_assigned) {
3075 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3076 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3077 TXSTS_QSPCAVAIL_SHIFT;
3078 if (qspcavail == 0) {
3079 no_queue_space = true;
3080 break;
3081 }
3082
3083 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
3084 if (!qh->channel) {
3085 qh_ptr = qh_ptr->next;
3086 continue;
3087 }
3088
3089 /* Make sure EP's TT buffer is clean before queueing qtds */
3090 if (qh->tt_buffer_dirty) {
3091 qh_ptr = qh_ptr->next;
3092 continue;
3093 }
3094
3095 /*
3096 * Set a flag if we're queuing high-bandwidth in slave mode.
3097 * The flag prevents any halts to get into the request queue in
3098 * the middle of multiple high-bandwidth packets getting queued.
3099 */
3100 if (!hsotg->params.host_dma &&
3101 qh->channel->multi_count > 1)
3102 hsotg->queuing_high_bandwidth = 1;
3103
3104 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3105 TXSTS_FSPCAVAIL_SHIFT;
3106 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3107 if (status < 0) {
3108 no_fifo_space = true;
3109 break;
3110 }
3111
3112 /*
3113 * In Slave mode, stay on the current transfer until there is
3114 * nothing more to do or the high-bandwidth request count is
3115 * reached. In DMA mode, only need to queue one request. The
3116 * controller automatically handles multiple packets for
3117 * high-bandwidth transfers.
3118 */
3119 if (hsotg->params.host_dma || status == 0 ||
3120 qh->channel->requests == qh->channel->multi_count) {
3121 qh_ptr = qh_ptr->next;
3122 /*
3123 * Move the QH from the periodic assigned schedule to
3124 * the periodic queued schedule
3125 */
3126 list_move_tail(&qh->qh_list_entry,
3127 &hsotg->periodic_sched_queued);
3128
3129 /* done queuing high bandwidth */
3130 hsotg->queuing_high_bandwidth = 0;
3131 }
3132 }
3133
3134 exit:
3135 if (no_queue_space || no_fifo_space ||
3136 (!hsotg->params.host_dma &&
3137 !list_empty(&hsotg->periodic_sched_assigned))) {
3138 /*
3139 * May need to queue more transactions as the request
3140 * queue or Tx FIFO empties. Enable the periodic Tx
3141 * FIFO empty interrupt. (Always use the half-empty
3142 * level to ensure that new requests are loaded as
3143 * soon as possible.)
3144 */
3145 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3146 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3147 gintmsk |= GINTSTS_PTXFEMP;
3148 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3149 }
3150 } else {
3151 /*
3152 * Disable the Tx FIFO empty interrupt since there are
3153 * no more transactions that need to be queued right
3154 * now. This function is called from interrupt
3155 * handlers to queue more transactions as transfer
3156 * states change.
3157 */
3158 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3159 if (gintmsk & GINTSTS_PTXFEMP) {
3160 gintmsk &= ~GINTSTS_PTXFEMP;
3161 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3162 }
3163 }
3164 }
3165
3166 /*
3167 * Processes active non-periodic channels and queues transactions for these
3168 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3169 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3170 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3171 * FIFO Empty interrupt is disabled.
3172 *
3173 * Must be called with interrupt disabled and spinlock held
3174 */
3175 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3176 {
3177 struct list_head *orig_qh_ptr;
3178 struct dwc2_qh *qh;
3179 u32 tx_status;
3180 u32 qspcavail;
3181 u32 fspcavail;
3182 u32 gintmsk;
3183 int status;
3184 int no_queue_space = 0;
3185 int no_fifo_space = 0;
3186 int more_to_do = 0;
3187
3188 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3189
3190 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3191 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3192 TXSTS_QSPCAVAIL_SHIFT;
3193 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3194 TXSTS_FSPCAVAIL_SHIFT;
3195 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3196 qspcavail);
3197 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3198 fspcavail);
3199
3200 /*
3201 * Keep track of the starting point. Skip over the start-of-list
3202 * entry.
3203 */
3204 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3205 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3206 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3207
3208 /*
3209 * Process once through the active list or until no more space is
3210 * available in the request queue or the Tx FIFO
3211 */
3212 do {
3213 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3214 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3215 TXSTS_QSPCAVAIL_SHIFT;
3216 if (!hsotg->params.host_dma && qspcavail == 0) {
3217 no_queue_space = 1;
3218 break;
3219 }
3220
3221 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3222 qh_list_entry);
3223 if (!qh->channel)
3224 goto next;
3225
3226 /* Make sure EP's TT buffer is clean before queueing qtds */
3227 if (qh->tt_buffer_dirty)
3228 goto next;
3229
3230 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3231 TXSTS_FSPCAVAIL_SHIFT;
3232 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3233
3234 if (status > 0) {
3235 more_to_do = 1;
3236 } else if (status < 0) {
3237 no_fifo_space = 1;
3238 break;
3239 }
3240 next:
3241 /* Advance to next QH, skipping start-of-list entry */
3242 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3243 if (hsotg->non_periodic_qh_ptr ==
3244 &hsotg->non_periodic_sched_active)
3245 hsotg->non_periodic_qh_ptr =
3246 hsotg->non_periodic_qh_ptr->next;
3247 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3248
3249 if (!hsotg->params.host_dma) {
3250 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3251 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3252 TXSTS_QSPCAVAIL_SHIFT;
3253 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3254 TXSTS_FSPCAVAIL_SHIFT;
3255 dev_vdbg(hsotg->dev,
3256 " NP Tx Req Queue Space Avail (after queue): %d\n",
3257 qspcavail);
3258 dev_vdbg(hsotg->dev,
3259 " NP Tx FIFO Space Avail (after queue): %d\n",
3260 fspcavail);
3261
3262 if (more_to_do || no_queue_space || no_fifo_space) {
3263 /*
3264 * May need to queue more transactions as the request
3265 * queue or Tx FIFO empties. Enable the non-periodic
3266 * Tx FIFO empty interrupt. (Always use the half-empty
3267 * level to ensure that new requests are loaded as
3268 * soon as possible.)
3269 */
3270 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3271 gintmsk |= GINTSTS_NPTXFEMP;
3272 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3273 } else {
3274 /*
3275 * Disable the Tx FIFO empty interrupt since there are
3276 * no more transactions that need to be queued right
3277 * now. This function is called from interrupt
3278 * handlers to queue more transactions as transfer
3279 * states change.
3280 */
3281 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3282 gintmsk &= ~GINTSTS_NPTXFEMP;
3283 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3284 }
3285 }
3286 }
3287
3288 /**
3289 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3290 * and queues transactions for these channels to the DWC_otg controller. Called
3291 * from the HCD interrupt handler functions.
3292 *
3293 * @hsotg: The HCD state structure
3294 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3295 * or both)
3296 *
3297 * Must be called with interrupt disabled and spinlock held
3298 */
3299 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3300 enum dwc2_transaction_type tr_type)
3301 {
3302 #ifdef DWC2_DEBUG_SOF
3303 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3304 #endif
3305 /* Process host channels associated with periodic transfers */
3306 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3307 tr_type == DWC2_TRANSACTION_ALL)
3308 dwc2_process_periodic_channels(hsotg);
3309
3310 /* Process host channels associated with non-periodic transfers */
3311 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3312 tr_type == DWC2_TRANSACTION_ALL) {
3313 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3314 dwc2_process_non_periodic_channels(hsotg);
3315 } else {
3316 /*
3317 * Ensure NP Tx FIFO empty interrupt is disabled when
3318 * there are no non-periodic transfers to process
3319 */
3320 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3321
3322 gintmsk &= ~GINTSTS_NPTXFEMP;
3323 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3324 }
3325 }
3326 }
3327
3328 static void dwc2_conn_id_status_change(struct work_struct *work)
3329 {
3330 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3331 wf_otg);
3332 u32 count = 0;
3333 u32 gotgctl;
3334 unsigned long flags;
3335
3336 dev_dbg(hsotg->dev, "%s()\n", __func__);
3337
3338 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3339 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3340 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3341 !!(gotgctl & GOTGCTL_CONID_B));
3342
3343 /* B-Device connector (Device Mode) */
3344 if (gotgctl & GOTGCTL_CONID_B) {
3345 /* Wait for switch to device mode */
3346 dev_dbg(hsotg->dev, "connId B\n");
3347 if (hsotg->bus_suspended) {
3348 dev_info(hsotg->dev,
3349 "Do port resume before switching to device mode\n");
3350 dwc2_port_resume(hsotg);
3351 }
3352 while (!dwc2_is_device_mode(hsotg)) {
3353 dev_info(hsotg->dev,
3354 "Waiting for Peripheral Mode, Mode=%s\n",
3355 dwc2_is_host_mode(hsotg) ? "Host" :
3356 "Peripheral");
3357 msleep(20);
3358 /*
3359 * Sometimes the initial GOTGCTRL read is wrong, so
3360 * check it again and jump to host mode if that was
3361 * the case.
3362 */
3363 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3364 if (!(gotgctl & GOTGCTL_CONID_B))
3365 goto host;
3366 if (++count > 250)
3367 break;
3368 }
3369 if (count > 250)
3370 dev_err(hsotg->dev,
3371 "Connection id status change timed out\n");
3372 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3373 dwc2_core_init(hsotg, false);
3374 dwc2_enable_global_interrupts(hsotg);
3375 spin_lock_irqsave(&hsotg->lock, flags);
3376 dwc2_hsotg_core_init_disconnected(hsotg, false);
3377 spin_unlock_irqrestore(&hsotg->lock, flags);
3378 dwc2_hsotg_core_connect(hsotg);
3379 } else {
3380 host:
3381 /* A-Device connector (Host Mode) */
3382 dev_dbg(hsotg->dev, "connId A\n");
3383 while (!dwc2_is_host_mode(hsotg)) {
3384 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3385 dwc2_is_host_mode(hsotg) ?
3386 "Host" : "Peripheral");
3387 msleep(20);
3388 if (++count > 250)
3389 break;
3390 }
3391 if (count > 250)
3392 dev_err(hsotg->dev,
3393 "Connection id status change timed out\n");
3394
3395 spin_lock_irqsave(&hsotg->lock, flags);
3396 dwc2_hsotg_disconnect(hsotg);
3397 spin_unlock_irqrestore(&hsotg->lock, flags);
3398
3399 hsotg->op_state = OTG_STATE_A_HOST;
3400 /* Initialize the Core for Host mode */
3401 dwc2_core_init(hsotg, false);
3402 dwc2_enable_global_interrupts(hsotg);
3403 dwc2_hcd_start(hsotg);
3404 }
3405 }
3406
3407 static void dwc2_wakeup_detected(unsigned long data)
3408 {
3409 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
3410 u32 hprt0;
3411
3412 dev_dbg(hsotg->dev, "%s()\n", __func__);
3413
3414 /*
3415 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3416 * so that OPT tests pass with all PHYs.)
3417 */
3418 hprt0 = dwc2_read_hprt0(hsotg);
3419 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3420 hprt0 &= ~HPRT0_RES;
3421 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3422 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3423 dwc2_readl(hsotg->regs + HPRT0));
3424
3425 dwc2_hcd_rem_wakeup(hsotg);
3426 hsotg->bus_suspended = false;
3427
3428 /* Change to L0 state */
3429 hsotg->lx_state = DWC2_L0;
3430 }
3431
3432 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3433 {
3434 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3435
3436 return hcd->self.b_hnp_enable;
3437 }
3438
3439 /* Must NOT be called with interrupt disabled or spinlock held */
3440 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3441 {
3442 unsigned long flags;
3443 u32 hprt0;
3444 u32 pcgctl;
3445 u32 gotgctl;
3446
3447 dev_dbg(hsotg->dev, "%s()\n", __func__);
3448
3449 spin_lock_irqsave(&hsotg->lock, flags);
3450
3451 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3452 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3453 gotgctl |= GOTGCTL_HSTSETHNPEN;
3454 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
3455 hsotg->op_state = OTG_STATE_A_SUSPEND;
3456 }
3457
3458 hprt0 = dwc2_read_hprt0(hsotg);
3459 hprt0 |= HPRT0_SUSP;
3460 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3461
3462 hsotg->bus_suspended = true;
3463
3464 /*
3465 * If hibernation is supported, Phy clock will be suspended
3466 * after registers are backuped.
3467 */
3468 if (!hsotg->params.hibernation) {
3469 /* Suspend the Phy Clock */
3470 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3471 pcgctl |= PCGCTL_STOPPCLK;
3472 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3473 udelay(10);
3474 }
3475
3476 /* For HNP the bus must be suspended for at least 200ms */
3477 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3478 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3479 pcgctl &= ~PCGCTL_STOPPCLK;
3480 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3481
3482 spin_unlock_irqrestore(&hsotg->lock, flags);
3483
3484 msleep(200);
3485 } else {
3486 spin_unlock_irqrestore(&hsotg->lock, flags);
3487 }
3488 }
3489
3490 /* Must NOT be called with interrupt disabled or spinlock held */
3491 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3492 {
3493 unsigned long flags;
3494 u32 hprt0;
3495 u32 pcgctl;
3496
3497 spin_lock_irqsave(&hsotg->lock, flags);
3498
3499 /*
3500 * If hibernation is supported, Phy clock is already resumed
3501 * after registers restore.
3502 */
3503 if (!hsotg->params.hibernation) {
3504 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3505 pcgctl &= ~PCGCTL_STOPPCLK;
3506 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3507 spin_unlock_irqrestore(&hsotg->lock, flags);
3508 msleep(20);
3509 spin_lock_irqsave(&hsotg->lock, flags);
3510 }
3511
3512 hprt0 = dwc2_read_hprt0(hsotg);
3513 hprt0 |= HPRT0_RES;
3514 hprt0 &= ~HPRT0_SUSP;
3515 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3516 spin_unlock_irqrestore(&hsotg->lock, flags);
3517
3518 msleep(USB_RESUME_TIMEOUT);
3519
3520 spin_lock_irqsave(&hsotg->lock, flags);
3521 hprt0 = dwc2_read_hprt0(hsotg);
3522 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3523 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3524 hsotg->bus_suspended = false;
3525 spin_unlock_irqrestore(&hsotg->lock, flags);
3526 }
3527
3528 /* Handles hub class-specific requests */
3529 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3530 u16 wvalue, u16 windex, char *buf, u16 wlength)
3531 {
3532 struct usb_hub_descriptor *hub_desc;
3533 int retval = 0;
3534 u32 hprt0;
3535 u32 port_status;
3536 u32 speed;
3537 u32 pcgctl;
3538
3539 switch (typereq) {
3540 case ClearHubFeature:
3541 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3542
3543 switch (wvalue) {
3544 case C_HUB_LOCAL_POWER:
3545 case C_HUB_OVER_CURRENT:
3546 /* Nothing required here */
3547 break;
3548
3549 default:
3550 retval = -EINVAL;
3551 dev_err(hsotg->dev,
3552 "ClearHubFeature request %1xh unknown\n",
3553 wvalue);
3554 }
3555 break;
3556
3557 case ClearPortFeature:
3558 if (wvalue != USB_PORT_FEAT_L1)
3559 if (!windex || windex > 1)
3560 goto error;
3561 switch (wvalue) {
3562 case USB_PORT_FEAT_ENABLE:
3563 dev_dbg(hsotg->dev,
3564 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3565 hprt0 = dwc2_read_hprt0(hsotg);
3566 hprt0 |= HPRT0_ENA;
3567 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3568 break;
3569
3570 case USB_PORT_FEAT_SUSPEND:
3571 dev_dbg(hsotg->dev,
3572 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3573
3574 if (hsotg->bus_suspended)
3575 dwc2_port_resume(hsotg);
3576 break;
3577
3578 case USB_PORT_FEAT_POWER:
3579 dev_dbg(hsotg->dev,
3580 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3581 hprt0 = dwc2_read_hprt0(hsotg);
3582 hprt0 &= ~HPRT0_PWR;
3583 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3584 break;
3585
3586 case USB_PORT_FEAT_INDICATOR:
3587 dev_dbg(hsotg->dev,
3588 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3589 /* Port indicator not supported */
3590 break;
3591
3592 case USB_PORT_FEAT_C_CONNECTION:
3593 /*
3594 * Clears driver's internal Connect Status Change flag
3595 */
3596 dev_dbg(hsotg->dev,
3597 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3598 hsotg->flags.b.port_connect_status_change = 0;
3599 break;
3600
3601 case USB_PORT_FEAT_C_RESET:
3602 /* Clears driver's internal Port Reset Change flag */
3603 dev_dbg(hsotg->dev,
3604 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3605 hsotg->flags.b.port_reset_change = 0;
3606 break;
3607
3608 case USB_PORT_FEAT_C_ENABLE:
3609 /*
3610 * Clears the driver's internal Port Enable/Disable
3611 * Change flag
3612 */
3613 dev_dbg(hsotg->dev,
3614 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3615 hsotg->flags.b.port_enable_change = 0;
3616 break;
3617
3618 case USB_PORT_FEAT_C_SUSPEND:
3619 /*
3620 * Clears the driver's internal Port Suspend Change
3621 * flag, which is set when resume signaling on the host
3622 * port is complete
3623 */
3624 dev_dbg(hsotg->dev,
3625 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3626 hsotg->flags.b.port_suspend_change = 0;
3627 break;
3628
3629 case USB_PORT_FEAT_C_PORT_L1:
3630 dev_dbg(hsotg->dev,
3631 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3632 hsotg->flags.b.port_l1_change = 0;
3633 break;
3634
3635 case USB_PORT_FEAT_C_OVER_CURRENT:
3636 dev_dbg(hsotg->dev,
3637 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3638 hsotg->flags.b.port_over_current_change = 0;
3639 break;
3640
3641 default:
3642 retval = -EINVAL;
3643 dev_err(hsotg->dev,
3644 "ClearPortFeature request %1xh unknown or unsupported\n",
3645 wvalue);
3646 }
3647 break;
3648
3649 case GetHubDescriptor:
3650 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3651 hub_desc = (struct usb_hub_descriptor *)buf;
3652 hub_desc->bDescLength = 9;
3653 hub_desc->bDescriptorType = USB_DT_HUB;
3654 hub_desc->bNbrPorts = 1;
3655 hub_desc->wHubCharacteristics =
3656 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3657 HUB_CHAR_INDV_PORT_OCPM);
3658 hub_desc->bPwrOn2PwrGood = 1;
3659 hub_desc->bHubContrCurrent = 0;
3660 hub_desc->u.hs.DeviceRemovable[0] = 0;
3661 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3662 break;
3663
3664 case GetHubStatus:
3665 dev_dbg(hsotg->dev, "GetHubStatus\n");
3666 memset(buf, 0, 4);
3667 break;
3668
3669 case GetPortStatus:
3670 dev_vdbg(hsotg->dev,
3671 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3672 hsotg->flags.d32);
3673 if (!windex || windex > 1)
3674 goto error;
3675
3676 port_status = 0;
3677 if (hsotg->flags.b.port_connect_status_change)
3678 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3679 if (hsotg->flags.b.port_enable_change)
3680 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3681 if (hsotg->flags.b.port_suspend_change)
3682 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3683 if (hsotg->flags.b.port_l1_change)
3684 port_status |= USB_PORT_STAT_C_L1 << 16;
3685 if (hsotg->flags.b.port_reset_change)
3686 port_status |= USB_PORT_STAT_C_RESET << 16;
3687 if (hsotg->flags.b.port_over_current_change) {
3688 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3689 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3690 }
3691
3692 if (!hsotg->flags.b.port_connect_status) {
3693 /*
3694 * The port is disconnected, which means the core is
3695 * either in device mode or it soon will be. Just
3696 * return 0's for the remainder of the port status
3697 * since the port register can't be read if the core
3698 * is in device mode.
3699 */
3700 *(__le32 *)buf = cpu_to_le32(port_status);
3701 break;
3702 }
3703
3704 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
3705 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3706
3707 if (hprt0 & HPRT0_CONNSTS)
3708 port_status |= USB_PORT_STAT_CONNECTION;
3709 if (hprt0 & HPRT0_ENA)
3710 port_status |= USB_PORT_STAT_ENABLE;
3711 if (hprt0 & HPRT0_SUSP)
3712 port_status |= USB_PORT_STAT_SUSPEND;
3713 if (hprt0 & HPRT0_OVRCURRACT)
3714 port_status |= USB_PORT_STAT_OVERCURRENT;
3715 if (hprt0 & HPRT0_RST)
3716 port_status |= USB_PORT_STAT_RESET;
3717 if (hprt0 & HPRT0_PWR)
3718 port_status |= USB_PORT_STAT_POWER;
3719
3720 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3721 if (speed == HPRT0_SPD_HIGH_SPEED)
3722 port_status |= USB_PORT_STAT_HIGH_SPEED;
3723 else if (speed == HPRT0_SPD_LOW_SPEED)
3724 port_status |= USB_PORT_STAT_LOW_SPEED;
3725
3726 if (hprt0 & HPRT0_TSTCTL_MASK)
3727 port_status |= USB_PORT_STAT_TEST;
3728 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3729
3730 if (hsotg->params.dma_desc_fs_enable) {
3731 /*
3732 * Enable descriptor DMA only if a full speed
3733 * device is connected.
3734 */
3735 if (hsotg->new_connection &&
3736 ((port_status &
3737 (USB_PORT_STAT_CONNECTION |
3738 USB_PORT_STAT_HIGH_SPEED |
3739 USB_PORT_STAT_LOW_SPEED)) ==
3740 USB_PORT_STAT_CONNECTION)) {
3741 u32 hcfg;
3742
3743 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3744 hsotg->params.dma_desc_enable = true;
3745 hcfg = dwc2_readl(hsotg->regs + HCFG);
3746 hcfg |= HCFG_DESCDMA;
3747 dwc2_writel(hcfg, hsotg->regs + HCFG);
3748 hsotg->new_connection = false;
3749 }
3750 }
3751
3752 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3753 *(__le32 *)buf = cpu_to_le32(port_status);
3754 break;
3755
3756 case SetHubFeature:
3757 dev_dbg(hsotg->dev, "SetHubFeature\n");
3758 /* No HUB features supported */
3759 break;
3760
3761 case SetPortFeature:
3762 dev_dbg(hsotg->dev, "SetPortFeature\n");
3763 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3764 goto error;
3765
3766 if (!hsotg->flags.b.port_connect_status) {
3767 /*
3768 * The port is disconnected, which means the core is
3769 * either in device mode or it soon will be. Just
3770 * return without doing anything since the port
3771 * register can't be written if the core is in device
3772 * mode.
3773 */
3774 break;
3775 }
3776
3777 switch (wvalue) {
3778 case USB_PORT_FEAT_SUSPEND:
3779 dev_dbg(hsotg->dev,
3780 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3781 if (windex != hsotg->otg_port)
3782 goto error;
3783 dwc2_port_suspend(hsotg, windex);
3784 break;
3785
3786 case USB_PORT_FEAT_POWER:
3787 dev_dbg(hsotg->dev,
3788 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3789 hprt0 = dwc2_read_hprt0(hsotg);
3790 hprt0 |= HPRT0_PWR;
3791 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3792 break;
3793
3794 case USB_PORT_FEAT_RESET:
3795 hprt0 = dwc2_read_hprt0(hsotg);
3796 dev_dbg(hsotg->dev,
3797 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3798 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3799 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3800 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3801 /* ??? Original driver does this */
3802 dwc2_writel(0, hsotg->regs + PCGCTL);
3803
3804 hprt0 = dwc2_read_hprt0(hsotg);
3805 /* Clear suspend bit if resetting from suspend state */
3806 hprt0 &= ~HPRT0_SUSP;
3807
3808 /*
3809 * When B-Host the Port reset bit is set in the Start
3810 * HCD Callback function, so that the reset is started
3811 * within 1ms of the HNP success interrupt
3812 */
3813 if (!dwc2_hcd_is_b_host(hsotg)) {
3814 hprt0 |= HPRT0_PWR | HPRT0_RST;
3815 dev_dbg(hsotg->dev,
3816 "In host mode, hprt0=%08x\n", hprt0);
3817 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3818 }
3819
3820 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3821 msleep(50);
3822 hprt0 &= ~HPRT0_RST;
3823 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3824 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3825 break;
3826
3827 case USB_PORT_FEAT_INDICATOR:
3828 dev_dbg(hsotg->dev,
3829 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3830 /* Not supported */
3831 break;
3832
3833 case USB_PORT_FEAT_TEST:
3834 hprt0 = dwc2_read_hprt0(hsotg);
3835 dev_dbg(hsotg->dev,
3836 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3837 hprt0 &= ~HPRT0_TSTCTL_MASK;
3838 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3839 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3840 break;
3841
3842 default:
3843 retval = -EINVAL;
3844 dev_err(hsotg->dev,
3845 "SetPortFeature %1xh unknown or unsupported\n",
3846 wvalue);
3847 break;
3848 }
3849 break;
3850
3851 default:
3852 error:
3853 retval = -EINVAL;
3854 dev_dbg(hsotg->dev,
3855 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3856 typereq, windex, wvalue);
3857 break;
3858 }
3859
3860 return retval;
3861 }
3862
3863 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3864 {
3865 int retval;
3866
3867 if (port != 1)
3868 return -EINVAL;
3869
3870 retval = (hsotg->flags.b.port_connect_status_change ||
3871 hsotg->flags.b.port_reset_change ||
3872 hsotg->flags.b.port_enable_change ||
3873 hsotg->flags.b.port_suspend_change ||
3874 hsotg->flags.b.port_over_current_change);
3875
3876 if (retval) {
3877 dev_dbg(hsotg->dev,
3878 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3879 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3880 hsotg->flags.b.port_connect_status_change);
3881 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3882 hsotg->flags.b.port_reset_change);
3883 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3884 hsotg->flags.b.port_enable_change);
3885 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3886 hsotg->flags.b.port_suspend_change);
3887 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3888 hsotg->flags.b.port_over_current_change);
3889 }
3890
3891 return retval;
3892 }
3893
3894 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3895 {
3896 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3897
3898 #ifdef DWC2_DEBUG_SOF
3899 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3900 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3901 #endif
3902 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3903 }
3904
3905 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3906 {
3907 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3908 u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3909 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3910 unsigned int us_per_frame;
3911 unsigned int frame_number;
3912 unsigned int remaining;
3913 unsigned int interval;
3914 unsigned int phy_clks;
3915
3916 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3917 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3918
3919 /* Extract fields */
3920 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3921 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3922 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3923
3924 /*
3925 * Number of phy clocks since the last tick of the frame number after
3926 * "us" has passed.
3927 */
3928 phy_clks = (interval - remaining) +
3929 DIV_ROUND_UP(interval * us, us_per_frame);
3930
3931 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3932 }
3933
3934 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3935 {
3936 return hsotg->op_state == OTG_STATE_B_HOST;
3937 }
3938
3939 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3940 int iso_desc_count,
3941 gfp_t mem_flags)
3942 {
3943 struct dwc2_hcd_urb *urb;
3944 u32 size = sizeof(*urb) + iso_desc_count *
3945 sizeof(struct dwc2_hcd_iso_packet_desc);
3946
3947 urb = kzalloc(size, mem_flags);
3948 if (urb)
3949 urb->packet_count = iso_desc_count;
3950 return urb;
3951 }
3952
3953 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3954 struct dwc2_hcd_urb *urb, u8 dev_addr,
3955 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3956 {
3957 if (dbg_perio() ||
3958 ep_type == USB_ENDPOINT_XFER_BULK ||
3959 ep_type == USB_ENDPOINT_XFER_CONTROL)
3960 dev_vdbg(hsotg->dev,
3961 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3962 dev_addr, ep_num, ep_dir, ep_type, mps);
3963 urb->pipe_info.dev_addr = dev_addr;
3964 urb->pipe_info.ep_num = ep_num;
3965 urb->pipe_info.pipe_type = ep_type;
3966 urb->pipe_info.pipe_dir = ep_dir;
3967 urb->pipe_info.mps = mps;
3968 }
3969
3970 /*
3971 * NOTE: This function will be removed once the peripheral controller code
3972 * is integrated and the driver is stable
3973 */
3974 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3975 {
3976 #ifdef DEBUG
3977 struct dwc2_host_chan *chan;
3978 struct dwc2_hcd_urb *urb;
3979 struct dwc2_qtd *qtd;
3980 int num_channels;
3981 u32 np_tx_status;
3982 u32 p_tx_status;
3983 int i;
3984
3985 num_channels = hsotg->params.host_channels;
3986 dev_dbg(hsotg->dev, "\n");
3987 dev_dbg(hsotg->dev,
3988 "************************************************************\n");
3989 dev_dbg(hsotg->dev, "HCD State:\n");
3990 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3991
3992 for (i = 0; i < num_channels; i++) {
3993 chan = hsotg->hc_ptr_array[i];
3994 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3995 dev_dbg(hsotg->dev,
3996 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3997 chan->dev_addr, chan->ep_num, chan->ep_is_in);
3998 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3999 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
4000 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
4001 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
4002 chan->data_pid_start);
4003 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
4004 dev_dbg(hsotg->dev, " xfer_started: %d\n",
4005 chan->xfer_started);
4006 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
4007 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
4008 (unsigned long)chan->xfer_dma);
4009 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
4010 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
4011 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
4012 chan->halt_on_queue);
4013 dev_dbg(hsotg->dev, " halt_pending: %d\n",
4014 chan->halt_pending);
4015 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
4016 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
4017 dev_dbg(hsotg->dev, " complete_split: %d\n",
4018 chan->complete_split);
4019 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
4020 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
4021 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
4022 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
4023 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
4024
4025 if (chan->xfer_started) {
4026 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
4027
4028 hfnum = dwc2_readl(hsotg->regs + HFNUM);
4029 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
4030 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
4031 hcint = dwc2_readl(hsotg->regs + HCINT(i));
4032 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
4033 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
4034 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
4035 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
4036 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
4037 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
4038 }
4039
4040 if (!(chan->xfer_started && chan->qh))
4041 continue;
4042
4043 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
4044 if (!qtd->in_process)
4045 break;
4046 urb = qtd->urb;
4047 dev_dbg(hsotg->dev, " URB Info:\n");
4048 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
4049 qtd, urb);
4050 if (urb) {
4051 dev_dbg(hsotg->dev,
4052 " Dev: %d, EP: %d %s\n",
4053 dwc2_hcd_get_dev_addr(&urb->pipe_info),
4054 dwc2_hcd_get_ep_num(&urb->pipe_info),
4055 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
4056 "IN" : "OUT");
4057 dev_dbg(hsotg->dev,
4058 " Max packet size: %d\n",
4059 dwc2_hcd_get_mps(&urb->pipe_info));
4060 dev_dbg(hsotg->dev,
4061 " transfer_buffer: %p\n",
4062 urb->buf);
4063 dev_dbg(hsotg->dev,
4064 " transfer_dma: %08lx\n",
4065 (unsigned long)urb->dma);
4066 dev_dbg(hsotg->dev,
4067 " transfer_buffer_length: %d\n",
4068 urb->length);
4069 dev_dbg(hsotg->dev, " actual_length: %d\n",
4070 urb->actual_length);
4071 }
4072 }
4073 }
4074
4075 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
4076 hsotg->non_periodic_channels);
4077 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
4078 hsotg->periodic_channels);
4079 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
4080 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
4081 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
4082 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4083 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
4084 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4085 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
4086 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4087 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4088 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
4089 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4090 dwc2_hcd_dump_frrem(hsotg);
4091 dwc2_dump_global_registers(hsotg);
4092 dwc2_dump_host_registers(hsotg);
4093 dev_dbg(hsotg->dev,
4094 "************************************************************\n");
4095 dev_dbg(hsotg->dev, "\n");
4096 #endif
4097 }
4098
4099 /*
4100 * NOTE: This function will be removed once the peripheral controller code
4101 * is integrated and the driver is stable
4102 */
4103 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
4104 {
4105 #ifdef DWC2_DUMP_FRREM
4106 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
4107 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4108 hsotg->frrem_samples, hsotg->frrem_accum,
4109 hsotg->frrem_samples > 0 ?
4110 hsotg->frrem_accum / hsotg->frrem_samples : 0);
4111 dev_dbg(hsotg->dev, "\n");
4112 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
4113 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4114 hsotg->hfnum_7_samples,
4115 hsotg->hfnum_7_frrem_accum,
4116 hsotg->hfnum_7_samples > 0 ?
4117 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
4118 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
4119 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4120 hsotg->hfnum_0_samples,
4121 hsotg->hfnum_0_frrem_accum,
4122 hsotg->hfnum_0_samples > 0 ?
4123 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
4124 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
4125 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4126 hsotg->hfnum_other_samples,
4127 hsotg->hfnum_other_frrem_accum,
4128 hsotg->hfnum_other_samples > 0 ?
4129 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
4130 0);
4131 dev_dbg(hsotg->dev, "\n");
4132 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
4133 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4134 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
4135 hsotg->hfnum_7_samples_a > 0 ?
4136 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
4137 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
4138 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4139 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
4140 hsotg->hfnum_0_samples_a > 0 ?
4141 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
4142 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
4143 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4144 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
4145 hsotg->hfnum_other_samples_a > 0 ?
4146 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
4147 : 0);
4148 dev_dbg(hsotg->dev, "\n");
4149 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
4150 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4151 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
4152 hsotg->hfnum_7_samples_b > 0 ?
4153 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
4154 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
4155 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4156 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
4157 (hsotg->hfnum_0_samples_b > 0) ?
4158 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
4159 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
4160 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4161 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
4162 (hsotg->hfnum_other_samples_b > 0) ?
4163 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
4164 : 0);
4165 #endif
4166 }
4167
4168 struct wrapper_priv_data {
4169 struct dwc2_hsotg *hsotg;
4170 };
4171
4172 /* Gets the dwc2_hsotg from a usb_hcd */
4173 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4174 {
4175 struct wrapper_priv_data *p;
4176
4177 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4178 return p->hsotg;
4179 }
4180
4181 /**
4182 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4183 *
4184 * This will get the dwc2_tt structure (and ttport) associated with the given
4185 * context (which is really just a struct urb pointer).
4186 *
4187 * The first time this is called for a given TT we allocate memory for our
4188 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4189 * then the refcount for the structure will go to 0 and we'll free it.
4190 *
4191 * @hsotg: The HCD state structure for the DWC OTG controller.
4192 * @qh: The QH structure.
4193 * @context: The priv pointer from a struct dwc2_hcd_urb.
4194 * @mem_flags: Flags for allocating memory.
4195 * @ttport: We'll return this device's port number here. That's used to
4196 * reference into the bitmap if we're on a multi_tt hub.
4197 *
4198 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4199 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4200 */
4201
4202 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4203 gfp_t mem_flags, int *ttport)
4204 {
4205 struct urb *urb = context;
4206 struct dwc2_tt *dwc_tt = NULL;
4207
4208 if (urb->dev->tt) {
4209 *ttport = urb->dev->ttport;
4210
4211 dwc_tt = urb->dev->tt->hcpriv;
4212 if (!dwc_tt) {
4213 size_t bitmap_size;
4214
4215 /*
4216 * For single_tt we need one schedule. For multi_tt
4217 * we need one per port.
4218 */
4219 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4220 sizeof(dwc_tt->periodic_bitmaps[0]);
4221 if (urb->dev->tt->multi)
4222 bitmap_size *= urb->dev->tt->hub->maxchild;
4223
4224 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4225 mem_flags);
4226 if (!dwc_tt)
4227 return NULL;
4228
4229 dwc_tt->usb_tt = urb->dev->tt;
4230 dwc_tt->usb_tt->hcpriv = dwc_tt;
4231 }
4232
4233 dwc_tt->refcount++;
4234 }
4235
4236 return dwc_tt;
4237 }
4238
4239 /**
4240 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4241 *
4242 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4243 * of the structure are done.
4244 *
4245 * It's OK to call this with NULL.
4246 *
4247 * @hsotg: The HCD state structure for the DWC OTG controller.
4248 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4249 */
4250 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4251 {
4252 /* Model kfree and make put of NULL a no-op */
4253 if (!dwc_tt)
4254 return;
4255
4256 WARN_ON(dwc_tt->refcount < 1);
4257
4258 dwc_tt->refcount--;
4259 if (!dwc_tt->refcount) {
4260 dwc_tt->usb_tt->hcpriv = NULL;
4261 kfree(dwc_tt);
4262 }
4263 }
4264
4265 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4266 {
4267 struct urb *urb = context;
4268
4269 return urb->dev->speed;
4270 }
4271
4272 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4273 struct urb *urb)
4274 {
4275 struct usb_bus *bus = hcd_to_bus(hcd);
4276
4277 if (urb->interval)
4278 bus->bandwidth_allocated += bw / urb->interval;
4279 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4280 bus->bandwidth_isoc_reqs++;
4281 else
4282 bus->bandwidth_int_reqs++;
4283 }
4284
4285 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4286 struct urb *urb)
4287 {
4288 struct usb_bus *bus = hcd_to_bus(hcd);
4289
4290 if (urb->interval)
4291 bus->bandwidth_allocated -= bw / urb->interval;
4292 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4293 bus->bandwidth_isoc_reqs--;
4294 else
4295 bus->bandwidth_int_reqs--;
4296 }
4297
4298 /*
4299 * Sets the final status of an URB and returns it to the upper layer. Any
4300 * required cleanup of the URB is performed.
4301 *
4302 * Must be called with interrupt disabled and spinlock held
4303 */
4304 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4305 int status)
4306 {
4307 struct urb *urb;
4308 int i;
4309
4310 if (!qtd) {
4311 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4312 return;
4313 }
4314
4315 if (!qtd->urb) {
4316 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4317 return;
4318 }
4319
4320 urb = qtd->urb->priv;
4321 if (!urb) {
4322 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4323 return;
4324 }
4325
4326 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4327
4328 if (dbg_urb(urb))
4329 dev_vdbg(hsotg->dev,
4330 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4331 __func__, urb, usb_pipedevice(urb->pipe),
4332 usb_pipeendpoint(urb->pipe),
4333 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4334 urb->actual_length);
4335
4336 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4337 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4338 for (i = 0; i < urb->number_of_packets; ++i) {
4339 urb->iso_frame_desc[i].actual_length =
4340 dwc2_hcd_urb_get_iso_desc_actual_length(
4341 qtd->urb, i);
4342 urb->iso_frame_desc[i].status =
4343 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4344 }
4345 }
4346
4347 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4348 for (i = 0; i < urb->number_of_packets; i++)
4349 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4350 i, urb->iso_frame_desc[i].status);
4351 }
4352
4353 urb->status = status;
4354 if (!status) {
4355 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4356 urb->actual_length < urb->transfer_buffer_length)
4357 urb->status = -EREMOTEIO;
4358 }
4359
4360 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4361 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4362 struct usb_host_endpoint *ep = urb->ep;
4363
4364 if (ep)
4365 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4366 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4367 urb);
4368 }
4369
4370 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4371 urb->hcpriv = NULL;
4372 kfree(qtd->urb);
4373 qtd->urb = NULL;
4374
4375 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4376 }
4377
4378 /*
4379 * Work queue function for starting the HCD when A-Cable is connected
4380 */
4381 static void dwc2_hcd_start_func(struct work_struct *work)
4382 {
4383 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4384 start_work.work);
4385
4386 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4387 dwc2_host_start(hsotg);
4388 }
4389
4390 /*
4391 * Reset work queue function
4392 */
4393 static void dwc2_hcd_reset_func(struct work_struct *work)
4394 {
4395 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4396 reset_work.work);
4397 unsigned long flags;
4398 u32 hprt0;
4399
4400 dev_dbg(hsotg->dev, "USB RESET function called\n");
4401
4402 spin_lock_irqsave(&hsotg->lock, flags);
4403
4404 hprt0 = dwc2_read_hprt0(hsotg);
4405 hprt0 &= ~HPRT0_RST;
4406 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4407 hsotg->flags.b.port_reset_change = 1;
4408
4409 spin_unlock_irqrestore(&hsotg->lock, flags);
4410 }
4411
4412 /*
4413 * =========================================================================
4414 * Linux HC Driver Functions
4415 * =========================================================================
4416 */
4417
4418 /*
4419 * Initializes the DWC_otg controller and its root hub and prepares it for host
4420 * mode operation. Activates the root port. Returns 0 on success and a negative
4421 * error code on failure.
4422 */
4423 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4424 {
4425 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4426 struct usb_bus *bus = hcd_to_bus(hcd);
4427 unsigned long flags;
4428
4429 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4430
4431 spin_lock_irqsave(&hsotg->lock, flags);
4432 hsotg->lx_state = DWC2_L0;
4433 hcd->state = HC_STATE_RUNNING;
4434 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4435
4436 if (dwc2_is_device_mode(hsotg)) {
4437 spin_unlock_irqrestore(&hsotg->lock, flags);
4438 return 0; /* why 0 ?? */
4439 }
4440
4441 dwc2_hcd_reinit(hsotg);
4442
4443 /* Initialize and connect root hub if one is not already attached */
4444 if (bus->root_hub) {
4445 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4446 /* Inform the HUB driver to resume */
4447 usb_hcd_resume_root_hub(hcd);
4448 }
4449
4450 spin_unlock_irqrestore(&hsotg->lock, flags);
4451 return 0;
4452 }
4453
4454 /*
4455 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4456 * stopped.
4457 */
4458 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4459 {
4460 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4461 unsigned long flags;
4462
4463 /* Turn off all host-specific interrupts */
4464 dwc2_disable_host_interrupts(hsotg);
4465
4466 /* Wait for interrupt processing to finish */
4467 synchronize_irq(hcd->irq);
4468
4469 spin_lock_irqsave(&hsotg->lock, flags);
4470 /* Ensure hcd is disconnected */
4471 dwc2_hcd_disconnect(hsotg, true);
4472 dwc2_hcd_stop(hsotg);
4473 hsotg->lx_state = DWC2_L3;
4474 hcd->state = HC_STATE_HALT;
4475 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4476 spin_unlock_irqrestore(&hsotg->lock, flags);
4477
4478 usleep_range(1000, 3000);
4479 }
4480
4481 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4482 {
4483 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4484 unsigned long flags;
4485 int ret = 0;
4486 u32 hprt0;
4487
4488 spin_lock_irqsave(&hsotg->lock, flags);
4489
4490 if (dwc2_is_device_mode(hsotg))
4491 goto unlock;
4492
4493 if (hsotg->lx_state != DWC2_L0)
4494 goto unlock;
4495
4496 if (!HCD_HW_ACCESSIBLE(hcd))
4497 goto unlock;
4498
4499 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4500 goto unlock;
4501
4502 if (!hsotg->params.hibernation)
4503 goto skip_power_saving;
4504
4505 /*
4506 * Drive USB suspend and disable port Power
4507 * if usb bus is not suspended.
4508 */
4509 if (!hsotg->bus_suspended) {
4510 hprt0 = dwc2_read_hprt0(hsotg);
4511 hprt0 |= HPRT0_SUSP;
4512 hprt0 &= ~HPRT0_PWR;
4513 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4514 }
4515
4516 /* Enter hibernation */
4517 ret = dwc2_enter_hibernation(hsotg);
4518 if (ret) {
4519 if (ret != -ENOTSUPP)
4520 dev_err(hsotg->dev,
4521 "enter hibernation failed\n");
4522 goto skip_power_saving;
4523 }
4524
4525 /* Ask phy to be suspended */
4526 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4527 spin_unlock_irqrestore(&hsotg->lock, flags);
4528 usb_phy_set_suspend(hsotg->uphy, true);
4529 spin_lock_irqsave(&hsotg->lock, flags);
4530 }
4531
4532 /* After entering hibernation, hardware is no more accessible */
4533 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4534
4535 skip_power_saving:
4536 hsotg->lx_state = DWC2_L2;
4537 unlock:
4538 spin_unlock_irqrestore(&hsotg->lock, flags);
4539
4540 return ret;
4541 }
4542
4543 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4544 {
4545 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4546 unsigned long flags;
4547 int ret = 0;
4548
4549 spin_lock_irqsave(&hsotg->lock, flags);
4550
4551 if (dwc2_is_device_mode(hsotg))
4552 goto unlock;
4553
4554 if (hsotg->lx_state != DWC2_L2)
4555 goto unlock;
4556
4557 if (!hsotg->params.hibernation) {
4558 hsotg->lx_state = DWC2_L0;
4559 goto unlock;
4560 }
4561
4562 /*
4563 * Set HW accessible bit before powering on the controller
4564 * since an interrupt may rise.
4565 */
4566 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4567
4568 /*
4569 * Enable power if not already done.
4570 * This must not be spinlocked since duration
4571 * of this call is unknown.
4572 */
4573 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4574 spin_unlock_irqrestore(&hsotg->lock, flags);
4575 usb_phy_set_suspend(hsotg->uphy, false);
4576 spin_lock_irqsave(&hsotg->lock, flags);
4577 }
4578
4579 /* Exit hibernation */
4580 ret = dwc2_exit_hibernation(hsotg, true);
4581 if (ret && (ret != -ENOTSUPP))
4582 dev_err(hsotg->dev, "exit hibernation failed\n");
4583
4584 hsotg->lx_state = DWC2_L0;
4585
4586 spin_unlock_irqrestore(&hsotg->lock, flags);
4587
4588 if (hsotg->bus_suspended) {
4589 spin_lock_irqsave(&hsotg->lock, flags);
4590 hsotg->flags.b.port_suspend_change = 1;
4591 spin_unlock_irqrestore(&hsotg->lock, flags);
4592 dwc2_port_resume(hsotg);
4593 } else {
4594 /* Wait for controller to correctly update D+/D- level */
4595 usleep_range(3000, 5000);
4596
4597 /*
4598 * Clear Port Enable and Port Status changes.
4599 * Enable Port Power.
4600 */
4601 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4602 HPRT0_ENACHG, hsotg->regs + HPRT0);
4603 /* Wait for controller to detect Port Connect */
4604 usleep_range(5000, 7000);
4605 }
4606
4607 return ret;
4608 unlock:
4609 spin_unlock_irqrestore(&hsotg->lock, flags);
4610
4611 return ret;
4612 }
4613
4614 /* Returns the current frame number */
4615 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4616 {
4617 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4618
4619 return dwc2_hcd_get_frame_number(hsotg);
4620 }
4621
4622 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4623 char *fn_name)
4624 {
4625 #ifdef VERBOSE_DEBUG
4626 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4627 char *pipetype = NULL;
4628 char *speed = NULL;
4629
4630 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4631 dev_vdbg(hsotg->dev, " Device address: %d\n",
4632 usb_pipedevice(urb->pipe));
4633 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4634 usb_pipeendpoint(urb->pipe),
4635 usb_pipein(urb->pipe) ? "IN" : "OUT");
4636
4637 switch (usb_pipetype(urb->pipe)) {
4638 case PIPE_CONTROL:
4639 pipetype = "CONTROL";
4640 break;
4641 case PIPE_BULK:
4642 pipetype = "BULK";
4643 break;
4644 case PIPE_INTERRUPT:
4645 pipetype = "INTERRUPT";
4646 break;
4647 case PIPE_ISOCHRONOUS:
4648 pipetype = "ISOCHRONOUS";
4649 break;
4650 }
4651
4652 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4653 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4654 "IN" : "OUT");
4655
4656 switch (urb->dev->speed) {
4657 case USB_SPEED_HIGH:
4658 speed = "HIGH";
4659 break;
4660 case USB_SPEED_FULL:
4661 speed = "FULL";
4662 break;
4663 case USB_SPEED_LOW:
4664 speed = "LOW";
4665 break;
4666 default:
4667 speed = "UNKNOWN";
4668 break;
4669 }
4670
4671 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4672 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4673 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4674 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4675 urb->transfer_buffer_length);
4676 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4677 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4678 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4679 urb->setup_packet, (unsigned long)urb->setup_dma);
4680 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4681
4682 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4683 int i;
4684
4685 for (i = 0; i < urb->number_of_packets; i++) {
4686 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4687 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4688 urb->iso_frame_desc[i].offset,
4689 urb->iso_frame_desc[i].length);
4690 }
4691 }
4692 #endif
4693 }
4694
4695 /*
4696 * Starts processing a USB transfer request specified by a USB Request Block
4697 * (URB). mem_flags indicates the type of memory allocation to use while
4698 * processing this URB.
4699 */
4700 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4701 gfp_t mem_flags)
4702 {
4703 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4704 struct usb_host_endpoint *ep = urb->ep;
4705 struct dwc2_hcd_urb *dwc2_urb;
4706 int i;
4707 int retval;
4708 int alloc_bandwidth = 0;
4709 u8 ep_type = 0;
4710 u32 tflags = 0;
4711 void *buf;
4712 unsigned long flags;
4713 struct dwc2_qh *qh;
4714 bool qh_allocated = false;
4715 struct dwc2_qtd *qtd;
4716
4717 if (dbg_urb(urb)) {
4718 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4719 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4720 }
4721
4722 if (!ep)
4723 return -EINVAL;
4724
4725 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4726 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4727 spin_lock_irqsave(&hsotg->lock, flags);
4728 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4729 alloc_bandwidth = 1;
4730 spin_unlock_irqrestore(&hsotg->lock, flags);
4731 }
4732
4733 switch (usb_pipetype(urb->pipe)) {
4734 case PIPE_CONTROL:
4735 ep_type = USB_ENDPOINT_XFER_CONTROL;
4736 break;
4737 case PIPE_ISOCHRONOUS:
4738 ep_type = USB_ENDPOINT_XFER_ISOC;
4739 break;
4740 case PIPE_BULK:
4741 ep_type = USB_ENDPOINT_XFER_BULK;
4742 break;
4743 case PIPE_INTERRUPT:
4744 ep_type = USB_ENDPOINT_XFER_INT;
4745 break;
4746 }
4747
4748 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4749 mem_flags);
4750 if (!dwc2_urb)
4751 return -ENOMEM;
4752
4753 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4754 usb_pipeendpoint(urb->pipe), ep_type,
4755 usb_pipein(urb->pipe),
4756 usb_maxpacket(urb->dev, urb->pipe,
4757 !(usb_pipein(urb->pipe))));
4758
4759 buf = urb->transfer_buffer;
4760
4761 if (hcd->self.uses_dma) {
4762 if (!buf && (urb->transfer_dma & 3)) {
4763 dev_err(hsotg->dev,
4764 "%s: unaligned transfer with no transfer_buffer",
4765 __func__);
4766 retval = -EINVAL;
4767 goto fail0;
4768 }
4769 }
4770
4771 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4772 tflags |= URB_GIVEBACK_ASAP;
4773 if (urb->transfer_flags & URB_ZERO_PACKET)
4774 tflags |= URB_SEND_ZERO_PACKET;
4775
4776 dwc2_urb->priv = urb;
4777 dwc2_urb->buf = buf;
4778 dwc2_urb->dma = urb->transfer_dma;
4779 dwc2_urb->length = urb->transfer_buffer_length;
4780 dwc2_urb->setup_packet = urb->setup_packet;
4781 dwc2_urb->setup_dma = urb->setup_dma;
4782 dwc2_urb->flags = tflags;
4783 dwc2_urb->interval = urb->interval;
4784 dwc2_urb->status = -EINPROGRESS;
4785
4786 for (i = 0; i < urb->number_of_packets; ++i)
4787 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4788 urb->iso_frame_desc[i].offset,
4789 urb->iso_frame_desc[i].length);
4790
4791 urb->hcpriv = dwc2_urb;
4792 qh = (struct dwc2_qh *)ep->hcpriv;
4793 /* Create QH for the endpoint if it doesn't exist */
4794 if (!qh) {
4795 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4796 if (!qh) {
4797 retval = -ENOMEM;
4798 goto fail0;
4799 }
4800 ep->hcpriv = qh;
4801 qh_allocated = true;
4802 }
4803
4804 qtd = kzalloc(sizeof(*qtd), mem_flags);
4805 if (!qtd) {
4806 retval = -ENOMEM;
4807 goto fail1;
4808 }
4809
4810 spin_lock_irqsave(&hsotg->lock, flags);
4811 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4812 if (retval)
4813 goto fail2;
4814
4815 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4816 if (retval)
4817 goto fail3;
4818
4819 if (alloc_bandwidth) {
4820 dwc2_allocate_bus_bandwidth(hcd,
4821 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4822 urb);
4823 }
4824
4825 spin_unlock_irqrestore(&hsotg->lock, flags);
4826
4827 return 0;
4828
4829 fail3:
4830 dwc2_urb->priv = NULL;
4831 usb_hcd_unlink_urb_from_ep(hcd, urb);
4832 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4833 qh->channel->qh = NULL;
4834 fail2:
4835 spin_unlock_irqrestore(&hsotg->lock, flags);
4836 urb->hcpriv = NULL;
4837 kfree(qtd);
4838 qtd = NULL;
4839 fail1:
4840 if (qh_allocated) {
4841 struct dwc2_qtd *qtd2, *qtd2_tmp;
4842
4843 ep->hcpriv = NULL;
4844 dwc2_hcd_qh_unlink(hsotg, qh);
4845 /* Free each QTD in the QH's QTD list */
4846 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4847 qtd_list_entry)
4848 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4849 dwc2_hcd_qh_free(hsotg, qh);
4850 }
4851 fail0:
4852 kfree(dwc2_urb);
4853
4854 return retval;
4855 }
4856
4857 /*
4858 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4859 */
4860 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4861 int status)
4862 {
4863 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4864 int rc;
4865 unsigned long flags;
4866
4867 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4868 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4869
4870 spin_lock_irqsave(&hsotg->lock, flags);
4871
4872 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4873 if (rc)
4874 goto out;
4875
4876 if (!urb->hcpriv) {
4877 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4878 goto out;
4879 }
4880
4881 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4882
4883 usb_hcd_unlink_urb_from_ep(hcd, urb);
4884
4885 kfree(urb->hcpriv);
4886 urb->hcpriv = NULL;
4887
4888 /* Higher layer software sets URB status */
4889 spin_unlock(&hsotg->lock);
4890 usb_hcd_giveback_urb(hcd, urb, status);
4891 spin_lock(&hsotg->lock);
4892
4893 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4894 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4895 out:
4896 spin_unlock_irqrestore(&hsotg->lock, flags);
4897
4898 return rc;
4899 }
4900
4901 /*
4902 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4903 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4904 * must already be dequeued.
4905 */
4906 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4907 struct usb_host_endpoint *ep)
4908 {
4909 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4910
4911 dev_dbg(hsotg->dev,
4912 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4913 ep->desc.bEndpointAddress, ep->hcpriv);
4914 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4915 }
4916
4917 /*
4918 * Resets endpoint specific parameter values, in current version used to reset
4919 * the data toggle (as a WA). This function can be called from usb_clear_halt
4920 * routine.
4921 */
4922 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4923 struct usb_host_endpoint *ep)
4924 {
4925 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4926 unsigned long flags;
4927
4928 dev_dbg(hsotg->dev,
4929 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4930 ep->desc.bEndpointAddress);
4931
4932 spin_lock_irqsave(&hsotg->lock, flags);
4933 dwc2_hcd_endpoint_reset(hsotg, ep);
4934 spin_unlock_irqrestore(&hsotg->lock, flags);
4935 }
4936
4937 /*
4938 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4939 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4940 * interrupt.
4941 *
4942 * This function is called by the USB core when an interrupt occurs
4943 */
4944 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4945 {
4946 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4947
4948 return dwc2_handle_hcd_intr(hsotg);
4949 }
4950
4951 /*
4952 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4953 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4954 * is the status change indicator for the single root port. Returns 1 if either
4955 * change indicator is 1, otherwise returns 0.
4956 */
4957 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4958 {
4959 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4960
4961 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4962 return buf[0] != 0;
4963 }
4964
4965 /* Handles hub class-specific requests */
4966 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4967 u16 windex, char *buf, u16 wlength)
4968 {
4969 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4970 wvalue, windex, buf, wlength);
4971 return retval;
4972 }
4973
4974 /* Handles hub TT buffer clear completions */
4975 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4976 struct usb_host_endpoint *ep)
4977 {
4978 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4979 struct dwc2_qh *qh;
4980 unsigned long flags;
4981
4982 qh = ep->hcpriv;
4983 if (!qh)
4984 return;
4985
4986 spin_lock_irqsave(&hsotg->lock, flags);
4987 qh->tt_buffer_dirty = 0;
4988
4989 if (hsotg->flags.b.port_connect_status)
4990 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4991
4992 spin_unlock_irqrestore(&hsotg->lock, flags);
4993 }
4994
4995 /*
4996 * HPRT0_SPD_HIGH_SPEED: high speed
4997 * HPRT0_SPD_FULL_SPEED: full speed
4998 */
4999 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
5000 {
5001 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5002
5003 if (hsotg->params.speed == speed)
5004 return;
5005
5006 hsotg->params.speed = speed;
5007 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
5008 }
5009
5010 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
5011 {
5012 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5013
5014 if (!hsotg->params.change_speed_quirk)
5015 return;
5016
5017 /*
5018 * On removal, set speed to default high-speed.
5019 */
5020 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
5021 udev->parent->speed < USB_SPEED_HIGH) {
5022 dev_info(hsotg->dev, "Set speed to default high-speed\n");
5023 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5024 }
5025 }
5026
5027 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
5028 {
5029 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5030
5031 if (!hsotg->params.change_speed_quirk)
5032 return 0;
5033
5034 if (udev->speed == USB_SPEED_HIGH) {
5035 dev_info(hsotg->dev, "Set speed to high-speed\n");
5036 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5037 } else if ((udev->speed == USB_SPEED_FULL ||
5038 udev->speed == USB_SPEED_LOW)) {
5039 /*
5040 * Change speed setting to full-speed if there's
5041 * a full-speed or low-speed device plugged in.
5042 */
5043 dev_info(hsotg->dev, "Set speed to full-speed\n");
5044 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
5045 }
5046
5047 return 0;
5048 }
5049
5050 static struct hc_driver dwc2_hc_driver = {
5051 .description = "dwc2_hsotg",
5052 .product_desc = "DWC OTG Controller",
5053 .hcd_priv_size = sizeof(struct wrapper_priv_data),
5054
5055 .irq = _dwc2_hcd_irq,
5056 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
5057
5058 .start = _dwc2_hcd_start,
5059 .stop = _dwc2_hcd_stop,
5060 .urb_enqueue = _dwc2_hcd_urb_enqueue,
5061 .urb_dequeue = _dwc2_hcd_urb_dequeue,
5062 .endpoint_disable = _dwc2_hcd_endpoint_disable,
5063 .endpoint_reset = _dwc2_hcd_endpoint_reset,
5064 .get_frame_number = _dwc2_hcd_get_frame_number,
5065
5066 .hub_status_data = _dwc2_hcd_hub_status_data,
5067 .hub_control = _dwc2_hcd_hub_control,
5068 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
5069
5070 .bus_suspend = _dwc2_hcd_suspend,
5071 .bus_resume = _dwc2_hcd_resume,
5072
5073 .map_urb_for_dma = dwc2_map_urb_for_dma,
5074 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
5075 };
5076
5077 /*
5078 * Frees secondary storage associated with the dwc2_hsotg structure contained
5079 * in the struct usb_hcd field
5080 */
5081 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5082 {
5083 u32 ahbcfg;
5084 u32 dctl;
5085 int i;
5086
5087 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
5088
5089 /* Free memory for QH/QTD lists */
5090 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
5091 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
5092 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
5093 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
5094 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5095 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5096
5097 /* Free memory for the host channels */
5098 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5099 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5100
5101 if (chan) {
5102 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5103 i, chan);
5104 hsotg->hc_ptr_array[i] = NULL;
5105 kfree(chan);
5106 }
5107 }
5108
5109 if (hsotg->params.host_dma) {
5110 if (hsotg->status_buf) {
5111 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5112 hsotg->status_buf,
5113 hsotg->status_buf_dma);
5114 hsotg->status_buf = NULL;
5115 }
5116 } else {
5117 kfree(hsotg->status_buf);
5118 hsotg->status_buf = NULL;
5119 }
5120
5121 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
5122
5123 /* Disable all interrupts */
5124 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5125 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
5126 dwc2_writel(0, hsotg->regs + GINTMSK);
5127
5128 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5129 dctl = dwc2_readl(hsotg->regs + DCTL);
5130 dctl |= DCTL_SFTDISCON;
5131 dwc2_writel(dctl, hsotg->regs + DCTL);
5132 }
5133
5134 if (hsotg->wq_otg) {
5135 if (!cancel_work_sync(&hsotg->wf_otg))
5136 flush_workqueue(hsotg->wq_otg);
5137 destroy_workqueue(hsotg->wq_otg);
5138 }
5139
5140 del_timer(&hsotg->wkp_timer);
5141 }
5142
5143 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5144 {
5145 /* Turn off all host-specific interrupts */
5146 dwc2_disable_host_interrupts(hsotg);
5147
5148 dwc2_hcd_free(hsotg);
5149 }
5150
5151 /*
5152 * Initializes the HCD. This function allocates memory for and initializes the
5153 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5154 * USB bus with the core and calls the hc_driver->start() function. It returns
5155 * a negative error on failure.
5156 */
5157 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5158 {
5159 struct platform_device *pdev = to_platform_device(hsotg->dev);
5160 struct resource *res;
5161 struct usb_hcd *hcd;
5162 struct dwc2_host_chan *channel;
5163 u32 hcfg;
5164 int i, num_channels;
5165 int retval;
5166
5167 if (usb_disabled())
5168 return -ENODEV;
5169
5170 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5171
5172 retval = -ENOMEM;
5173
5174 hcfg = dwc2_readl(hsotg->regs + HCFG);
5175 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5176
5177 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5178 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
5179 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5180 if (!hsotg->frame_num_array)
5181 goto error1;
5182 hsotg->last_frame_num_array = kzalloc(
5183 sizeof(*hsotg->last_frame_num_array) *
5184 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5185 if (!hsotg->last_frame_num_array)
5186 goto error1;
5187 #endif
5188 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5189
5190 /* Check if the bus driver or platform code has setup a dma_mask */
5191 if (hsotg->params.host_dma &&
5192 !hsotg->dev->dma_mask) {
5193 dev_warn(hsotg->dev,
5194 "dma_mask not set, disabling DMA\n");
5195 hsotg->params.host_dma = false;
5196 hsotg->params.dma_desc_enable = false;
5197 }
5198
5199 /* Set device flags indicating whether the HCD supports DMA */
5200 if (hsotg->params.host_dma) {
5201 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5202 dev_warn(hsotg->dev, "can't set DMA mask\n");
5203 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5204 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5205 }
5206
5207 if (hsotg->params.change_speed_quirk) {
5208 dwc2_hc_driver.free_dev = dwc2_free_dev;
5209 dwc2_hc_driver.reset_device = dwc2_reset_device;
5210 }
5211
5212 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5213 if (!hcd)
5214 goto error1;
5215
5216 if (!hsotg->params.host_dma)
5217 hcd->self.uses_dma = 0;
5218
5219 hcd->has_tt = 1;
5220
5221 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5222 hcd->rsrc_start = res->start;
5223 hcd->rsrc_len = resource_size(res);
5224
5225 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5226 hsotg->priv = hcd;
5227
5228 /*
5229 * Disable the global interrupt until all the interrupt handlers are
5230 * installed
5231 */
5232 dwc2_disable_global_interrupts(hsotg);
5233
5234 /* Initialize the DWC_otg core, and select the Phy type */
5235 retval = dwc2_core_init(hsotg, true);
5236 if (retval)
5237 goto error2;
5238
5239 /* Create new workqueue and init work */
5240 retval = -ENOMEM;
5241 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5242 if (!hsotg->wq_otg) {
5243 dev_err(hsotg->dev, "Failed to create workqueue\n");
5244 goto error2;
5245 }
5246 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5247
5248 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
5249 (unsigned long)hsotg);
5250
5251 /* Initialize the non-periodic schedule */
5252 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5253 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5254
5255 /* Initialize the periodic schedule */
5256 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5257 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5258 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5259 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5260
5261 INIT_LIST_HEAD(&hsotg->split_order);
5262
5263 /*
5264 * Create a host channel descriptor for each host channel implemented
5265 * in the controller. Initialize the channel descriptor array.
5266 */
5267 INIT_LIST_HEAD(&hsotg->free_hc_list);
5268 num_channels = hsotg->params.host_channels;
5269 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5270
5271 for (i = 0; i < num_channels; i++) {
5272 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5273 if (!channel)
5274 goto error3;
5275 channel->hc_num = i;
5276 INIT_LIST_HEAD(&channel->split_order_list_entry);
5277 hsotg->hc_ptr_array[i] = channel;
5278 }
5279
5280 /* Initialize hsotg start work */
5281 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5282
5283 /* Initialize port reset work */
5284 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5285
5286 /*
5287 * Allocate space for storing data on status transactions. Normally no
5288 * data is sent, but this space acts as a bit bucket. This must be
5289 * done after usb_add_hcd since that function allocates the DMA buffer
5290 * pool.
5291 */
5292 if (hsotg->params.host_dma)
5293 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5294 DWC2_HCD_STATUS_BUF_SIZE,
5295 &hsotg->status_buf_dma, GFP_KERNEL);
5296 else
5297 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5298 GFP_KERNEL);
5299
5300 if (!hsotg->status_buf)
5301 goto error3;
5302
5303 /*
5304 * Create kmem caches to handle descriptor buffers in descriptor
5305 * DMA mode.
5306 * Alignment must be set to 512 bytes.
5307 */
5308 if (hsotg->params.dma_desc_enable ||
5309 hsotg->params.dma_desc_fs_enable) {
5310 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5311 sizeof(struct dwc2_dma_desc) *
5312 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5313 NULL);
5314 if (!hsotg->desc_gen_cache) {
5315 dev_err(hsotg->dev,
5316 "unable to create dwc2 generic desc cache\n");
5317
5318 /*
5319 * Disable descriptor dma mode since it will not be
5320 * usable.
5321 */
5322 hsotg->params.dma_desc_enable = false;
5323 hsotg->params.dma_desc_fs_enable = false;
5324 }
5325
5326 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5327 sizeof(struct dwc2_dma_desc) *
5328 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5329 if (!hsotg->desc_hsisoc_cache) {
5330 dev_err(hsotg->dev,
5331 "unable to create dwc2 hs isoc desc cache\n");
5332
5333 kmem_cache_destroy(hsotg->desc_gen_cache);
5334
5335 /*
5336 * Disable descriptor dma mode since it will not be
5337 * usable.
5338 */
5339 hsotg->params.dma_desc_enable = false;
5340 hsotg->params.dma_desc_fs_enable = false;
5341 }
5342 }
5343
5344 if (hsotg->params.host_dma) {
5345 /*
5346 * Create kmem caches to handle non-aligned buffer
5347 * in Buffer DMA mode.
5348 */
5349 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5350 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5351 SLAB_CACHE_DMA, NULL);
5352 if (!hsotg->unaligned_cache)
5353 dev_err(hsotg->dev,
5354 "unable to create dwc2 unaligned cache\n");
5355 }
5356
5357 hsotg->otg_port = 1;
5358 hsotg->frame_list = NULL;
5359 hsotg->frame_list_dma = 0;
5360 hsotg->periodic_qh_count = 0;
5361
5362 /* Initiate lx_state to L3 disconnected state */
5363 hsotg->lx_state = DWC2_L3;
5364
5365 hcd->self.otg_port = hsotg->otg_port;
5366
5367 /* Don't support SG list at this point */
5368 hcd->self.sg_tablesize = 0;
5369
5370 if (!IS_ERR_OR_NULL(hsotg->uphy))
5371 otg_set_host(hsotg->uphy->otg, &hcd->self);
5372
5373 /*
5374 * Finish generic HCD initialization and start the HCD. This function
5375 * allocates the DMA buffer pool, registers the USB bus, requests the
5376 * IRQ line, and calls hcd_start method.
5377 */
5378 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5379 if (retval < 0)
5380 goto error4;
5381
5382 device_wakeup_enable(hcd->self.controller);
5383
5384 dwc2_hcd_dump_state(hsotg);
5385
5386 dwc2_enable_global_interrupts(hsotg);
5387
5388 return 0;
5389
5390 error4:
5391 kmem_cache_destroy(hsotg->unaligned_cache);
5392 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5393 kmem_cache_destroy(hsotg->desc_gen_cache);
5394 error3:
5395 dwc2_hcd_release(hsotg);
5396 error2:
5397 usb_put_hcd(hcd);
5398 error1:
5399
5400 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5401 kfree(hsotg->last_frame_num_array);
5402 kfree(hsotg->frame_num_array);
5403 #endif
5404
5405 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5406 return retval;
5407 }
5408
5409 /*
5410 * Removes the HCD.
5411 * Frees memory and resources associated with the HCD and deregisters the bus.
5412 */
5413 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5414 {
5415 struct usb_hcd *hcd;
5416
5417 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5418
5419 hcd = dwc2_hsotg_to_hcd(hsotg);
5420 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5421
5422 if (!hcd) {
5423 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5424 __func__);
5425 return;
5426 }
5427
5428 if (!IS_ERR_OR_NULL(hsotg->uphy))
5429 otg_set_host(hsotg->uphy->otg, NULL);
5430
5431 usb_remove_hcd(hcd);
5432 hsotg->priv = NULL;
5433
5434 kmem_cache_destroy(hsotg->unaligned_cache);
5435 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5436 kmem_cache_destroy(hsotg->desc_gen_cache);
5437
5438 dwc2_hcd_release(hsotg);
5439 usb_put_hcd(hcd);
5440
5441 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5442 kfree(hsotg->last_frame_num_array);
5443 kfree(hsotg->frame_num_array);
5444 #endif
5445 }
5446
5447 /**
5448 * dwc2_backup_host_registers() - Backup controller host registers.
5449 * When suspending usb bus, registers needs to be backuped
5450 * if controller power is disabled once suspended.
5451 *
5452 * @hsotg: Programming view of the DWC_otg controller
5453 */
5454 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5455 {
5456 struct dwc2_hregs_backup *hr;
5457 int i;
5458
5459 dev_dbg(hsotg->dev, "%s\n", __func__);
5460
5461 /* Backup Host regs */
5462 hr = &hsotg->hr_backup;
5463 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5464 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
5465 for (i = 0; i < hsotg->params.host_channels; ++i)
5466 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5467
5468 hr->hprt0 = dwc2_read_hprt0(hsotg);
5469 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5470 hr->valid = true;
5471
5472 return 0;
5473 }
5474
5475 /**
5476 * dwc2_restore_host_registers() - Restore controller host registers.
5477 * When resuming usb bus, device registers needs to be restored
5478 * if controller power were disabled.
5479 *
5480 * @hsotg: Programming view of the DWC_otg controller
5481 */
5482 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5483 {
5484 struct dwc2_hregs_backup *hr;
5485 int i;
5486
5487 dev_dbg(hsotg->dev, "%s\n", __func__);
5488
5489 /* Restore host regs */
5490 hr = &hsotg->hr_backup;
5491 if (!hr->valid) {
5492 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5493 __func__);
5494 return -EINVAL;
5495 }
5496 hr->valid = false;
5497
5498 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5499 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5500
5501 for (i = 0; i < hsotg->params.host_channels; ++i)
5502 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5503
5504 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5505 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5506 hsotg->frame_number = 0;
5507
5508 return 0;
5509 }
Linux with added FPC-III support