| blob | 24e93dfcee9ffa40225544a9778d818841f99d81 |
1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Shunli Wang <shunli.wang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
15 #ifndef _DT_BINDINGS_CLK_MT2701_H
16 #define _DT_BINDINGS_CLK_MT2701_H
18 /* TOPCKGEN */
19 #define CLK_TOP_SYSPLL 1
20 #define CLK_TOP_SYSPLL_D2 2
21 #define CLK_TOP_SYSPLL_D3 3
22 #define CLK_TOP_SYSPLL_D5 4
23 #define CLK_TOP_SYSPLL_D7 5
24 #define CLK_TOP_SYSPLL1_D2 6
25 #define CLK_TOP_SYSPLL1_D4 7
26 #define CLK_TOP_SYSPLL1_D8 8
27 #define CLK_TOP_SYSPLL1_D16 9
28 #define CLK_TOP_SYSPLL2_D2 10
29 #define CLK_TOP_SYSPLL2_D4 11
30 #define CLK_TOP_SYSPLL2_D8 12
31 #define CLK_TOP_SYSPLL3_D2 13
32 #define CLK_TOP_SYSPLL3_D4 14
33 #define CLK_TOP_SYSPLL4_D2 15
34 #define CLK_TOP_SYSPLL4_D4 16
35 #define CLK_TOP_UNIVPLL 17
36 #define CLK_TOP_UNIVPLL_D2 18
37 #define CLK_TOP_UNIVPLL_D3 19
38 #define CLK_TOP_UNIVPLL_D5 20
39 #define CLK_TOP_UNIVPLL_D7 21
40 #define CLK_TOP_UNIVPLL_D26 22
41 #define CLK_TOP_UNIVPLL_D52 23
42 #define CLK_TOP_UNIVPLL_D108 24
43 #define CLK_TOP_USB_PHY48M 25
44 #define CLK_TOP_UNIVPLL1_D2 26
45 #define CLK_TOP_UNIVPLL1_D4 27
46 #define CLK_TOP_UNIVPLL1_D8 28
47 #define CLK_TOP_UNIVPLL2_D2 29
48 #define CLK_TOP_UNIVPLL2_D4 30
49 #define CLK_TOP_UNIVPLL2_D8 31
50 #define CLK_TOP_UNIVPLL2_D16 32
51 #define CLK_TOP_UNIVPLL2_D32 33
52 #define CLK_TOP_UNIVPLL3_D2 34
53 #define CLK_TOP_UNIVPLL3_D4 35
54 #define CLK_TOP_UNIVPLL3_D8 36
55 #define CLK_TOP_MSDCPLL 37
56 #define CLK_TOP_MSDCPLL_D2 38
57 #define CLK_TOP_MSDCPLL_D4 39
58 #define CLK_TOP_MSDCPLL_D8 40
59 #define CLK_TOP_MMPLL 41
60 #define CLK_TOP_MMPLL_D2 42
61 #define CLK_TOP_DMPLL 43
62 #define CLK_TOP_DMPLL_D2 44
63 #define CLK_TOP_DMPLL_D4 45
64 #define CLK_TOP_DMPLL_X2 46
65 #define CLK_TOP_TVDPLL 47
66 #define CLK_TOP_TVDPLL_D2 48
67 #define CLK_TOP_TVDPLL_D4 49
68 #define CLK_TOP_TVD2PLL 50
69 #define CLK_TOP_TVD2PLL_D2 51
70 #define CLK_TOP_HADDS2PLL_98M 52
71 #define CLK_TOP_HADDS2PLL_294M 53
72 #define CLK_TOP_HADDS2_FB 54
73 #define CLK_TOP_MIPIPLL_D2 55
74 #define CLK_TOP_MIPIPLL_D4 56
75 #define CLK_TOP_HDMIPLL 57
76 #define CLK_TOP_HDMIPLL_D2 58
77 #define CLK_TOP_HDMIPLL_D3 59
78 #define CLK_TOP_HDMI_SCL_RX 60
79 #define CLK_TOP_HDMI_0_PIX340M 61
80 #define CLK_TOP_HDMI_0_DEEP340M 62
81 #define CLK_TOP_HDMI_0_PLL340M 63
82 #define CLK_TOP_AUD1PLL_98M 64
83 #define CLK_TOP_AUD2PLL_90M 65
84 #define CLK_TOP_AUDPLL 66
85 #define CLK_TOP_AUDPLL_D4 67
86 #define CLK_TOP_AUDPLL_D8 68
87 #define CLK_TOP_AUDPLL_D16 69
88 #define CLK_TOP_AUDPLL_D24 70
89 #define CLK_TOP_ETHPLL_500M 71
90 #define CLK_TOP_VDECPLL 72
91 #define CLK_TOP_VENCPLL 73
92 #define CLK_TOP_MIPIPLL 74
93 #define CLK_TOP_ARMPLL_1P3G 75
95 #define CLK_TOP_MM_SEL 76
96 #define CLK_TOP_DDRPHYCFG_SEL 77
97 #define CLK_TOP_MEM_SEL 78
98 #define CLK_TOP_AXI_SEL 79
99 #define CLK_TOP_CAMTG_SEL 80
100 #define CLK_TOP_MFG_SEL 81
101 #define CLK_TOP_VDEC_SEL 82
102 #define CLK_TOP_PWM_SEL 83
103 #define CLK_TOP_MSDC30_0_SEL 84
104 #define CLK_TOP_USB20_SEL 85
105 #define CLK_TOP_SPI0_SEL 86
106 #define CLK_TOP_UART_SEL 87
107 #define CLK_TOP_AUDINTBUS_SEL 88
108 #define CLK_TOP_AUDIO_SEL 89
109 #define CLK_TOP_MSDC30_2_SEL 90
110 #define CLK_TOP_MSDC30_1_SEL 91
111 #define CLK_TOP_DPI1_SEL 92
112 #define CLK_TOP_DPI0_SEL 93
113 #define CLK_TOP_SCP_SEL 94
114 #define CLK_TOP_PMICSPI_SEL 95
115 #define CLK_TOP_APLL_SEL 96
116 #define CLK_TOP_HDMI_SEL 97
117 #define CLK_TOP_TVE_SEL 98
118 #define CLK_TOP_EMMC_HCLK_SEL 99
119 #define CLK_TOP_NFI2X_SEL 100
120 #define CLK_TOP_RTC_SEL 101
121 #define CLK_TOP_OSD_SEL 102
122 #define CLK_TOP_NR_SEL 103
123 #define CLK_TOP_DI_SEL 104
124 #define CLK_TOP_FLASH_SEL 105
125 #define CLK_TOP_ASM_M_SEL 106
126 #define CLK_TOP_ASM_I_SEL 107
127 #define CLK_TOP_INTDIR_SEL 108
128 #define CLK_TOP_HDMIRX_BIST_SEL 109
129 #define CLK_TOP_ETHIF_SEL 110
130 #define CLK_TOP_MS_CARD_SEL 111
131 #define CLK_TOP_ASM_H_SEL 112
132 #define CLK_TOP_SPI1_SEL 113
133 #define CLK_TOP_CMSYS_SEL 114
134 #define CLK_TOP_MSDC30_3_SEL 115
135 #define CLK_TOP_HDMIRX26_24_SEL 116
136 #define CLK_TOP_AUD2DVD_SEL 117
137 #define CLK_TOP_8BDAC_SEL 118
138 #define CLK_TOP_SPI2_SEL 119
139 #define CLK_TOP_AUD_MUX1_SEL 120
140 #define CLK_TOP_AUD_MUX2_SEL 121
141 #define CLK_TOP_AUDPLL_MUX_SEL 122
142 #define CLK_TOP_AUD_K1_SRC_SEL 123
143 #define CLK_TOP_AUD_K2_SRC_SEL 124
144 #define CLK_TOP_AUD_K3_SRC_SEL 125
145 #define CLK_TOP_AUD_K4_SRC_SEL 126
146 #define CLK_TOP_AUD_K5_SRC_SEL 127
147 #define CLK_TOP_AUD_K6_SRC_SEL 128
148 #define CLK_TOP_PADMCLK_SEL 129
149 #define CLK_TOP_AUD_EXTCK1_DIV 130
150 #define CLK_TOP_AUD_EXTCK2_DIV 131
151 #define CLK_TOP_AUD_MUX1_DIV 132
152 #define CLK_TOP_AUD_MUX2_DIV 133
153 #define CLK_TOP_AUD_K1_SRC_DIV 134
154 #define CLK_TOP_AUD_K2_SRC_DIV 135
155 #define CLK_TOP_AUD_K3_SRC_DIV 136
156 #define CLK_TOP_AUD_K4_SRC_DIV 137
157 #define CLK_TOP_AUD_K5_SRC_DIV 138
158 #define CLK_TOP_AUD_K6_SRC_DIV 139
159 #define CLK_TOP_AUD_I2S1_MCLK 140
160 #define CLK_TOP_AUD_I2S2_MCLK 141
161 #define CLK_TOP_AUD_I2S3_MCLK 142
162 #define CLK_TOP_AUD_I2S4_MCLK 143
163 #define CLK_TOP_AUD_I2S5_MCLK 144
164 #define CLK_TOP_AUD_I2S6_MCLK 145
165 #define CLK_TOP_AUD_48K_TIMING 146
166 #define CLK_TOP_AUD_44K_TIMING 147
168 #define CLK_TOP_32K_INTERNAL 148
169 #define CLK_TOP_32K_EXTERNAL 149
170 #define CLK_TOP_CLK26M_D8 150
171 #define CLK_TOP_8BDAC 151
172 #define CLK_TOP_WBG_DIG_416M 152
173 #define CLK_TOP_DPI 153
174 #define CLK_TOP_HDMITX_CLKDIG_CTS 154
175 #define CLK_TOP_DSI0_LNTC_DSI 155
176 #define CLK_TOP_AUD_EXT1 156
177 #define CLK_TOP_AUD_EXT2 157
178 #define CLK_TOP_NFI1X_PAD 158
179 #define CLK_TOP_AXISEL_D4 159
180 #define CLK_TOP_NR 160
182 /* APMIXEDSYS */
184 #define CLK_APMIXED_ARMPLL 1
185 #define CLK_APMIXED_MAINPLL 2
186 #define CLK_APMIXED_UNIVPLL 3
187 #define CLK_APMIXED_MMPLL 4
188 #define CLK_APMIXED_MSDCPLL 5
189 #define CLK_APMIXED_TVDPLL 6
190 #define CLK_APMIXED_AUD1PLL 7
191 #define CLK_APMIXED_TRGPLL 8
192 #define CLK_APMIXED_ETHPLL 9
193 #define CLK_APMIXED_VDECPLL 10
194 #define CLK_APMIXED_HADDS2PLL 11
195 #define CLK_APMIXED_AUD2PLL 12
196 #define CLK_APMIXED_TVD2PLL 13
197 #define CLK_APMIXED_NR 14
199 /* DDRPHY */
201 #define CLK_DDRPHY_VENCPLL 1
202 #define CLK_DDRPHY_NR 2
204 /* INFRACFG */
206 #define CLK_INFRA_DBG 1
207 #define CLK_INFRA_SMI 2
208 #define CLK_INFRA_QAXI_CM4 3
209 #define CLK_INFRA_AUD_SPLIN_B 4
210 #define CLK_INFRA_AUDIO 5
211 #define CLK_INFRA_EFUSE 6
212 #define CLK_INFRA_L2C_SRAM 7
213 #define CLK_INFRA_M4U 8
214 #define CLK_INFRA_CONNMCU 9
215 #define CLK_INFRA_TRNG 10
216 #define CLK_INFRA_RAMBUFIF 11
217 #define CLK_INFRA_CPUM 12
218 #define CLK_INFRA_KP 13
219 #define CLK_INFRA_CEC 14
220 #define CLK_INFRA_IRRX 15
221 #define CLK_INFRA_PMICSPI 16
222 #define CLK_INFRA_PMICWRAP 17
223 #define CLK_INFRA_DDCCI 18
224 #define CLK_INFRA_CLK_13M 19
225 #define CLK_INFRA_CPUSEL 20
226 #define CLK_INFRA_NR 21
228 /* PERICFG */
230 #define CLK_PERI_NFI 1
231 #define CLK_PERI_THERM 2
232 #define CLK_PERI_PWM1 3
233 #define CLK_PERI_PWM2 4
234 #define CLK_PERI_PWM3 5
235 #define CLK_PERI_PWM4 6
236 #define CLK_PERI_PWM5 7
237 #define CLK_PERI_PWM6 8
238 #define CLK_PERI_PWM7 9
239 #define CLK_PERI_PWM 10
240 #define CLK_PERI_USB0 11
241 #define CLK_PERI_USB1 12
242 #define CLK_PERI_AP_DMA 13
243 #define CLK_PERI_MSDC30_0 14
244 #define CLK_PERI_MSDC30_1 15
245 #define CLK_PERI_MSDC30_2 16
246 #define CLK_PERI_MSDC30_3 17
247 #define CLK_PERI_MSDC50_3 18
248 #define CLK_PERI_NLI 19
249 #define CLK_PERI_UART0 20
250 #define CLK_PERI_UART1 21
251 #define CLK_PERI_UART2 22
252 #define CLK_PERI_UART3 23
253 #define CLK_PERI_BTIF 24
254 #define CLK_PERI_I2C0 25
255 #define CLK_PERI_I2C1 26
256 #define CLK_PERI_I2C2 27
257 #define CLK_PERI_I2C3 28
258 #define CLK_PERI_AUXADC 29
259 #define CLK_PERI_SPI0 30
260 #define CLK_PERI_ETH 31
261 #define CLK_PERI_USB0_MCU 32
263 #define CLK_PERI_USB1_MCU 33
264 #define CLK_PERI_USB_SLV 34
265 #define CLK_PERI_GCPU 35
266 #define CLK_PERI_NFI_ECC 36
267 #define CLK_PERI_NFI_PAD 37
268 #define CLK_PERI_FLASH 38
269 #define CLK_PERI_HOST89_INT 39
270 #define CLK_PERI_HOST89_SPI 40
271 #define CLK_PERI_HOST89_DVD 41
272 #define CLK_PERI_SPI1 42
273 #define CLK_PERI_SPI2 43
274 #define CLK_PERI_FCI 44
276 #define CLK_PERI_UART0_SEL 45
277 #define CLK_PERI_UART1_SEL 46
278 #define CLK_PERI_UART2_SEL 47
279 #define CLK_PERI_UART3_SEL 48
280 #define CLK_PERI_NR 49
282 /* AUDIO */
284 #define CLK_AUD_AFE 1
285 #define CLK_AUD_LRCK_DETECT 2
286 #define CLK_AUD_I2S 3
287 #define CLK_AUD_APLL_TUNER 4
288 #define CLK_AUD_HDMI 5
289 #define CLK_AUD_SPDF 6
290 #define CLK_AUD_SPDF2 7
291 #define CLK_AUD_APLL 8
292 #define CLK_AUD_TML 9
293 #define CLK_AUD_AHB_IDLE_EXT 10
294 #define CLK_AUD_AHB_IDLE_INT 11
296 #define CLK_AUD_I2SIN1 12
297 #define CLK_AUD_I2SIN2 13
298 #define CLK_AUD_I2SIN3 14
299 #define CLK_AUD_I2SIN4 15
300 #define CLK_AUD_I2SIN5 16
301 #define CLK_AUD_I2SIN6 17
302 #define CLK_AUD_I2SO1 18
303 #define CLK_AUD_I2SO2 19
304 #define CLK_AUD_I2SO3 20
305 #define CLK_AUD_I2SO4 21
306 #define CLK_AUD_I2SO5 22
307 #define CLK_AUD_I2SO6 23
308 #define CLK_AUD_ASRCI1 24
309 #define CLK_AUD_ASRCI2 25
310 #define CLK_AUD_ASRCO1 26
311 #define CLK_AUD_ASRCO2 27
312 #define CLK_AUD_ASRC11 28
313 #define CLK_AUD_ASRC12 29
314 #define CLK_AUD_HDMIRX 30
315 #define CLK_AUD_INTDIR 31
316 #define CLK_AUD_A1SYS 32
317 #define CLK_AUD_A2SYS 33
318 #define CLK_AUD_AFE_CONN 34
319 #define CLK_AUD_AFE_PCMIF 35
320 #define CLK_AUD_AFE_MRGIF 36
322 #define CLK_AUD_MMIF_UL1 37
323 #define CLK_AUD_MMIF_UL2 38
324 #define CLK_AUD_MMIF_UL3 39
325 #define CLK_AUD_MMIF_UL4 40
326 #define CLK_AUD_MMIF_UL5 41
327 #define CLK_AUD_MMIF_UL6 42
328 #define CLK_AUD_MMIF_DL1 43
329 #define CLK_AUD_MMIF_DL2 44
330 #define CLK_AUD_MMIF_DL3 45
331 #define CLK_AUD_MMIF_DL4 46
332 #define CLK_AUD_MMIF_DL5 47
333 #define CLK_AUD_MMIF_DL6 48
334 #define CLK_AUD_MMIF_DLMCH 49
335 #define CLK_AUD_MMIF_ARB1 50
336 #define CLK_AUD_MMIF_AWB1 51
337 #define CLK_AUD_MMIF_AWB2 52
338 #define CLK_AUD_MMIF_DAI 53
340 #define CLK_AUD_DMIC1 54
341 #define CLK_AUD_DMIC2 55
342 #define CLK_AUD_ASRCI3 56
343 #define CLK_AUD_ASRCI4 57
344 #define CLK_AUD_ASRCI5 58
345 #define CLK_AUD_ASRCI6 59
346 #define CLK_AUD_ASRCO3 60
347 #define CLK_AUD_ASRCO4 61
348 #define CLK_AUD_ASRCO5 62
349 #define CLK_AUD_ASRCO6 63
350 #define CLK_AUD_MEM_ASRC1 64
351 #define CLK_AUD_MEM_ASRC2 65
352 #define CLK_AUD_MEM_ASRC3 66
353 #define CLK_AUD_MEM_ASRC4 67
354 #define CLK_AUD_MEM_ASRC5 68
355 #define CLK_AUD_DSD_ENC 69
356 #define CLK_AUD_ASRC_BRG 70
357 #define CLK_AUD_NR 71
359 /* MMSYS */
361 #define CLK_MM_SMI_COMMON 1
362 #define CLK_MM_SMI_LARB0 2
363 #define CLK_MM_CMDQ 3
364 #define CLK_MM_MUTEX 4
365 #define CLK_MM_DISP_COLOR 5
366 #define CLK_MM_DISP_BLS 6
367 #define CLK_MM_DISP_WDMA 7
368 #define CLK_MM_DISP_RDMA 8
369 #define CLK_MM_DISP_OVL 9
370 #define CLK_MM_MDP_TDSHP 10
371 #define CLK_MM_MDP_WROT 11
372 #define CLK_MM_MDP_WDMA 12
373 #define CLK_MM_MDP_RSZ1 13
374 #define CLK_MM_MDP_RSZ0 14
375 #define CLK_MM_MDP_RDMA 15
376 #define CLK_MM_MDP_BLS_26M 16
377 #define CLK_MM_CAM_MDP 17
378 #define CLK_MM_FAKE_ENG 18
379 #define CLK_MM_MUTEX_32K 19
380 #define CLK_MM_DISP_RDMA1 20
381 #define CLK_MM_DISP_UFOE 21
383 #define CLK_MM_DSI_ENGINE 22
384 #define CLK_MM_DSI_DIG 23
385 #define CLK_MM_DPI_DIGL 24
386 #define CLK_MM_DPI_ENGINE 25
387 #define CLK_MM_DPI1_DIGL 26
388 #define CLK_MM_DPI1_ENGINE 27
389 #define CLK_MM_TVE_OUTPUT 28
390 #define CLK_MM_TVE_INPUT 29
391 #define CLK_MM_HDMI_PIXEL 30
392 #define CLK_MM_HDMI_PLL 31
393 #define CLK_MM_HDMI_AUDIO 32
394 #define CLK_MM_HDMI_SPDIF 33
395 #define CLK_MM_TVE_FMM 34
396 #define CLK_MM_NR 35
398 /* IMGSYS */
400 #define CLK_IMG_SMI_COMM 1
401 #define CLK_IMG_RESZ 2
402 #define CLK_IMG_JPGDEC_SMI 3
403 #define CLK_IMG_JPGDEC 4
404 #define CLK_IMG_VENC_LT 5
405 #define CLK_IMG_VENC 6
406 #define CLK_IMG_NR 7
408 /* VDEC */
410 #define CLK_VDEC_CKGEN 1
411 #define CLK_VDEC_LARB 2
412 #define CLK_VDEC_NR 3
414 /* HIFSYS */
416 #define CLK_HIFSYS_USB0PHY 1
417 #define CLK_HIFSYS_USB1PHY 2
418 #define CLK_HIFSYS_PCIE0 3
419 #define CLK_HIFSYS_PCIE1 4
420 #define CLK_HIFSYS_PCIE2 5
421 #define CLK_HIFSYS_NR 6
423 /* ETHSYS */
424 #define CLK_ETHSYS_HSDMA 1
425 #define CLK_ETHSYS_ESW 2
426 #define CLK_ETHSYS_GP2 3
427 #define CLK_ETHSYS_GP1 4
428 #define CLK_ETHSYS_PCM 5
429 #define CLK_ETHSYS_GDMA 6
430 #define CLK_ETHSYS_I2S 7
431 #define CLK_ETHSYS_CRYPTO 8
432 #define CLK_ETHSYS_NR 9
434 /* BDP */
436 #define CLK_BDP_BRG_BA 1
437 #define CLK_BDP_BRG_DRAM 2
438 #define CLK_BDP_LARB_DRAM 3
439 #define CLK_BDP_WR_VDI_PXL 4
440 #define CLK_BDP_WR_VDI_DRAM 5
441 #define CLK_BDP_WR_B 6
442 #define CLK_BDP_DGI_IN 7
443 #define CLK_BDP_DGI_OUT 8
444 #define CLK_BDP_FMT_MAST_27 9
445 #define CLK_BDP_FMT_B 10
446 #define CLK_BDP_OSD_B 11
447 #define CLK_BDP_OSD_DRAM 12
448 #define CLK_BDP_OSD_AGENT 13
449 #define CLK_BDP_OSD_PXL 14
450 #define CLK_BDP_RLE_B 15
451 #define CLK_BDP_RLE_AGENT 16
452 #define CLK_BDP_RLE_DRAM 17
453 #define CLK_BDP_F27M 18
454 #define CLK_BDP_F27M_VDOUT 19
455 #define CLK_BDP_F27_74_74 20
456 #define CLK_BDP_F2FS 21
457 #define CLK_BDP_F2FS74_148 22
458 #define CLK_BDP_FB 23
459 #define CLK_BDP_VDO_DRAM 24
460 #define CLK_BDP_VDO_2FS 25
461 #define CLK_BDP_VDO_B 26
462 #define CLK_BDP_WR_DI_PXL 27
463 #define CLK_BDP_WR_DI_DRAM 28
464 #define CLK_BDP_WR_DI_B 29
465 #define CLK_BDP_NR_PXL 30
466 #define CLK_BDP_NR_DRAM 31
467 #define CLK_BDP_NR_B 32
469 #define CLK_BDP_RX_F 33
470 #define CLK_BDP_RX_X 34
471 #define CLK_BDP_RXPDT 35
472 #define CLK_BDP_RX_CSCL_N 36
473 #define CLK_BDP_RX_CSCL 37
474 #define CLK_BDP_RX_DDCSCL_N 38
475 #define CLK_BDP_RX_DDCSCL 39
476 #define CLK_BDP_RX_VCO 40
477 #define CLK_BDP_RX_DP 41
478 #define CLK_BDP_RX_P 42
479 #define CLK_BDP_RX_M 43
480 #define CLK_BDP_RX_PLL 44
481 #define CLK_BDP_BRG_RT_B 45
482 #define CLK_BDP_BRG_RT_DRAM 46
483 #define CLK_BDP_LARBRT_DRAM 47
484 #define CLK_BDP_TMDS_SYN 48
485 #define CLK_BDP_HDMI_MON 49
486 #define CLK_BDP_NR 50