2 * Analog Devices ADAU1373 Audio Codec drive
4 * Copyright 2011 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * Licensed under the GPL-2 or later.
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
14 #include <linux/i2c.h>
15 #include <linux/slab.h>
16 #include <linux/gcd.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/tlv.h>
22 #include <sound/soc.h>
23 #include <sound/adau1373.h>
26 #include "adau-utils.h"
36 struct regmap
*regmap
;
37 struct adau1373_dai dais
[3];
40 #define ADAU1373_INPUT_MODE 0x00
41 #define ADAU1373_AINL_CTRL(x) (0x01 + (x) * 2)
42 #define ADAU1373_AINR_CTRL(x) (0x02 + (x) * 2)
43 #define ADAU1373_LLINE_OUT(x) (0x9 + (x) * 2)
44 #define ADAU1373_RLINE_OUT(x) (0xa + (x) * 2)
45 #define ADAU1373_LSPK_OUT 0x0d
46 #define ADAU1373_RSPK_OUT 0x0e
47 #define ADAU1373_LHP_OUT 0x0f
48 #define ADAU1373_RHP_OUT 0x10
49 #define ADAU1373_ADC_GAIN 0x11
50 #define ADAU1373_LADC_MIXER 0x12
51 #define ADAU1373_RADC_MIXER 0x13
52 #define ADAU1373_LLINE1_MIX 0x14
53 #define ADAU1373_RLINE1_MIX 0x15
54 #define ADAU1373_LLINE2_MIX 0x16
55 #define ADAU1373_RLINE2_MIX 0x17
56 #define ADAU1373_LSPK_MIX 0x18
57 #define ADAU1373_RSPK_MIX 0x19
58 #define ADAU1373_LHP_MIX 0x1a
59 #define ADAU1373_RHP_MIX 0x1b
60 #define ADAU1373_EP_MIX 0x1c
61 #define ADAU1373_HP_CTRL 0x1d
62 #define ADAU1373_HP_CTRL2 0x1e
63 #define ADAU1373_LS_CTRL 0x1f
64 #define ADAU1373_EP_CTRL 0x21
65 #define ADAU1373_MICBIAS_CTRL1 0x22
66 #define ADAU1373_MICBIAS_CTRL2 0x23
67 #define ADAU1373_OUTPUT_CTRL 0x24
68 #define ADAU1373_PWDN_CTRL1 0x25
69 #define ADAU1373_PWDN_CTRL2 0x26
70 #define ADAU1373_PWDN_CTRL3 0x27
71 #define ADAU1373_DPLL_CTRL(x) (0x28 + (x) * 7)
72 #define ADAU1373_PLL_CTRL1(x) (0x29 + (x) * 7)
73 #define ADAU1373_PLL_CTRL2(x) (0x2a + (x) * 7)
74 #define ADAU1373_PLL_CTRL3(x) (0x2b + (x) * 7)
75 #define ADAU1373_PLL_CTRL4(x) (0x2c + (x) * 7)
76 #define ADAU1373_PLL_CTRL5(x) (0x2d + (x) * 7)
77 #define ADAU1373_PLL_CTRL6(x) (0x2e + (x) * 7)
78 #define ADAU1373_HEADDECT 0x36
79 #define ADAU1373_ADC_DAC_STATUS 0x37
80 #define ADAU1373_ADC_CTRL 0x3c
81 #define ADAU1373_DAI(x) (0x44 + (x))
82 #define ADAU1373_CLK_SRC_DIV(x) (0x40 + (x) * 2)
83 #define ADAU1373_BCLKDIV(x) (0x47 + (x))
84 #define ADAU1373_SRC_RATIOA(x) (0x4a + (x) * 2)
85 #define ADAU1373_SRC_RATIOB(x) (0x4b + (x) * 2)
86 #define ADAU1373_DEEMP_CTRL 0x50
87 #define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x))
88 #define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x))
89 #define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x))
90 #define ADAU1373_DAI_PBL_VOL(x) (0x62 + (x) * 2)
91 #define ADAU1373_DAI_PBR_VOL(x) (0x63 + (x) * 2)
92 #define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2)
93 #define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2)
94 #define ADAU1373_DAC1_PBL_VOL 0x6e
95 #define ADAU1373_DAC1_PBR_VOL 0x6f
96 #define ADAU1373_DAC2_PBL_VOL 0x70
97 #define ADAU1373_DAC2_PBR_VOL 0x71
98 #define ADAU1373_ADC_RECL_VOL 0x72
99 #define ADAU1373_ADC_RECR_VOL 0x73
100 #define ADAU1373_DMIC_RECL_VOL 0x74
101 #define ADAU1373_DMIC_RECR_VOL 0x75
102 #define ADAU1373_VOL_GAIN1 0x76
103 #define ADAU1373_VOL_GAIN2 0x77
104 #define ADAU1373_VOL_GAIN3 0x78
105 #define ADAU1373_HPF_CTRL 0x7d
106 #define ADAU1373_BASS1 0x7e
107 #define ADAU1373_BASS2 0x7f
108 #define ADAU1373_DRC(x) (0x80 + (x) * 0x10)
109 #define ADAU1373_3D_CTRL1 0xc0
110 #define ADAU1373_3D_CTRL2 0xc1
111 #define ADAU1373_FDSP_SEL1 0xdc
112 #define ADAU1373_FDSP_SEL2 0xdd
113 #define ADAU1373_FDSP_SEL3 0xde
114 #define ADAU1373_FDSP_SEL4 0xdf
115 #define ADAU1373_DIGMICCTRL 0xe2
116 #define ADAU1373_DIGEN 0xeb
117 #define ADAU1373_SOFT_RESET 0xff
120 #define ADAU1373_PLL_CTRL6_DPLL_BYPASS BIT(1)
121 #define ADAU1373_PLL_CTRL6_PLL_EN BIT(0)
123 #define ADAU1373_DAI_INVERT_BCLK BIT(7)
124 #define ADAU1373_DAI_MASTER BIT(6)
125 #define ADAU1373_DAI_INVERT_LRCLK BIT(4)
126 #define ADAU1373_DAI_WLEN_16 0x0
127 #define ADAU1373_DAI_WLEN_20 0x4
128 #define ADAU1373_DAI_WLEN_24 0x8
129 #define ADAU1373_DAI_WLEN_32 0xc
130 #define ADAU1373_DAI_WLEN_MASK 0xc
131 #define ADAU1373_DAI_FORMAT_RIGHT_J 0x0
132 #define ADAU1373_DAI_FORMAT_LEFT_J 0x1
133 #define ADAU1373_DAI_FORMAT_I2S 0x2
134 #define ADAU1373_DAI_FORMAT_DSP 0x3
136 #define ADAU1373_BCLKDIV_SOURCE BIT(5)
137 #define ADAU1373_BCLKDIV_SR_MASK (0x07 << 2)
138 #define ADAU1373_BCLKDIV_BCLK_MASK 0x03
139 #define ADAU1373_BCLKDIV_32 0x03
140 #define ADAU1373_BCLKDIV_64 0x02
141 #define ADAU1373_BCLKDIV_128 0x01
142 #define ADAU1373_BCLKDIV_256 0x00
144 #define ADAU1373_ADC_CTRL_PEAK_DETECT BIT(0)
145 #define ADAU1373_ADC_CTRL_RESET BIT(1)
146 #define ADAU1373_ADC_CTRL_RESET_FORCE BIT(2)
148 #define ADAU1373_OUTPUT_CTRL_LDIFF BIT(3)
149 #define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2)
151 #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0)
153 #define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4
154 #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2
156 static const struct reg_default adau1373_reg_defaults
[] = {
157 { ADAU1373_INPUT_MODE
, 0x00 },
158 { ADAU1373_AINL_CTRL(0), 0x00 },
159 { ADAU1373_AINR_CTRL(0), 0x00 },
160 { ADAU1373_AINL_CTRL(1), 0x00 },
161 { ADAU1373_AINR_CTRL(1), 0x00 },
162 { ADAU1373_AINL_CTRL(2), 0x00 },
163 { ADAU1373_AINR_CTRL(2), 0x00 },
164 { ADAU1373_AINL_CTRL(3), 0x00 },
165 { ADAU1373_AINR_CTRL(3), 0x00 },
166 { ADAU1373_LLINE_OUT(0), 0x00 },
167 { ADAU1373_RLINE_OUT(0), 0x00 },
168 { ADAU1373_LLINE_OUT(1), 0x00 },
169 { ADAU1373_RLINE_OUT(1), 0x00 },
170 { ADAU1373_LSPK_OUT
, 0x00 },
171 { ADAU1373_RSPK_OUT
, 0x00 },
172 { ADAU1373_LHP_OUT
, 0x00 },
173 { ADAU1373_RHP_OUT
, 0x00 },
174 { ADAU1373_ADC_GAIN
, 0x00 },
175 { ADAU1373_LADC_MIXER
, 0x00 },
176 { ADAU1373_RADC_MIXER
, 0x00 },
177 { ADAU1373_LLINE1_MIX
, 0x00 },
178 { ADAU1373_RLINE1_MIX
, 0x00 },
179 { ADAU1373_LLINE2_MIX
, 0x00 },
180 { ADAU1373_RLINE2_MIX
, 0x00 },
181 { ADAU1373_LSPK_MIX
, 0x00 },
182 { ADAU1373_RSPK_MIX
, 0x00 },
183 { ADAU1373_LHP_MIX
, 0x00 },
184 { ADAU1373_RHP_MIX
, 0x00 },
185 { ADAU1373_EP_MIX
, 0x00 },
186 { ADAU1373_HP_CTRL
, 0x00 },
187 { ADAU1373_HP_CTRL2
, 0x00 },
188 { ADAU1373_LS_CTRL
, 0x00 },
189 { ADAU1373_EP_CTRL
, 0x00 },
190 { ADAU1373_MICBIAS_CTRL1
, 0x00 },
191 { ADAU1373_MICBIAS_CTRL2
, 0x00 },
192 { ADAU1373_OUTPUT_CTRL
, 0x00 },
193 { ADAU1373_PWDN_CTRL1
, 0x00 },
194 { ADAU1373_PWDN_CTRL2
, 0x00 },
195 { ADAU1373_PWDN_CTRL3
, 0x00 },
196 { ADAU1373_DPLL_CTRL(0), 0x00 },
197 { ADAU1373_PLL_CTRL1(0), 0x00 },
198 { ADAU1373_PLL_CTRL2(0), 0x00 },
199 { ADAU1373_PLL_CTRL3(0), 0x00 },
200 { ADAU1373_PLL_CTRL4(0), 0x00 },
201 { ADAU1373_PLL_CTRL5(0), 0x00 },
202 { ADAU1373_PLL_CTRL6(0), 0x02 },
203 { ADAU1373_DPLL_CTRL(1), 0x00 },
204 { ADAU1373_PLL_CTRL1(1), 0x00 },
205 { ADAU1373_PLL_CTRL2(1), 0x00 },
206 { ADAU1373_PLL_CTRL3(1), 0x00 },
207 { ADAU1373_PLL_CTRL4(1), 0x00 },
208 { ADAU1373_PLL_CTRL5(1), 0x00 },
209 { ADAU1373_PLL_CTRL6(1), 0x02 },
210 { ADAU1373_HEADDECT
, 0x00 },
211 { ADAU1373_ADC_CTRL
, 0x00 },
212 { ADAU1373_CLK_SRC_DIV(0), 0x00 },
213 { ADAU1373_CLK_SRC_DIV(1), 0x00 },
214 { ADAU1373_DAI(0), 0x0a },
215 { ADAU1373_DAI(1), 0x0a },
216 { ADAU1373_DAI(2), 0x0a },
217 { ADAU1373_BCLKDIV(0), 0x00 },
218 { ADAU1373_BCLKDIV(1), 0x00 },
219 { ADAU1373_BCLKDIV(2), 0x00 },
220 { ADAU1373_SRC_RATIOA(0), 0x00 },
221 { ADAU1373_SRC_RATIOB(0), 0x00 },
222 { ADAU1373_SRC_RATIOA(1), 0x00 },
223 { ADAU1373_SRC_RATIOB(1), 0x00 },
224 { ADAU1373_SRC_RATIOA(2), 0x00 },
225 { ADAU1373_SRC_RATIOB(2), 0x00 },
226 { ADAU1373_DEEMP_CTRL
, 0x00 },
227 { ADAU1373_SRC_DAI_CTRL(0), 0x08 },
228 { ADAU1373_SRC_DAI_CTRL(1), 0x08 },
229 { ADAU1373_SRC_DAI_CTRL(2), 0x08 },
230 { ADAU1373_DIN_MIX_CTRL(0), 0x00 },
231 { ADAU1373_DIN_MIX_CTRL(1), 0x00 },
232 { ADAU1373_DIN_MIX_CTRL(2), 0x00 },
233 { ADAU1373_DIN_MIX_CTRL(3), 0x00 },
234 { ADAU1373_DIN_MIX_CTRL(4), 0x00 },
235 { ADAU1373_DOUT_MIX_CTRL(0), 0x00 },
236 { ADAU1373_DOUT_MIX_CTRL(1), 0x00 },
237 { ADAU1373_DOUT_MIX_CTRL(2), 0x00 },
238 { ADAU1373_DOUT_MIX_CTRL(3), 0x00 },
239 { ADAU1373_DOUT_MIX_CTRL(4), 0x00 },
240 { ADAU1373_DAI_PBL_VOL(0), 0x00 },
241 { ADAU1373_DAI_PBR_VOL(0), 0x00 },
242 { ADAU1373_DAI_PBL_VOL(1), 0x00 },
243 { ADAU1373_DAI_PBR_VOL(1), 0x00 },
244 { ADAU1373_DAI_PBL_VOL(2), 0x00 },
245 { ADAU1373_DAI_PBR_VOL(2), 0x00 },
246 { ADAU1373_DAI_RECL_VOL(0), 0x00 },
247 { ADAU1373_DAI_RECR_VOL(0), 0x00 },
248 { ADAU1373_DAI_RECL_VOL(1), 0x00 },
249 { ADAU1373_DAI_RECR_VOL(1), 0x00 },
250 { ADAU1373_DAI_RECL_VOL(2), 0x00 },
251 { ADAU1373_DAI_RECR_VOL(2), 0x00 },
252 { ADAU1373_DAC1_PBL_VOL
, 0x00 },
253 { ADAU1373_DAC1_PBR_VOL
, 0x00 },
254 { ADAU1373_DAC2_PBL_VOL
, 0x00 },
255 { ADAU1373_DAC2_PBR_VOL
, 0x00 },
256 { ADAU1373_ADC_RECL_VOL
, 0x00 },
257 { ADAU1373_ADC_RECR_VOL
, 0x00 },
258 { ADAU1373_DMIC_RECL_VOL
, 0x00 },
259 { ADAU1373_DMIC_RECR_VOL
, 0x00 },
260 { ADAU1373_VOL_GAIN1
, 0x00 },
261 { ADAU1373_VOL_GAIN2
, 0x00 },
262 { ADAU1373_VOL_GAIN3
, 0x00 },
263 { ADAU1373_HPF_CTRL
, 0x00 },
264 { ADAU1373_BASS1
, 0x00 },
265 { ADAU1373_BASS2
, 0x00 },
266 { ADAU1373_DRC(0) + 0x0, 0x78 },
267 { ADAU1373_DRC(0) + 0x1, 0x18 },
268 { ADAU1373_DRC(0) + 0x2, 0x00 },
269 { ADAU1373_DRC(0) + 0x3, 0x00 },
270 { ADAU1373_DRC(0) + 0x4, 0x00 },
271 { ADAU1373_DRC(0) + 0x5, 0xc0 },
272 { ADAU1373_DRC(0) + 0x6, 0x00 },
273 { ADAU1373_DRC(0) + 0x7, 0x00 },
274 { ADAU1373_DRC(0) + 0x8, 0x00 },
275 { ADAU1373_DRC(0) + 0x9, 0xc0 },
276 { ADAU1373_DRC(0) + 0xa, 0x88 },
277 { ADAU1373_DRC(0) + 0xb, 0x7a },
278 { ADAU1373_DRC(0) + 0xc, 0xdf },
279 { ADAU1373_DRC(0) + 0xd, 0x20 },
280 { ADAU1373_DRC(0) + 0xe, 0x00 },
281 { ADAU1373_DRC(0) + 0xf, 0x00 },
282 { ADAU1373_DRC(1) + 0x0, 0x78 },
283 { ADAU1373_DRC(1) + 0x1, 0x18 },
284 { ADAU1373_DRC(1) + 0x2, 0x00 },
285 { ADAU1373_DRC(1) + 0x3, 0x00 },
286 { ADAU1373_DRC(1) + 0x4, 0x00 },
287 { ADAU1373_DRC(1) + 0x5, 0xc0 },
288 { ADAU1373_DRC(1) + 0x6, 0x00 },
289 { ADAU1373_DRC(1) + 0x7, 0x00 },
290 { ADAU1373_DRC(1) + 0x8, 0x00 },
291 { ADAU1373_DRC(1) + 0x9, 0xc0 },
292 { ADAU1373_DRC(1) + 0xa, 0x88 },
293 { ADAU1373_DRC(1) + 0xb, 0x7a },
294 { ADAU1373_DRC(1) + 0xc, 0xdf },
295 { ADAU1373_DRC(1) + 0xd, 0x20 },
296 { ADAU1373_DRC(1) + 0xe, 0x00 },
297 { ADAU1373_DRC(1) + 0xf, 0x00 },
298 { ADAU1373_DRC(2) + 0x0, 0x78 },
299 { ADAU1373_DRC(2) + 0x1, 0x18 },
300 { ADAU1373_DRC(2) + 0x2, 0x00 },
301 { ADAU1373_DRC(2) + 0x3, 0x00 },
302 { ADAU1373_DRC(2) + 0x4, 0x00 },
303 { ADAU1373_DRC(2) + 0x5, 0xc0 },
304 { ADAU1373_DRC(2) + 0x6, 0x00 },
305 { ADAU1373_DRC(2) + 0x7, 0x00 },
306 { ADAU1373_DRC(2) + 0x8, 0x00 },
307 { ADAU1373_DRC(2) + 0x9, 0xc0 },
308 { ADAU1373_DRC(2) + 0xa, 0x88 },
309 { ADAU1373_DRC(2) + 0xb, 0x7a },
310 { ADAU1373_DRC(2) + 0xc, 0xdf },
311 { ADAU1373_DRC(2) + 0xd, 0x20 },
312 { ADAU1373_DRC(2) + 0xe, 0x00 },
313 { ADAU1373_DRC(2) + 0xf, 0x00 },
314 { ADAU1373_3D_CTRL1
, 0x00 },
315 { ADAU1373_3D_CTRL2
, 0x00 },
316 { ADAU1373_FDSP_SEL1
, 0x00 },
317 { ADAU1373_FDSP_SEL2
, 0x00 },
318 { ADAU1373_FDSP_SEL2
, 0x00 },
319 { ADAU1373_FDSP_SEL4
, 0x00 },
320 { ADAU1373_DIGMICCTRL
, 0x00 },
321 { ADAU1373_DIGEN
, 0x00 },
324 static const DECLARE_TLV_DB_RANGE(adau1373_out_tlv
,
325 0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
326 8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0),
327 16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0),
328 24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0)
331 static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv
, -9563, 0);
332 static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv
, -1300, 100, 1);
333 static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv
, -600, 600, 1);
335 static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv
, 0, 2000, 0);
336 static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv
, 0, 600, 0);
337 static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv
, 1200, 600, 0);
339 static const char *adau1373_fdsp_sel_text
[] = {
348 static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum
,
349 ADAU1373_FDSP_SEL1
, 4, adau1373_fdsp_sel_text
);
350 static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum
,
351 ADAU1373_FDSP_SEL1
, 0, adau1373_fdsp_sel_text
);
352 static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum
,
353 ADAU1373_FDSP_SEL2
, 0, adau1373_fdsp_sel_text
);
354 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum
,
355 ADAU1373_FDSP_SEL3
, 0, adau1373_fdsp_sel_text
);
356 static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum
,
357 ADAU1373_FDSP_SEL4
, 4, adau1373_fdsp_sel_text
);
359 static const char *adau1373_hpf_cutoff_text
[] = {
360 "3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz",
361 "400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz",
365 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum
,
366 ADAU1373_HPF_CTRL
, 3, adau1373_hpf_cutoff_text
);
368 static const char *adau1373_bass_lpf_cutoff_text
[] = {
372 static const char *adau1373_bass_clip_level_text
[] = {
373 "0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875",
376 static const unsigned int adau1373_bass_clip_level_values
[] = {
380 static const char *adau1373_bass_hpf_cutoff_text
[] = {
381 "158Hz", "232Hz", "347Hz", "520Hz",
384 static const DECLARE_TLV_DB_RANGE(adau1373_bass_tlv
,
385 0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1),
386 3, 4, TLV_DB_SCALE_ITEM(950, 250, 0),
387 5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0)
390 static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum
,
391 ADAU1373_BASS1
, 5, adau1373_bass_lpf_cutoff_text
);
393 static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum
,
394 ADAU1373_BASS1
, 2, 7, adau1373_bass_clip_level_text
,
395 adau1373_bass_clip_level_values
);
397 static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum
,
398 ADAU1373_BASS1
, 0, adau1373_bass_hpf_cutoff_text
);
400 static const char *adau1373_3d_level_text
[] = {
401 "0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%",
402 "40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%",
403 "80%", "86.67", "99.33%", "100%"
406 static const char *adau1373_3d_cutoff_text
[] = {
407 "No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs",
408 "0.16875 fs", "0.27083 fs"
411 static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum
,
412 ADAU1373_3D_CTRL1
, 4, adau1373_3d_level_text
);
413 static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum
,
414 ADAU1373_3D_CTRL1
, 0, adau1373_3d_cutoff_text
);
416 static const DECLARE_TLV_DB_RANGE(adau1373_3d_tlv
,
417 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
418 1, 7, TLV_DB_LINEAR_ITEM(-1800, -120)
421 static const char *adau1373_lr_mux_text
[] = {
423 "Right Channel (L+R)",
424 "Left Channel (L+R)",
428 static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum
,
429 ADAU1373_OUTPUT_CTRL
, 4, adau1373_lr_mux_text
);
430 static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum
,
431 ADAU1373_OUTPUT_CTRL
, 6, adau1373_lr_mux_text
);
432 static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum
,
433 ADAU1373_LS_CTRL
, 4, adau1373_lr_mux_text
);
435 static const struct snd_kcontrol_new adau1373_controls
[] = {
436 SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0),
437 ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv
),
438 SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1),
439 ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv
),
440 SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2),
441 ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv
),
443 SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL
,
444 ADAU1373_ADC_RECR_VOL
, 0, 0xff, 1, adau1373_digital_tlv
),
445 SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL
,
446 ADAU1373_DMIC_RECR_VOL
, 0, 0xff, 1, adau1373_digital_tlv
),
448 SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0),
449 ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv
),
450 SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1),
451 ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv
),
452 SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2),
453 ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv
),
455 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL
,
456 ADAU1373_DAC1_PBR_VOL
, 0, 0xff, 1, adau1373_digital_tlv
),
457 SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL
,
458 ADAU1373_DAC2_PBR_VOL
, 0, 0xff, 1, adau1373_digital_tlv
),
460 SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0),
461 ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv
),
462 SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT
,
463 ADAU1373_RSPK_OUT
, 0, 0x1f, 0, adau1373_out_tlv
),
464 SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT
,
465 ADAU1373_RHP_OUT
, 0, 0x1f, 0, adau1373_out_tlv
),
467 SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0),
468 ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv
),
469 SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1),
470 ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv
),
471 SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2),
472 ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv
),
473 SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3),
474 ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv
),
476 SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL
, 0, 3, 0,
479 SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1
, 4, 5,
480 1, 0, adau1373_gain_boost_tlv
),
481 SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1
, 2, 3,
482 1, 0, adau1373_gain_boost_tlv
),
483 SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1
, 0, 1,
484 1, 0, adau1373_gain_boost_tlv
),
485 SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2
, 4, 5,
486 1, 0, adau1373_gain_boost_tlv
),
487 SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2
, 2, 3,
488 1, 0, adau1373_gain_boost_tlv
),
489 SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2
, 0, 1,
490 1, 0, adau1373_gain_boost_tlv
),
491 SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3
, 6, 7,
492 1, 0, adau1373_gain_boost_tlv
),
493 SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3
, 4, 5,
494 1, 0, adau1373_gain_boost_tlv
),
495 SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3
, 2, 3,
496 1, 0, adau1373_gain_boost_tlv
),
497 SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3
, 0, 1,
498 1, 0, adau1373_gain_boost_tlv
),
500 SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN
, 0, 4,
501 1, 0, adau1373_input_boost_tlv
),
502 SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN
, 1, 5,
503 1, 0, adau1373_input_boost_tlv
),
504 SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN
, 2, 6,
505 1, 0, adau1373_input_boost_tlv
),
506 SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN
, 3, 7,
507 1, 0, adau1373_input_boost_tlv
),
509 SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL
, 2, 3,
510 1, 0, adau1373_speaker_boost_tlv
),
512 SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum
),
513 SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum
),
515 SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum
),
516 SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL
, 1, 0, 1, 0),
517 SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum
),
519 SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum
),
520 SOC_ENUM("Bass Clip Level Threshold", adau1373_bass_clip_level_enum
),
521 SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum
),
522 SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2
, 0, 1, 1, 0),
523 SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2
, 2, 7, 0,
525 SOC_ENUM("Bass Channel", adau1373_bass_channel_enum
),
527 SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum
),
528 SOC_ENUM("3D Level", adau1373_3d_level_enum
),
529 SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2
, 0, 1, 0),
530 SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2
, 2, 7, 0,
532 SOC_ENUM("3D Channel", adau1373_bass_channel_enum
),
534 SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3
, 7, 1, 0),
537 static const struct snd_kcontrol_new adau1373_lineout2_controls
[] = {
538 SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1),
539 ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv
),
540 SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum
),
543 static const struct snd_kcontrol_new adau1373_drc_controls
[] = {
544 SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum
),
545 SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum
),
546 SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum
),
549 static int adau1373_pll_event(struct snd_soc_dapm_widget
*w
,
550 struct snd_kcontrol
*kcontrol
, int event
)
552 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
553 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(codec
);
554 unsigned int pll_id
= w
->name
[3] - '1';
557 if (SND_SOC_DAPM_EVENT_ON(event
))
558 val
= ADAU1373_PLL_CTRL6_PLL_EN
;
562 regmap_update_bits(adau1373
->regmap
, ADAU1373_PLL_CTRL6(pll_id
),
563 ADAU1373_PLL_CTRL6_PLL_EN
, val
);
565 if (SND_SOC_DAPM_EVENT_ON(event
))
571 static const char *adau1373_decimator_text
[] = {
576 static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum
,
577 adau1373_decimator_text
);
579 static const struct snd_kcontrol_new adau1373_decimator_mux
=
580 SOC_DAPM_ENUM("Decimator Mux", adau1373_decimator_enum
);
582 static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls
[] = {
583 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER
, 4, 1, 0),
584 SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER
, 3, 1, 0),
585 SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER
, 2, 1, 0),
586 SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER
, 1, 1, 0),
587 SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER
, 0, 1, 0),
590 static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls
[] = {
591 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER
, 4, 1, 0),
592 SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER
, 3, 1, 0),
593 SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER
, 2, 1, 0),
594 SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER
, 1, 1, 0),
595 SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER
, 0, 1, 0),
598 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \
599 const struct snd_kcontrol_new _name[] = { \
600 SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \
601 SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \
602 SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \
603 SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \
604 SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
605 SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
606 SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
607 SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
610 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls
,
611 ADAU1373_LLINE1_MIX
);
612 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls
,
613 ADAU1373_RLINE1_MIX
);
614 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls
,
615 ADAU1373_LLINE2_MIX
);
616 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls
,
617 ADAU1373_RLINE2_MIX
);
618 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls
,
620 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls
,
622 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls
,
625 static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls
[] = {
626 SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX
, 5, 1, 0),
627 SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX
, 4, 1, 0),
628 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX
, 3, 1, 0),
629 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX
, 2, 1, 0),
630 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX
, 1, 1, 0),
631 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX
, 0, 1, 0),
634 static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls
[] = {
635 SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX
, 5, 1, 0),
636 SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX
, 4, 1, 0),
637 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX
, 3, 1, 0),
638 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX
, 2, 1, 0),
639 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX
, 1, 1, 0),
640 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX
, 0, 1, 0),
643 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \
644 const struct snd_kcontrol_new _name[] = { \
645 SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \
646 SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \
647 SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \
648 SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \
649 SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \
650 SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \
651 SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \
654 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls
,
655 ADAU1373_DIN_MIX_CTRL(0));
656 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls
,
657 ADAU1373_DIN_MIX_CTRL(1));
658 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls
,
659 ADAU1373_DIN_MIX_CTRL(2));
660 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls
,
661 ADAU1373_DIN_MIX_CTRL(3));
662 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls
,
663 ADAU1373_DIN_MIX_CTRL(4));
665 #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \
666 const struct snd_kcontrol_new _name[] = { \
667 SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \
668 SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \
669 SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \
670 SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \
671 SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \
674 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls
,
675 ADAU1373_DOUT_MIX_CTRL(0));
676 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls
,
677 ADAU1373_DOUT_MIX_CTRL(1));
678 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls
,
679 ADAU1373_DOUT_MIX_CTRL(2));
680 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls
,
681 ADAU1373_DOUT_MIX_CTRL(3));
682 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls
,
683 ADAU1373_DOUT_MIX_CTRL(4));
685 static const struct snd_soc_dapm_widget adau1373_dapm_widgets
[] = {
686 /* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that
687 * doesn't seem to be the case. */
688 SND_SOC_DAPM_ADC("Left ADC", NULL
, ADAU1373_PWDN_CTRL1
, 7, 0),
689 SND_SOC_DAPM_ADC("Right ADC", NULL
, ADAU1373_PWDN_CTRL1
, 6, 0),
691 SND_SOC_DAPM_ADC("DMIC1", NULL
, ADAU1373_DIGMICCTRL
, 0, 0),
692 SND_SOC_DAPM_ADC("DMIC2", NULL
, ADAU1373_DIGMICCTRL
, 2, 0),
694 SND_SOC_DAPM_MUX("Decimator Mux", SND_SOC_NOPM
, 0, 0,
695 &adau1373_decimator_mux
),
697 SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1
, 5, 0, NULL
, 0),
698 SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1
, 4, 0, NULL
, 0),
700 SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1
, 3, 0, NULL
, 0),
701 SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1
, 2, 0, NULL
, 0),
702 SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1
, 1, 0, NULL
, 0),
703 SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1
, 0, 0, NULL
, 0),
705 SND_SOC_DAPM_DAC("Left DAC2", NULL
, ADAU1373_PWDN_CTRL2
, 7, 0),
706 SND_SOC_DAPM_DAC("Right DAC2", NULL
, ADAU1373_PWDN_CTRL2
, 6, 0),
707 SND_SOC_DAPM_DAC("Left DAC1", NULL
, ADAU1373_PWDN_CTRL2
, 5, 0),
708 SND_SOC_DAPM_DAC("Right DAC1", NULL
, ADAU1373_PWDN_CTRL2
, 4, 0),
710 SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM
, 0, 0,
711 adau1373_left_adc_mixer_controls
),
712 SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM
, 0, 0,
713 adau1373_right_adc_mixer_controls
),
715 SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2
, 3, 0,
716 adau1373_left_line2_mixer_controls
),
717 SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2
, 2, 0,
718 adau1373_right_line2_mixer_controls
),
719 SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2
, 1, 0,
720 adau1373_left_line1_mixer_controls
),
721 SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2
, 0, 0,
722 adau1373_right_line1_mixer_controls
),
724 SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3
, 4, 0,
725 adau1373_ep_mixer_controls
),
726 SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3
, 3, 0,
727 adau1373_left_spk_mixer_controls
),
728 SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3
, 2, 0,
729 adau1373_right_spk_mixer_controls
),
730 SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM
, 0, 0,
731 adau1373_left_hp_mixer_controls
),
732 SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM
, 0, 0,
733 adau1373_right_hp_mixer_controls
),
734 SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3
, 1, 0,
737 SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0,
739 SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0,
741 SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0,
743 SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0,
745 SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0,
747 SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0,
749 SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0,
751 SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0,
753 SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0,
756 SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM
, 0, 0),
757 SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM
, 0, 0),
758 SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM
, 0, 0),
759 SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM
, 0, 0),
760 SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM
, 0, 0),
761 SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM
, 0, 0),
763 SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM
, 0, 0,
764 adau1373_dsp_channel1_mixer_controls
),
765 SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM
, 0, 0,
766 adau1373_dsp_channel2_mixer_controls
),
767 SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM
, 0, 0,
768 adau1373_dsp_channel3_mixer_controls
),
769 SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM
, 0, 0,
770 adau1373_dsp_channel4_mixer_controls
),
771 SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM
, 0, 0,
772 adau1373_dsp_channel5_mixer_controls
),
774 SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM
, 0, 0,
775 adau1373_aif1_mixer_controls
),
776 SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM
, 0, 0,
777 adau1373_aif2_mixer_controls
),
778 SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM
, 0, 0,
779 adau1373_aif3_mixer_controls
),
780 SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM
, 0, 0,
781 adau1373_dac1_mixer_controls
),
782 SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM
, 0, 0,
783 adau1373_dac2_mixer_controls
),
785 SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN
, 4, 0, NULL
, 0),
786 SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN
, 3, 0, NULL
, 0),
787 SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN
, 2, 0, NULL
, 0),
788 SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN
, 1, 0, NULL
, 0),
789 SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN
, 0, 0, NULL
, 0),
791 SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM
, 0, 0, adau1373_pll_event
,
792 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
793 SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM
, 0, 0, adau1373_pll_event
,
794 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
795 SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL
, 0),
796 SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL
, 0),
798 SND_SOC_DAPM_INPUT("AIN1L"),
799 SND_SOC_DAPM_INPUT("AIN1R"),
800 SND_SOC_DAPM_INPUT("AIN2L"),
801 SND_SOC_DAPM_INPUT("AIN2R"),
802 SND_SOC_DAPM_INPUT("AIN3L"),
803 SND_SOC_DAPM_INPUT("AIN3R"),
804 SND_SOC_DAPM_INPUT("AIN4L"),
805 SND_SOC_DAPM_INPUT("AIN4R"),
807 SND_SOC_DAPM_INPUT("DMIC1DAT"),
808 SND_SOC_DAPM_INPUT("DMIC2DAT"),
810 SND_SOC_DAPM_OUTPUT("LOUT1L"),
811 SND_SOC_DAPM_OUTPUT("LOUT1R"),
812 SND_SOC_DAPM_OUTPUT("LOUT2L"),
813 SND_SOC_DAPM_OUTPUT("LOUT2R"),
814 SND_SOC_DAPM_OUTPUT("HPL"),
815 SND_SOC_DAPM_OUTPUT("HPR"),
816 SND_SOC_DAPM_OUTPUT("SPKL"),
817 SND_SOC_DAPM_OUTPUT("SPKR"),
818 SND_SOC_DAPM_OUTPUT("EP"),
821 static int adau1373_check_aif_clk(struct snd_soc_dapm_widget
*source
,
822 struct snd_soc_dapm_widget
*sink
)
824 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(source
->dapm
);
825 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(codec
);
829 dai
= sink
->name
[3] - '1';
831 if (!adau1373
->dais
[dai
].master
)
834 if (adau1373
->dais
[dai
].clk_src
== ADAU1373_CLK_SRC_PLL1
)
839 return strcmp(source
->name
, clk
) == 0;
842 static int adau1373_check_src(struct snd_soc_dapm_widget
*source
,
843 struct snd_soc_dapm_widget
*sink
)
845 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(source
->dapm
);
846 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(codec
);
849 dai
= sink
->name
[3] - '1';
851 return adau1373
->dais
[dai
].enable_src
;
854 #define DSP_CHANNEL_MIXER_ROUTES(_sink) \
855 { _sink, "DMIC2 Swapped Switch", "DMIC2" }, \
856 { _sink, "DMIC2 Switch", "DMIC2" }, \
857 { _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \
858 { _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \
859 { _sink, "AIF1 Switch", "AIF1 IN" }, \
860 { _sink, "AIF2 Switch", "AIF2 IN" }, \
861 { _sink, "AIF3 Switch", "AIF3 IN" }
863 #define DSP_OUTPUT_MIXER_ROUTES(_sink) \
864 { _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \
865 { _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \
866 { _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \
867 { _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \
868 { _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" }
870 #define LEFT_OUTPUT_MIXER_ROUTES(_sink) \
871 { _sink, "Right DAC2 Switch", "Right DAC2" }, \
872 { _sink, "Left DAC2 Switch", "Left DAC2" }, \
873 { _sink, "Right DAC1 Switch", "Right DAC1" }, \
874 { _sink, "Left DAC1 Switch", "Left DAC1" }, \
875 { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
876 { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
877 { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
878 { _sink, "Input 4 Bypass Switch", "IN4PGA" }
880 #define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \
881 { _sink, "Right DAC2 Switch", "Right DAC2" }, \
882 { _sink, "Left DAC2 Switch", "Left DAC2" }, \
883 { _sink, "Right DAC1 Switch", "Right DAC1" }, \
884 { _sink, "Left DAC1 Switch", "Left DAC1" }, \
885 { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
886 { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
887 { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
888 { _sink, "Input 4 Bypass Switch", "IN4PGA" }
890 static const struct snd_soc_dapm_route adau1373_dapm_routes
[] = {
891 { "Left ADC Mixer", "DAC1 Switch", "Left DAC1" },
892 { "Left ADC Mixer", "Input 1 Switch", "IN1PGA" },
893 { "Left ADC Mixer", "Input 2 Switch", "IN2PGA" },
894 { "Left ADC Mixer", "Input 3 Switch", "IN3PGA" },
895 { "Left ADC Mixer", "Input 4 Switch", "IN4PGA" },
897 { "Right ADC Mixer", "DAC1 Switch", "Right DAC1" },
898 { "Right ADC Mixer", "Input 1 Switch", "IN1PGA" },
899 { "Right ADC Mixer", "Input 2 Switch", "IN2PGA" },
900 { "Right ADC Mixer", "Input 3 Switch", "IN3PGA" },
901 { "Right ADC Mixer", "Input 4 Switch", "IN4PGA" },
903 { "Left ADC", NULL
, "Left ADC Mixer" },
904 { "Right ADC", NULL
, "Right ADC Mixer" },
906 { "Decimator Mux", "ADC", "Left ADC" },
907 { "Decimator Mux", "ADC", "Right ADC" },
908 { "Decimator Mux", "DMIC1", "DMIC1" },
910 DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"),
911 DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"),
912 DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"),
913 DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"),
914 DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"),
916 DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"),
917 DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"),
918 DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"),
919 DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"),
920 DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"),
922 { "AIF1 OUT", NULL
, "AIF1 Mixer" },
923 { "AIF2 OUT", NULL
, "AIF2 Mixer" },
924 { "AIF3 OUT", NULL
, "AIF3 Mixer" },
925 { "Left DAC1", NULL
, "DAC1 Mixer" },
926 { "Right DAC1", NULL
, "DAC1 Mixer" },
927 { "Left DAC2", NULL
, "DAC2 Mixer" },
928 { "Right DAC2", NULL
, "DAC2 Mixer" },
930 LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"),
931 RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"),
932 LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"),
933 RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"),
934 LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"),
935 RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"),
937 { "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" },
938 { "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" },
939 { "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
940 { "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
941 { "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
942 { "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
943 { "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" },
944 { "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" },
945 { "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
946 { "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
947 { "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
948 { "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
950 { "Left Headphone Mixer", NULL
, "Headphone Enable" },
951 { "Right Headphone Mixer", NULL
, "Headphone Enable" },
953 { "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" },
954 { "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" },
955 { "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" },
956 { "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" },
957 { "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" },
958 { "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" },
959 { "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" },
960 { "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" },
962 { "LOUT1L", NULL
, "Left Lineout1 Mixer" },
963 { "LOUT1R", NULL
, "Right Lineout1 Mixer" },
964 { "LOUT2L", NULL
, "Left Lineout2 Mixer" },
965 { "LOUT2R", NULL
, "Right Lineout2 Mixer" },
966 { "SPKL", NULL
, "Left Speaker Mixer" },
967 { "SPKR", NULL
, "Right Speaker Mixer" },
968 { "HPL", NULL
, "Left Headphone Mixer" },
969 { "HPR", NULL
, "Right Headphone Mixer" },
970 { "EP", NULL
, "Earpiece Mixer" },
972 { "IN1PGA", NULL
, "AIN1L" },
973 { "IN2PGA", NULL
, "AIN2L" },
974 { "IN3PGA", NULL
, "AIN3L" },
975 { "IN4PGA", NULL
, "AIN4L" },
976 { "IN1PGA", NULL
, "AIN1R" },
977 { "IN2PGA", NULL
, "AIN2R" },
978 { "IN3PGA", NULL
, "AIN3R" },
979 { "IN4PGA", NULL
, "AIN4R" },
981 { "SYSCLK1", NULL
, "PLL1" },
982 { "SYSCLK2", NULL
, "PLL2" },
984 { "Left DAC1", NULL
, "SYSCLK1" },
985 { "Right DAC1", NULL
, "SYSCLK1" },
986 { "Left DAC2", NULL
, "SYSCLK1" },
987 { "Right DAC2", NULL
, "SYSCLK1" },
988 { "Left ADC", NULL
, "SYSCLK1" },
989 { "Right ADC", NULL
, "SYSCLK1" },
991 { "DSP", NULL
, "SYSCLK1" },
993 { "AIF1 Mixer", NULL
, "DSP" },
994 { "AIF2 Mixer", NULL
, "DSP" },
995 { "AIF3 Mixer", NULL
, "DSP" },
996 { "DAC1 Mixer", NULL
, "DSP" },
997 { "DAC2 Mixer", NULL
, "DSP" },
998 { "DAC1 Mixer", NULL
, "Playback Engine A" },
999 { "DAC2 Mixer", NULL
, "Playback Engine B" },
1000 { "Left ADC Mixer", NULL
, "Recording Engine A" },
1001 { "Right ADC Mixer", NULL
, "Recording Engine A" },
1003 { "AIF1 CLK", NULL
, "SYSCLK1", adau1373_check_aif_clk
},
1004 { "AIF2 CLK", NULL
, "SYSCLK1", adau1373_check_aif_clk
},
1005 { "AIF3 CLK", NULL
, "SYSCLK1", adau1373_check_aif_clk
},
1006 { "AIF1 CLK", NULL
, "SYSCLK2", adau1373_check_aif_clk
},
1007 { "AIF2 CLK", NULL
, "SYSCLK2", adau1373_check_aif_clk
},
1008 { "AIF3 CLK", NULL
, "SYSCLK2", adau1373_check_aif_clk
},
1010 { "AIF1 IN", NULL
, "AIF1 CLK" },
1011 { "AIF1 OUT", NULL
, "AIF1 CLK" },
1012 { "AIF2 IN", NULL
, "AIF2 CLK" },
1013 { "AIF2 OUT", NULL
, "AIF2 CLK" },
1014 { "AIF3 IN", NULL
, "AIF3 CLK" },
1015 { "AIF3 OUT", NULL
, "AIF3 CLK" },
1016 { "AIF1 IN", NULL
, "AIF1 IN SRC", adau1373_check_src
},
1017 { "AIF1 OUT", NULL
, "AIF1 OUT SRC", adau1373_check_src
},
1018 { "AIF2 IN", NULL
, "AIF2 IN SRC", adau1373_check_src
},
1019 { "AIF2 OUT", NULL
, "AIF2 OUT SRC", adau1373_check_src
},
1020 { "AIF3 IN", NULL
, "AIF3 IN SRC", adau1373_check_src
},
1021 { "AIF3 OUT", NULL
, "AIF3 OUT SRC", adau1373_check_src
},
1023 { "DMIC1", NULL
, "DMIC1DAT" },
1024 { "DMIC1", NULL
, "SYSCLK1" },
1025 { "DMIC1", NULL
, "Recording Engine A" },
1026 { "DMIC2", NULL
, "DMIC2DAT" },
1027 { "DMIC2", NULL
, "SYSCLK1" },
1028 { "DMIC2", NULL
, "Recording Engine B" },
1031 static int adau1373_hw_params(struct snd_pcm_substream
*substream
,
1032 struct snd_pcm_hw_params
*params
, struct snd_soc_dai
*dai
)
1034 struct snd_soc_codec
*codec
= dai
->codec
;
1035 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(codec
);
1036 struct adau1373_dai
*adau1373_dai
= &adau1373
->dais
[dai
->id
];
1041 freq
= adau1373_dai
->sysclk
;
1043 if (freq
% params_rate(params
) != 0)
1046 switch (freq
/ params_rate(params
)) {
1047 case 1024: /* sysclk / 256 */
1050 case 1536: /* 2/3 sysclk / 256 */
1053 case 2048: /* 1/2 sysclk / 256 */
1056 case 3072: /* 1/3 sysclk / 256 */
1059 case 4096: /* 1/4 sysclk / 256 */
1062 case 6144: /* 1/6 sysclk / 256 */
1065 case 5632: /* 2/11 sysclk / 256 */
1072 adau1373_dai
->enable_src
= (div
!= 0);
1074 regmap_update_bits(adau1373
->regmap
, ADAU1373_BCLKDIV(dai
->id
),
1075 ADAU1373_BCLKDIV_SR_MASK
| ADAU1373_BCLKDIV_BCLK_MASK
,
1076 (div
<< 2) | ADAU1373_BCLKDIV_64
);
1078 switch (params_width(params
)) {
1080 ctrl
= ADAU1373_DAI_WLEN_16
;
1083 ctrl
= ADAU1373_DAI_WLEN_20
;
1086 ctrl
= ADAU1373_DAI_WLEN_24
;
1089 ctrl
= ADAU1373_DAI_WLEN_32
;
1095 return regmap_update_bits(adau1373
->regmap
, ADAU1373_DAI(dai
->id
),
1096 ADAU1373_DAI_WLEN_MASK
, ctrl
);
1099 static int adau1373_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1101 struct snd_soc_codec
*codec
= dai
->codec
;
1102 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(codec
);
1103 struct adau1373_dai
*adau1373_dai
= &adau1373
->dais
[dai
->id
];
1106 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1107 case SND_SOC_DAIFMT_CBM_CFM
:
1108 ctrl
= ADAU1373_DAI_MASTER
;
1109 adau1373_dai
->master
= true;
1111 case SND_SOC_DAIFMT_CBS_CFS
:
1113 adau1373_dai
->master
= false;
1119 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1120 case SND_SOC_DAIFMT_I2S
:
1121 ctrl
|= ADAU1373_DAI_FORMAT_I2S
;
1123 case SND_SOC_DAIFMT_LEFT_J
:
1124 ctrl
|= ADAU1373_DAI_FORMAT_LEFT_J
;
1126 case SND_SOC_DAIFMT_RIGHT_J
:
1127 ctrl
|= ADAU1373_DAI_FORMAT_RIGHT_J
;
1129 case SND_SOC_DAIFMT_DSP_B
:
1130 ctrl
|= ADAU1373_DAI_FORMAT_DSP
;
1136 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1137 case SND_SOC_DAIFMT_NB_NF
:
1139 case SND_SOC_DAIFMT_IB_NF
:
1140 ctrl
|= ADAU1373_DAI_INVERT_BCLK
;
1142 case SND_SOC_DAIFMT_NB_IF
:
1143 ctrl
|= ADAU1373_DAI_INVERT_LRCLK
;
1145 case SND_SOC_DAIFMT_IB_IF
:
1146 ctrl
|= ADAU1373_DAI_INVERT_LRCLK
| ADAU1373_DAI_INVERT_BCLK
;
1152 regmap_update_bits(adau1373
->regmap
, ADAU1373_DAI(dai
->id
),
1153 ~ADAU1373_DAI_WLEN_MASK
, ctrl
);
1158 static int adau1373_set_dai_sysclk(struct snd_soc_dai
*dai
,
1159 int clk_id
, unsigned int freq
, int dir
)
1161 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(dai
->codec
);
1162 struct adau1373_dai
*adau1373_dai
= &adau1373
->dais
[dai
->id
];
1165 case ADAU1373_CLK_SRC_PLL1
:
1166 case ADAU1373_CLK_SRC_PLL2
:
1172 adau1373_dai
->sysclk
= freq
;
1173 adau1373_dai
->clk_src
= clk_id
;
1175 regmap_update_bits(adau1373
->regmap
, ADAU1373_BCLKDIV(dai
->id
),
1176 ADAU1373_BCLKDIV_SOURCE
, clk_id
<< 5);
1181 static const struct snd_soc_dai_ops adau1373_dai_ops
= {
1182 .hw_params
= adau1373_hw_params
,
1183 .set_sysclk
= adau1373_set_dai_sysclk
,
1184 .set_fmt
= adau1373_set_dai_fmt
,
1187 #define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1188 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1190 static struct snd_soc_dai_driver adau1373_dai_driver
[] = {
1193 .name
= "adau1373-aif1",
1195 .stream_name
= "AIF1 Playback",
1198 .rates
= SNDRV_PCM_RATE_8000_48000
,
1199 .formats
= ADAU1373_FORMATS
,
1202 .stream_name
= "AIF1 Capture",
1205 .rates
= SNDRV_PCM_RATE_8000_48000
,
1206 .formats
= ADAU1373_FORMATS
,
1208 .ops
= &adau1373_dai_ops
,
1209 .symmetric_rates
= 1,
1213 .name
= "adau1373-aif2",
1215 .stream_name
= "AIF2 Playback",
1218 .rates
= SNDRV_PCM_RATE_8000_48000
,
1219 .formats
= ADAU1373_FORMATS
,
1222 .stream_name
= "AIF2 Capture",
1225 .rates
= SNDRV_PCM_RATE_8000_48000
,
1226 .formats
= ADAU1373_FORMATS
,
1228 .ops
= &adau1373_dai_ops
,
1229 .symmetric_rates
= 1,
1233 .name
= "adau1373-aif3",
1235 .stream_name
= "AIF3 Playback",
1238 .rates
= SNDRV_PCM_RATE_8000_48000
,
1239 .formats
= ADAU1373_FORMATS
,
1242 .stream_name
= "AIF3 Capture",
1245 .rates
= SNDRV_PCM_RATE_8000_48000
,
1246 .formats
= ADAU1373_FORMATS
,
1248 .ops
= &adau1373_dai_ops
,
1249 .symmetric_rates
= 1,
1253 static int adau1373_set_pll(struct snd_soc_codec
*codec
, int pll_id
,
1254 int source
, unsigned int freq_in
, unsigned int freq_out
)
1256 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(codec
);
1257 unsigned int dpll_div
= 0;
1258 uint8_t pll_regs
[5];
1270 case ADAU1373_PLL_SRC_BCLK1
:
1271 case ADAU1373_PLL_SRC_BCLK2
:
1272 case ADAU1373_PLL_SRC_BCLK3
:
1273 case ADAU1373_PLL_SRC_LRCLK1
:
1274 case ADAU1373_PLL_SRC_LRCLK2
:
1275 case ADAU1373_PLL_SRC_LRCLK3
:
1276 case ADAU1373_PLL_SRC_MCLK1
:
1277 case ADAU1373_PLL_SRC_MCLK2
:
1278 case ADAU1373_PLL_SRC_GPIO1
:
1279 case ADAU1373_PLL_SRC_GPIO2
:
1280 case ADAU1373_PLL_SRC_GPIO3
:
1281 case ADAU1373_PLL_SRC_GPIO4
:
1287 if (freq_in
< 7813 || freq_in
> 27000000)
1290 if (freq_out
< 45158000 || freq_out
> 49152000)
1293 /* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the
1294 * DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */
1295 while (freq_in
< 8000000) {
1300 ret
= adau_calc_pll_cfg(freq_in
, freq_out
, pll_regs
);
1305 dpll_div
= 11 - dpll_div
;
1306 regmap_update_bits(adau1373
->regmap
, ADAU1373_PLL_CTRL6(pll_id
),
1307 ADAU1373_PLL_CTRL6_DPLL_BYPASS
, 0);
1309 regmap_update_bits(adau1373
->regmap
, ADAU1373_PLL_CTRL6(pll_id
),
1310 ADAU1373_PLL_CTRL6_DPLL_BYPASS
,
1311 ADAU1373_PLL_CTRL6_DPLL_BYPASS
);
1314 regmap_write(adau1373
->regmap
, ADAU1373_DPLL_CTRL(pll_id
),
1315 (source
<< 4) | dpll_div
);
1316 regmap_write(adau1373
->regmap
, ADAU1373_PLL_CTRL1(pll_id
), pll_regs
[0]);
1317 regmap_write(adau1373
->regmap
, ADAU1373_PLL_CTRL2(pll_id
), pll_regs
[1]);
1318 regmap_write(adau1373
->regmap
, ADAU1373_PLL_CTRL3(pll_id
), pll_regs
[2]);
1319 regmap_write(adau1373
->regmap
, ADAU1373_PLL_CTRL4(pll_id
), pll_regs
[3]);
1320 regmap_write(adau1373
->regmap
, ADAU1373_PLL_CTRL5(pll_id
), pll_regs
[4]);
1322 /* Set sysclk to pll_rate / 4 */
1323 regmap_update_bits(adau1373
->regmap
, ADAU1373_CLK_SRC_DIV(pll_id
), 0x3f, 0x09);
1328 static void adau1373_load_drc_settings(struct adau1373
*adau1373
,
1329 unsigned int nr
, uint8_t *drc
)
1333 for (i
= 0; i
< ADAU1373_DRC_SIZE
; ++i
)
1334 regmap_write(adau1373
->regmap
, ADAU1373_DRC(nr
) + i
, drc
[i
]);
1337 static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias
)
1340 case ADAU1373_MICBIAS_2_9V
:
1341 case ADAU1373_MICBIAS_2_2V
:
1342 case ADAU1373_MICBIAS_2_6V
:
1343 case ADAU1373_MICBIAS_1_8V
:
1351 static int adau1373_probe(struct snd_soc_codec
*codec
)
1353 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(codec
);
1354 struct adau1373_platform_data
*pdata
= codec
->dev
->platform_data
;
1355 bool lineout_differential
= false;
1360 if (pdata
->num_drc
> ARRAY_SIZE(pdata
->drc_setting
))
1363 if (!adau1373_valid_micbias(pdata
->micbias1
) ||
1364 !adau1373_valid_micbias(pdata
->micbias2
))
1367 for (i
= 0; i
< pdata
->num_drc
; ++i
) {
1368 adau1373_load_drc_settings(adau1373
, i
,
1369 pdata
->drc_setting
[i
]);
1372 snd_soc_add_codec_controls(codec
, adau1373_drc_controls
,
1376 for (i
= 0; i
< 4; ++i
) {
1377 if (pdata
->input_differential
[i
])
1380 regmap_write(adau1373
->regmap
, ADAU1373_INPUT_MODE
, val
);
1383 if (pdata
->lineout_differential
)
1384 val
|= ADAU1373_OUTPUT_CTRL_LDIFF
;
1385 if (pdata
->lineout_ground_sense
)
1386 val
|= ADAU1373_OUTPUT_CTRL_LNFBEN
;
1387 regmap_write(adau1373
->regmap
, ADAU1373_OUTPUT_CTRL
, val
);
1389 lineout_differential
= pdata
->lineout_differential
;
1391 regmap_write(adau1373
->regmap
, ADAU1373_EP_CTRL
,
1392 (pdata
->micbias1
<< ADAU1373_EP_CTRL_MICBIAS1_OFFSET
) |
1393 (pdata
->micbias2
<< ADAU1373_EP_CTRL_MICBIAS2_OFFSET
));
1396 if (!lineout_differential
) {
1397 snd_soc_add_codec_controls(codec
, adau1373_lineout2_controls
,
1398 ARRAY_SIZE(adau1373_lineout2_controls
));
1401 regmap_write(adau1373
->regmap
, ADAU1373_ADC_CTRL
,
1402 ADAU1373_ADC_CTRL_RESET_FORCE
| ADAU1373_ADC_CTRL_PEAK_DETECT
);
1407 static int adau1373_set_bias_level(struct snd_soc_codec
*codec
,
1408 enum snd_soc_bias_level level
)
1410 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(codec
);
1413 case SND_SOC_BIAS_ON
:
1415 case SND_SOC_BIAS_PREPARE
:
1417 case SND_SOC_BIAS_STANDBY
:
1418 regmap_update_bits(adau1373
->regmap
, ADAU1373_PWDN_CTRL3
,
1419 ADAU1373_PWDN_CTRL3_PWR_EN
, ADAU1373_PWDN_CTRL3_PWR_EN
);
1421 case SND_SOC_BIAS_OFF
:
1422 regmap_update_bits(adau1373
->regmap
, ADAU1373_PWDN_CTRL3
,
1423 ADAU1373_PWDN_CTRL3_PWR_EN
, 0);
1429 static int adau1373_resume(struct snd_soc_codec
*codec
)
1431 struct adau1373
*adau1373
= snd_soc_codec_get_drvdata(codec
);
1433 regcache_sync(adau1373
->regmap
);
1438 static bool adau1373_register_volatile(struct device
*dev
, unsigned int reg
)
1441 case ADAU1373_SOFT_RESET
:
1442 case ADAU1373_ADC_DAC_STATUS
:
1449 static const struct regmap_config adau1373_regmap_config
= {
1453 .volatile_reg
= adau1373_register_volatile
,
1454 .max_register
= ADAU1373_SOFT_RESET
,
1456 .cache_type
= REGCACHE_RBTREE
,
1457 .reg_defaults
= adau1373_reg_defaults
,
1458 .num_reg_defaults
= ARRAY_SIZE(adau1373_reg_defaults
),
1461 static const struct snd_soc_codec_driver adau1373_codec_driver
= {
1462 .probe
= adau1373_probe
,
1463 .resume
= adau1373_resume
,
1464 .set_bias_level
= adau1373_set_bias_level
,
1465 .idle_bias_off
= true,
1467 .set_pll
= adau1373_set_pll
,
1469 .component_driver
= {
1470 .controls
= adau1373_controls
,
1471 .num_controls
= ARRAY_SIZE(adau1373_controls
),
1472 .dapm_widgets
= adau1373_dapm_widgets
,
1473 .num_dapm_widgets
= ARRAY_SIZE(adau1373_dapm_widgets
),
1474 .dapm_routes
= adau1373_dapm_routes
,
1475 .num_dapm_routes
= ARRAY_SIZE(adau1373_dapm_routes
),
1479 static int adau1373_i2c_probe(struct i2c_client
*client
,
1480 const struct i2c_device_id
*id
)
1482 struct adau1373
*adau1373
;
1485 adau1373
= devm_kzalloc(&client
->dev
, sizeof(*adau1373
), GFP_KERNEL
);
1489 adau1373
->regmap
= devm_regmap_init_i2c(client
,
1490 &adau1373_regmap_config
);
1491 if (IS_ERR(adau1373
->regmap
))
1492 return PTR_ERR(adau1373
->regmap
);
1494 regmap_write(adau1373
->regmap
, ADAU1373_SOFT_RESET
, 0x00);
1496 dev_set_drvdata(&client
->dev
, adau1373
);
1498 ret
= snd_soc_register_codec(&client
->dev
, &adau1373_codec_driver
,
1499 adau1373_dai_driver
, ARRAY_SIZE(adau1373_dai_driver
));
1503 static int adau1373_i2c_remove(struct i2c_client
*client
)
1505 snd_soc_unregister_codec(&client
->dev
);
1509 static const struct i2c_device_id adau1373_i2c_id
[] = {
1513 MODULE_DEVICE_TABLE(i2c
, adau1373_i2c_id
);
1515 static struct i2c_driver adau1373_i2c_driver
= {
1519 .probe
= adau1373_i2c_probe
,
1520 .remove
= adau1373_i2c_remove
,
1521 .id_table
= adau1373_i2c_id
,
1524 module_i2c_driver(adau1373_i2c_driver
);
1526 MODULE_DESCRIPTION("ASoC ADAU1373 driver");
1527 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1528 MODULE_LICENSE("GPL");