2 * NAU8825 ALSA SoC audio driver
4 * Copyright 2015 Google Inc.
5 * Author: Anatol Pomozov <anatol.pomozov@chrominium.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 #define NAU8825_REG_RESET 0x00
16 #define NAU8825_REG_ENA_CTRL 0x01
17 #define NAU8825_REG_IIC_ADDR_SET 0x02
18 #define NAU8825_REG_CLK_DIVIDER 0x03
19 #define NAU8825_REG_FLL1 0x04
20 #define NAU8825_REG_FLL2 0x05
21 #define NAU8825_REG_FLL3 0x06
22 #define NAU8825_REG_FLL4 0x07
23 #define NAU8825_REG_FLL5 0x08
24 #define NAU8825_REG_FLL6 0x09
25 #define NAU8825_REG_FLL_VCO_RSV 0x0a
26 #define NAU8825_REG_HSD_CTRL 0x0c
27 #define NAU8825_REG_JACK_DET_CTRL 0x0d
28 #define NAU8825_REG_INTERRUPT_MASK 0x0f
29 #define NAU8825_REG_IRQ_STATUS 0x10
30 #define NAU8825_REG_INT_CLR_KEY_STATUS 0x11
31 #define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12
32 #define NAU8825_REG_SAR_CTRL 0x13
33 #define NAU8825_REG_KEYDET_CTRL 0x14
34 #define NAU8825_REG_VDET_THRESHOLD_1 0x15
35 #define NAU8825_REG_VDET_THRESHOLD_2 0x16
36 #define NAU8825_REG_VDET_THRESHOLD_3 0x17
37 #define NAU8825_REG_VDET_THRESHOLD_4 0x18
38 #define NAU8825_REG_GPIO34_CTRL 0x19
39 #define NAU8825_REG_GPIO12_CTRL 0x1a
40 #define NAU8825_REG_TDM_CTRL 0x1b
41 #define NAU8825_REG_I2S_PCM_CTRL1 0x1c
42 #define NAU8825_REG_I2S_PCM_CTRL2 0x1d
43 #define NAU8825_REG_LEFT_TIME_SLOT 0x1e
44 #define NAU8825_REG_RIGHT_TIME_SLOT 0x1f
45 #define NAU8825_REG_BIQ_CTRL 0x20
46 #define NAU8825_REG_BIQ_COF1 0x21
47 #define NAU8825_REG_BIQ_COF2 0x22
48 #define NAU8825_REG_BIQ_COF3 0x23
49 #define NAU8825_REG_BIQ_COF4 0x24
50 #define NAU8825_REG_BIQ_COF5 0x25
51 #define NAU8825_REG_BIQ_COF6 0x26
52 #define NAU8825_REG_BIQ_COF7 0x27
53 #define NAU8825_REG_BIQ_COF8 0x28
54 #define NAU8825_REG_BIQ_COF9 0x29
55 #define NAU8825_REG_BIQ_COF10 0x2a
56 #define NAU8825_REG_ADC_RATE 0x2b
57 #define NAU8825_REG_DAC_CTRL1 0x2c
58 #define NAU8825_REG_DAC_CTRL2 0x2d
59 #define NAU8825_REG_DAC_DGAIN_CTRL 0x2f
60 #define NAU8825_REG_ADC_DGAIN_CTRL 0x30
61 #define NAU8825_REG_MUTE_CTRL 0x31
62 #define NAU8825_REG_HSVOL_CTRL 0x32
63 #define NAU8825_REG_DACL_CTRL 0x33
64 #define NAU8825_REG_DACR_CTRL 0x34
65 #define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38
66 #define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39
67 #define NAU8825_REG_ADC_DRC_SLOPES 0x3a
68 #define NAU8825_REG_ADC_DRC_ATKDCY 0x3b
69 #define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45
70 #define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46
71 #define NAU8825_REG_DAC_DRC_SLOPES 0x47
72 #define NAU8825_REG_DAC_DRC_ATKDCY 0x48
73 #define NAU8825_REG_IMM_MODE_CTRL 0x4c
74 #define NAU8825_REG_IMM_RMS_L 0x4d
75 #define NAU8825_REG_IMM_RMS_R 0x4e
76 #define NAU8825_REG_CLASSG_CTRL 0x50
77 #define NAU8825_REG_OPT_EFUSE_CTRL 0x51
78 #define NAU8825_REG_MISC_CTRL 0x55
79 #define NAU8825_REG_I2C_DEVICE_ID 0x58
80 #define NAU8825_REG_SARDOUT_RAM_STATUS 0x59
81 #define NAU8825_REG_BIAS_ADJ 0x66
82 #define NAU8825_REG_TRIM_SETTINGS 0x68
83 #define NAU8825_REG_ANALOG_CONTROL_1 0x69
84 #define NAU8825_REG_ANALOG_CONTROL_2 0x6a
85 #define NAU8825_REG_ANALOG_ADC_1 0x71
86 #define NAU8825_REG_ANALOG_ADC_2 0x72
87 #define NAU8825_REG_RDAC 0x73
88 #define NAU8825_REG_MIC_BIAS 0x74
89 #define NAU8825_REG_BOOST 0x76
90 #define NAU8825_REG_FEPGA 0x77
91 #define NAU8825_REG_POWER_UP_CONTROL 0x7f
92 #define NAU8825_REG_CHARGE_PUMP 0x80
93 #define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81
94 #define NAU8825_REG_GENERAL_STATUS 0x82
95 #define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS
96 /* 16-bit control register address, and 16-bits control register data */
97 #define NAU8825_REG_ADDR_LEN 16
98 #define NAU8825_REG_DATA_LEN 16
101 #define NAU8825_ENABLE_DACR_SFT 10
102 #define NAU8825_ENABLE_DACR (1 << NAU8825_ENABLE_DACR_SFT)
103 #define NAU8825_ENABLE_DACL_SFT 9
104 #define NAU8825_ENABLE_DACL (1 << NAU8825_ENABLE_DACL_SFT)
105 #define NAU8825_ENABLE_ADC_SFT 8
106 #define NAU8825_ENABLE_ADC (1 << NAU8825_ENABLE_ADC_SFT)
107 #define NAU8825_ENABLE_ADC_CLK_SFT 7
108 #define NAU8825_ENABLE_ADC_CLK (1 << NAU8825_ENABLE_ADC_CLK_SFT)
109 #define NAU8825_ENABLE_DAC_CLK_SFT 6
110 #define NAU8825_ENABLE_DAC_CLK (1 << NAU8825_ENABLE_DAC_CLK_SFT)
111 #define NAU8825_ENABLE_SAR_SFT 1
113 /* CLK_DIVIDER (0x3) */
114 #define NAU8825_CLK_SRC_SFT 15
115 #define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT)
116 #define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT)
117 #define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT)
118 #define NAU8825_CLK_ADC_SRC_SFT 6
119 #define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT)
120 #define NAU8825_CLK_DAC_SRC_SFT 4
121 #define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT)
122 #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0)
125 #define NAU8825_ICTRL_LATCH_SFT 10
126 #define NAU8825_ICTRL_LATCH_MASK (0x7 << NAU8825_ICTRL_LATCH_SFT)
127 #define NAU8825_FLL_RATIO_MASK (0x7f << 0)
130 #define NAU8825_GAIN_ERR_SFT 12
131 #define NAU8825_GAIN_ERR_MASK (0xf << NAU8825_GAIN_ERR_SFT)
132 #define NAU8825_FLL_INTEGER_MASK (0x3ff << 0)
133 #define NAU8825_FLL_CLK_SRC_SFT 10
134 #define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT)
135 #define NAU8825_FLL_CLK_SRC_MCLK (0 << NAU8825_FLL_CLK_SRC_SFT)
136 #define NAU8825_FLL_CLK_SRC_BLK (0x2 << NAU8825_FLL_CLK_SRC_SFT)
137 #define NAU8825_FLL_CLK_SRC_FS (0x3 << NAU8825_FLL_CLK_SRC_SFT)
140 #define NAU8825_FLL_REF_DIV_SFT 10
141 #define NAU8825_FLL_REF_DIV_MASK (0x3 << NAU8825_FLL_REF_DIV_SFT)
144 #define NAU8825_FLL_PDB_DAC_EN (0x1 << 15)
145 #define NAU8825_FLL_LOOP_FTR_EN (0x1 << 14)
146 #define NAU8825_FLL_CLK_SW_MASK (0x1 << 13)
147 #define NAU8825_FLL_CLK_SW_N2 (0x1 << 13)
148 #define NAU8825_FLL_CLK_SW_REF (0x0 << 13)
149 #define NAU8825_FLL_FTR_SW_MASK (0x1 << 12)
150 #define NAU8825_FLL_FTR_SW_ACCU (0x1 << 12)
151 #define NAU8825_FLL_FTR_SW_FILTER (0x0 << 12)
154 #define NAU8825_DCO_EN (0x1 << 15)
155 #define NAU8825_SDM_EN (0x1 << 14)
156 #define NAU8825_CUTOFF500 (0x1 << 13)
159 #define NAU8825_HSD_AUTO_MODE (1 << 6)
160 /* 0 - open, 1 - short to GND */
161 #define NAU8825_SPKR_DWN1R (1 << 1)
162 #define NAU8825_SPKR_DWN1L (1 << 0)
164 /* JACK_DET_CTRL (0xd) */
165 #define NAU8825_JACK_DET_RESTART (1 << 9)
166 #define NAU8825_JACK_DET_DB_BYPASS (1 << 8)
167 #define NAU8825_JACK_INSERT_DEBOUNCE_SFT 5
168 #define NAU8825_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT)
169 #define NAU8825_JACK_EJECT_DEBOUNCE_SFT 2
170 #define NAU8825_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT)
171 #define NAU8825_JACK_POLARITY (1 << 1) /* 0 - active low, 1 - active high */
173 /* INTERRUPT_MASK (0xf) */
174 #define NAU8825_IRQ_OUTPUT_EN (1 << 11)
175 #define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10)
176 #define NAU8825_IRQ_RMS_EN (1 << 8)
177 #define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7)
178 #define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5)
179 #define NAU8825_IRQ_EJECT_EN (1 << 2)
180 #define NAU8825_IRQ_INSERT_EN (1 << 0)
182 /* IRQ_STATUS (0x10) */
183 #define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10)
184 #define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9)
185 #define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8)
186 #define NAU8825_KEY_IRQ_MASK (0x7 << 5)
187 #define NAU8825_KEY_RELEASE_IRQ (1 << 7)
188 #define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6)
189 #define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5)
190 #define NAU8825_MIC_DETECTION_IRQ (1 << 4)
191 #define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2)
192 #define NAU8825_JACK_EJECTION_DETECTED (1 << 2)
193 #define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0)
194 #define NAU8825_JACK_INSERTION_DETECTED (1 << 0)
196 /* INTERRUPT_DIS_CTRL (0x12) */
197 #define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10)
198 #define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7)
199 #define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5)
200 #define NAU8825_IRQ_EJECT_DIS (1 << 2)
201 #define NAU8825_IRQ_INSERT_DIS (1 << 0)
203 /* SAR_CTRL (0x13) */
204 #define NAU8825_SAR_ADC_EN_SFT 12
205 #define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT)
206 #define NAU8825_SAR_INPUT_MASK (1 << 11)
207 #define NAU8825_SAR_INPUT_JKSLV (1 << 11)
208 #define NAU8825_SAR_INPUT_JKR2 (0 << 11)
209 #define NAU8825_SAR_TRACKING_GAIN_SFT 8
210 #define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT)
211 #define NAU8825_SAR_COMPARE_TIME_SFT 2
212 #define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2)
213 #define NAU8825_SAR_SAMPLING_TIME_SFT 0
214 #define NAU8825_SAR_SAMPLING_TIME_MASK (3 << 0)
216 /* KEYDET_CTRL (0x14) */
217 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT 12
218 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT)
219 #define NAU8825_KEYDET_LEVELS_NR_SFT 8
220 #define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8)
221 #define NAU8825_KEYDET_HYSTERESIS_SFT 0
222 #define NAU8825_KEYDET_HYSTERESIS_MASK 0xf
224 /* GPIO12_CTRL (0x1a) */
225 #define NAU8825_JKDET_PULL_UP (1 << 11) /* 0 - pull down, 1 - pull up */
226 #define NAU8825_JKDET_PULL_EN (1 << 9) /* 0 - enable pull, 1 - disable */
227 #define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */
229 /* I2S_PCM_CTRL1 (0x1c) */
230 #define NAU8825_I2S_BP_SFT 7
231 #define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT)
232 #define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT)
233 #define NAU8825_I2S_PCMB_SFT 6
234 #define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT)
235 #define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT)
236 #define NAU8825_I2S_DL_SFT 2
237 #define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT)
238 #define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT)
239 #define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT)
240 #define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT)
241 #define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT)
242 #define NAU8825_I2S_DF_SFT 0
243 #define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT)
244 #define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT)
245 #define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT)
246 #define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT)
247 #define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT)
249 /* I2S_PCM_CTRL2 (0x1d) */
250 #define NAU8825_I2S_TRISTATE (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */
251 #define NAU8825_I2S_LRC_DIV_SFT 12
252 #define NAU8825_I2S_LRC_DIV_MASK (0x3 << NAU8825_I2S_LRC_DIV_SFT)
253 #define NAU8825_I2S_MS_SFT 3
254 #define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT)
255 #define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT)
256 #define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT)
257 #define NAU8825_I2S_BLK_DIV_MASK 0x7
259 /* LEFT_TIME_SLOT (0x1e) */
260 #define NAU8825_FS_ERR_CMP_SEL_SFT 14
261 #define NAU8825_FS_ERR_CMP_SEL_MASK (0x3 << NAU8825_FS_ERR_CMP_SEL_SFT)
262 #define NAU8825_DIS_FS_SHORT_DET (1 << 13)
264 /* BIQ_CTRL (0x20) */
265 #define NAU8825_BIQ_WRT_SFT 4
266 #define NAU8825_BIQ_WRT_EN (1 << NAU8825_BIQ_WRT_SFT)
267 #define NAU8825_BIQ_PATH_SFT 0
268 #define NAU8825_BIQ_PATH_MASK (1 << NAU8825_BIQ_PATH_SFT)
269 #define NAU8825_BIQ_PATH_ADC (0 << NAU8825_BIQ_PATH_SFT)
270 #define NAU8825_BIQ_PATH_DAC (1 << NAU8825_BIQ_PATH_SFT)
272 /* ADC_RATE (0x2b) */
273 #define NAU8825_ADC_SINC4_SFT 4
274 #define NAU8825_ADC_SINC4_EN (1 << NAU8825_ADC_SINC4_SFT)
275 #define NAU8825_ADC_SYNC_DOWN_SFT 0
276 #define NAU8825_ADC_SYNC_DOWN_MASK 0x3
277 #define NAU8825_ADC_SYNC_DOWN_32 0
278 #define NAU8825_ADC_SYNC_DOWN_64 1
279 #define NAU8825_ADC_SYNC_DOWN_128 2
280 #define NAU8825_ADC_SYNC_DOWN_256 3
282 /* DAC_CTRL1 (0x2c) */
283 #define NAU8825_DAC_CLIP_OFF (1 << 7)
284 #define NAU8825_DAC_OVERSAMPLE_SFT 0
285 #define NAU8825_DAC_OVERSAMPLE_MASK 0x7
286 #define NAU8825_DAC_OVERSAMPLE_64 0
287 #define NAU8825_DAC_OVERSAMPLE_256 1
288 #define NAU8825_DAC_OVERSAMPLE_128 2
289 #define NAU8825_DAC_OVERSAMPLE_32 4
291 /* ADC_DGAIN_CTRL (0x30) */
292 #define NAU8825_ADC_DIG_VOL_MASK 0xff
294 /* MUTE_CTRL (0x31) */
295 #define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9)
296 #define NAU8825_DAC_SOFT_MUTE (1 << 9)
298 /* HSVOL_CTRL (0x32) */
299 #define NAU8825_HP_MUTE (1 << 15)
300 #define NAU8825_HP_MUTE_AUTO (1 << 14)
301 #define NAU8825_HPL_MUTE (1 << 13)
302 #define NAU8825_HPR_MUTE (1 << 12)
303 #define NAU8825_HPL_VOL_SFT 6
304 #define NAU8825_HPL_VOL_MASK (0x3f << NAU8825_HPL_VOL_SFT)
305 #define NAU8825_HPR_VOL_SFT 0
306 #define NAU8825_HPR_VOL_MASK (0x3f << NAU8825_HPR_VOL_SFT)
307 #define NAU8825_HP_VOL_MIN 0x36
309 /* DACL_CTRL (0x33) */
310 #define NAU8825_DACL_CH_SEL_SFT 9
311 #define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT)
312 #define NAU8825_DACL_CH_SEL_L (0x0 << NAU8825_DACL_CH_SEL_SFT)
313 #define NAU8825_DACL_CH_SEL_R (0x1 << NAU8825_DACL_CH_SEL_SFT)
314 #define NAU8825_DACL_CH_VOL_MASK 0xff
316 /* DACR_CTRL (0x34) */
317 #define NAU8825_DACR_CH_SEL_SFT 9
318 #define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT)
319 #define NAU8825_DACR_CH_SEL_L (0x0 << NAU8825_DACR_CH_SEL_SFT)
320 #define NAU8825_DACR_CH_SEL_R (0x1 << NAU8825_DACR_CH_SEL_SFT)
321 #define NAU8825_DACR_CH_VOL_MASK 0xff
323 /* IMM_MODE_CTRL (0x4C) */
324 #define NAU8825_IMM_THD_SFT 8
325 #define NAU8825_IMM_THD_MASK (0x3f << NAU8825_IMM_THD_SFT)
326 #define NAU8825_IMM_GEN_VOL_SFT 6
327 #define NAU8825_IMM_GEN_VOL_MASK (0x3 << NAU8825_IMM_GEN_VOL_SFT)
328 #define NAU8825_IMM_GEN_VOL_1_2nd (0x0 << NAU8825_IMM_GEN_VOL_SFT)
329 #define NAU8825_IMM_GEN_VOL_1_4th (0x1 << NAU8825_IMM_GEN_VOL_SFT)
330 #define NAU8825_IMM_GEN_VOL_1_8th (0x2 << NAU8825_IMM_GEN_VOL_SFT)
331 #define NAU8825_IMM_GEN_VOL_1_16th (0x3 << NAU8825_IMM_GEN_VOL_SFT)
333 #define NAU8825_IMM_CYC_SFT 4
334 #define NAU8825_IMM_CYC_MASK (0x3 << NAU8825_IMM_CYC_SFT)
335 #define NAU8825_IMM_CYC_1024 (0x0 << NAU8825_IMM_CYC_SFT)
336 #define NAU8825_IMM_CYC_2048 (0x1 << NAU8825_IMM_CYC_SFT)
337 #define NAU8825_IMM_CYC_4096 (0x2 << NAU8825_IMM_CYC_SFT)
338 #define NAU8825_IMM_CYC_8192 (0x3 << NAU8825_IMM_CYC_SFT)
339 #define NAU8825_IMM_EN (1 << 3)
340 #define NAU8825_IMM_DAC_SRC_MASK 0x7
341 #define NAU8825_IMM_DAC_SRC_BIQ 0x0
342 #define NAU8825_IMM_DAC_SRC_DRC 0x1
343 #define NAU8825_IMM_DAC_SRC_MIX 0x2
344 #define NAU8825_IMM_DAC_SRC_SIN 0x3
346 /* CLASSG_CTRL (0x50) */
347 #define NAU8825_CLASSG_TIMER_SFT 8
348 #define NAU8825_CLASSG_TIMER_MASK (0x3f << NAU8825_CLASSG_TIMER_SFT)
349 #define NAU8825_CLASSG_TIMER_1ms (0x1 << NAU8825_CLASSG_TIMER_SFT)
350 #define NAU8825_CLASSG_TIMER_2ms (0x2 << NAU8825_CLASSG_TIMER_SFT)
351 #define NAU8825_CLASSG_TIMER_8ms (0x4 << NAU8825_CLASSG_TIMER_SFT)
352 #define NAU8825_CLASSG_TIMER_16ms (0x8 << NAU8825_CLASSG_TIMER_SFT)
353 #define NAU8825_CLASSG_TIMER_32ms (0x10 << NAU8825_CLASSG_TIMER_SFT)
354 #define NAU8825_CLASSG_TIMER_64ms (0x20 << NAU8825_CLASSG_TIMER_SFT)
355 #define NAU8825_CLASSG_LDAC_EN (0x1 << 2)
356 #define NAU8825_CLASSG_RDAC_EN (0x1 << 1)
357 #define NAU8825_CLASSG_EN (1 << 0)
359 /* I2C_DEVICE_ID (0x58) */
360 #define NAU8825_GPIO2JD1 (1 << 7)
361 #define NAU8825_SOFTWARE_ID_MASK 0x3
362 #define NAU8825_SOFTWARE_ID_NAU8825 0x0
364 /* BIAS_ADJ (0x66) */
365 #define NAU8825_BIAS_HPR_IMP (1 << 15)
366 #define NAU8825_BIAS_HPL_IMP (1 << 14)
367 #define NAU8825_BIAS_TESTDAC_SFT 8
368 #define NAU8825_BIAS_TESTDAC_EN (0x3 << NAU8825_BIAS_TESTDAC_SFT)
369 #define NAU8825_BIAS_TESTDACR_EN (0x2 << NAU8825_BIAS_TESTDAC_SFT)
370 #define NAU8825_BIAS_TESTDACL_EN (0x1 << NAU8825_BIAS_TESTDAC_SFT)
371 #define NAU8825_BIAS_VMID (1 << 6)
372 #define NAU8825_BIAS_VMID_SEL_SFT 4
373 #define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT)
375 /* ANALOG_CONTROL_2 (0x6a) */
376 #define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12)
377 #define NAU8825_DAC_CAPACITOR_MSB (1 << 1)
378 #define NAU8825_DAC_CAPACITOR_LSB (1 << 0)
380 /* ANALOG_ADC_2 (0x72) */
381 #define NAU8825_ADC_VREFSEL_MASK (0x3 << 8)
382 #define NAU8825_ADC_VREFSEL_ANALOG (0 << 8)
383 #define NAU8825_ADC_VREFSEL_VMID (1 << 8)
384 #define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8)
385 #define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8)
386 #define NAU8825_POWERUP_ADCL (1 << 6)
389 #define NAU8825_RDAC_FS_BCLK_ENB (1 << 15)
390 #define NAU8825_RDAC_EN_SFT 12
391 #define NAU8825_RDAC_EN (0x3 << NAU8825_RDAC_EN_SFT)
392 #define NAU8825_RDAC_CLK_EN_SFT 8
393 #define NAU8825_RDAC_CLK_EN (0x3 << NAU8825_RDAC_CLK_EN_SFT)
394 #define NAU8825_RDAC_CLK_DELAY_SFT 4
395 #define NAU8825_RDAC_CLK_DELAY_MASK (0x7 << NAU8825_RDAC_CLK_DELAY_SFT)
396 #define NAU8825_RDAC_VREF_SFT 2
397 #define NAU8825_RDAC_VREF_MASK (0x3 << NAU8825_RDAC_VREF_SFT)
399 /* MIC_BIAS (0x74) */
400 #define NAU8825_MICBIAS_JKSLV (1 << 14)
401 #define NAU8825_MICBIAS_JKR2 (1 << 12)
402 #define NAU8825_MICBIAS_POWERUP_SFT 8
403 #define NAU8825_MICBIAS_VOLTAGE_SFT 0
404 #define NAU8825_MICBIAS_VOLTAGE_MASK 0x7
407 #define NAU8825_PRECHARGE_DIS (1 << 13)
408 #define NAU8825_GLOBAL_BIAS_EN (1 << 12)
409 #define NAU8825_HP_BOOST_DIS (1 << 9)
410 #define NAU8825_HP_BOOST_G_DIS (1 << 8)
411 #define NAU8825_SHORT_SHUTDOWN_EN (1 << 6)
413 /* POWER_UP_CONTROL (0x7f) */
414 #define NAU8825_POWERUP_INTEGR_R (1 << 5)
415 #define NAU8825_POWERUP_INTEGR_L (1 << 4)
416 #define NAU8825_POWERUP_DRV_IN_R (1 << 3)
417 #define NAU8825_POWERUP_DRV_IN_L (1 << 2)
418 #define NAU8825_POWERUP_HP_DRV_R (1 << 1)
419 #define NAU8825_POWERUP_HP_DRV_L (1 << 0)
421 /* CHARGE_PUMP (0x80) */
422 #define NAU8825_JAMNODCLOW (1 << 10)
423 #define NAU8825_POWER_DOWN_DACR (1 << 9)
424 #define NAU8825_POWER_DOWN_DACL (1 << 8)
425 #define NAU8825_CHANRGE_PUMP_EN (1 << 5)
428 /* System Clock Source */
432 NAU8825_CLK_INTERNAL
,
433 NAU8825_CLK_FLL_MCLK
,
438 /* Cross talk detection state */
440 NAU8825_XTALK_PREPARE
= 0,
441 NAU8825_XTALK_HPR_R2L
,
442 NAU8825_XTALK_HPL_R2L
,
449 struct regmap
*regmap
;
450 struct snd_soc_dapm_context
*dapm
;
451 struct snd_soc_jack
*jack
;
453 struct work_struct xtalk_work
;
454 struct semaphore xtalk_sem
;
456 int mclk_freq
; /* 0 - mclk is disabled */
461 bool jkdet_pull_enable
;
464 int sar_threshold_num
;
465 int sar_threshold
[8];
468 int sar_compare_time
;
469 int sar_sampling_time
;
471 int jack_insert_debounce
;
472 int jack_eject_debounce
;
476 int xtalk_event_mask
;
478 int imp_rms
[NAU8825_XTALK_IMM
];
482 int nau8825_enable_jack_detect(struct snd_soc_codec
*codec
,
483 struct snd_soc_jack
*jack
);
486 #endif /* __NAU8825_H__ */