2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/acpi.h>
20 #include <linux/workqueue.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
33 #define RT5663_DEVICE_ID_2 0x6451
34 #define RT5663_DEVICE_ID_1 0x6406
42 struct snd_soc_codec
*codec
;
43 struct rt5663_platform_data pdata
;
44 struct regmap
*regmap
;
45 struct delayed_work jack_detect_work
;
46 struct snd_soc_jack
*hs_jack
;
47 struct timer_list btn_check_timer
;
61 static const struct reg_sequence rt5663_patch_list
[] = {
66 static const struct reg_default rt5663_v2_reg
[] = {
468 static const struct reg_default rt5663_reg
[] = {
726 static bool rt5663_volatile_register(struct device
*dev
, unsigned int reg
)
730 case RT5663_SIL_DET_CTL
:
731 case RT5663_HP_IMP_GAIN_2
:
732 case RT5663_AD_DA_MIXER
:
733 case RT5663_FRAC_DIV_2
:
734 case RT5663_MICBIAS_1
:
735 case RT5663_ASRC_11_2
:
736 case RT5663_ADC_EQ_1
:
737 case RT5663_INT_ST_1
:
738 case RT5663_INT_ST_2
:
739 case RT5663_GPIO_STA1
:
740 case RT5663_SIN_GEN_1
:
741 case RT5663_IL_CMD_1
:
742 case RT5663_IL_CMD_5
:
743 case RT5663_IL_CMD_PWRSAV1
:
744 case RT5663_EM_JACK_TYPE_1
:
745 case RT5663_EM_JACK_TYPE_2
:
746 case RT5663_EM_JACK_TYPE_3
:
747 case RT5663_JD_CTRL2
:
748 case RT5663_VENDOR_ID
:
749 case RT5663_VENDOR_ID_1
:
750 case RT5663_VENDOR_ID_2
:
751 case RT5663_PLL_INT_REG
:
752 case RT5663_SOFT_RAMP
:
753 case RT5663_STO_DRE_1
:
754 case RT5663_STO_DRE_5
:
755 case RT5663_STO_DRE_6
:
756 case RT5663_STO_DRE_7
:
757 case RT5663_MIC_DECRO_1
:
758 case RT5663_MIC_DECRO_4
:
759 case RT5663_HP_IMP_SEN_1
:
760 case RT5663_HP_IMP_SEN_3
:
761 case RT5663_HP_IMP_SEN_4
:
762 case RT5663_HP_IMP_SEN_5
:
763 case RT5663_HP_CALIB_1_1
:
764 case RT5663_HP_CALIB_9
:
765 case RT5663_HP_CALIB_ST1
:
766 case RT5663_HP_CALIB_ST2
:
767 case RT5663_HP_CALIB_ST3
:
768 case RT5663_HP_CALIB_ST4
:
769 case RT5663_HP_CALIB_ST5
:
770 case RT5663_HP_CALIB_ST6
:
771 case RT5663_HP_CALIB_ST7
:
772 case RT5663_HP_CALIB_ST8
:
773 case RT5663_HP_CALIB_ST9
:
781 static bool rt5663_readable_register(struct device
*dev
, unsigned int reg
)
785 case RT5663_HP_OUT_EN
:
786 case RT5663_HP_LCH_DRE
:
787 case RT5663_HP_RCH_DRE
:
788 case RT5663_CALIB_BST
:
790 case RT5663_SIL_DET_CTL
:
791 case RT5663_PWR_SAV_SILDET
:
792 case RT5663_SIDETONE_CTL
:
793 case RT5663_STO1_DAC_DIG_VOL
:
794 case RT5663_STO1_ADC_DIG_VOL
:
795 case RT5663_STO1_BOOST
:
796 case RT5663_HP_IMP_GAIN_1
:
797 case RT5663_HP_IMP_GAIN_2
:
798 case RT5663_STO1_ADC_MIXER
:
799 case RT5663_AD_DA_MIXER
:
800 case RT5663_STO_DAC_MIXER
:
801 case RT5663_DIG_SIDE_MIXER
:
802 case RT5663_BYPASS_STO_DAC
:
803 case RT5663_CALIB_REC_MIX
:
804 case RT5663_PWR_DIG_1
:
805 case RT5663_PWR_DIG_2
:
806 case RT5663_PWR_ANLG_1
:
807 case RT5663_PWR_ANLG_2
:
808 case RT5663_PWR_ANLG_3
:
809 case RT5663_PWR_MIXER
:
810 case RT5663_SIG_CLK_DET
:
811 case RT5663_PRE_DIV_GATING_1
:
812 case RT5663_PRE_DIV_GATING_2
:
813 case RT5663_I2S1_SDP
:
814 case RT5663_ADDA_CLK_1
:
815 case RT5663_ADDA_RST
:
816 case RT5663_FRAC_DIV_1
:
817 case RT5663_FRAC_DIV_2
:
829 case RT5663_DUMMY_REG
:
836 case RT5663_HP_CHARGE_PUMP_1
:
837 case RT5663_HP_CHARGE_PUMP_2
:
838 case RT5663_MICBIAS_1
:
840 case RT5663_ASRC_11_2
:
841 case RT5663_DUMMY_REG_2
:
842 case RT5663_REC_PATH_GAIN
:
843 case RT5663_AUTO_1MRC_CLK
:
844 case RT5663_ADC_EQ_1
:
845 case RT5663_ADC_EQ_2
:
851 case RT5663_INT_ST_1
:
852 case RT5663_INT_ST_2
:
855 case RT5663_GPIO_STA1
:
856 case RT5663_SIN_GEN_1
:
857 case RT5663_SIN_GEN_2
:
858 case RT5663_SIN_GEN_3
:
859 case RT5663_SOF_VOL_ZC1
:
860 case RT5663_IL_CMD_1
:
861 case RT5663_IL_CMD_2
:
862 case RT5663_IL_CMD_3
:
863 case RT5663_IL_CMD_4
:
864 case RT5663_IL_CMD_5
:
865 case RT5663_IL_CMD_6
:
866 case RT5663_IL_CMD_7
:
867 case RT5663_IL_CMD_8
:
868 case RT5663_IL_CMD_PWRSAV1
:
869 case RT5663_IL_CMD_PWRSAV2
:
870 case RT5663_EM_JACK_TYPE_1
:
871 case RT5663_EM_JACK_TYPE_2
:
872 case RT5663_EM_JACK_TYPE_3
:
873 case RT5663_EM_JACK_TYPE_4
:
874 case RT5663_EM_JACK_TYPE_5
:
875 case RT5663_EM_JACK_TYPE_6
:
876 case RT5663_STO1_HPF_ADJ1
:
877 case RT5663_STO1_HPF_ADJ2
:
878 case RT5663_FAST_OFF_MICBIAS
:
879 case RT5663_JD_CTRL1
:
880 case RT5663_JD_CTRL2
:
881 case RT5663_DIG_MISC
:
882 case RT5663_VENDOR_ID
:
883 case RT5663_VENDOR_ID_1
:
884 case RT5663_VENDOR_ID_2
:
885 case RT5663_DIG_VOL_ZCD
:
886 case RT5663_ANA_BIAS_CUR_1
:
887 case RT5663_ANA_BIAS_CUR_2
:
888 case RT5663_ANA_BIAS_CUR_3
:
889 case RT5663_ANA_BIAS_CUR_4
:
890 case RT5663_ANA_BIAS_CUR_5
:
891 case RT5663_ANA_BIAS_CUR_6
:
892 case RT5663_BIAS_CUR_5
:
893 case RT5663_BIAS_CUR_6
:
894 case RT5663_BIAS_CUR_7
:
895 case RT5663_BIAS_CUR_8
:
896 case RT5663_DACREF_LDO
:
897 case RT5663_DUMMY_REG_3
:
898 case RT5663_BIAS_CUR_9
:
899 case RT5663_DUMMY_REG_4
:
900 case RT5663_VREFADJ_OP
:
901 case RT5663_VREF_RECMIX
:
902 case RT5663_CHARGE_PUMP_1
:
903 case RT5663_CHARGE_PUMP_1_2
:
904 case RT5663_CHARGE_PUMP_1_3
:
905 case RT5663_CHARGE_PUMP_2
:
906 case RT5663_DIG_IN_PIN1
:
907 case RT5663_PAD_DRV_CTL
:
908 case RT5663_PLL_INT_REG
:
909 case RT5663_CHOP_DAC_L
:
910 case RT5663_CHOP_ADC
:
911 case RT5663_CALIB_ADC
:
912 case RT5663_CHOP_DAC_R
:
913 case RT5663_DUMMY_CTL_DACLR
:
914 case RT5663_DUMMY_REG_5
:
915 case RT5663_SOFT_RAMP
:
916 case RT5663_TEST_MODE_1
:
917 case RT5663_TEST_MODE_2
:
918 case RT5663_TEST_MODE_3
:
919 case RT5663_STO_DRE_1
:
920 case RT5663_STO_DRE_2
:
921 case RT5663_STO_DRE_3
:
922 case RT5663_STO_DRE_4
:
923 case RT5663_STO_DRE_5
:
924 case RT5663_STO_DRE_6
:
925 case RT5663_STO_DRE_7
:
926 case RT5663_STO_DRE_8
:
927 case RT5663_STO_DRE_9
:
928 case RT5663_STO_DRE_10
:
929 case RT5663_MIC_DECRO_1
:
930 case RT5663_MIC_DECRO_2
:
931 case RT5663_MIC_DECRO_3
:
932 case RT5663_MIC_DECRO_4
:
933 case RT5663_MIC_DECRO_5
:
934 case RT5663_MIC_DECRO_6
:
935 case RT5663_HP_DECRO_1
:
936 case RT5663_HP_DECRO_2
:
937 case RT5663_HP_DECRO_3
:
938 case RT5663_HP_DECRO_4
:
939 case RT5663_HP_DECOUP
:
940 case RT5663_HP_IMP_SEN_MAP8
:
941 case RT5663_HP_IMP_SEN_MAP9
:
942 case RT5663_HP_IMP_SEN_MAP10
:
943 case RT5663_HP_IMP_SEN_MAP11
:
944 case RT5663_HP_IMP_SEN_1
:
945 case RT5663_HP_IMP_SEN_2
:
946 case RT5663_HP_IMP_SEN_3
:
947 case RT5663_HP_IMP_SEN_4
:
948 case RT5663_HP_IMP_SEN_5
:
949 case RT5663_HP_IMP_SEN_6
:
950 case RT5663_HP_IMP_SEN_7
:
951 case RT5663_HP_IMP_SEN_8
:
952 case RT5663_HP_IMP_SEN_9
:
953 case RT5663_HP_IMP_SEN_10
:
954 case RT5663_HP_IMP_SEN_11
:
955 case RT5663_HP_IMP_SEN_12
:
956 case RT5663_HP_IMP_SEN_13
:
957 case RT5663_HP_IMP_SEN_14
:
958 case RT5663_HP_IMP_SEN_15
:
959 case RT5663_HP_IMP_SEN_16
:
960 case RT5663_HP_IMP_SEN_17
:
961 case RT5663_HP_IMP_SEN_18
:
962 case RT5663_HP_IMP_SEN_19
:
963 case RT5663_HP_IMPSEN_DIG5
:
964 case RT5663_HP_IMPSEN_MAP1
:
965 case RT5663_HP_IMPSEN_MAP2
:
966 case RT5663_HP_IMPSEN_MAP3
:
967 case RT5663_HP_IMPSEN_MAP4
:
968 case RT5663_HP_IMPSEN_MAP5
:
969 case RT5663_HP_IMPSEN_MAP7
:
970 case RT5663_HP_LOGIC_1
:
971 case RT5663_HP_LOGIC_2
:
972 case RT5663_HP_CALIB_1
:
973 case RT5663_HP_CALIB_1_1
:
974 case RT5663_HP_CALIB_2
:
975 case RT5663_HP_CALIB_3
:
976 case RT5663_HP_CALIB_4
:
977 case RT5663_HP_CALIB_5
:
978 case RT5663_HP_CALIB_5_1
:
979 case RT5663_HP_CALIB_6
:
980 case RT5663_HP_CALIB_7
:
981 case RT5663_HP_CALIB_9
:
982 case RT5663_HP_CALIB_10
:
983 case RT5663_HP_CALIB_11
:
984 case RT5663_HP_CALIB_ST1
:
985 case RT5663_HP_CALIB_ST2
:
986 case RT5663_HP_CALIB_ST3
:
987 case RT5663_HP_CALIB_ST4
:
988 case RT5663_HP_CALIB_ST5
:
989 case RT5663_HP_CALIB_ST6
:
990 case RT5663_HP_CALIB_ST7
:
991 case RT5663_HP_CALIB_ST8
:
992 case RT5663_HP_CALIB_ST9
:
993 case RT5663_HP_AMP_DET
:
994 case RT5663_DUMMY_REG_6
:
1000 case RT5663_DUMMY_2
:
1001 case RT5663_DUMMY_3
:
1003 case RT5663_ADC_LCH_LPF1_A1
:
1004 case RT5663_ADC_RCH_LPF1_A1
:
1005 case RT5663_ADC_LCH_LPF1_H0
:
1006 case RT5663_ADC_RCH_LPF1_H0
:
1007 case RT5663_ADC_LCH_BPF1_A1
:
1008 case RT5663_ADC_RCH_BPF1_A1
:
1009 case RT5663_ADC_LCH_BPF1_A2
:
1010 case RT5663_ADC_RCH_BPF1_A2
:
1011 case RT5663_ADC_LCH_BPF1_H0
:
1012 case RT5663_ADC_RCH_BPF1_H0
:
1013 case RT5663_ADC_LCH_BPF2_A1
:
1014 case RT5663_ADC_RCH_BPF2_A1
:
1015 case RT5663_ADC_LCH_BPF2_A2
:
1016 case RT5663_ADC_RCH_BPF2_A2
:
1017 case RT5663_ADC_LCH_BPF2_H0
:
1018 case RT5663_ADC_RCH_BPF2_H0
:
1019 case RT5663_ADC_LCH_BPF3_A1
:
1020 case RT5663_ADC_RCH_BPF3_A1
:
1021 case RT5663_ADC_LCH_BPF3_A2
:
1022 case RT5663_ADC_RCH_BPF3_A2
:
1023 case RT5663_ADC_LCH_BPF3_H0
:
1024 case RT5663_ADC_RCH_BPF3_H0
:
1025 case RT5663_ADC_LCH_BPF4_A1
:
1026 case RT5663_ADC_RCH_BPF4_A1
:
1027 case RT5663_ADC_LCH_BPF4_A2
:
1028 case RT5663_ADC_RCH_BPF4_A2
:
1029 case RT5663_ADC_LCH_BPF4_H0
:
1030 case RT5663_ADC_RCH_BPF4_H0
:
1031 case RT5663_ADC_LCH_HPF1_A1
:
1032 case RT5663_ADC_RCH_HPF1_A1
:
1033 case RT5663_ADC_LCH_HPF1_H0
:
1034 case RT5663_ADC_RCH_HPF1_H0
:
1035 case RT5663_ADC_EQ_PRE_VOL_L
:
1036 case RT5663_ADC_EQ_PRE_VOL_R
:
1037 case RT5663_ADC_EQ_POST_VOL_L
:
1038 case RT5663_ADC_EQ_POST_VOL_R
:
1045 static bool rt5663_v2_volatile_register(struct device
*dev
, unsigned int reg
)
1049 case RT5663_CBJ_TYPE_2
:
1050 case RT5663_PDM_OUT_CTL
:
1051 case RT5663_PDM_I2C_DATA_CTL1
:
1052 case RT5663_PDM_I2C_DATA_CTL4
:
1053 case RT5663_ALC_BK_GAIN
:
1055 case RT5663_MICBIAS_1
:
1056 case RT5663_ADC_EQ_1
:
1057 case RT5663_INT_ST_1
:
1058 case RT5663_GPIO_STA2
:
1059 case RT5663_IL_CMD_1
:
1060 case RT5663_IL_CMD_5
:
1061 case RT5663_A_JD_CTRL
:
1062 case RT5663_JD_CTRL2
:
1063 case RT5663_VENDOR_ID
:
1064 case RT5663_VENDOR_ID_1
:
1065 case RT5663_VENDOR_ID_2
:
1066 case RT5663_STO_DRE_1
:
1067 case RT5663_STO_DRE_5
:
1068 case RT5663_STO_DRE_6
:
1069 case RT5663_STO_DRE_7
:
1070 case RT5663_MONO_DYNA_6
:
1071 case RT5663_STO1_SIL_DET
:
1072 case RT5663_MONOL_SIL_DET
:
1073 case RT5663_MONOR_SIL_DET
:
1074 case RT5663_STO2_DAC_SIL
:
1075 case RT5663_MONO_AMP_CAL_ST1
:
1076 case RT5663_MONO_AMP_CAL_ST2
:
1077 case RT5663_MONO_AMP_CAL_ST3
:
1078 case RT5663_MONO_AMP_CAL_ST4
:
1079 case RT5663_HP_IMP_SEN_2
:
1080 case RT5663_HP_IMP_SEN_3
:
1081 case RT5663_HP_IMP_SEN_4
:
1082 case RT5663_HP_IMP_SEN_10
:
1083 case RT5663_HP_CALIB_1
:
1084 case RT5663_HP_CALIB_10
:
1085 case RT5663_HP_CALIB_ST1
:
1086 case RT5663_HP_CALIB_ST4
:
1087 case RT5663_HP_CALIB_ST5
:
1088 case RT5663_HP_CALIB_ST6
:
1089 case RT5663_HP_CALIB_ST7
:
1090 case RT5663_HP_CALIB_ST8
:
1091 case RT5663_HP_CALIB_ST9
:
1092 case RT5663_HP_CALIB_ST10
:
1093 case RT5663_HP_CALIB_ST11
:
1100 static bool rt5663_v2_readable_register(struct device
*dev
, unsigned int reg
)
1103 case RT5663_LOUT_CTRL
:
1104 case RT5663_HP_AMP_2
:
1105 case RT5663_MONO_OUT
:
1106 case RT5663_MONO_GAIN
:
1107 case RT5663_AEC_BST
:
1108 case RT5663_IN1_IN2
:
1109 case RT5663_IN3_IN4
:
1110 case RT5663_INL1_INR1
:
1111 case RT5663_CBJ_TYPE_2
:
1112 case RT5663_CBJ_TYPE_3
:
1113 case RT5663_CBJ_TYPE_4
:
1114 case RT5663_CBJ_TYPE_5
:
1115 case RT5663_CBJ_TYPE_8
:
1116 case RT5663_DAC3_DIG_VOL
:
1117 case RT5663_DAC3_CTRL
:
1118 case RT5663_MONO_ADC_DIG_VOL
:
1119 case RT5663_STO2_ADC_DIG_VOL
:
1120 case RT5663_MONO_ADC_BST_GAIN
:
1121 case RT5663_STO2_ADC_BST_GAIN
:
1122 case RT5663_SIDETONE_CTRL
:
1123 case RT5663_MONO1_ADC_MIXER
:
1124 case RT5663_STO2_ADC_MIXER
:
1125 case RT5663_MONO_DAC_MIXER
:
1126 case RT5663_DAC2_SRC_CTRL
:
1127 case RT5663_IF_3_4_DATA_CTL
:
1128 case RT5663_IF_5_DATA_CTL
:
1129 case RT5663_PDM_OUT_CTL
:
1130 case RT5663_PDM_I2C_DATA_CTL1
:
1131 case RT5663_PDM_I2C_DATA_CTL2
:
1132 case RT5663_PDM_I2C_DATA_CTL3
:
1133 case RT5663_PDM_I2C_DATA_CTL4
:
1134 case RT5663_RECMIX1_NEW
:
1135 case RT5663_RECMIX1L_0
:
1136 case RT5663_RECMIX1L
:
1137 case RT5663_RECMIX1R_0
:
1138 case RT5663_RECMIX1R
:
1139 case RT5663_RECMIX2_NEW
:
1140 case RT5663_RECMIX2_L_2
:
1141 case RT5663_RECMIX2_R
:
1142 case RT5663_RECMIX2_R_2
:
1143 case RT5663_CALIB_REC_LR
:
1144 case RT5663_ALC_BK_GAIN
:
1145 case RT5663_MONOMIX_GAIN
:
1146 case RT5663_MONOMIX_IN_GAIN
:
1147 case RT5663_OUT_MIXL_GAIN
:
1148 case RT5663_OUT_LMIX_IN_GAIN
:
1149 case RT5663_OUT_RMIX_IN_GAIN
:
1150 case RT5663_OUT_RMIX_IN_GAIN1
:
1151 case RT5663_LOUT_MIXER_CTRL
:
1152 case RT5663_PWR_VOL
:
1153 case RT5663_ADCDAC_RST
:
1154 case RT5663_I2S34_SDP
:
1155 case RT5663_I2S5_SDP
:
1163 case RT5663_PLL_TRK_13
:
1164 case RT5663_I2S_M_CLK_CTL
:
1165 case RT5663_FDIV_I2S34_M_CLK
:
1166 case RT5663_FDIV_I2S34_M_CLK2
:
1167 case RT5663_FDIV_I2S5_M_CLK
:
1168 case RT5663_FDIV_I2S5_M_CLK2
:
1169 case RT5663_V2_IRQ_4
:
1172 case RT5663_GPIO_STA2
:
1173 case RT5663_HP_AMP_DET1
:
1174 case RT5663_HP_AMP_DET2
:
1175 case RT5663_HP_AMP_DET3
:
1176 case RT5663_MID_BD_HP_AMP
:
1177 case RT5663_LOW_BD_HP_AMP
:
1178 case RT5663_SOF_VOL_ZC2
:
1179 case RT5663_ADC_STO2_ADJ1
:
1180 case RT5663_ADC_STO2_ADJ2
:
1181 case RT5663_A_JD_CTRL
:
1182 case RT5663_JD1_TRES_CTRL
:
1183 case RT5663_JD2_TRES_CTRL
:
1184 case RT5663_V2_JD_CTRL2
:
1185 case RT5663_DUM_REG_2
:
1186 case RT5663_DUM_REG_3
:
1187 case RT5663_VENDOR_ID
:
1188 case RT5663_VENDOR_ID_1
:
1189 case RT5663_VENDOR_ID_2
:
1190 case RT5663_DACADC_DIG_VOL2
:
1191 case RT5663_DIG_IN_PIN2
:
1192 case RT5663_PAD_DRV_CTL1
:
1193 case RT5663_SOF_RAM_DEPOP
:
1194 case RT5663_VOL_TEST
:
1195 case RT5663_TEST_MODE_4
:
1196 case RT5663_TEST_MODE_5
:
1197 case RT5663_STO_DRE_9
:
1198 case RT5663_MONO_DYNA_1
:
1199 case RT5663_MONO_DYNA_2
:
1200 case RT5663_MONO_DYNA_3
:
1201 case RT5663_MONO_DYNA_4
:
1202 case RT5663_MONO_DYNA_5
:
1203 case RT5663_MONO_DYNA_6
:
1204 case RT5663_STO1_SIL_DET
:
1205 case RT5663_MONOL_SIL_DET
:
1206 case RT5663_MONOR_SIL_DET
:
1207 case RT5663_STO2_DAC_SIL
:
1208 case RT5663_PWR_SAV_CTL1
:
1209 case RT5663_PWR_SAV_CTL2
:
1210 case RT5663_PWR_SAV_CTL3
:
1211 case RT5663_PWR_SAV_CTL4
:
1212 case RT5663_PWR_SAV_CTL5
:
1213 case RT5663_PWR_SAV_CTL6
:
1214 case RT5663_MONO_AMP_CAL1
:
1215 case RT5663_MONO_AMP_CAL2
:
1216 case RT5663_MONO_AMP_CAL3
:
1217 case RT5663_MONO_AMP_CAL4
:
1218 case RT5663_MONO_AMP_CAL5
:
1219 case RT5663_MONO_AMP_CAL6
:
1220 case RT5663_MONO_AMP_CAL7
:
1221 case RT5663_MONO_AMP_CAL_ST1
:
1222 case RT5663_MONO_AMP_CAL_ST2
:
1223 case RT5663_MONO_AMP_CAL_ST3
:
1224 case RT5663_MONO_AMP_CAL_ST4
:
1225 case RT5663_MONO_AMP_CAL_ST5
:
1226 case RT5663_V2_HP_IMP_SEN_13
:
1227 case RT5663_V2_HP_IMP_SEN_14
:
1228 case RT5663_V2_HP_IMP_SEN_6
:
1229 case RT5663_V2_HP_IMP_SEN_7
:
1230 case RT5663_V2_HP_IMP_SEN_8
:
1231 case RT5663_V2_HP_IMP_SEN_9
:
1232 case RT5663_V2_HP_IMP_SEN_10
:
1233 case RT5663_HP_LOGIC_3
:
1234 case RT5663_HP_CALIB_ST10
:
1235 case RT5663_HP_CALIB_ST11
:
1236 case RT5663_PRO_REG_TBL_4
:
1237 case RT5663_PRO_REG_TBL_5
:
1238 case RT5663_PRO_REG_TBL_6
:
1239 case RT5663_PRO_REG_TBL_7
:
1240 case RT5663_PRO_REG_TBL_8
:
1241 case RT5663_PRO_REG_TBL_9
:
1242 case RT5663_SAR_ADC_INL_1
:
1243 case RT5663_SAR_ADC_INL_2
:
1244 case RT5663_SAR_ADC_INL_3
:
1245 case RT5663_SAR_ADC_INL_4
:
1246 case RT5663_SAR_ADC_INL_5
:
1247 case RT5663_SAR_ADC_INL_6
:
1248 case RT5663_SAR_ADC_INL_7
:
1249 case RT5663_SAR_ADC_INL_8
:
1250 case RT5663_SAR_ADC_INL_9
:
1251 case RT5663_SAR_ADC_INL_10
:
1252 case RT5663_SAR_ADC_INL_11
:
1253 case RT5663_SAR_ADC_INL_12
:
1254 case RT5663_DRC_CTRL_1
:
1255 case RT5663_DRC1_CTRL_2
:
1256 case RT5663_DRC1_CTRL_3
:
1257 case RT5663_DRC1_CTRL_4
:
1258 case RT5663_DRC1_CTRL_5
:
1259 case RT5663_DRC1_CTRL_6
:
1260 case RT5663_DRC1_HD_CTRL_1
:
1261 case RT5663_DRC1_HD_CTRL_2
:
1262 case RT5663_DRC1_PRI_REG_1
:
1263 case RT5663_DRC1_PRI_REG_2
:
1264 case RT5663_DRC1_PRI_REG_3
:
1265 case RT5663_DRC1_PRI_REG_4
:
1266 case RT5663_DRC1_PRI_REG_5
:
1267 case RT5663_DRC1_PRI_REG_6
:
1268 case RT5663_DRC1_PRI_REG_7
:
1269 case RT5663_DRC1_PRI_REG_8
:
1270 case RT5663_ALC_PGA_CTL_1
:
1271 case RT5663_ALC_PGA_CTL_2
:
1272 case RT5663_ALC_PGA_CTL_3
:
1273 case RT5663_ALC_PGA_CTL_4
:
1274 case RT5663_ALC_PGA_CTL_5
:
1275 case RT5663_ALC_PGA_CTL_6
:
1276 case RT5663_ALC_PGA_CTL_7
:
1277 case RT5663_ALC_PGA_CTL_8
:
1278 case RT5663_ALC_PGA_REG_1
:
1279 case RT5663_ALC_PGA_REG_2
:
1280 case RT5663_ALC_PGA_REG_3
:
1281 case RT5663_ADC_EQ_RECOV_1
:
1282 case RT5663_ADC_EQ_RECOV_2
:
1283 case RT5663_ADC_EQ_RECOV_3
:
1284 case RT5663_ADC_EQ_RECOV_4
:
1285 case RT5663_ADC_EQ_RECOV_5
:
1286 case RT5663_ADC_EQ_RECOV_6
:
1287 case RT5663_ADC_EQ_RECOV_7
:
1288 case RT5663_ADC_EQ_RECOV_8
:
1289 case RT5663_ADC_EQ_RECOV_9
:
1290 case RT5663_ADC_EQ_RECOV_10
:
1291 case RT5663_ADC_EQ_RECOV_11
:
1292 case RT5663_ADC_EQ_RECOV_12
:
1293 case RT5663_ADC_EQ_RECOV_13
:
1294 case RT5663_VID_HIDDEN
:
1295 case RT5663_VID_CUSTOMER
:
1296 case RT5663_SCAN_MODE
:
1297 case RT5663_I2C_BYPA
:
1300 case RT5663_DEPOP_3
:
1301 case RT5663_ASRC_11_2
:
1302 case RT5663_INT_ST_2
:
1303 case RT5663_GPIO_STA1
:
1304 case RT5663_SIN_GEN_1
:
1305 case RT5663_SIN_GEN_2
:
1306 case RT5663_SIN_GEN_3
:
1307 case RT5663_IL_CMD_PWRSAV1
:
1308 case RT5663_IL_CMD_PWRSAV2
:
1309 case RT5663_EM_JACK_TYPE_1
:
1310 case RT5663_EM_JACK_TYPE_2
:
1311 case RT5663_EM_JACK_TYPE_3
:
1312 case RT5663_EM_JACK_TYPE_4
:
1313 case RT5663_FAST_OFF_MICBIAS
:
1314 case RT5663_ANA_BIAS_CUR_1
:
1315 case RT5663_ANA_BIAS_CUR_2
:
1316 case RT5663_BIAS_CUR_9
:
1317 case RT5663_DUMMY_REG_4
:
1318 case RT5663_VREF_RECMIX
:
1319 case RT5663_CHARGE_PUMP_1_2
:
1320 case RT5663_CHARGE_PUMP_1_3
:
1321 case RT5663_CHARGE_PUMP_2
:
1322 case RT5663_CHOP_DAC_R
:
1323 case RT5663_DUMMY_CTL_DACLR
:
1324 case RT5663_DUMMY_REG_5
:
1325 case RT5663_SOFT_RAMP
:
1326 case RT5663_TEST_MODE_1
:
1327 case RT5663_STO_DRE_10
:
1328 case RT5663_MIC_DECRO_1
:
1329 case RT5663_MIC_DECRO_2
:
1330 case RT5663_MIC_DECRO_3
:
1331 case RT5663_MIC_DECRO_4
:
1332 case RT5663_MIC_DECRO_5
:
1333 case RT5663_MIC_DECRO_6
:
1334 case RT5663_HP_DECRO_1
:
1335 case RT5663_HP_DECRO_2
:
1336 case RT5663_HP_DECRO_3
:
1337 case RT5663_HP_DECRO_4
:
1338 case RT5663_HP_DECOUP
:
1339 case RT5663_HP_IMPSEN_MAP4
:
1340 case RT5663_HP_IMPSEN_MAP5
:
1341 case RT5663_HP_IMPSEN_MAP7
:
1342 case RT5663_HP_CALIB_1
:
1348 return rt5663_readable_register(dev
, reg
);
1352 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv
, -2400, 150, 0);
1353 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv
, -2250, 150, 0);
1354 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv
, -6525, 75, 0);
1355 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv
, -1725, 75, 0);
1357 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1358 static const DECLARE_TLV_DB_RANGE(in_bst_tlv
,
1359 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1360 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1361 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1362 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1363 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1364 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1365 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1368 /* Interface data select */
1369 static const char * const rt5663_if1_adc_data_select
[] = {
1370 "L/R", "R/L", "L/L", "R/R"
1373 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum
, RT5663_TDM_2
,
1374 RT5663_DATA_SWAP_ADCDAT1_SHIFT
, rt5663_if1_adc_data_select
);
1376 static void rt5663_enable_push_button_irq(struct snd_soc_codec
*codec
,
1379 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
1382 snd_soc_update_bits(codec
, RT5663_IL_CMD_6
,
1383 RT5663_EN_4BTN_INL_MASK
, RT5663_EN_4BTN_INL_EN
);
1384 /* reset in-line command */
1385 snd_soc_update_bits(codec
, RT5663_IL_CMD_6
,
1386 RT5663_RESET_4BTN_INL_MASK
,
1387 RT5663_RESET_4BTN_INL_RESET
);
1388 snd_soc_update_bits(codec
, RT5663_IL_CMD_6
,
1389 RT5663_RESET_4BTN_INL_MASK
,
1390 RT5663_RESET_4BTN_INL_NOR
);
1391 switch (rt5663
->codec_ver
) {
1393 snd_soc_update_bits(codec
, RT5663_IRQ_3
,
1394 RT5663_V2_EN_IRQ_INLINE_MASK
,
1395 RT5663_V2_EN_IRQ_INLINE_NOR
);
1398 snd_soc_update_bits(codec
, RT5663_IRQ_2
,
1399 RT5663_EN_IRQ_INLINE_MASK
,
1400 RT5663_EN_IRQ_INLINE_NOR
);
1403 dev_err(codec
->dev
, "Unknown CODEC Version\n");
1406 switch (rt5663
->codec_ver
) {
1408 snd_soc_update_bits(codec
, RT5663_IRQ_3
,
1409 RT5663_V2_EN_IRQ_INLINE_MASK
,
1410 RT5663_V2_EN_IRQ_INLINE_BYP
);
1413 snd_soc_update_bits(codec
, RT5663_IRQ_2
,
1414 RT5663_EN_IRQ_INLINE_MASK
,
1415 RT5663_EN_IRQ_INLINE_BYP
);
1418 dev_err(codec
->dev
, "Unknown CODEC Version\n");
1420 snd_soc_update_bits(codec
, RT5663_IL_CMD_6
,
1421 RT5663_EN_4BTN_INL_MASK
, RT5663_EN_4BTN_INL_DIS
);
1422 /* reset in-line command */
1423 snd_soc_update_bits(codec
, RT5663_IL_CMD_6
,
1424 RT5663_RESET_4BTN_INL_MASK
,
1425 RT5663_RESET_4BTN_INL_RESET
);
1426 snd_soc_update_bits(codec
, RT5663_IL_CMD_6
,
1427 RT5663_RESET_4BTN_INL_MASK
,
1428 RT5663_RESET_4BTN_INL_NOR
);
1433 * rt5663_v2_jack_detect - Detect headset.
1434 * @codec: SoC audio codec device.
1435 * @jack_insert: Jack insert or not.
1437 * Detect whether is headset or not when jack inserted.
1439 * Returns detect status.
1442 static int rt5663_v2_jack_detect(struct snd_soc_codec
*codec
, int jack_insert
)
1444 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
1445 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
1446 int val
, i
= 0, sleep_time
[5] = {300, 150, 100, 50, 30};
1448 dev_dbg(codec
->dev
, "%s jack_insert:%d\n", __func__
, jack_insert
);
1450 snd_soc_write(codec
, RT5663_CBJ_TYPE_2
, 0x8040);
1451 snd_soc_write(codec
, RT5663_CBJ_TYPE_3
, 0x1484);
1453 snd_soc_dapm_force_enable_pin(dapm
, "MICBIAS1");
1454 snd_soc_dapm_force_enable_pin(dapm
, "MICBIAS2");
1455 snd_soc_dapm_force_enable_pin(dapm
, "Mic Det Power");
1456 snd_soc_dapm_force_enable_pin(dapm
, "CBJ Power");
1457 snd_soc_dapm_sync(dapm
);
1458 snd_soc_update_bits(codec
, RT5663_RC_CLK
,
1459 RT5663_DIG_1M_CLK_MASK
, RT5663_DIG_1M_CLK_EN
);
1460 snd_soc_update_bits(codec
, RT5663_RECMIX
, 0x8, 0x8);
1463 msleep(sleep_time
[i
]);
1464 val
= snd_soc_read(codec
, RT5663_CBJ_TYPE_2
) & 0x0003;
1465 if (val
== 0x1 || val
== 0x2 || val
== 0x3)
1467 dev_dbg(codec
->dev
, "%s: MX-0011 val=%x sleep %d\n",
1468 __func__
, val
, sleep_time
[i
]);
1471 dev_dbg(codec
->dev
, "%s val = %d\n", __func__
, val
);
1475 rt5663
->jack_type
= SND_JACK_HEADSET
;
1476 rt5663_enable_push_button_irq(codec
, true);
1479 snd_soc_dapm_disable_pin(dapm
, "MICBIAS1");
1480 snd_soc_dapm_disable_pin(dapm
, "MICBIAS2");
1481 snd_soc_dapm_disable_pin(dapm
, "Mic Det Power");
1482 snd_soc_dapm_disable_pin(dapm
, "CBJ Power");
1483 snd_soc_dapm_sync(dapm
);
1484 rt5663
->jack_type
= SND_JACK_HEADPHONE
;
1488 snd_soc_update_bits(codec
, RT5663_RECMIX
, 0x8, 0x0);
1490 if (rt5663
->jack_type
== SND_JACK_HEADSET
) {
1491 rt5663_enable_push_button_irq(codec
, false);
1492 snd_soc_dapm_disable_pin(dapm
, "MICBIAS1");
1493 snd_soc_dapm_disable_pin(dapm
, "MICBIAS2");
1494 snd_soc_dapm_disable_pin(dapm
, "Mic Det Power");
1495 snd_soc_dapm_disable_pin(dapm
, "CBJ Power");
1496 snd_soc_dapm_sync(dapm
);
1498 rt5663
->jack_type
= 0;
1501 dev_dbg(codec
->dev
, "jack_type = %d\n", rt5663
->jack_type
);
1502 return rt5663
->jack_type
;
1506 * rt5663_jack_detect - Detect headset.
1507 * @codec: SoC audio codec device.
1508 * @jack_insert: Jack insert or not.
1510 * Detect whether is headset or not when jack inserted.
1512 * Returns detect status.
1514 static int rt5663_jack_detect(struct snd_soc_codec
*codec
, int jack_insert
)
1516 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
1519 dev_dbg(codec
->dev
, "%s jack_insert:%d\n", __func__
, jack_insert
);
1522 snd_soc_update_bits(codec
, RT5663_DIG_MISC
,
1523 RT5663_DIG_GATE_CTRL_MASK
, RT5663_DIG_GATE_CTRL_EN
);
1524 snd_soc_update_bits(codec
, RT5663_HP_CHARGE_PUMP_1
,
1525 RT5663_SI_HP_MASK
| RT5663_OSW_HP_L_MASK
|
1526 RT5663_OSW_HP_R_MASK
, RT5663_SI_HP_EN
|
1527 RT5663_OSW_HP_L_DIS
| RT5663_OSW_HP_R_DIS
);
1528 snd_soc_update_bits(codec
, RT5663_DUMMY_1
,
1529 RT5663_EMB_CLK_MASK
| RT5663_HPA_CPL_BIAS_MASK
|
1530 RT5663_HPA_CPR_BIAS_MASK
, RT5663_EMB_CLK_EN
|
1531 RT5663_HPA_CPL_BIAS_1
| RT5663_HPA_CPR_BIAS_1
);
1532 snd_soc_update_bits(codec
, RT5663_CBJ_1
,
1533 RT5663_INBUF_CBJ_BST1_MASK
| RT5663_CBJ_SENSE_BST1_MASK
,
1534 RT5663_INBUF_CBJ_BST1_ON
| RT5663_CBJ_SENSE_BST1_L
);
1535 snd_soc_update_bits(codec
, RT5663_IL_CMD_2
,
1536 RT5663_PWR_MIC_DET_MASK
, RT5663_PWR_MIC_DET_ON
);
1537 /* BST1 power on for JD */
1538 snd_soc_update_bits(codec
, RT5663_PWR_ANLG_2
,
1539 RT5663_PWR_BST1_MASK
, RT5663_PWR_BST1_ON
);
1540 snd_soc_update_bits(codec
, RT5663_EM_JACK_TYPE_1
,
1541 RT5663_CBJ_DET_MASK
| RT5663_EXT_JD_MASK
|
1542 RT5663_POL_EXT_JD_MASK
, RT5663_CBJ_DET_EN
|
1543 RT5663_EXT_JD_EN
| RT5663_POL_EXT_JD_EN
);
1544 snd_soc_update_bits(codec
, RT5663_PWR_ANLG_1
,
1545 RT5663_PWR_MB_MASK
| RT5663_LDO1_DVO_MASK
|
1546 RT5663_AMP_HP_MASK
, RT5663_PWR_MB
|
1547 RT5663_LDO1_DVO_0_9V
| RT5663_AMP_HP_3X
);
1548 snd_soc_update_bits(codec
, RT5663_AUTO_1MRC_CLK
,
1549 RT5663_IRQ_POW_SAV_MASK
, RT5663_IRQ_POW_SAV_EN
);
1550 snd_soc_update_bits(codec
, RT5663_IRQ_1
,
1551 RT5663_EN_IRQ_JD1_MASK
, RT5663_EN_IRQ_JD1_EN
);
1554 regmap_read(rt5663
->regmap
, RT5663_INT_ST_2
, &val
);
1556 usleep_range(10000, 10005);
1565 val
= snd_soc_read(codec
, RT5663_EM_JACK_TYPE_2
) & 0x0003;
1566 dev_dbg(codec
->dev
, "%s val = %d\n", __func__
, val
);
1568 snd_soc_update_bits(codec
, RT5663_HP_CHARGE_PUMP_1
,
1569 RT5663_OSW_HP_L_MASK
| RT5663_OSW_HP_R_MASK
,
1570 RT5663_OSW_HP_L_EN
| RT5663_OSW_HP_R_EN
);
1575 rt5663
->jack_type
= SND_JACK_HEADSET
;
1576 rt5663_enable_push_button_irq(codec
, true);
1578 if (rt5663
->pdata
.dc_offset_l_manual_mic
) {
1579 regmap_write(rt5663
->regmap
, RT5663_MIC_DECRO_2
,
1580 rt5663
->pdata
.dc_offset_l_manual_mic
>>
1582 regmap_write(rt5663
->regmap
, RT5663_MIC_DECRO_3
,
1583 rt5663
->pdata
.dc_offset_l_manual_mic
&
1587 if (rt5663
->pdata
.dc_offset_r_manual_mic
) {
1588 regmap_write(rt5663
->regmap
, RT5663_MIC_DECRO_5
,
1589 rt5663
->pdata
.dc_offset_r_manual_mic
>>
1591 regmap_write(rt5663
->regmap
, RT5663_MIC_DECRO_6
,
1592 rt5663
->pdata
.dc_offset_r_manual_mic
&
1597 rt5663
->jack_type
= SND_JACK_HEADPHONE
;
1599 if (rt5663
->pdata
.dc_offset_l_manual
) {
1600 regmap_write(rt5663
->regmap
, RT5663_MIC_DECRO_2
,
1601 rt5663
->pdata
.dc_offset_l_manual
>> 16);
1602 regmap_write(rt5663
->regmap
, RT5663_MIC_DECRO_3
,
1603 rt5663
->pdata
.dc_offset_l_manual
&
1607 if (rt5663
->pdata
.dc_offset_r_manual
) {
1608 regmap_write(rt5663
->regmap
, RT5663_MIC_DECRO_5
,
1609 rt5663
->pdata
.dc_offset_r_manual
>> 16);
1610 regmap_write(rt5663
->regmap
, RT5663_MIC_DECRO_6
,
1611 rt5663
->pdata
.dc_offset_r_manual
&
1617 if (rt5663
->jack_type
== SND_JACK_HEADSET
)
1618 rt5663_enable_push_button_irq(codec
, false);
1619 rt5663
->jack_type
= 0;
1622 dev_dbg(codec
->dev
, "jack_type = %d\n", rt5663
->jack_type
);
1623 return rt5663
->jack_type
;
1626 static int rt5663_button_detect(struct snd_soc_codec
*codec
)
1630 val
= snd_soc_read(codec
, RT5663_IL_CMD_5
);
1631 dev_dbg(codec
->dev
, "%s: val=0x%x\n", __func__
, val
);
1632 btn_type
= val
& 0xfff0;
1633 snd_soc_write(codec
, RT5663_IL_CMD_5
, val
);
1638 static irqreturn_t
rt5663_irq(int irq
, void *data
)
1640 struct rt5663_priv
*rt5663
= data
;
1642 dev_dbg(regmap_get_device(rt5663
->regmap
), "%s IRQ queue work\n",
1645 queue_delayed_work(system_wq
, &rt5663
->jack_detect_work
,
1646 msecs_to_jiffies(250));
1651 int rt5663_set_jack_detect(struct snd_soc_codec
*codec
,
1652 struct snd_soc_jack
*hs_jack
)
1654 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
1656 rt5663
->hs_jack
= hs_jack
;
1658 rt5663_irq(0, rt5663
);
1662 EXPORT_SYMBOL_GPL(rt5663_set_jack_detect
);
1664 static bool rt5663_check_jd_status(struct snd_soc_codec
*codec
)
1666 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
1667 int val
= snd_soc_read(codec
, RT5663_INT_ST_1
);
1669 dev_dbg(codec
->dev
, "%s val=%x\n", __func__
, val
);
1672 switch (rt5663
->codec_ver
) {
1674 return !(val
& 0x2000);
1676 return !(val
& 0x1000);
1678 dev_err(codec
->dev
, "Unknown CODEC Version\n");
1684 static void rt5663_jack_detect_work(struct work_struct
*work
)
1686 struct rt5663_priv
*rt5663
=
1687 container_of(work
, struct rt5663_priv
, jack_detect_work
.work
);
1688 struct snd_soc_codec
*codec
= rt5663
->codec
;
1689 int btn_type
, report
= 0;
1694 if (rt5663_check_jd_status(codec
)) {
1696 if (rt5663
->jack_type
== 0) {
1697 /* jack was out, report jack type */
1698 switch (rt5663
->codec_ver
) {
1700 report
= rt5663_v2_jack_detect(
1704 report
= rt5663_jack_detect(rt5663
->codec
, 1);
1707 dev_err(codec
->dev
, "Unknown CODEC Version\n");
1710 /* Delay the jack insert report to avoid pop noise */
1713 /* jack is already in, report button event */
1714 report
= SND_JACK_HEADSET
;
1715 btn_type
= rt5663_button_detect(rt5663
->codec
);
1717 * rt5663 can report three kinds of button behavior,
1718 * one click, double click and hold. However,
1719 * currently we will report button pressed/released
1720 * event. So all the three button behaviors are
1721 * treated as button pressed.
1727 report
|= SND_JACK_BTN_0
;
1732 report
|= SND_JACK_BTN_1
;
1737 report
|= SND_JACK_BTN_2
;
1742 report
|= SND_JACK_BTN_3
;
1744 case 0x0000: /* unpressed */
1748 dev_err(rt5663
->codec
->dev
,
1749 "Unexpected button code 0x%04x\n",
1753 /* button release or spurious interrput*/
1755 report
= rt5663
->jack_type
;
1759 switch (rt5663
->codec_ver
) {
1761 report
= rt5663_v2_jack_detect(rt5663
->codec
, 0);
1764 report
= rt5663_jack_detect(rt5663
->codec
, 0);
1767 dev_err(codec
->dev
, "Unknown CODEC Version\n");
1770 dev_dbg(codec
->dev
, "%s jack report: 0x%04x\n", __func__
, report
);
1771 snd_soc_jack_report(rt5663
->hs_jack
, report
, SND_JACK_HEADSET
|
1772 SND_JACK_BTN_0
| SND_JACK_BTN_1
|
1773 SND_JACK_BTN_2
| SND_JACK_BTN_3
);
1776 static const struct snd_kcontrol_new rt5663_snd_controls
[] = {
1777 /* DAC Digital Volume */
1778 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL
,
1779 RT5663_DAC_L1_VOL_SHIFT
+ 1, RT5663_DAC_R1_VOL_SHIFT
+ 1,
1780 87, 0, dac_vol_tlv
),
1781 /* ADC Digital Volume Control */
1782 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL
,
1783 RT5663_ADC_L_MUTE_SHIFT
, RT5663_ADC_R_MUTE_SHIFT
, 1, 1),
1784 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL
,
1785 RT5663_ADC_L_VOL_SHIFT
+ 1, RT5663_ADC_R_VOL_SHIFT
+ 1,
1786 63, 0, adc_vol_tlv
),
1789 static const struct snd_kcontrol_new rt5663_v2_specific_controls
[] = {
1790 /* Headphone Output Volume */
1791 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE
,
1792 RT5663_HP_RCH_DRE
, RT5663_GAIN_HP_SHIFT
, 15, 1,
1793 rt5663_v2_hp_vol_tlv
),
1794 /* Mic Boost Volume */
1795 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST
,
1796 RT5663_GAIN_CBJ_SHIFT
, 8, 0, in_bst_tlv
),
1799 static const struct snd_kcontrol_new rt5663_specific_controls
[] = {
1800 /* Headphone Output Volume */
1801 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9
,
1802 RT5663_STO_DRE_10
, RT5663_DRE_GAIN_HP_SHIFT
, 23, 1,
1804 /* Mic Boost Volume*/
1805 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2
,
1806 RT5663_GAIN_BST1_SHIFT
, 8, 0, in_bst_tlv
),
1807 /* Data Swap for Slot0/1 in ADCDAT1 */
1808 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum
),
1811 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget
*w
,
1812 struct snd_soc_dapm_widget
*sink
)
1815 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1817 val
= snd_soc_read(codec
, RT5663_GLB_CLK
);
1818 val
&= RT5663_SCLK_SRC_MASK
;
1819 if (val
== RT5663_SCLK_SRC_PLL1
)
1825 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget
*w
,
1826 struct snd_soc_dapm_widget
*sink
)
1828 unsigned int reg
, shift
, val
;
1829 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
1830 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
1832 if (rt5663
->codec_ver
== CODEC_VER_1
) {
1834 case RT5663_ADC_STO1_ASRC_SHIFT
:
1835 reg
= RT5663_ASRC_3
;
1836 shift
= RT5663_V2_AD_STO1_TRACK_SHIFT
;
1838 case RT5663_DAC_STO1_ASRC_SHIFT
:
1839 reg
= RT5663_ASRC_2
;
1840 shift
= RT5663_DA_STO1_TRACK_SHIFT
;
1847 case RT5663_ADC_STO1_ASRC_SHIFT
:
1848 reg
= RT5663_ASRC_2
;
1849 shift
= RT5663_AD_STO1_TRACK_SHIFT
;
1851 case RT5663_DAC_STO1_ASRC_SHIFT
:
1852 reg
= RT5663_ASRC_2
;
1853 shift
= RT5663_DA_STO1_TRACK_SHIFT
;
1860 val
= (snd_soc_read(codec
, reg
) >> shift
) & 0x7;
1868 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget
*source
,
1869 struct snd_soc_dapm_widget
*sink
)
1871 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(source
->dapm
);
1872 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
1873 int da_asrc_en
, ad_asrc_en
;
1875 da_asrc_en
= (snd_soc_read(codec
, RT5663_ASRC_2
) &
1876 RT5663_DA_STO1_TRACK_MASK
) ? 1 : 0;
1877 switch (rt5663
->codec_ver
) {
1879 ad_asrc_en
= (snd_soc_read(codec
, RT5663_ASRC_3
) &
1880 RT5663_V2_AD_STO1_TRACK_MASK
) ? 1 : 0;
1883 ad_asrc_en
= (snd_soc_read(codec
, RT5663_ASRC_2
) &
1884 RT5663_AD_STO1_TRACK_MASK
) ? 1 : 0;
1887 dev_err(codec
->dev
, "Unknown CODEC Version\n");
1891 if (da_asrc_en
|| ad_asrc_en
)
1892 if (rt5663
->sysclk
> rt5663
->lrck
* 384)
1895 dev_err(codec
->dev
, "sysclk < 384 x fs, disable i2s asrc\n");
1901 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
1902 * @codec: SoC audio codec device.
1903 * @filter_mask: mask of filters.
1904 * @clk_src: clock source
1906 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
1907 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1908 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1909 * ASRC function will track i2s clock and generate a corresponding system clock
1910 * for codec. This function provides an API to select the clock source for a
1911 * set of filters specified by the mask. And the codec driver will turn on ASRC
1912 * for these filters if ASRC is selected as their clock source.
1914 int rt5663_sel_asrc_clk_src(struct snd_soc_codec
*codec
,
1915 unsigned int filter_mask
, unsigned int clk_src
)
1917 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
1918 unsigned int asrc2_mask
= 0;
1919 unsigned int asrc2_value
= 0;
1920 unsigned int asrc3_mask
= 0;
1921 unsigned int asrc3_value
= 0;
1924 case RT5663_CLK_SEL_SYS
:
1925 case RT5663_CLK_SEL_I2S1_ASRC
:
1932 if (filter_mask
& RT5663_DA_STEREO_FILTER
) {
1933 asrc2_mask
|= RT5663_DA_STO1_TRACK_MASK
;
1934 asrc2_value
|= clk_src
<< RT5663_DA_STO1_TRACK_SHIFT
;
1937 if (filter_mask
& RT5663_AD_STEREO_FILTER
) {
1938 switch (rt5663
->codec_ver
) {
1940 asrc3_mask
|= RT5663_V2_AD_STO1_TRACK_MASK
;
1941 asrc3_value
|= clk_src
<< RT5663_V2_AD_STO1_TRACK_SHIFT
;
1944 asrc2_mask
|= RT5663_AD_STO1_TRACK_MASK
;
1945 asrc2_value
|= clk_src
<< RT5663_AD_STO1_TRACK_SHIFT
;
1948 dev_err(codec
->dev
, "Unknown CODEC Version\n");
1953 snd_soc_update_bits(codec
, RT5663_ASRC_2
, asrc2_mask
,
1957 snd_soc_update_bits(codec
, RT5663_ASRC_3
, asrc3_mask
,
1962 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src
);
1965 static const struct snd_kcontrol_new rt5663_recmix1l
[] = {
1966 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L
,
1967 RT5663_RECMIX1L_BST2_SHIFT
, 1, 1),
1968 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L
,
1969 RT5663_RECMIX1L_BST1_CBJ_SHIFT
, 1, 1),
1972 static const struct snd_kcontrol_new rt5663_recmix1r
[] = {
1973 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R
,
1974 RT5663_RECMIX1R_BST2_SHIFT
, 1, 1),
1978 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix
[] = {
1979 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER
,
1980 RT5663_M_STO1_ADC_L1_SHIFT
, 1, 1),
1981 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER
,
1982 RT5663_M_STO1_ADC_L2_SHIFT
, 1, 1),
1985 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix
[] = {
1986 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER
,
1987 RT5663_M_STO1_ADC_R1_SHIFT
, 1, 1),
1988 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER
,
1989 RT5663_M_STO1_ADC_R2_SHIFT
, 1, 1),
1992 static const struct snd_kcontrol_new rt5663_adda_l_mix
[] = {
1993 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER
,
1994 RT5663_M_ADCMIX_L_SHIFT
, 1, 1),
1995 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER
,
1996 RT5663_M_DAC1_L_SHIFT
, 1, 1),
1999 static const struct snd_kcontrol_new rt5663_adda_r_mix
[] = {
2000 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER
,
2001 RT5663_M_ADCMIX_R_SHIFT
, 1, 1),
2002 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER
,
2003 RT5663_M_DAC1_R_SHIFT
, 1, 1),
2006 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix
[] = {
2007 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER
,
2008 RT5663_M_DAC_L1_STO_L_SHIFT
, 1, 1),
2011 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix
[] = {
2012 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER
,
2013 RT5663_M_DAC_R1_STO_R_SHIFT
, 1, 1),
2017 static const struct snd_kcontrol_new rt5663_hpo_switch
=
2018 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2
,
2019 RT5663_EN_DAC_HPO_SHIFT
, 1, 0);
2021 /* Stereo ADC source */
2022 static const char * const rt5663_sto1_adc_src
[] = {
2026 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum
, RT5663_STO1_ADC_MIXER
,
2027 RT5663_STO1_ADC_L_SRC_SHIFT
, rt5663_sto1_adc_src
);
2029 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux
=
2030 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum
);
2032 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum
, RT5663_STO1_ADC_MIXER
,
2033 RT5663_STO1_ADC_R_SRC_SHIFT
, rt5663_sto1_adc_src
);
2035 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux
=
2036 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum
);
2038 /* RT5663: Analog DACL1 input source */
2039 static const char * const rt5663_alg_dacl_src
[] = {
2040 "DAC L", "STO DAC MIXL"
2043 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum
, RT5663_BYPASS_STO_DAC
,
2044 RT5663_DACL1_SRC_SHIFT
, rt5663_alg_dacl_src
);
2046 static const struct snd_kcontrol_new rt5663_alg_dacl_mux
=
2047 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum
);
2049 /* RT5663: Analog DACR1 input source */
2050 static const char * const rt5663_alg_dacr_src
[] = {
2051 "DAC R", "STO DAC MIXR"
2054 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum
, RT5663_BYPASS_STO_DAC
,
2055 RT5663_DACR1_SRC_SHIFT
, rt5663_alg_dacr_src
);
2057 static const struct snd_kcontrol_new rt5663_alg_dacr_mux
=
2058 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum
);
2060 static int rt5663_hp_event(struct snd_soc_dapm_widget
*w
,
2061 struct snd_kcontrol
*kcontrol
, int event
)
2063 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
2064 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2067 case SND_SOC_DAPM_POST_PMU
:
2068 if (rt5663
->codec_ver
== CODEC_VER_1
) {
2069 snd_soc_update_bits(codec
, RT5663_HP_CHARGE_PUMP_1
,
2070 RT5663_SEL_PM_HP_SHIFT
, RT5663_SEL_PM_HP_HIGH
);
2071 snd_soc_update_bits(codec
, RT5663_HP_LOGIC_2
,
2072 RT5663_HP_SIG_SRC1_MASK
,
2073 RT5663_HP_SIG_SRC1_SILENCE
);
2075 snd_soc_write(codec
, RT5663_DEPOP_2
, 0x3003);
2076 snd_soc_update_bits(codec
, RT5663_HP_CHARGE_PUMP_1
,
2077 RT5663_OVCD_HP_MASK
, RT5663_OVCD_HP_DIS
);
2078 snd_soc_write(codec
, RT5663_HP_CHARGE_PUMP_2
, 0x1371);
2079 snd_soc_write(codec
, RT5663_HP_BIAS
, 0xabba);
2080 snd_soc_write(codec
, RT5663_CHARGE_PUMP_1
, 0x2224);
2081 snd_soc_write(codec
, RT5663_ANA_BIAS_CUR_1
, 0x7766);
2082 snd_soc_write(codec
, RT5663_HP_BIAS
, 0xafaa);
2083 snd_soc_write(codec
, RT5663_CHARGE_PUMP_2
, 0x7777);
2084 snd_soc_update_bits(codec
, RT5663_STO_DRE_1
, 0x8000,
2086 snd_soc_update_bits(codec
, RT5663_DEPOP_1
, 0x3000,
2091 case SND_SOC_DAPM_PRE_PMD
:
2092 if (rt5663
->codec_ver
== CODEC_VER_1
) {
2093 snd_soc_update_bits(codec
, RT5663_HP_LOGIC_2
,
2094 RT5663_HP_SIG_SRC1_MASK
,
2095 RT5663_HP_SIG_SRC1_REG
);
2097 snd_soc_update_bits(codec
, RT5663_DEPOP_1
, 0x3000, 0x0);
2098 snd_soc_update_bits(codec
, RT5663_HP_CHARGE_PUMP_1
,
2099 RT5663_OVCD_HP_MASK
, RT5663_OVCD_HP_EN
);
2110 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget
*w
,
2111 struct snd_kcontrol
*kcontrol
, int event
)
2113 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
2114 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2117 case SND_SOC_DAPM_PRE_PMU
:
2118 if (rt5663
->codec_ver
== CODEC_VER_0
) {
2119 snd_soc_update_bits(codec
, RT5663_DEPOP_1
, 0x0030,
2121 snd_soc_update_bits(codec
, RT5663_DEPOP_1
, 0x0003,
2126 case SND_SOC_DAPM_POST_PMD
:
2127 if (rt5663
->codec_ver
== CODEC_VER_0
) {
2128 snd_soc_update_bits(codec
, RT5663_DEPOP_1
, 0x0003, 0);
2129 snd_soc_update_bits(codec
, RT5663_DEPOP_1
, 0x0030, 0);
2140 static int rt5663_bst2_power(struct snd_soc_dapm_widget
*w
,
2141 struct snd_kcontrol
*kcontrol
, int event
)
2143 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
2146 case SND_SOC_DAPM_POST_PMU
:
2147 snd_soc_update_bits(codec
, RT5663_PWR_ANLG_2
,
2148 RT5663_PWR_BST2_MASK
| RT5663_PWR_BST2_OP_MASK
,
2149 RT5663_PWR_BST2
| RT5663_PWR_BST2_OP
);
2152 case SND_SOC_DAPM_PRE_PMD
:
2153 snd_soc_update_bits(codec
, RT5663_PWR_ANLG_2
,
2154 RT5663_PWR_BST2_MASK
| RT5663_PWR_BST2_OP_MASK
, 0);
2164 static int rt5663_pre_div_power(struct snd_soc_dapm_widget
*w
,
2165 struct snd_kcontrol
*kcontrol
, int event
)
2167 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
2170 case SND_SOC_DAPM_POST_PMU
:
2171 snd_soc_write(codec
, RT5663_PRE_DIV_GATING_1
, 0xff00);
2172 snd_soc_write(codec
, RT5663_PRE_DIV_GATING_2
, 0xfffc);
2175 case SND_SOC_DAPM_PRE_PMD
:
2176 snd_soc_write(codec
, RT5663_PRE_DIV_GATING_1
, 0x0000);
2177 snd_soc_write(codec
, RT5663_PRE_DIV_GATING_2
, 0x0000);
2187 static const struct snd_soc_dapm_widget rt5663_dapm_widgets
[] = {
2188 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3
, RT5663_PWR_PLL_SHIFT
, 0,
2192 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2
,
2193 RT5663_PWR_MB1_SHIFT
, 0),
2194 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2
,
2195 RT5663_PWR_MB2_SHIFT
, 0),
2198 SND_SOC_DAPM_INPUT("IN1P"),
2199 SND_SOC_DAPM_INPUT("IN1N"),
2201 /* REC Mixer Power */
2202 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2
,
2203 RT5663_PWR_RECMIX1_SHIFT
, 0, NULL
, 0),
2206 SND_SOC_DAPM_ADC("ADC L", NULL
, SND_SOC_NOPM
, 0, 0),
2207 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1
,
2208 RT5663_PWR_ADC_L1_SHIFT
, 0, NULL
, 0),
2209 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC
,
2210 RT5663_CKGEN_ADCC_SHIFT
, 0, NULL
, 0),
2213 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM
,
2214 0, 0, rt5663_sto1_adc_l_mix
,
2215 ARRAY_SIZE(rt5663_sto1_adc_l_mix
)),
2217 /* ADC Filter Power */
2218 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2
,
2219 RT5663_PWR_ADC_S1F_SHIFT
, 0, NULL
, 0),
2221 /* Digital Interface */
2222 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1
, RT5663_PWR_I2S1_SHIFT
, 0,
2224 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2225 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2226 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2227 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2228 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2230 /* Audio Interface */
2231 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM
, 0, 0),
2232 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM
, 0, 0),
2234 /* DAC mixer before sound effect */
2235 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM
, 0, 0, rt5663_adda_l_mix
,
2236 ARRAY_SIZE(rt5663_adda_l_mix
)),
2237 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM
, 0, 0, rt5663_adda_r_mix
,
2238 ARRAY_SIZE(rt5663_adda_r_mix
)),
2239 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2240 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2243 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2
,
2244 RT5663_PWR_DAC_S1F_SHIFT
, 0, NULL
, 0),
2245 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM
, 0, 0,
2246 rt5663_sto1_dac_l_mix
, ARRAY_SIZE(rt5663_sto1_dac_l_mix
)),
2247 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM
, 0, 0,
2248 rt5663_sto1_dac_r_mix
, ARRAY_SIZE(rt5663_sto1_dac_r_mix
)),
2251 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1
,
2252 RT5663_PWR_DAC_L1_SHIFT
, 0, NULL
, 0),
2253 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1
,
2254 RT5663_PWR_DAC_R1_SHIFT
, 0, NULL
, 0),
2255 SND_SOC_DAPM_DAC("DAC L", NULL
, SND_SOC_NOPM
, 0, 0),
2256 SND_SOC_DAPM_DAC("DAC R", NULL
, SND_SOC_NOPM
, 0, 0),
2259 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM
, 0, 0,
2260 rt5663_charge_pump_event
, SND_SOC_DAPM_PRE_PMU
|
2261 SND_SOC_DAPM_POST_PMD
),
2262 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM
, 0, 0, rt5663_hp_event
,
2263 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMU
),
2266 SND_SOC_DAPM_OUTPUT("HPOL"),
2267 SND_SOC_DAPM_OUTPUT("HPOR"),
2270 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets
[] = {
2271 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3
,
2272 RT5663_PWR_LDO2_SHIFT
, 0, NULL
, 0),
2273 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL
,
2274 RT5663_V2_PWR_MIC_DET_SHIFT
, 0, NULL
, 0),
2275 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1
,
2276 RT5663_PWR_LDO_DACREF_SHIFT
, 0, NULL
, 0),
2279 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1
,
2280 RT5663_I2S1_ASRC_SHIFT
, 0, NULL
, 0),
2281 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1
,
2282 RT5663_DAC_STO1_ASRC_SHIFT
, 0, NULL
, 0),
2283 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1
,
2284 RT5663_ADC_STO1_ASRC_SHIFT
, 0, NULL
, 0),
2287 SND_SOC_DAPM_INPUT("IN2P"),
2288 SND_SOC_DAPM_INPUT("IN2N"),
2291 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2292 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3
,
2293 RT5663_PWR_CBJ_SHIFT
, 0, NULL
, 0),
2294 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2295 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM
, 0, 0,
2296 rt5663_bst2_power
, SND_SOC_DAPM_PRE_PMD
|
2297 SND_SOC_DAPM_POST_PMU
),
2300 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM
, 0, 0, rt5663_recmix1l
,
2301 ARRAY_SIZE(rt5663_recmix1l
)),
2302 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM
, 0, 0, rt5663_recmix1r
,
2303 ARRAY_SIZE(rt5663_recmix1r
)),
2304 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2
,
2305 RT5663_PWR_RECMIX2_SHIFT
, 0, NULL
, 0),
2308 SND_SOC_DAPM_ADC("ADC R", NULL
, SND_SOC_NOPM
, 0, 0),
2309 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1
,
2310 RT5663_PWR_ADC_R1_SHIFT
, 0, NULL
, 0),
2313 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER
,
2314 RT5663_STO1_ADC_L1_SRC_SHIFT
, 0, NULL
, 0),
2315 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER
,
2316 RT5663_STO1_ADC_R1_SRC_SHIFT
, 0, NULL
, 0),
2317 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER
,
2318 RT5663_STO1_ADC_L2_SRC_SHIFT
, 1, NULL
, 0),
2319 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER
,
2320 RT5663_STO1_ADC_R2_SRC_SHIFT
, 1, NULL
, 0),
2322 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM
, 0, 0,
2323 &rt5663_sto1_adcl_mux
),
2324 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM
, 0, 0,
2325 &rt5663_sto1_adcr_mux
),
2328 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM
, 0, 0,
2329 rt5663_sto1_adc_r_mix
, ARRAY_SIZE(rt5663_sto1_adc_r_mix
)),
2331 /* Analog DAC Clock */
2332 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L
,
2333 RT5663_CKGEN_DAC1_SHIFT
, 0, NULL
, 0),
2336 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM
, 0, 0,
2337 &rt5663_hpo_switch
),
2340 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets
[] = {
2341 /* System Clock Pre Divider Gating */
2342 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM
, 0, 0,
2343 rt5663_pre_div_power
, SND_SOC_DAPM_POST_PMU
|
2344 SND_SOC_DAPM_PRE_PMD
),
2347 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1
,
2348 RT5663_PWR_LDO_DACREF_SHIFT
, 0, NULL
, 0),
2351 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1
,
2352 RT5663_I2S1_ASRC_SHIFT
, 0, NULL
, 0),
2353 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1
,
2354 RT5663_DAC_STO1_ASRC_SHIFT
, 0, NULL
, 0),
2355 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1
,
2356 RT5663_ADC_STO1_ASRC_SHIFT
, 0, NULL
, 0),
2359 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2362 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2363 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM
, 0, 0, NULL
, 0),
2365 /* Analog DAC source */
2366 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM
, 0, 0, &rt5663_alg_dacl_mux
),
2367 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM
, 0, 0, &rt5663_alg_dacr_mux
),
2370 static const struct snd_soc_dapm_route rt5663_dapm_routes
[] = {
2372 { "I2S", NULL
, "PLL", rt5663_is_sys_clk_from_pll
},
2375 { "STO1 ADC Filter", NULL
, "ADC ASRC", rt5663_is_using_asrc
},
2376 { "STO1 DAC Filter", NULL
, "DAC ASRC", rt5663_is_using_asrc
},
2377 { "I2S", NULL
, "I2S ASRC", rt5663_i2s_use_asrc
},
2379 { "ADC L", NULL
, "ADC L Power" },
2380 { "ADC L", NULL
, "ADC Clock" },
2382 { "STO1 ADC L2", NULL
, "STO1 DAC MIXL" },
2384 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2385 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2386 { "STO1 ADC MIXL", NULL
, "STO1 ADC Filter" },
2388 { "IF1 ADC1", NULL
, "STO1 ADC MIXL" },
2389 { "IF ADC", NULL
, "IF1 ADC1" },
2390 { "AIFTX", NULL
, "IF ADC" },
2391 { "AIFTX", NULL
, "I2S" },
2393 { "AIFRX", NULL
, "I2S" },
2394 { "IF DAC", NULL
, "AIFRX" },
2395 { "IF1 DAC1 L", NULL
, "IF DAC" },
2396 { "IF1 DAC1 R", NULL
, "IF DAC" },
2398 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2399 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2400 { "ADDA MIXL", NULL
, "STO1 DAC Filter" },
2401 { "ADDA MIXL", NULL
, "STO1 DAC L Power" },
2402 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2403 { "ADDA MIXR", NULL
, "STO1 DAC Filter" },
2404 { "ADDA MIXR", NULL
, "STO1 DAC R Power" },
2406 { "DAC L1", NULL
, "ADDA MIXL" },
2407 { "DAC R1", NULL
, "ADDA MIXR" },
2409 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2410 { "STO1 DAC MIXL", NULL
, "STO1 DAC L Power" },
2411 { "STO1 DAC MIXL", NULL
, "STO1 DAC Filter" },
2412 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2413 { "STO1 DAC MIXR", NULL
, "STO1 DAC R Power" },
2414 { "STO1 DAC MIXR", NULL
, "STO1 DAC Filter" },
2416 { "HP Amp", NULL
, "HP Charge Pump" },
2417 { "HP Amp", NULL
, "DAC L" },
2418 { "HP Amp", NULL
, "DAC R" },
2421 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes
[] = {
2422 { "MICBIAS1", NULL
, "LDO2" },
2423 { "MICBIAS2", NULL
, "LDO2" },
2425 { "BST1 CBJ", NULL
, "IN1P" },
2426 { "BST1 CBJ", NULL
, "IN1N" },
2427 { "BST1 CBJ", NULL
, "CBJ Power" },
2429 { "BST2", NULL
, "IN2P" },
2430 { "BST2", NULL
, "IN2N" },
2431 { "BST2", NULL
, "BST2 Power" },
2433 { "RECMIX1L", "BST2 Switch", "BST2" },
2434 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2435 { "RECMIX1L", NULL
, "RECMIX1L Power" },
2436 { "RECMIX1R", "BST2 Switch", "BST2" },
2437 { "RECMIX1R", NULL
, "RECMIX1R Power" },
2439 { "ADC L", NULL
, "RECMIX1L" },
2440 { "ADC R", NULL
, "RECMIX1R" },
2441 { "ADC R", NULL
, "ADC R Power" },
2442 { "ADC R", NULL
, "ADC Clock" },
2444 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2445 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2446 { "STO1 ADC L1", NULL
, "STO1 ADC L Mux" },
2448 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2449 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2450 { "STO1 ADC R1", NULL
, "STO1 ADC R Mux" },
2451 { "STO1 ADC R2", NULL
, "STO1 DAC MIXR" },
2453 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2454 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2455 { "STO1 ADC MIXR", NULL
, "STO1 ADC Filter" },
2457 { "IF1 ADC1", NULL
, "STO1 ADC MIXR" },
2459 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2461 { "DAC L", NULL
, "STO1 DAC MIXL" },
2462 { "DAC L", NULL
, "LDO DAC" },
2463 { "DAC L", NULL
, "DAC Clock" },
2464 { "DAC R", NULL
, "STO1 DAC MIXR" },
2465 { "DAC R", NULL
, "LDO DAC" },
2466 { "DAC R", NULL
, "DAC Clock" },
2468 { "HPO Playback", "Switch", "HP Amp" },
2469 { "HPOL", NULL
, "HPO Playback" },
2470 { "HPOR", NULL
, "HPO Playback" },
2473 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes
[] = {
2474 { "I2S", NULL
, "Pre Div Power" },
2476 { "BST1", NULL
, "IN1P" },
2477 { "BST1", NULL
, "IN1N" },
2478 { "BST1", NULL
, "RECMIX1L Power" },
2480 { "ADC L", NULL
, "BST1" },
2482 { "STO1 ADC L1", NULL
, "ADC L" },
2484 { "DAC L Mux", "DAC L", "DAC L1" },
2485 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2486 { "DAC R Mux", "DAC R", "DAC R1"},
2487 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2489 { "DAC L", NULL
, "DAC L Mux" },
2490 { "DAC R", NULL
, "DAC R Mux" },
2492 { "HPOL", NULL
, "HP Amp" },
2493 { "HPOR", NULL
, "HP Amp" },
2496 static int rt5663_hw_params(struct snd_pcm_substream
*substream
,
2497 struct snd_pcm_hw_params
*params
, struct snd_soc_dai
*dai
)
2499 struct snd_soc_codec
*codec
= dai
->codec
;
2500 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2501 unsigned int val_len
= 0;
2504 rt5663
->lrck
= params_rate(params
);
2506 dev_dbg(dai
->dev
, "bclk is %dHz and sysclk is %dHz\n",
2507 rt5663
->lrck
, rt5663
->sysclk
);
2509 pre_div
= rl6231_get_clk_info(rt5663
->sysclk
, rt5663
->lrck
);
2511 dev_err(codec
->dev
, "Unsupported clock setting %d for DAI %d\n",
2512 rt5663
->lrck
, dai
->id
);
2516 dev_dbg(dai
->dev
, "pre_div is %d for iis %d\n", pre_div
, dai
->id
);
2518 switch (params_width(params
)) {
2520 val_len
= RT5663_I2S_DL_8
;
2523 val_len
= RT5663_I2S_DL_16
;
2526 val_len
= RT5663_I2S_DL_20
;
2529 val_len
= RT5663_I2S_DL_24
;
2535 snd_soc_update_bits(codec
, RT5663_I2S1_SDP
,
2536 RT5663_I2S_DL_MASK
, val_len
);
2538 snd_soc_update_bits(codec
, RT5663_ADDA_CLK_1
,
2539 RT5663_I2S_PD1_MASK
, pre_div
<< RT5663_I2S_PD1_SHIFT
);
2544 static int rt5663_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2546 struct snd_soc_codec
*codec
= dai
->codec
;
2547 unsigned int reg_val
= 0;
2549 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2550 case SND_SOC_DAIFMT_CBM_CFM
:
2552 case SND_SOC_DAIFMT_CBS_CFS
:
2553 reg_val
|= RT5663_I2S_MS_S
;
2559 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2560 case SND_SOC_DAIFMT_NB_NF
:
2562 case SND_SOC_DAIFMT_IB_NF
:
2563 reg_val
|= RT5663_I2S_BP_INV
;
2569 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2570 case SND_SOC_DAIFMT_I2S
:
2572 case SND_SOC_DAIFMT_LEFT_J
:
2573 reg_val
|= RT5663_I2S_DF_LEFT
;
2575 case SND_SOC_DAIFMT_DSP_A
:
2576 reg_val
|= RT5663_I2S_DF_PCM_A
;
2578 case SND_SOC_DAIFMT_DSP_B
:
2579 reg_val
|= RT5663_I2S_DF_PCM_B
;
2585 snd_soc_update_bits(codec
, RT5663_I2S1_SDP
, RT5663_I2S_MS_MASK
|
2586 RT5663_I2S_BP_MASK
| RT5663_I2S_DF_MASK
, reg_val
);
2591 static int rt5663_set_dai_sysclk(struct snd_soc_dai
*dai
, int clk_id
,
2592 unsigned int freq
, int dir
)
2594 struct snd_soc_codec
*codec
= dai
->codec
;
2595 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2596 unsigned int reg_val
= 0;
2598 if (freq
== rt5663
->sysclk
&& clk_id
== rt5663
->sysclk_src
)
2602 case RT5663_SCLK_S_MCLK
:
2603 reg_val
|= RT5663_SCLK_SRC_MCLK
;
2605 case RT5663_SCLK_S_PLL1
:
2606 reg_val
|= RT5663_SCLK_SRC_PLL1
;
2608 case RT5663_SCLK_S_RCCLK
:
2609 reg_val
|= RT5663_SCLK_SRC_RCCLK
;
2612 dev_err(codec
->dev
, "Invalid clock id (%d)\n", clk_id
);
2615 snd_soc_update_bits(codec
, RT5663_GLB_CLK
, RT5663_SCLK_SRC_MASK
,
2617 rt5663
->sysclk
= freq
;
2618 rt5663
->sysclk_src
= clk_id
;
2620 dev_dbg(codec
->dev
, "Sysclk is %dHz and clock id is %d\n",
2626 static int rt5663_set_dai_pll(struct snd_soc_dai
*dai
, int pll_id
, int source
,
2627 unsigned int freq_in
, unsigned int freq_out
)
2629 struct snd_soc_codec
*codec
= dai
->codec
;
2630 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2631 struct rl6231_pll_code pll_code
;
2633 int mask
, shift
, val
;
2635 if (source
== rt5663
->pll_src
&& freq_in
== rt5663
->pll_in
&&
2636 freq_out
== rt5663
->pll_out
)
2639 if (!freq_in
|| !freq_out
) {
2640 dev_dbg(codec
->dev
, "PLL disabled\n");
2643 rt5663
->pll_out
= 0;
2644 snd_soc_update_bits(codec
, RT5663_GLB_CLK
,
2645 RT5663_SCLK_SRC_MASK
, RT5663_SCLK_SRC_MCLK
);
2649 switch (rt5663
->codec_ver
) {
2651 mask
= RT5663_V2_PLL1_SRC_MASK
;
2652 shift
= RT5663_V2_PLL1_SRC_SHIFT
;
2655 mask
= RT5663_PLL1_SRC_MASK
;
2656 shift
= RT5663_PLL1_SRC_SHIFT
;
2659 dev_err(codec
->dev
, "Unknown CODEC Version\n");
2664 case RT5663_PLL1_S_MCLK
:
2667 case RT5663_PLL1_S_BCLK1
:
2671 dev_err(codec
->dev
, "Unknown PLL source %d\n", source
);
2674 snd_soc_update_bits(codec
, RT5663_GLB_CLK
, mask
, (val
<< shift
));
2676 ret
= rl6231_pll_calc(freq_in
, freq_out
, &pll_code
);
2678 dev_err(codec
->dev
, "Unsupport input clock %d\n", freq_in
);
2682 dev_dbg(codec
->dev
, "bypass=%d m=%d n=%d k=%d\n", pll_code
.m_bp
,
2683 (pll_code
.m_bp
? 0 : pll_code
.m_code
), pll_code
.n_code
,
2686 snd_soc_write(codec
, RT5663_PLL_1
,
2687 pll_code
.n_code
<< RT5663_PLL_N_SHIFT
| pll_code
.k_code
);
2688 snd_soc_write(codec
, RT5663_PLL_2
,
2689 (pll_code
.m_bp
? 0 : pll_code
.m_code
) << RT5663_PLL_M_SHIFT
|
2690 pll_code
.m_bp
<< RT5663_PLL_M_BP_SHIFT
);
2692 rt5663
->pll_in
= freq_in
;
2693 rt5663
->pll_out
= freq_out
;
2694 rt5663
->pll_src
= source
;
2699 static int rt5663_set_tdm_slot(struct snd_soc_dai
*dai
, unsigned int tx_mask
,
2700 unsigned int rx_mask
, int slots
, int slot_width
)
2702 struct snd_soc_codec
*codec
= dai
->codec
;
2703 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2704 unsigned int val
= 0, reg
;
2706 if (rx_mask
|| tx_mask
)
2707 val
|= RT5663_TDM_MODE_TDM
;
2711 val
|= RT5663_TDM_IN_CH_4
;
2712 val
|= RT5663_TDM_OUT_CH_4
;
2715 val
|= RT5663_TDM_IN_CH_6
;
2716 val
|= RT5663_TDM_OUT_CH_6
;
2719 val
|= RT5663_TDM_IN_CH_8
;
2720 val
|= RT5663_TDM_OUT_CH_8
;
2728 switch (slot_width
) {
2730 val
|= RT5663_TDM_IN_LEN_20
;
2731 val
|= RT5663_TDM_OUT_LEN_20
;
2734 val
|= RT5663_TDM_IN_LEN_24
;
2735 val
|= RT5663_TDM_OUT_LEN_24
;
2738 val
|= RT5663_TDM_IN_LEN_32
;
2739 val
|= RT5663_TDM_OUT_LEN_32
;
2747 switch (rt5663
->codec_ver
) {
2755 dev_err(codec
->dev
, "Unknown CODEC Version\n");
2759 snd_soc_update_bits(codec
, reg
, RT5663_TDM_MODE_MASK
|
2760 RT5663_TDM_IN_CH_MASK
| RT5663_TDM_OUT_CH_MASK
|
2761 RT5663_TDM_IN_LEN_MASK
| RT5663_TDM_OUT_LEN_MASK
, val
);
2766 static int rt5663_set_bclk_ratio(struct snd_soc_dai
*dai
, unsigned int ratio
)
2768 struct snd_soc_codec
*codec
= dai
->codec
;
2769 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2772 dev_dbg(codec
->dev
, "%s ratio = %d\n", __func__
, ratio
);
2774 if (rt5663
->codec_ver
== CODEC_VER_1
)
2781 snd_soc_update_bits(codec
, reg
,
2782 RT5663_TDM_LENGTN_MASK
,
2783 RT5663_TDM_LENGTN_16
);
2786 snd_soc_update_bits(codec
, reg
,
2787 RT5663_TDM_LENGTN_MASK
,
2788 RT5663_TDM_LENGTN_20
);
2791 snd_soc_update_bits(codec
, reg
,
2792 RT5663_TDM_LENGTN_MASK
,
2793 RT5663_TDM_LENGTN_24
);
2796 snd_soc_update_bits(codec
, reg
,
2797 RT5663_TDM_LENGTN_MASK
,
2798 RT5663_TDM_LENGTN_32
);
2801 dev_err(codec
->dev
, "Invalid ratio!\n");
2808 static int rt5663_set_bias_level(struct snd_soc_codec
*codec
,
2809 enum snd_soc_bias_level level
)
2811 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2814 case SND_SOC_BIAS_ON
:
2815 snd_soc_update_bits(codec
, RT5663_PWR_ANLG_1
,
2816 RT5663_PWR_FV1_MASK
| RT5663_PWR_FV2_MASK
,
2817 RT5663_PWR_FV1
| RT5663_PWR_FV2
);
2820 case SND_SOC_BIAS_PREPARE
:
2821 if (rt5663
->codec_ver
== CODEC_VER_1
) {
2822 snd_soc_update_bits(codec
, RT5663_DIG_MISC
,
2823 RT5663_DIG_GATE_CTRL_MASK
,
2824 RT5663_DIG_GATE_CTRL_EN
);
2825 snd_soc_update_bits(codec
, RT5663_SIG_CLK_DET
,
2826 RT5663_EN_ANA_CLK_DET_MASK
|
2827 RT5663_PWR_CLK_DET_MASK
,
2828 RT5663_EN_ANA_CLK_DET_AUTO
|
2829 RT5663_PWR_CLK_DET_EN
);
2833 case SND_SOC_BIAS_STANDBY
:
2834 if (rt5663
->codec_ver
== CODEC_VER_1
)
2835 snd_soc_update_bits(codec
, RT5663_DIG_MISC
,
2836 RT5663_DIG_GATE_CTRL_MASK
,
2837 RT5663_DIG_GATE_CTRL_DIS
);
2838 snd_soc_update_bits(codec
, RT5663_PWR_ANLG_1
,
2839 RT5663_PWR_VREF1_MASK
| RT5663_PWR_VREF2_MASK
|
2840 RT5663_PWR_FV1_MASK
| RT5663_PWR_FV2_MASK
|
2841 RT5663_PWR_MB_MASK
, RT5663_PWR_VREF1
|
2842 RT5663_PWR_VREF2
| RT5663_PWR_MB
);
2843 usleep_range(10000, 10005);
2844 if (rt5663
->codec_ver
== CODEC_VER_1
) {
2845 snd_soc_update_bits(codec
, RT5663_SIG_CLK_DET
,
2846 RT5663_EN_ANA_CLK_DET_MASK
|
2847 RT5663_PWR_CLK_DET_MASK
,
2848 RT5663_EN_ANA_CLK_DET_DIS
|
2849 RT5663_PWR_CLK_DET_DIS
);
2853 case SND_SOC_BIAS_OFF
:
2854 snd_soc_update_bits(codec
, RT5663_PWR_ANLG_1
,
2855 RT5663_PWR_VREF1_MASK
| RT5663_PWR_VREF2_MASK
|
2856 RT5663_PWR_FV1
| RT5663_PWR_FV2
, 0x0);
2866 static int rt5663_probe(struct snd_soc_codec
*codec
)
2868 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
2869 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2871 rt5663
->codec
= codec
;
2873 switch (rt5663
->codec_ver
) {
2875 snd_soc_dapm_new_controls(dapm
,
2876 rt5663_v2_specific_dapm_widgets
,
2877 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets
));
2878 snd_soc_dapm_add_routes(dapm
,
2879 rt5663_v2_specific_dapm_routes
,
2880 ARRAY_SIZE(rt5663_v2_specific_dapm_routes
));
2881 snd_soc_add_codec_controls(codec
, rt5663_v2_specific_controls
,
2882 ARRAY_SIZE(rt5663_v2_specific_controls
));
2885 snd_soc_dapm_new_controls(dapm
,
2886 rt5663_specific_dapm_widgets
,
2887 ARRAY_SIZE(rt5663_specific_dapm_widgets
));
2888 snd_soc_dapm_add_routes(dapm
,
2889 rt5663_specific_dapm_routes
,
2890 ARRAY_SIZE(rt5663_specific_dapm_routes
));
2891 snd_soc_add_codec_controls(codec
, rt5663_specific_controls
,
2892 ARRAY_SIZE(rt5663_specific_controls
));
2899 static int rt5663_remove(struct snd_soc_codec
*codec
)
2901 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2903 regmap_write(rt5663
->regmap
, RT5663_RESET
, 0);
2909 static int rt5663_suspend(struct snd_soc_codec
*codec
)
2911 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2913 regcache_cache_only(rt5663
->regmap
, true);
2914 regcache_mark_dirty(rt5663
->regmap
);
2919 static int rt5663_resume(struct snd_soc_codec
*codec
)
2921 struct rt5663_priv
*rt5663
= snd_soc_codec_get_drvdata(codec
);
2923 regcache_cache_only(rt5663
->regmap
, false);
2924 regcache_sync(rt5663
->regmap
);
2926 rt5663_irq(0, rt5663
);
2931 #define rt5663_suspend NULL
2932 #define rt5663_resume NULL
2935 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2936 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2937 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2939 static const struct snd_soc_dai_ops rt5663_aif_dai_ops
= {
2940 .hw_params
= rt5663_hw_params
,
2941 .set_fmt
= rt5663_set_dai_fmt
,
2942 .set_sysclk
= rt5663_set_dai_sysclk
,
2943 .set_pll
= rt5663_set_dai_pll
,
2944 .set_tdm_slot
= rt5663_set_tdm_slot
,
2945 .set_bclk_ratio
= rt5663_set_bclk_ratio
,
2948 static struct snd_soc_dai_driver rt5663_dai
[] = {
2950 .name
= "rt5663-aif",
2953 .stream_name
= "AIF Playback",
2956 .rates
= RT5663_STEREO_RATES
,
2957 .formats
= RT5663_FORMATS
,
2960 .stream_name
= "AIF Capture",
2963 .rates
= RT5663_STEREO_RATES
,
2964 .formats
= RT5663_FORMATS
,
2966 .ops
= &rt5663_aif_dai_ops
,
2970 static const struct snd_soc_codec_driver soc_codec_dev_rt5663
= {
2971 .probe
= rt5663_probe
,
2972 .remove
= rt5663_remove
,
2973 .suspend
= rt5663_suspend
,
2974 .resume
= rt5663_resume
,
2975 .set_bias_level
= rt5663_set_bias_level
,
2976 .idle_bias_off
= true,
2977 .component_driver
= {
2978 .controls
= rt5663_snd_controls
,
2979 .num_controls
= ARRAY_SIZE(rt5663_snd_controls
),
2980 .dapm_widgets
= rt5663_dapm_widgets
,
2981 .num_dapm_widgets
= ARRAY_SIZE(rt5663_dapm_widgets
),
2982 .dapm_routes
= rt5663_dapm_routes
,
2983 .num_dapm_routes
= ARRAY_SIZE(rt5663_dapm_routes
),
2987 static const struct regmap_config rt5663_v2_regmap
= {
2990 .use_single_rw
= true,
2991 .max_register
= 0x07fa,
2992 .volatile_reg
= rt5663_v2_volatile_register
,
2993 .readable_reg
= rt5663_v2_readable_register
,
2994 .cache_type
= REGCACHE_RBTREE
,
2995 .reg_defaults
= rt5663_v2_reg
,
2996 .num_reg_defaults
= ARRAY_SIZE(rt5663_v2_reg
),
2999 static const struct regmap_config rt5663_regmap
= {
3002 .use_single_rw
= true,
3003 .max_register
= 0x03f3,
3004 .volatile_reg
= rt5663_volatile_register
,
3005 .readable_reg
= rt5663_readable_register
,
3006 .cache_type
= REGCACHE_RBTREE
,
3007 .reg_defaults
= rt5663_reg
,
3008 .num_reg_defaults
= ARRAY_SIZE(rt5663_reg
),
3011 static const struct regmap_config temp_regmap
= {
3015 .use_single_rw
= true,
3016 .max_register
= 0x03f3,
3017 .cache_type
= REGCACHE_NONE
,
3020 static const struct i2c_device_id rt5663_i2c_id
[] = {
3024 MODULE_DEVICE_TABLE(i2c
, rt5663_i2c_id
);
3026 #if defined(CONFIG_OF)
3027 static const struct of_device_id rt5663_of_match
[] = {
3028 { .compatible
= "realtek,rt5663", },
3031 MODULE_DEVICE_TABLE(of
, rt5663_of_match
);
3035 static const struct acpi_device_id rt5663_acpi_match
[] = {
3039 MODULE_DEVICE_TABLE(acpi
, rt5663_acpi_match
);
3042 static void rt5663_v2_calibrate(struct rt5663_priv
*rt5663
)
3044 regmap_write(rt5663
->regmap
, RT5663_BIAS_CUR_8
, 0xa402);
3045 regmap_write(rt5663
->regmap
, RT5663_PWR_DIG_1
, 0x0100);
3046 regmap_write(rt5663
->regmap
, RT5663_RECMIX
, 0x4040);
3047 regmap_write(rt5663
->regmap
, RT5663_DIG_MISC
, 0x0001);
3048 regmap_write(rt5663
->regmap
, RT5663_RC_CLK
, 0x0380);
3049 regmap_write(rt5663
->regmap
, RT5663_GLB_CLK
, 0x8000);
3050 regmap_write(rt5663
->regmap
, RT5663_ADDA_CLK_1
, 0x1000);
3051 regmap_write(rt5663
->regmap
, RT5663_CHOP_DAC_L
, 0x3030);
3052 regmap_write(rt5663
->regmap
, RT5663_CALIB_ADC
, 0x3c05);
3053 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_1
, 0xa23e);
3055 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_1
, 0xf23e);
3056 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_2
, 0x0321);
3057 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_1
, 0xfc00);
3061 static void rt5663_calibrate(struct rt5663_priv
*rt5663
)
3065 regmap_write(rt5663
->regmap
, RT5663_RESET
, 0x0000);
3067 regmap_write(rt5663
->regmap
, RT5663_ANA_BIAS_CUR_4
, 0x00a1);
3068 regmap_write(rt5663
->regmap
, RT5663_RC_CLK
, 0x0380);
3069 regmap_write(rt5663
->regmap
, RT5663_GLB_CLK
, 0x8000);
3070 regmap_write(rt5663
->regmap
, RT5663_ADDA_CLK_1
, 0x1000);
3071 regmap_write(rt5663
->regmap
, RT5663_VREF_RECMIX
, 0x0032);
3072 regmap_write(rt5663
->regmap
, RT5663_HP_IMP_SEN_19
, 0x000c);
3073 regmap_write(rt5663
->regmap
, RT5663_DUMMY_1
, 0x0324);
3074 regmap_write(rt5663
->regmap
, RT5663_DIG_MISC
, 0x8001);
3075 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_1
, 0xa23b);
3077 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_1
, 0xf23b);
3078 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_2
, 0x8000);
3079 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_3
, 0x0008);
3080 regmap_write(rt5663
->regmap
, RT5663_PRE_DIV_GATING_1
, 0xffff);
3081 regmap_write(rt5663
->regmap
, RT5663_PRE_DIV_GATING_2
, 0xffff);
3082 regmap_write(rt5663
->regmap
, RT5663_CBJ_1
, 0x8c10);
3083 regmap_write(rt5663
->regmap
, RT5663_IL_CMD_2
, 0x00c1);
3084 regmap_write(rt5663
->regmap
, RT5663_EM_JACK_TYPE_1
, 0xb880);
3085 regmap_write(rt5663
->regmap
, RT5663_EM_JACK_TYPE_2
, 0x4110);
3086 regmap_write(rt5663
->regmap
, RT5663_EM_JACK_TYPE_2
, 0x4118);
3090 regmap_read(rt5663
->regmap
, RT5663_INT_ST_2
, &value
);
3091 if (!(value
& 0x80))
3092 usleep_range(10000, 10005);
3100 regmap_write(rt5663
->regmap
, RT5663_HP_IMP_SEN_19
, 0x0000);
3101 regmap_write(rt5663
->regmap
, RT5663_DEPOP_2
, 0x3003);
3102 regmap_write(rt5663
->regmap
, RT5663_DEPOP_1
, 0x0038);
3103 regmap_write(rt5663
->regmap
, RT5663_DEPOP_1
, 0x003b);
3104 regmap_write(rt5663
->regmap
, RT5663_PWR_DIG_2
, 0x8400);
3105 regmap_write(rt5663
->regmap
, RT5663_PWR_DIG_1
, 0x8df8);
3106 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_2
, 0x8003);
3107 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_3
, 0x018c);
3108 regmap_write(rt5663
->regmap
, RT5663_HP_CHARGE_PUMP_1
, 0x1e32);
3109 regmap_write(rt5663
->regmap
, RT5663_DACREF_LDO
, 0x3b0b);
3111 regmap_write(rt5663
->regmap
, RT5663_STO_DAC_MIXER
, 0x0000);
3112 regmap_write(rt5663
->regmap
, RT5663_BYPASS_STO_DAC
, 0x000c);
3113 regmap_write(rt5663
->regmap
, RT5663_HP_BIAS
, 0xafaa);
3114 regmap_write(rt5663
->regmap
, RT5663_CHARGE_PUMP_1
, 0x2224);
3115 regmap_write(rt5663
->regmap
, RT5663_HP_OUT_EN
, 0x8088);
3116 regmap_write(rt5663
->regmap
, RT5663_STO_DRE_9
, 0x0017);
3117 regmap_write(rt5663
->regmap
, RT5663_STO_DRE_10
, 0x0017);
3118 regmap_write(rt5663
->regmap
, RT5663_STO1_ADC_MIXER
, 0x4040);
3119 regmap_write(rt5663
->regmap
, RT5663_CHOP_ADC
, 0x3000);
3120 regmap_write(rt5663
->regmap
, RT5663_RECMIX
, 0x0005);
3121 regmap_write(rt5663
->regmap
, RT5663_ADDA_RST
, 0xc000);
3122 regmap_write(rt5663
->regmap
, RT5663_STO1_HPF_ADJ1
, 0x3320);
3123 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_2
, 0x00c9);
3124 regmap_write(rt5663
->regmap
, RT5663_DUMMY_1
, 0x004c);
3125 regmap_write(rt5663
->regmap
, RT5663_ANA_BIAS_CUR_1
, 0x1111);
3126 regmap_write(rt5663
->regmap
, RT5663_BIAS_CUR_8
, 0x4402);
3127 regmap_write(rt5663
->regmap
, RT5663_CHARGE_PUMP_2
, 0x3311);
3128 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_1
, 0x0069);
3129 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_3
, 0x06ce);
3130 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_1_1
, 0x6800);
3131 regmap_write(rt5663
->regmap
, RT5663_CHARGE_PUMP_2
, 0x1100);
3132 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_7
, 0x0057);
3133 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_1_1
, 0xe800);
3137 regmap_read(rt5663
->regmap
, RT5663_HP_CALIB_1_1
, &value
);
3139 usleep_range(10000, 10005);
3148 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_1_1
, 0x6200);
3149 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_7
, 0x0059);
3150 regmap_write(rt5663
->regmap
, RT5663_HP_CALIB_1_1
, 0xe200);
3154 regmap_read(rt5663
->regmap
, RT5663_HP_CALIB_1_1
, &value
);
3156 usleep_range(10000, 10005);
3165 regmap_write(rt5663
->regmap
, RT5663_EM_JACK_TYPE_1
, 0xb8e0);
3166 usleep_range(10000, 10005);
3167 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_1
, 0x003b);
3168 usleep_range(10000, 10005);
3169 regmap_write(rt5663
->regmap
, RT5663_PWR_DIG_1
, 0x0000);
3170 usleep_range(10000, 10005);
3171 regmap_write(rt5663
->regmap
, RT5663_DEPOP_1
, 0x000b);
3172 usleep_range(10000, 10005);
3173 regmap_write(rt5663
->regmap
, RT5663_DEPOP_1
, 0x0008);
3174 usleep_range(10000, 10005);
3175 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_2
, 0x0000);
3176 usleep_range(10000, 10005);
3179 static int rt5663_parse_dp(struct rt5663_priv
*rt5663
, struct device
*dev
)
3181 device_property_read_u32(dev
, "realtek,dc_offset_l_manual",
3182 &rt5663
->pdata
.dc_offset_l_manual
);
3183 device_property_read_u32(dev
, "realtek,dc_offset_r_manual",
3184 &rt5663
->pdata
.dc_offset_r_manual
);
3185 device_property_read_u32(dev
, "realtek,dc_offset_l_manual_mic",
3186 &rt5663
->pdata
.dc_offset_l_manual_mic
);
3187 device_property_read_u32(dev
, "realtek,dc_offset_r_manual_mic",
3188 &rt5663
->pdata
.dc_offset_r_manual_mic
);
3193 static int rt5663_i2c_probe(struct i2c_client
*i2c
,
3194 const struct i2c_device_id
*id
)
3196 struct rt5663_platform_data
*pdata
= dev_get_platdata(&i2c
->dev
);
3197 struct rt5663_priv
*rt5663
;
3200 struct regmap
*regmap
;
3202 rt5663
= devm_kzalloc(&i2c
->dev
, sizeof(struct rt5663_priv
),
3208 i2c_set_clientdata(i2c
, rt5663
);
3211 rt5663
->pdata
= *pdata
;
3213 rt5663_parse_dp(rt5663
, &i2c
->dev
);
3215 regmap
= devm_regmap_init_i2c(i2c
, &temp_regmap
);
3216 if (IS_ERR(regmap
)) {
3217 ret
= PTR_ERR(regmap
);
3218 dev_err(&i2c
->dev
, "Failed to allocate temp register map: %d\n",
3222 regmap_read(regmap
, RT5663_VENDOR_ID_2
, &val
);
3224 case RT5663_DEVICE_ID_2
:
3225 rt5663
->regmap
= devm_regmap_init_i2c(i2c
, &rt5663_v2_regmap
);
3226 rt5663
->codec_ver
= CODEC_VER_1
;
3228 case RT5663_DEVICE_ID_1
:
3229 rt5663
->regmap
= devm_regmap_init_i2c(i2c
, &rt5663_regmap
);
3230 rt5663
->codec_ver
= CODEC_VER_0
;
3234 "Device with ID register %#x is not rt5663\n",
3239 if (IS_ERR(rt5663
->regmap
)) {
3240 ret
= PTR_ERR(rt5663
->regmap
);
3241 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
3246 /* reset and calibrate */
3247 regmap_write(rt5663
->regmap
, RT5663_RESET
, 0);
3248 regcache_cache_bypass(rt5663
->regmap
, true);
3249 switch (rt5663
->codec_ver
) {
3251 rt5663_v2_calibrate(rt5663
);
3254 rt5663_calibrate(rt5663
);
3257 dev_err(&i2c
->dev
, "%s:Unknown codec type\n", __func__
);
3259 regcache_cache_bypass(rt5663
->regmap
, false);
3260 regmap_write(rt5663
->regmap
, RT5663_RESET
, 0);
3261 dev_dbg(&i2c
->dev
, "calibrate done\n");
3263 switch (rt5663
->codec_ver
) {
3267 ret
= regmap_register_patch(rt5663
->regmap
, rt5663_patch_list
,
3268 ARRAY_SIZE(rt5663_patch_list
));
3271 "Failed to apply regmap patch: %d\n", ret
);
3274 dev_err(&i2c
->dev
, "%s:Unknown codec type\n", __func__
);
3278 regmap_update_bits(rt5663
->regmap
, RT5663_GPIO_1
, RT5663_GP1_PIN_MASK
,
3279 RT5663_GP1_PIN_IRQ
);
3280 /* 4btn inline command debounce */
3281 regmap_update_bits(rt5663
->regmap
, RT5663_IL_CMD_5
,
3282 RT5663_4BTN_CLK_DEB_MASK
, RT5663_4BTN_CLK_DEB_65MS
);
3284 switch (rt5663
->codec_ver
) {
3286 regmap_write(rt5663
->regmap
, RT5663_BIAS_CUR_8
, 0xa402);
3288 regmap_update_bits(rt5663
->regmap
, RT5663_AUTO_1MRC_CLK
,
3289 RT5663_IRQ_POW_SAV_MASK
| RT5663_IRQ_POW_SAV_JD1_MASK
,
3290 RT5663_IRQ_POW_SAV_EN
| RT5663_IRQ_POW_SAV_JD1_EN
);
3291 regmap_update_bits(rt5663
->regmap
, RT5663_PWR_ANLG_2
,
3292 RT5663_PWR_JD1_MASK
, RT5663_PWR_JD1
);
3293 regmap_update_bits(rt5663
->regmap
, RT5663_IRQ_1
,
3294 RT5663_EN_CB_JD_MASK
, RT5663_EN_CB_JD_EN
);
3296 regmap_update_bits(rt5663
->regmap
, RT5663_HP_LOGIC_2
,
3297 RT5663_HP_SIG_SRC1_MASK
, RT5663_HP_SIG_SRC1_REG
);
3298 regmap_update_bits(rt5663
->regmap
, RT5663_RECMIX
,
3299 RT5663_VREF_BIAS_MASK
| RT5663_CBJ_DET_MASK
|
3300 RT5663_DET_TYPE_MASK
, RT5663_VREF_BIAS_REG
|
3301 RT5663_CBJ_DET_EN
| RT5663_DET_TYPE_QFN
);
3302 /* Set GPIO4 and GPIO8 as input for combo jack */
3303 regmap_update_bits(rt5663
->regmap
, RT5663_GPIO_2
,
3304 RT5663_GP4_PIN_CONF_MASK
, RT5663_GP4_PIN_CONF_INPUT
);
3305 regmap_update_bits(rt5663
->regmap
, RT5663_GPIO_3
,
3306 RT5663_GP8_PIN_CONF_MASK
, RT5663_GP8_PIN_CONF_INPUT
);
3307 regmap_update_bits(rt5663
->regmap
, RT5663_PWR_ANLG_1
,
3308 RT5663_LDO1_DVO_MASK
| RT5663_AMP_HP_MASK
,
3309 RT5663_LDO1_DVO_0_9V
| RT5663_AMP_HP_3X
);
3312 regmap_update_bits(rt5663
->regmap
, RT5663_DIG_MISC
,
3313 RT5663_DIG_GATE_CTRL_MASK
, RT5663_DIG_GATE_CTRL_EN
);
3314 regmap_update_bits(rt5663
->regmap
, RT5663_AUTO_1MRC_CLK
,
3315 RT5663_IRQ_MANUAL_MASK
, RT5663_IRQ_MANUAL_EN
);
3316 regmap_update_bits(rt5663
->regmap
, RT5663_IRQ_1
,
3317 RT5663_EN_IRQ_JD1_MASK
, RT5663_EN_IRQ_JD1_EN
);
3318 regmap_update_bits(rt5663
->regmap
, RT5663_GPIO_1
,
3319 RT5663_GPIO1_TYPE_MASK
, RT5663_GPIO1_TYPE_EN
);
3320 regmap_write(rt5663
->regmap
, RT5663_VREF_RECMIX
, 0x0032);
3321 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_1
, 0xa2be);
3323 regmap_write(rt5663
->regmap
, RT5663_PWR_ANLG_1
, 0xf2be);
3324 regmap_update_bits(rt5663
->regmap
, RT5663_GPIO_2
,
3325 RT5663_GP1_PIN_CONF_MASK
| RT5663_SEL_GPIO1_MASK
,
3326 RT5663_GP1_PIN_CONF_OUTPUT
| RT5663_SEL_GPIO1_EN
);
3327 /* DACREF LDO control */
3328 regmap_update_bits(rt5663
->regmap
, RT5663_DACREF_LDO
, 0x3e0e,
3330 regmap_update_bits(rt5663
->regmap
, RT5663_RECMIX
,
3331 RT5663_RECMIX1_BST1_MASK
, RT5663_RECMIX1_BST1_ON
);
3332 regmap_update_bits(rt5663
->regmap
, RT5663_TDM_2
,
3333 RT5663_DATA_SWAP_ADCDAT1_MASK
,
3334 RT5663_DATA_SWAP_ADCDAT1_LL
);
3337 dev_err(&i2c
->dev
, "%s:Unknown codec type\n", __func__
);
3340 INIT_DELAYED_WORK(&rt5663
->jack_detect_work
, rt5663_jack_detect_work
);
3343 ret
= request_irq(i2c
->irq
, rt5663_irq
,
3344 IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
3345 | IRQF_ONESHOT
, "rt5663", rt5663
);
3347 dev_err(&i2c
->dev
, "%s Failed to reguest IRQ: %d\n",
3351 ret
= snd_soc_register_codec(&i2c
->dev
, &soc_codec_dev_rt5663
,
3352 rt5663_dai
, ARRAY_SIZE(rt5663_dai
));
3356 free_irq(i2c
->irq
, rt5663
);
3362 static int rt5663_i2c_remove(struct i2c_client
*i2c
)
3364 struct rt5663_priv
*rt5663
= i2c_get_clientdata(i2c
);
3367 free_irq(i2c
->irq
, rt5663
);
3369 snd_soc_unregister_codec(&i2c
->dev
);
3374 static void rt5663_i2c_shutdown(struct i2c_client
*client
)
3376 struct rt5663_priv
*rt5663
= i2c_get_clientdata(client
);
3378 regmap_write(rt5663
->regmap
, RT5663_RESET
, 0);
3381 static struct i2c_driver rt5663_i2c_driver
= {
3384 .acpi_match_table
= ACPI_PTR(rt5663_acpi_match
),
3385 .of_match_table
= of_match_ptr(rt5663_of_match
),
3387 .probe
= rt5663_i2c_probe
,
3388 .remove
= rt5663_i2c_remove
,
3389 .shutdown
= rt5663_i2c_shutdown
,
3390 .id_table
= rt5663_i2c_id
,
3392 module_i2c_driver(rt5663_i2c_driver
);
3394 MODULE_DESCRIPTION("ASoC RT5663 driver");
3395 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3396 MODULE_LICENSE("GPL v2");