sound/soc/codecs/rt5665.c

   1 /*
   2  * rt5665.c  --  RT5665/RT5658 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2016 Realtek Semiconductor Corp.
   5  * Author: Bard Liao <bardliao@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/pm.h>
  17 #include <linux/i2c.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/acpi.h>
  21 #include <linux/gpio.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/mutex.h>
  25 #include <sound/core.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/jack.h>
  29 #include <sound/soc.h>
  30 #include <sound/soc-dapm.h>
  31 #include <sound/initval.h>
  32 #include <sound/tlv.h>
  33 #include <sound/rt5665.h>
  34
  35 #include "rl6231.h"
  36 #include "rt5665.h"
  37
  38 #define RT5665_NUM_SUPPLIES 3
  39
  40 static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
  41         "AVDD",
  42         "MICVDD",
  43         "VBAT",
  44 };
  45
  46 struct rt5665_priv {
  47         struct snd_soc_codec *codec;
  48         struct rt5665_platform_data pdata;
  49         struct regmap *regmap;
  50         struct gpio_desc *gpiod_ldo1_en;
  51         struct gpio_desc *gpiod_reset;
  52         struct snd_soc_jack *hs_jack;
  53         struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
  54         struct delayed_work jack_detect_work;
  55         struct delayed_work calibrate_work;
  56         struct delayed_work jd_check_work;
  57         struct mutex calibrate_mutex;
  58
  59         int sysclk;
  60         int sysclk_src;
  61         int lrck[RT5665_AIFS];
  62         int bclk[RT5665_AIFS];
  63         int master[RT5665_AIFS];
  64         int id;
  65
  66         int pll_src;
  67         int pll_in;
  68         int pll_out;
  69
  70         int jack_type;
  71         int irq_work_delay_time;
  72         unsigned int sar_adc_value;
  73         bool calibration_done;
  74 };
  75
  76 static const struct reg_default rt5665_reg[] = {
  77         {0x0000, 0x0000},
  78         {0x0001, 0xc8c8},
  79         {0x0002, 0x8080},
  80         {0x0003, 0x8000},
  81         {0x0004, 0xc80a},
  82         {0x0005, 0x0000},
  83         {0x0006, 0x0000},
  84         {0x0007, 0x0000},
  85         {0x000a, 0x0000},
  86         {0x000b, 0x0000},
  87         {0x000c, 0x0000},
  88         {0x000d, 0x0000},
  89         {0x000f, 0x0808},
  90         {0x0010, 0x4040},
  91         {0x0011, 0x0000},
  92         {0x0012, 0x1404},
  93         {0x0013, 0x1000},
  94         {0x0014, 0xa00a},
  95         {0x0015, 0x0404},
  96         {0x0016, 0x0404},
  97         {0x0017, 0x0011},
  98         {0x0018, 0xafaf},
  99         {0x0019, 0xafaf},
 100         {0x001a, 0xafaf},
 101         {0x001b, 0x0011},
 102         {0x001c, 0x2f2f},
 103         {0x001d, 0x2f2f},
 104         {0x001e, 0x2f2f},
 105         {0x001f, 0x0000},
 106         {0x0020, 0x0000},
 107         {0x0021, 0x0000},
 108         {0x0022, 0x5757},
 109         {0x0023, 0x0039},
 110         {0x0026, 0xc0c0},
 111         {0x0027, 0xc0c0},
 112         {0x0028, 0xc0c0},
 113         {0x0029, 0x8080},
 114         {0x002a, 0xaaaa},
 115         {0x002b, 0xaaaa},
 116         {0x002c, 0xaba8},
 117         {0x002d, 0x0000},
 118         {0x002e, 0x0000},
 119         {0x002f, 0x0000},
 120         {0x0030, 0x0000},
 121         {0x0031, 0x5000},
 122         {0x0032, 0x0000},
 123         {0x0033, 0x0000},
 124         {0x0034, 0x0000},
 125         {0x0035, 0x0000},
 126         {0x003a, 0x0000},
 127         {0x003b, 0x0000},
 128         {0x003c, 0x00ff},
 129         {0x003d, 0x0000},
 130         {0x003e, 0x00ff},
 131         {0x003f, 0x0000},
 132         {0x0040, 0x0000},
 133         {0x0041, 0x00ff},
 134         {0x0042, 0x0000},
 135         {0x0043, 0x00ff},
 136         {0x0044, 0x0c0c},
 137         {0x0049, 0xc00b},
 138         {0x004a, 0x0000},
 139         {0x004b, 0x031f},
 140         {0x004d, 0x0000},
 141         {0x004e, 0x001f},
 142         {0x004f, 0x0000},
 143         {0x0050, 0x001f},
 144         {0x0052, 0xf000},
 145         {0x0061, 0x0000},
 146         {0x0062, 0x0000},
 147         {0x0063, 0x003e},
 148         {0x0064, 0x0000},
 149         {0x0065, 0x0000},
 150         {0x0066, 0x003f},
 151         {0x0067, 0x0000},
 152         {0x006b, 0x0000},
 153         {0x006d, 0xff00},
 154         {0x006e, 0x2808},
 155         {0x006f, 0x000a},
 156         {0x0070, 0x8000},
 157         {0x0071, 0x8000},
 158         {0x0072, 0x8000},
 159         {0x0073, 0x7000},
 160         {0x0074, 0x7770},
 161         {0x0075, 0x0002},
 162         {0x0076, 0x0001},
 163         {0x0078, 0x00f0},
 164         {0x0079, 0x0000},
 165         {0x007a, 0x0000},
 166         {0x007b, 0x0000},
 167         {0x007c, 0x0000},
 168         {0x007d, 0x0123},
 169         {0x007e, 0x4500},
 170         {0x007f, 0x8003},
 171         {0x0080, 0x0000},
 172         {0x0081, 0x0000},
 173         {0x0082, 0x0000},
 174         {0x0083, 0x0000},
 175         {0x0084, 0x0000},
 176         {0x0085, 0x0000},
 177         {0x0086, 0x0008},
 178         {0x0087, 0x0000},
 179         {0x0088, 0x0000},
 180         {0x0089, 0x0000},
 181         {0x008a, 0x0000},
 182         {0x008b, 0x0000},
 183         {0x008c, 0x0003},
 184         {0x008e, 0x0060},
 185         {0x008f, 0x1000},
 186         {0x0091, 0x0c26},
 187         {0x0092, 0x0073},
 188         {0x0093, 0x0000},
 189         {0x0094, 0x0080},
 190         {0x0098, 0x0000},
 191         {0x0099, 0x0000},
 192         {0x009a, 0x0007},
 193         {0x009f, 0x0000},
 194         {0x00a0, 0x0000},
 195         {0x00a1, 0x0002},
 196         {0x00a2, 0x0001},
 197         {0x00a3, 0x0002},
 198         {0x00a4, 0x0001},
 199         {0x00ae, 0x2040},
 200         {0x00af, 0x0000},
 201         {0x00b6, 0x0000},
 202         {0x00b7, 0x0000},
 203         {0x00b8, 0x0000},
 204         {0x00b9, 0x0000},
 205         {0x00ba, 0x0002},
 206         {0x00bb, 0x0000},
 207         {0x00be, 0x0000},
 208         {0x00c0, 0x0000},
 209         {0x00c1, 0x0aaa},
 210         {0x00c2, 0xaa80},
 211         {0x00c3, 0x0003},
 212         {0x00c4, 0x0000},
 213         {0x00d0, 0x0000},
 214         {0x00d1, 0x2244},
 215         {0x00d3, 0x3300},
 216         {0x00d4, 0x2200},
 217         {0x00d9, 0x0809},
 218         {0x00da, 0x0000},
 219         {0x00db, 0x0008},
 220         {0x00dc, 0x00c0},
 221         {0x00dd, 0x6724},
 222         {0x00de, 0x3131},
 223         {0x00df, 0x0008},
 224         {0x00e0, 0x4000},
 225         {0x00e1, 0x3131},
 226         {0x00e2, 0x600c},
 227         {0x00ea, 0xb320},
 228         {0x00eb, 0x0000},
 229         {0x00ec, 0xb300},
 230         {0x00ed, 0x0000},
 231         {0x00ee, 0xb320},
 232         {0x00ef, 0x0000},
 233         {0x00f0, 0x0201},
 234         {0x00f1, 0x0ddd},
 235         {0x00f2, 0x0ddd},
 236         {0x00f6, 0x0000},
 237         {0x00f7, 0x0000},
 238         {0x00f8, 0x0000},
 239         {0x00fa, 0x0000},
 240         {0x00fb, 0x0000},
 241         {0x00fc, 0x0000},
 242         {0x00fd, 0x0000},
 243         {0x00fe, 0x10ec},
 244         {0x00ff, 0x6451},
 245         {0x0100, 0xaaaa},
 246         {0x0101, 0x000a},
 247         {0x010a, 0xaaaa},
 248         {0x010b, 0xa0a0},
 249         {0x010c, 0xaeae},
 250         {0x010d, 0xaaaa},
 251         {0x010e, 0xaaaa},
 252         {0x010f, 0xaaaa},
 253         {0x0110, 0xe002},
 254         {0x0111, 0xa402},
 255         {0x0112, 0xaaaa},
 256         {0x0113, 0x2000},
 257         {0x0117, 0x0f00},
 258         {0x0125, 0x0410},
 259         {0x0132, 0x0000},
 260         {0x0133, 0x0000},
 261         {0x0137, 0x5540},
 262         {0x0138, 0x3700},
 263         {0x0139, 0x79a1},
 264         {0x013a, 0x2020},
 265         {0x013b, 0x2020},
 266         {0x013c, 0x2005},
 267         {0x013f, 0x0000},
 268         {0x0145, 0x0002},
 269         {0x0146, 0x0000},
 270         {0x0147, 0x0000},
 271         {0x0148, 0x0000},
 272         {0x0150, 0x0000},
 273         {0x0160, 0x4eff},
 274         {0x0161, 0x0080},
 275         {0x0162, 0x0200},
 276         {0x0163, 0x0800},
 277         {0x0164, 0x0000},
 278         {0x0165, 0x0000},
 279         {0x0166, 0x0000},
 280         {0x0167, 0x000f},
 281         {0x0170, 0x4e87},
 282         {0x0171, 0x0080},
 283         {0x0172, 0x0200},
 284         {0x0173, 0x0800},
 285         {0x0174, 0x00ff},
 286         {0x0175, 0x0000},
 287         {0x0190, 0x413d},
 288         {0x0191, 0x4139},
 289         {0x0192, 0x4135},
 290         {0x0193, 0x413d},
 291         {0x0194, 0x0000},
 292         {0x0195, 0x0000},
 293         {0x0196, 0x0000},
 294         {0x0197, 0x0000},
 295         {0x0198, 0x0000},
 296         {0x0199, 0x0000},
 297         {0x01a0, 0x1e64},
 298         {0x01a1, 0x06a3},
 299         {0x01a2, 0x0000},
 300         {0x01a3, 0x0000},
 301         {0x01a4, 0x0000},
 302         {0x01a5, 0x0000},
 303         {0x01a6, 0x0000},
 304         {0x01a7, 0x8000},
 305         {0x01a8, 0x0000},
 306         {0x01a9, 0x0000},
 307         {0x01aa, 0x0000},
 308         {0x01ab, 0x0000},
 309         {0x01b5, 0x0000},
 310         {0x01b6, 0x01c3},
 311         {0x01b7, 0x02a0},
 312         {0x01b8, 0x03e9},
 313         {0x01b9, 0x1389},
 314         {0x01ba, 0xc351},
 315         {0x01bb, 0x0009},
 316         {0x01bc, 0x0018},
 317         {0x01bd, 0x002a},
 318         {0x01be, 0x004c},
 319         {0x01bf, 0x0097},
 320         {0x01c0, 0x433d},
 321         {0x01c1, 0x0000},
 322         {0x01c2, 0x0000},
 323         {0x01c3, 0x0000},
 324         {0x01c4, 0x0000},
 325         {0x01c5, 0x0000},
 326         {0x01c6, 0x0000},
 327         {0x01c7, 0x0000},
 328         {0x01c8, 0x40af},
 329         {0x01c9, 0x0702},
 330         {0x01ca, 0x0000},
 331         {0x01cb, 0x0000},
 332         {0x01cc, 0x5757},
 333         {0x01cd, 0x5757},
 334         {0x01ce, 0x5757},
 335         {0x01cf, 0x5757},
 336         {0x01d0, 0x5757},
 337         {0x01d1, 0x5757},
 338         {0x01d2, 0x5757},
 339         {0x01d3, 0x5757},
 340         {0x01d4, 0x5757},
 341         {0x01d5, 0x5757},
 342         {0x01d6, 0x003c},
 343         {0x01da, 0x0000},
 344         {0x01db, 0x0000},
 345         {0x01dc, 0x0000},
 346         {0x01de, 0x7c00},
 347         {0x01df, 0x0320},
 348         {0x01e0, 0x06a1},
 349         {0x01e1, 0x0000},
 350         {0x01e2, 0x0000},
 351         {0x01e3, 0x0000},
 352         {0x01e4, 0x0000},
 353         {0x01e6, 0x0001},
 354         {0x01e7, 0x0000},
 355         {0x01e8, 0x0000},
 356         {0x01ea, 0xbf3f},
 357         {0x01eb, 0x0000},
 358         {0x01ec, 0x0000},
 359         {0x01ed, 0x0000},
 360         {0x01ee, 0x0000},
 361         {0x01ef, 0x0000},
 362         {0x01f0, 0x0000},
 363         {0x01f1, 0x0000},
 364         {0x01f2, 0x0000},
 365         {0x01f3, 0x0000},
 366         {0x01f4, 0x0000},
 367         {0x0200, 0x0000},
 368         {0x0201, 0x0000},
 369         {0x0202, 0x0000},
 370         {0x0203, 0x0000},
 371         {0x0204, 0x0000},
 372         {0x0205, 0x0000},
 373         {0x0206, 0x0000},
 374         {0x0207, 0x0000},
 375         {0x0208, 0x0000},
 376         {0x0210, 0x60b1},
 377         {0x0211, 0xa005},
 378         {0x0212, 0x024c},
 379         {0x0213, 0xf7ff},
 380         {0x0214, 0x024c},
 381         {0x0215, 0x0102},
 382         {0x0216, 0x00a3},
 383         {0x0217, 0x0048},
 384         {0x0218, 0xa2c0},
 385         {0x0219, 0x0400},
 386         {0x021a, 0x00c8},
 387         {0x021b, 0x00c0},
 388         {0x02ff, 0x0110},
 389         {0x0300, 0x001f},
 390         {0x0301, 0x032c},
 391         {0x0302, 0x5f21},
 392         {0x0303, 0x4000},
 393         {0x0304, 0x4000},
 394         {0x0305, 0x06d5},
 395         {0x0306, 0x8000},
 396         {0x0307, 0x0700},
 397         {0x0310, 0x4560},
 398         {0x0311, 0xa4a8},
 399         {0x0312, 0x7418},
 400         {0x0313, 0x0000},
 401         {0x0314, 0x0006},
 402         {0x0315, 0xffff},
 403         {0x0316, 0xc400},
 404         {0x0317, 0x0000},
 405         {0x0330, 0x00a6},
 406         {0x0331, 0x04c3},
 407         {0x0332, 0x27c8},
 408         {0x0333, 0xbf50},
 409         {0x0334, 0x0045},
 410         {0x0335, 0x0007},
 411         {0x0336, 0x7418},
 412         {0x0337, 0x0501},
 413         {0x0338, 0x0000},
 414         {0x0339, 0x0010},
 415         {0x033a, 0x1010},
 416         {0x03c0, 0x7e00},
 417         {0x03c1, 0x8000},
 418         {0x03c2, 0x8000},
 419         {0x03c3, 0x8000},
 420         {0x03c4, 0x8000},
 421         {0x03c5, 0x8000},
 422         {0x03c6, 0x8000},
 423         {0x03c7, 0x8000},
 424         {0x03c8, 0x8000},
 425         {0x03c9, 0x8000},
 426         {0x03ca, 0x8000},
 427         {0x03cb, 0x8000},
 428         {0x03cc, 0x8000},
 429         {0x03d0, 0x0000},
 430         {0x03d1, 0x0000},
 431         {0x03d2, 0x0000},
 432         {0x03d3, 0x0000},
 433         {0x03d4, 0x2000},
 434         {0x03d5, 0x2000},
 435         {0x03d6, 0x0000},
 436         {0x03d7, 0x0000},
 437         {0x03d8, 0x2000},
 438         {0x03d9, 0x2000},
 439         {0x03da, 0x2000},
 440         {0x03db, 0x2000},
 441         {0x03dc, 0x0000},
 442         {0x03dd, 0x0000},
 443         {0x03de, 0x0000},
 444         {0x03df, 0x2000},
 445         {0x03e0, 0x0000},
 446         {0x03e1, 0x0000},
 447         {0x03e2, 0x0000},
 448         {0x03e3, 0x0000},
 449         {0x03e4, 0x0000},
 450         {0x03e5, 0x0000},
 451         {0x03e6, 0x0000},
 452         {0x03e7, 0x0000},
 453         {0x03e8, 0x0000},
 454         {0x03e9, 0x0000},
 455         {0x03ea, 0x0000},
 456         {0x03eb, 0x0000},
 457         {0x03ec, 0x0000},
 458         {0x03ed, 0x0000},
 459         {0x03ee, 0x0000},
 460         {0x03ef, 0x0000},
 461         {0x03f0, 0x0800},
 462         {0x03f1, 0x0800},
 463         {0x03f2, 0x0800},
 464         {0x03f3, 0x0800},
 465 };
 466
 467 static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
 468 {
 469         switch (reg) {
 470         case RT5665_RESET:
 471         case RT5665_EJD_CTRL_2:
 472         case RT5665_GPIO_STA:
 473         case RT5665_INT_ST_1:
 474         case RT5665_IL_CMD_1:
 475         case RT5665_4BTN_IL_CMD_1:
 476         case RT5665_PSV_IL_CMD_1:
 477         case RT5665_AJD1_CTRL:
 478         case RT5665_JD_CTRL_3:
 479         case RT5665_STO_NG2_CTRL_1:
 480         case RT5665_SAR_IL_CMD_4:
 481         case RT5665_DEVICE_ID:
 482         case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
 483         case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
 484         case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
 485         case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
 486                 return true;
 487         default:
 488                 return false;
 489         }
 490 }
 491
 492 static bool rt5665_readable_register(struct device *dev, unsigned int reg)
 493 {
 494         switch (reg) {
 495         case RT5665_RESET:
 496         case RT5665_VENDOR_ID:
 497         case RT5665_VENDOR_ID_1:
 498         case RT5665_DEVICE_ID:
 499         case RT5665_LOUT:
 500         case RT5665_HP_CTRL_1:
 501         case RT5665_HP_CTRL_2:
 502         case RT5665_MONO_OUT:
 503         case RT5665_HPL_GAIN:
 504         case RT5665_HPR_GAIN:
 505         case RT5665_MONO_GAIN:
 506         case RT5665_CAL_BST_CTRL:
 507         case RT5665_CBJ_BST_CTRL:
 508         case RT5665_IN1_IN2:
 509         case RT5665_IN3_IN4:
 510         case RT5665_INL1_INR1_VOL:
 511         case RT5665_EJD_CTRL_1:
 512         case RT5665_EJD_CTRL_2:
 513         case RT5665_EJD_CTRL_3:
 514         case RT5665_EJD_CTRL_4:
 515         case RT5665_EJD_CTRL_5:
 516         case RT5665_EJD_CTRL_6:
 517         case RT5665_EJD_CTRL_7:
 518         case RT5665_DAC2_CTRL:
 519         case RT5665_DAC2_DIG_VOL:
 520         case RT5665_DAC1_DIG_VOL:
 521         case RT5665_DAC3_DIG_VOL:
 522         case RT5665_DAC3_CTRL:
 523         case RT5665_STO1_ADC_DIG_VOL:
 524         case RT5665_MONO_ADC_DIG_VOL:
 525         case RT5665_STO2_ADC_DIG_VOL:
 526         case RT5665_STO1_ADC_BOOST:
 527         case RT5665_MONO_ADC_BOOST:
 528         case RT5665_STO2_ADC_BOOST:
 529         case RT5665_HP_IMP_GAIN_1:
 530         case RT5665_HP_IMP_GAIN_2:
 531         case RT5665_STO1_ADC_MIXER:
 532         case RT5665_MONO_ADC_MIXER:
 533         case RT5665_STO2_ADC_MIXER:
 534         case RT5665_AD_DA_MIXER:
 535         case RT5665_STO1_DAC_MIXER:
 536         case RT5665_MONO_DAC_MIXER:
 537         case RT5665_STO2_DAC_MIXER:
 538         case RT5665_A_DAC1_MUX:
 539         case RT5665_A_DAC2_MUX:
 540         case RT5665_DIG_INF2_DATA:
 541         case RT5665_DIG_INF3_DATA:
 542         case RT5665_PDM_OUT_CTRL:
 543         case RT5665_PDM_DATA_CTRL_1:
 544         case RT5665_PDM_DATA_CTRL_2:
 545         case RT5665_PDM_DATA_CTRL_3:
 546         case RT5665_PDM_DATA_CTRL_4:
 547         case RT5665_REC1_GAIN:
 548         case RT5665_REC1_L1_MIXER:
 549         case RT5665_REC1_L2_MIXER:
 550         case RT5665_REC1_R1_MIXER:
 551         case RT5665_REC1_R2_MIXER:
 552         case RT5665_REC2_GAIN:
 553         case RT5665_REC2_L1_MIXER:
 554         case RT5665_REC2_L2_MIXER:
 555         case RT5665_REC2_R1_MIXER:
 556         case RT5665_REC2_R2_MIXER:
 557         case RT5665_CAL_REC:
 558         case RT5665_ALC_BACK_GAIN:
 559         case RT5665_MONOMIX_GAIN:
 560         case RT5665_MONOMIX_IN_GAIN:
 561         case RT5665_OUT_L_GAIN:
 562         case RT5665_OUT_L_MIXER:
 563         case RT5665_OUT_R_GAIN:
 564         case RT5665_OUT_R_MIXER:
 565         case RT5665_LOUT_MIXER:
 566         case RT5665_PWR_DIG_1:
 567         case RT5665_PWR_DIG_2:
 568         case RT5665_PWR_ANLG_1:
 569         case RT5665_PWR_ANLG_2:
 570         case RT5665_PWR_ANLG_3:
 571         case RT5665_PWR_MIXER:
 572         case RT5665_PWR_VOL:
 573         case RT5665_CLK_DET:
 574         case RT5665_HPF_CTRL1:
 575         case RT5665_DMIC_CTRL_1:
 576         case RT5665_DMIC_CTRL_2:
 577         case RT5665_I2S1_SDP:
 578         case RT5665_I2S2_SDP:
 579         case RT5665_I2S3_SDP:
 580         case RT5665_ADDA_CLK_1:
 581         case RT5665_ADDA_CLK_2:
 582         case RT5665_I2S1_F_DIV_CTRL_1:
 583         case RT5665_I2S1_F_DIV_CTRL_2:
 584         case RT5665_TDM_CTRL_1:
 585         case RT5665_TDM_CTRL_2:
 586         case RT5665_TDM_CTRL_3:
 587         case RT5665_TDM_CTRL_4:
 588         case RT5665_TDM_CTRL_5:
 589         case RT5665_TDM_CTRL_6:
 590         case RT5665_TDM_CTRL_7:
 591         case RT5665_TDM_CTRL_8:
 592         case RT5665_GLB_CLK:
 593         case RT5665_PLL_CTRL_1:
 594         case RT5665_PLL_CTRL_2:
 595         case RT5665_ASRC_1:
 596         case RT5665_ASRC_2:
 597         case RT5665_ASRC_3:
 598         case RT5665_ASRC_4:
 599         case RT5665_ASRC_5:
 600         case RT5665_ASRC_6:
 601         case RT5665_ASRC_7:
 602         case RT5665_ASRC_8:
 603         case RT5665_ASRC_9:
 604         case RT5665_ASRC_10:
 605         case RT5665_DEPOP_1:
 606         case RT5665_DEPOP_2:
 607         case RT5665_HP_CHARGE_PUMP_1:
 608         case RT5665_HP_CHARGE_PUMP_2:
 609         case RT5665_MICBIAS_1:
 610         case RT5665_MICBIAS_2:
 611         case RT5665_ASRC_12:
 612         case RT5665_ASRC_13:
 613         case RT5665_ASRC_14:
 614         case RT5665_RC_CLK_CTRL:
 615         case RT5665_I2S_M_CLK_CTRL_1:
 616         case RT5665_I2S2_F_DIV_CTRL_1:
 617         case RT5665_I2S2_F_DIV_CTRL_2:
 618         case RT5665_I2S3_F_DIV_CTRL_1:
 619         case RT5665_I2S3_F_DIV_CTRL_2:
 620         case RT5665_EQ_CTRL_1:
 621         case RT5665_EQ_CTRL_2:
 622         case RT5665_IRQ_CTRL_1:
 623         case RT5665_IRQ_CTRL_2:
 624         case RT5665_IRQ_CTRL_3:
 625         case RT5665_IRQ_CTRL_4:
 626         case RT5665_IRQ_CTRL_5:
 627         case RT5665_IRQ_CTRL_6:
 628         case RT5665_INT_ST_1:
 629         case RT5665_GPIO_CTRL_1:
 630         case RT5665_GPIO_CTRL_2:
 631         case RT5665_GPIO_CTRL_3:
 632         case RT5665_GPIO_CTRL_4:
 633         case RT5665_GPIO_STA:
 634         case RT5665_HP_AMP_DET_CTRL_1:
 635         case RT5665_HP_AMP_DET_CTRL_2:
 636         case RT5665_MID_HP_AMP_DET:
 637         case RT5665_LOW_HP_AMP_DET:
 638         case RT5665_SV_ZCD_1:
 639         case RT5665_SV_ZCD_2:
 640         case RT5665_IL_CMD_1:
 641         case RT5665_IL_CMD_2:
 642         case RT5665_IL_CMD_3:
 643         case RT5665_IL_CMD_4:
 644         case RT5665_4BTN_IL_CMD_1:
 645         case RT5665_4BTN_IL_CMD_2:
 646         case RT5665_4BTN_IL_CMD_3:
 647         case RT5665_PSV_IL_CMD_1:
 648         case RT5665_ADC_STO1_HP_CTRL_1:
 649         case RT5665_ADC_STO1_HP_CTRL_2:
 650         case RT5665_ADC_MONO_HP_CTRL_1:
 651         case RT5665_ADC_MONO_HP_CTRL_2:
 652         case RT5665_ADC_STO2_HP_CTRL_1:
 653         case RT5665_ADC_STO2_HP_CTRL_2:
 654         case RT5665_AJD1_CTRL:
 655         case RT5665_JD1_THD:
 656         case RT5665_JD2_THD:
 657         case RT5665_JD_CTRL_1:
 658         case RT5665_JD_CTRL_2:
 659         case RT5665_JD_CTRL_3:
 660         case RT5665_DIG_MISC:
 661         case RT5665_DUMMY_2:
 662         case RT5665_DUMMY_3:
 663         case RT5665_DAC_ADC_DIG_VOL1:
 664         case RT5665_DAC_ADC_DIG_VOL2:
 665         case RT5665_BIAS_CUR_CTRL_1:
 666         case RT5665_BIAS_CUR_CTRL_2:
 667         case RT5665_BIAS_CUR_CTRL_3:
 668         case RT5665_BIAS_CUR_CTRL_4:
 669         case RT5665_BIAS_CUR_CTRL_5:
 670         case RT5665_BIAS_CUR_CTRL_6:
 671         case RT5665_BIAS_CUR_CTRL_7:
 672         case RT5665_BIAS_CUR_CTRL_8:
 673         case RT5665_BIAS_CUR_CTRL_9:
 674         case RT5665_BIAS_CUR_CTRL_10:
 675         case RT5665_VREF_REC_OP_FB_CAP_CTRL:
 676         case RT5665_CHARGE_PUMP_1:
 677         case RT5665_DIG_IN_CTRL_1:
 678         case RT5665_DIG_IN_CTRL_2:
 679         case RT5665_PAD_DRIVING_CTRL:
 680         case RT5665_SOFT_RAMP_DEPOP:
 681         case RT5665_PLL:
 682         case RT5665_CHOP_DAC:
 683         case RT5665_CHOP_ADC:
 684         case RT5665_CALIB_ADC_CTRL:
 685         case RT5665_VOL_TEST:
 686         case RT5665_TEST_MODE_CTRL_1:
 687         case RT5665_TEST_MODE_CTRL_2:
 688         case RT5665_TEST_MODE_CTRL_3:
 689         case RT5665_TEST_MODE_CTRL_4:
 690         case RT5665_BASSBACK_CTRL:
 691         case RT5665_STO_NG2_CTRL_1:
 692         case RT5665_STO_NG2_CTRL_2:
 693         case RT5665_STO_NG2_CTRL_3:
 694         case RT5665_STO_NG2_CTRL_4:
 695         case RT5665_STO_NG2_CTRL_5:
 696         case RT5665_STO_NG2_CTRL_6:
 697         case RT5665_STO_NG2_CTRL_7:
 698         case RT5665_STO_NG2_CTRL_8:
 699         case RT5665_MONO_NG2_CTRL_1:
 700         case RT5665_MONO_NG2_CTRL_2:
 701         case RT5665_MONO_NG2_CTRL_3:
 702         case RT5665_MONO_NG2_CTRL_4:
 703         case RT5665_MONO_NG2_CTRL_5:
 704         case RT5665_MONO_NG2_CTRL_6:
 705         case RT5665_STO1_DAC_SIL_DET:
 706         case RT5665_MONOL_DAC_SIL_DET:
 707         case RT5665_MONOR_DAC_SIL_DET:
 708         case RT5665_STO2_DAC_SIL_DET:
 709         case RT5665_SIL_PSV_CTRL1:
 710         case RT5665_SIL_PSV_CTRL2:
 711         case RT5665_SIL_PSV_CTRL3:
 712         case RT5665_SIL_PSV_CTRL4:
 713         case RT5665_SIL_PSV_CTRL5:
 714         case RT5665_SIL_PSV_CTRL6:
 715         case RT5665_MONO_AMP_CALIB_CTRL_1:
 716         case RT5665_MONO_AMP_CALIB_CTRL_2:
 717         case RT5665_MONO_AMP_CALIB_CTRL_3:
 718         case RT5665_MONO_AMP_CALIB_CTRL_4:
 719         case RT5665_MONO_AMP_CALIB_CTRL_5:
 720         case RT5665_MONO_AMP_CALIB_CTRL_6:
 721         case RT5665_MONO_AMP_CALIB_CTRL_7:
 722         case RT5665_MONO_AMP_CALIB_STA1:
 723         case RT5665_MONO_AMP_CALIB_STA2:
 724         case RT5665_MONO_AMP_CALIB_STA3:
 725         case RT5665_MONO_AMP_CALIB_STA4:
 726         case RT5665_MONO_AMP_CALIB_STA6:
 727         case RT5665_HP_IMP_SENS_CTRL_01:
 728         case RT5665_HP_IMP_SENS_CTRL_02:
 729         case RT5665_HP_IMP_SENS_CTRL_03:
 730         case RT5665_HP_IMP_SENS_CTRL_04:
 731         case RT5665_HP_IMP_SENS_CTRL_05:
 732         case RT5665_HP_IMP_SENS_CTRL_06:
 733         case RT5665_HP_IMP_SENS_CTRL_07:
 734         case RT5665_HP_IMP_SENS_CTRL_08:
 735         case RT5665_HP_IMP_SENS_CTRL_09:
 736         case RT5665_HP_IMP_SENS_CTRL_10:
 737         case RT5665_HP_IMP_SENS_CTRL_11:
 738         case RT5665_HP_IMP_SENS_CTRL_12:
 739         case RT5665_HP_IMP_SENS_CTRL_13:
 740         case RT5665_HP_IMP_SENS_CTRL_14:
 741         case RT5665_HP_IMP_SENS_CTRL_15:
 742         case RT5665_HP_IMP_SENS_CTRL_16:
 743         case RT5665_HP_IMP_SENS_CTRL_17:
 744         case RT5665_HP_IMP_SENS_CTRL_18:
 745         case RT5665_HP_IMP_SENS_CTRL_19:
 746         case RT5665_HP_IMP_SENS_CTRL_20:
 747         case RT5665_HP_IMP_SENS_CTRL_21:
 748         case RT5665_HP_IMP_SENS_CTRL_22:
 749         case RT5665_HP_IMP_SENS_CTRL_23:
 750         case RT5665_HP_IMP_SENS_CTRL_24:
 751         case RT5665_HP_IMP_SENS_CTRL_25:
 752         case RT5665_HP_IMP_SENS_CTRL_26:
 753         case RT5665_HP_IMP_SENS_CTRL_27:
 754         case RT5665_HP_IMP_SENS_CTRL_28:
 755         case RT5665_HP_IMP_SENS_CTRL_29:
 756         case RT5665_HP_IMP_SENS_CTRL_30:
 757         case RT5665_HP_IMP_SENS_CTRL_31:
 758         case RT5665_HP_IMP_SENS_CTRL_32:
 759         case RT5665_HP_IMP_SENS_CTRL_33:
 760         case RT5665_HP_IMP_SENS_CTRL_34:
 761         case RT5665_HP_LOGIC_CTRL_1:
 762         case RT5665_HP_LOGIC_CTRL_2:
 763         case RT5665_HP_LOGIC_CTRL_3:
 764         case RT5665_HP_CALIB_CTRL_1:
 765         case RT5665_HP_CALIB_CTRL_2:
 766         case RT5665_HP_CALIB_CTRL_3:
 767         case RT5665_HP_CALIB_CTRL_4:
 768         case RT5665_HP_CALIB_CTRL_5:
 769         case RT5665_HP_CALIB_CTRL_6:
 770         case RT5665_HP_CALIB_CTRL_7:
 771         case RT5665_HP_CALIB_CTRL_9:
 772         case RT5665_HP_CALIB_CTRL_10:
 773         case RT5665_HP_CALIB_CTRL_11:
 774         case RT5665_HP_CALIB_STA_1:
 775         case RT5665_HP_CALIB_STA_2:
 776         case RT5665_HP_CALIB_STA_3:
 777         case RT5665_HP_CALIB_STA_4:
 778         case RT5665_HP_CALIB_STA_5:
 779         case RT5665_HP_CALIB_STA_6:
 780         case RT5665_HP_CALIB_STA_7:
 781         case RT5665_HP_CALIB_STA_8:
 782         case RT5665_HP_CALIB_STA_9:
 783         case RT5665_HP_CALIB_STA_10:
 784         case RT5665_HP_CALIB_STA_11:
 785         case RT5665_PGM_TAB_CTRL1:
 786         case RT5665_PGM_TAB_CTRL2:
 787         case RT5665_PGM_TAB_CTRL3:
 788         case RT5665_PGM_TAB_CTRL4:
 789         case RT5665_PGM_TAB_CTRL5:
 790         case RT5665_PGM_TAB_CTRL6:
 791         case RT5665_PGM_TAB_CTRL7:
 792         case RT5665_PGM_TAB_CTRL8:
 793         case RT5665_PGM_TAB_CTRL9:
 794         case RT5665_SAR_IL_CMD_1:
 795         case RT5665_SAR_IL_CMD_2:
 796         case RT5665_SAR_IL_CMD_3:
 797         case RT5665_SAR_IL_CMD_4:
 798         case RT5665_SAR_IL_CMD_5:
 799         case RT5665_SAR_IL_CMD_6:
 800         case RT5665_SAR_IL_CMD_7:
 801         case RT5665_SAR_IL_CMD_8:
 802         case RT5665_SAR_IL_CMD_9:
 803         case RT5665_SAR_IL_CMD_10:
 804         case RT5665_SAR_IL_CMD_11:
 805         case RT5665_SAR_IL_CMD_12:
 806         case RT5665_DRC1_CTRL_0:
 807         case RT5665_DRC1_CTRL_1:
 808         case RT5665_DRC1_CTRL_2:
 809         case RT5665_DRC1_CTRL_3:
 810         case RT5665_DRC1_CTRL_4:
 811         case RT5665_DRC1_CTRL_5:
 812         case RT5665_DRC1_CTRL_6:
 813         case RT5665_DRC1_HARD_LMT_CTRL_1:
 814         case RT5665_DRC1_HARD_LMT_CTRL_2:
 815         case RT5665_DRC1_PRIV_1:
 816         case RT5665_DRC1_PRIV_2:
 817         case RT5665_DRC1_PRIV_3:
 818         case RT5665_DRC1_PRIV_4:
 819         case RT5665_DRC1_PRIV_5:
 820         case RT5665_DRC1_PRIV_6:
 821         case RT5665_DRC1_PRIV_7:
 822         case RT5665_DRC1_PRIV_8:
 823         case RT5665_ALC_PGA_CTRL_1:
 824         case RT5665_ALC_PGA_CTRL_2:
 825         case RT5665_ALC_PGA_CTRL_3:
 826         case RT5665_ALC_PGA_CTRL_4:
 827         case RT5665_ALC_PGA_CTRL_5:
 828         case RT5665_ALC_PGA_CTRL_6:
 829         case RT5665_ALC_PGA_CTRL_7:
 830         case RT5665_ALC_PGA_CTRL_8:
 831         case RT5665_ALC_PGA_STA_1:
 832         case RT5665_ALC_PGA_STA_2:
 833         case RT5665_ALC_PGA_STA_3:
 834         case RT5665_EQ_AUTO_RCV_CTRL1:
 835         case RT5665_EQ_AUTO_RCV_CTRL2:
 836         case RT5665_EQ_AUTO_RCV_CTRL3:
 837         case RT5665_EQ_AUTO_RCV_CTRL4:
 838         case RT5665_EQ_AUTO_RCV_CTRL5:
 839         case RT5665_EQ_AUTO_RCV_CTRL6:
 840         case RT5665_EQ_AUTO_RCV_CTRL7:
 841         case RT5665_EQ_AUTO_RCV_CTRL8:
 842         case RT5665_EQ_AUTO_RCV_CTRL9:
 843         case RT5665_EQ_AUTO_RCV_CTRL10:
 844         case RT5665_EQ_AUTO_RCV_CTRL11:
 845         case RT5665_EQ_AUTO_RCV_CTRL12:
 846         case RT5665_EQ_AUTO_RCV_CTRL13:
 847         case RT5665_ADC_L_EQ_LPF1_A1:
 848         case RT5665_R_EQ_LPF1_A1:
 849         case RT5665_L_EQ_LPF1_H0:
 850         case RT5665_R_EQ_LPF1_H0:
 851         case RT5665_L_EQ_BPF1_A1:
 852         case RT5665_R_EQ_BPF1_A1:
 853         case RT5665_L_EQ_BPF1_A2:
 854         case RT5665_R_EQ_BPF1_A2:
 855         case RT5665_L_EQ_BPF1_H0:
 856         case RT5665_R_EQ_BPF1_H0:
 857         case RT5665_L_EQ_BPF2_A1:
 858         case RT5665_R_EQ_BPF2_A1:
 859         case RT5665_L_EQ_BPF2_A2:
 860         case RT5665_R_EQ_BPF2_A2:
 861         case RT5665_L_EQ_BPF2_H0:
 862         case RT5665_R_EQ_BPF2_H0:
 863         case RT5665_L_EQ_BPF3_A1:
 864         case RT5665_R_EQ_BPF3_A1:
 865         case RT5665_L_EQ_BPF3_A2:
 866         case RT5665_R_EQ_BPF3_A2:
 867         case RT5665_L_EQ_BPF3_H0:
 868         case RT5665_R_EQ_BPF3_H0:
 869         case RT5665_L_EQ_BPF4_A1:
 870         case RT5665_R_EQ_BPF4_A1:
 871         case RT5665_L_EQ_BPF4_A2:
 872         case RT5665_R_EQ_BPF4_A2:
 873         case RT5665_L_EQ_BPF4_H0:
 874         case RT5665_R_EQ_BPF4_H0:
 875         case RT5665_L_EQ_HPF1_A1:
 876         case RT5665_R_EQ_HPF1_A1:
 877         case RT5665_L_EQ_HPF1_H0:
 878         case RT5665_R_EQ_HPF1_H0:
 879         case RT5665_L_EQ_PRE_VOL:
 880         case RT5665_R_EQ_PRE_VOL:
 881         case RT5665_L_EQ_POST_VOL:
 882         case RT5665_R_EQ_POST_VOL:
 883         case RT5665_SCAN_MODE_CTRL:
 884         case RT5665_I2C_MODE:
 885                 return true;
 886         default:
 887                 return false;
 888         }
 889 }
 890
 891 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
 892 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
 893 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
 894 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
 895 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
 896 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
 897 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
 898 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
 899
 900 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
 901 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 902         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 903         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
 904         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
 905         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
 906         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
 907         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
 908         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
 909 );
 910
 911 /* Interface data select */
 912 static const char * const rt5665_data_select[] = {
 913         "L/R", "R/L", "L/L", "R/R"
 914 };
 915
 916 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
 917         RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
 918
 919 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
 920         RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
 921
 922 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
 923         RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
 924
 925 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
 926         RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
 927
 928 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
 929         RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
 930
 931 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
 932         RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
 933
 934 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
 935         RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
 936
 937 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
 938         RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
 939
 940 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
 941         RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
 942
 943 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
 944         RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
 945
 946 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
 947         RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
 948
 949 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
 950         RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
 951
 952 static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
 953         RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
 954
 955 static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
 956         RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
 957
 958 static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
 959         SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
 960
 961 static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
 962         SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
 963
 964 static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
 965         SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
 966
 967 static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
 968         SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
 969
 970 static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
 971         SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
 972
 973 static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
 974         SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
 975
 976 static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
 977         SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
 978
 979 static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
 980         SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
 981
 982 static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
 983         SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
 984
 985 static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
 986         SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
 987
 988 static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
 989         SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
 990
 991 static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
 992         SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
 993
 994 static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
 995         SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
 996
 997 static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
 998         SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
 999
1000 static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1001                 struct snd_ctl_elem_value *ucontrol)
1002 {
1003         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1004         int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1005
1006         if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1007                 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1008                         RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1009                 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1010                         RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1011         }
1012
1013         return ret;
1014 }
1015
1016 static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1017                 struct snd_ctl_elem_value *ucontrol)
1018 {
1019         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1020         int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1021
1022         if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1023                 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1024                         RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1025                 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1026                         RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1027         }
1028
1029         return ret;
1030 }
1031
1032 /**
1033  * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1034  * @codec: SoC audio codec device.
1035  * @filter_mask: mask of filters.
1036  * @clk_src: clock source
1037  *
1038  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1039  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1040  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1041  * ASRC function will track i2s clock and generate a corresponding system clock
1042  * for codec. This function provides an API to select the clock source for a
1043  * set of filters specified by the mask. And the codec driver will turn on ASRC
1044  * for these filters if ASRC is selected as their clock source.
1045  */
1046 int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1047                 unsigned int filter_mask, unsigned int clk_src)
1048 {
1049         unsigned int asrc2_mask = 0;
1050         unsigned int asrc2_value = 0;
1051         unsigned int asrc3_mask = 0;
1052         unsigned int asrc3_value = 0;
1053
1054         switch (clk_src) {
1055         case RT5665_CLK_SEL_SYS:
1056         case RT5665_CLK_SEL_I2S1_ASRC:
1057         case RT5665_CLK_SEL_I2S2_ASRC:
1058         case RT5665_CLK_SEL_I2S3_ASRC:
1059         case RT5665_CLK_SEL_SYS2:
1060         case RT5665_CLK_SEL_SYS3:
1061         case RT5665_CLK_SEL_SYS4:
1062                 break;
1063
1064         default:
1065                 return -EINVAL;
1066         }
1067
1068         if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1069                 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1070                 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1071                         | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1072         }
1073
1074         if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1075                 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1076                 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1077                         | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1078         }
1079
1080         if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1081                 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1082                 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1083                         | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1084         }
1085
1086         if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1087                 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1088                 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1089                         | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1090         }
1091
1092         if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1093                 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1094                 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1095                         | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1096         }
1097
1098         if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1099                 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1100                 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1101                         | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1102         }
1103
1104         if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1105                 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1106                 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1107                         | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1108         }
1109
1110         if (filter_mask & RT5665_AD_MONO_R_FILTER)  {
1111                 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1112                 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1113                         | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1114         }
1115
1116         if (asrc2_mask)
1117                 snd_soc_update_bits(codec, RT5665_ASRC_2,
1118                         asrc2_mask, asrc2_value);
1119
1120         if (asrc3_mask)
1121                 snd_soc_update_bits(codec, RT5665_ASRC_3,
1122                         asrc3_mask, asrc3_value);
1123
1124         return 0;
1125 }
1126 EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1127
1128 static int rt5665_button_detect(struct snd_soc_codec *codec)
1129 {
1130         int btn_type, val;
1131
1132         val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1133         btn_type = val & 0xfff0;
1134         snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1135
1136         return btn_type;
1137 }
1138
1139 static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1140         bool enable)
1141 {
1142         if (enable) {
1143                 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x0003);
1144                 snd_soc_update_bits(codec, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
1145                 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1146                 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1147                                 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1148                                 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1149                 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1150                                 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1151         } else {
1152                 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1153                                 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1154                 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1155                                 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1156                 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1157                                 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1158         }
1159 }
1160
1161 /**
1162  * rt5665_headset_detect - Detect headset.
1163  * @codec: SoC audio codec device.
1164  * @jack_insert: Jack insert or not.
1165  *
1166  * Detect whether is headset or not when jack inserted.
1167  *
1168  * Returns detect status.
1169  */
1170 static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1171 {
1172         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1173         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1174         unsigned int sar_hs_type, val;
1175
1176         if (jack_insert) {
1177                 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1178                 snd_soc_dapm_sync(dapm);
1179
1180                 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1181                         0x100);
1182
1183                 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1184                 if (val & 0x4) {
1185                         regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1186                                 0x100, 0);
1187
1188                         regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1189                         while (val & 0x4) {
1190                                 usleep_range(10000, 15000);
1191                                 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1192                                         &val);
1193                         }
1194                 }
1195
1196                 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1197                         0x1a0, 0x120);
1198                 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1199                 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
1200                 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1201
1202                 usleep_range(10000, 15000);
1203
1204                 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1205                         RT5665_SAR_IL_CMD_4) & 0x7ff;
1206
1207                 sar_hs_type = rt5665->pdata.sar_hs_type ?
1208                         rt5665->pdata.sar_hs_type : 729;
1209
1210                 if (rt5665->sar_adc_value > sar_hs_type) {
1211                         rt5665->jack_type = SND_JACK_HEADSET;
1212                         rt5665_enable_push_button_irq(codec, true);
1213                         } else {
1214                         rt5665->jack_type = SND_JACK_HEADPHONE;
1215                         regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1216                                 0x2291);
1217                         regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1218                                 0x100, 0);
1219                         snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1220                         snd_soc_dapm_sync(dapm);
1221                 }
1222         } else {
1223                 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1224                 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1225                 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1226                 snd_soc_dapm_sync(dapm);
1227                 if (rt5665->jack_type == SND_JACK_HEADSET)
1228                         rt5665_enable_push_button_irq(codec, false);
1229                 rt5665->jack_type = 0;
1230         }
1231
1232         dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1233         return rt5665->jack_type;
1234 }
1235
1236 static irqreturn_t rt5665_irq(int irq, void *data)
1237 {
1238         struct rt5665_priv *rt5665 = data;
1239
1240         mod_delayed_work(system_power_efficient_wq,
1241                            &rt5665->jack_detect_work, msecs_to_jiffies(250));
1242
1243         return IRQ_HANDLED;
1244 }
1245
1246 static void rt5665_jd_check_handler(struct work_struct *work)
1247 {
1248         struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1249                 jd_check_work.work);
1250
1251         if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1252                 /* jack out */
1253                 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1254
1255                 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1256                                 SND_JACK_HEADSET |
1257                                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1258                                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1259         } else {
1260                 schedule_delayed_work(&rt5665->jd_check_work, 500);
1261         }
1262 }
1263
1264 static int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1265         struct snd_soc_jack *hs_jack, void *data)
1266 {
1267         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1268
1269         switch (rt5665->pdata.jd_src) {
1270         case RT5665_JD1:
1271                 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1272                         RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1273                 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1274                                 0xc000, 0xc000);
1275                 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1276                         RT5665_PWR_JD1, RT5665_PWR_JD1);
1277                 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1278                 break;
1279
1280         case RT5665_JD_NULL:
1281                 break;
1282
1283         default:
1284                 dev_warn(codec->dev, "Wrong JD source\n");
1285                 break;
1286         }
1287
1288         rt5665->hs_jack = hs_jack;
1289
1290         return 0;
1291 }
1292
1293 static void rt5665_jack_detect_handler(struct work_struct *work)
1294 {
1295         struct rt5665_priv *rt5665 =
1296                 container_of(work, struct rt5665_priv, jack_detect_work.work);
1297         int val, btn_type;
1298
1299         while (!rt5665->codec) {
1300                 pr_debug("%s codec = null\n", __func__);
1301                 usleep_range(10000, 15000);
1302         }
1303
1304         while (!rt5665->codec->component.card->instantiated) {
1305                 pr_debug("%s\n", __func__);
1306                 usleep_range(10000, 15000);
1307         }
1308
1309         while (!rt5665->calibration_done) {
1310                 pr_debug("%s calibration not ready\n", __func__);
1311                 usleep_range(10000, 15000);
1312         }
1313
1314         mutex_lock(&rt5665->calibrate_mutex);
1315
1316         val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1317         if (!val) {
1318                 /* jack in */
1319                 if (rt5665->jack_type == 0) {
1320                         /* jack was out, report jack type */
1321                         rt5665->jack_type =
1322                                 rt5665_headset_detect(rt5665->codec, 1);
1323                 } else {
1324                         /* jack is already in, report button event */
1325                         rt5665->jack_type = SND_JACK_HEADSET;
1326                         btn_type = rt5665_button_detect(rt5665->codec);
1327                         /**
1328                          * rt5665 can report three kinds of button behavior,
1329                          * one click, double click and hold. However,
1330                          * currently we will report button pressed/released
1331                          * event. So all the three button behaviors are
1332                          * treated as button pressed.
1333                          */
1334                         switch (btn_type) {
1335                         case 0x8000:
1336                         case 0x4000:
1337                         case 0x2000:
1338                                 rt5665->jack_type |= SND_JACK_BTN_0;
1339                                 break;
1340                         case 0x1000:
1341                         case 0x0800:
1342                         case 0x0400:
1343                                 rt5665->jack_type |= SND_JACK_BTN_1;
1344                                 break;
1345                         case 0x0200:
1346                         case 0x0100:
1347                         case 0x0080:
1348                                 rt5665->jack_type |= SND_JACK_BTN_2;
1349                                 break;
1350                         case 0x0040:
1351                         case 0x0020:
1352                         case 0x0010:
1353                                 rt5665->jack_type |= SND_JACK_BTN_3;
1354                                 break;
1355                         case 0x0000: /* unpressed */
1356                                 break;
1357                         default:
1358                                 btn_type = 0;
1359                                 dev_err(rt5665->codec->dev,
1360                                         "Unexpected button code 0x%04x\n",
1361                                         btn_type);
1362                                 break;
1363                         }
1364                 }
1365         } else {
1366                 /* jack out */
1367                 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1368         }
1369
1370         snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1371                         SND_JACK_HEADSET |
1372                             SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1373                             SND_JACK_BTN_2 | SND_JACK_BTN_3);
1374
1375         if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1376                 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1377                 schedule_delayed_work(&rt5665->jd_check_work, 0);
1378         else
1379                 cancel_delayed_work_sync(&rt5665->jd_check_work);
1380
1381         mutex_unlock(&rt5665->calibrate_mutex);
1382 }
1383
1384 static const char * const rt5665_clk_sync[] = {
1385         "I2S1_1", "I2S1_2", "I2S2", "I2S3", "IF2 Slave", "IF3 Slave"
1386 };
1387
1388 static const struct soc_enum rt5665_enum[] = {
1389         SOC_ENUM_SINGLE(RT5665_I2S1_SDP, 11, 5, rt5665_clk_sync),
1390         SOC_ENUM_SINGLE(RT5665_I2S2_SDP, 11, 5, rt5665_clk_sync),
1391         SOC_ENUM_SINGLE(RT5665_I2S3_SDP, 11, 5, rt5665_clk_sync),
1392 };
1393
1394 static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1395         /* Headphone Output Volume */
1396         SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1397                 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1398                 rt5665_hp_vol_put, hp_vol_tlv),
1399
1400         /* Mono Output Volume */
1401         SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1402                 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1403                 rt5665_mono_vol_put, mono_vol_tlv),
1404
1405         SOC_SINGLE_TLV("MONOVOL Playback Volume", RT5665_MONO_OUT,
1406                 RT5665_L_VOL_SFT, 39, 1, out_vol_tlv),
1407
1408         /* Output Volume */
1409         SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1410                 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1411
1412         /* DAC Digital Volume */
1413         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1414                 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1415         SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1416                 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1417         SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1418                 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1419
1420         /* IN1/IN2/IN3/IN4 Volume */
1421         SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1422                 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1423         SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1424                 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1425         SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1426                 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1427         SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1428                 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1429         SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1430                 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1431
1432         /* INL/INR Volume Control */
1433         SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1434                 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1435
1436         /* ADC Digital Volume Control */
1437         SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1438                 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1439         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1440                 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1441         SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1442                 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1443         SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1444                 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1445         SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1446                 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1447         SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1448                 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1449
1450         /* ADC Boost Volume Control */
1451         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1452                 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1453                 3, 0, adc_bst_tlv),
1454
1455         SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1456                 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1457                 3, 0, adc_bst_tlv),
1458
1459         SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1460                 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1461                 3, 0, adc_bst_tlv),
1462
1463         /* I2S3 CLK Source */
1464         SOC_ENUM("I2S1 Master Clk Sel", rt5665_enum[0]),
1465         SOC_ENUM("I2S2 Master Clk Sel", rt5665_enum[1]),
1466         SOC_ENUM("I2S3 Master Clk Sel", rt5665_enum[2]),
1467 };
1468
1469 /**
1470  * set_dmic_clk - Set parameter of dmic.
1471  *
1472  * @w: DAPM widget.
1473  * @kcontrol: The kcontrol of this widget.
1474  * @event: Event id.
1475  *
1476  * Choose dmic clock between 1MHz and 3MHz.
1477  * It is better for clock to approximate 3MHz.
1478  */
1479 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1480         struct snd_kcontrol *kcontrol, int event)
1481 {
1482         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1483         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1484         int pd, idx = -EINVAL;
1485
1486         pd = rl6231_get_pre_div(rt5665->regmap,
1487                 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1488         idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1489
1490         if (idx < 0)
1491                 dev_err(codec->dev, "Failed to set DMIC clock\n");
1492         else {
1493                 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1494                         RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1495         }
1496         return idx;
1497 }
1498
1499 static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1500         struct snd_kcontrol *kcontrol, int event)
1501 {
1502         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1503
1504         switch (event) {
1505         case SND_SOC_DAPM_PRE_PMU:
1506                 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1507                         RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1508                         RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1509                 break;
1510         case SND_SOC_DAPM_POST_PMD:
1511                 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1512                         RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1513                         RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1514                 break;
1515         default:
1516                 return 0;
1517         }
1518
1519         return 0;
1520 }
1521
1522 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1523                          struct snd_soc_dapm_widget *sink)
1524 {
1525         unsigned int val;
1526         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1527
1528         val = snd_soc_read(codec, RT5665_GLB_CLK);
1529         val &= RT5665_SCLK_SRC_MASK;
1530         if (val == RT5665_SCLK_SRC_PLL1)
1531                 return 1;
1532         else
1533                 return 0;
1534 }
1535
1536 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1537                          struct snd_soc_dapm_widget *sink)
1538 {
1539         unsigned int reg, shift, val;
1540         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1541
1542         switch (w->shift) {
1543         case RT5665_ADC_MONO_R_ASRC_SFT:
1544                 reg = RT5665_ASRC_3;
1545                 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1546                 break;
1547         case RT5665_ADC_MONO_L_ASRC_SFT:
1548                 reg = RT5665_ASRC_3;
1549                 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1550                 break;
1551         case RT5665_ADC_STO1_ASRC_SFT:
1552                 reg = RT5665_ASRC_3;
1553                 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1554                 break;
1555         case RT5665_ADC_STO2_ASRC_SFT:
1556                 reg = RT5665_ASRC_3;
1557                 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1558                 break;
1559         case RT5665_DAC_MONO_R_ASRC_SFT:
1560                 reg = RT5665_ASRC_2;
1561                 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1562                 break;
1563         case RT5665_DAC_MONO_L_ASRC_SFT:
1564                 reg = RT5665_ASRC_2;
1565                 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1566                 break;
1567         case RT5665_DAC_STO1_ASRC_SFT:
1568                 reg = RT5665_ASRC_2;
1569                 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1570                 break;
1571         case RT5665_DAC_STO2_ASRC_SFT:
1572                 reg = RT5665_ASRC_2;
1573                 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1574                 break;
1575         default:
1576                 return 0;
1577         }
1578
1579         val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1580         switch (val) {
1581         case RT5665_CLK_SEL_I2S1_ASRC:
1582         case RT5665_CLK_SEL_I2S2_ASRC:
1583         case RT5665_CLK_SEL_I2S3_ASRC:
1584                 /* I2S_Pre_Div1 should be 1 in asrc mode */
1585                 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1586                         RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1587                 return 1;
1588         default:
1589                 return 0;
1590         }
1591
1592 }
1593
1594 /* Digital Mixer */
1595 static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1596         SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1597                         RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1598         SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1599                         RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1600 };
1601
1602 static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1603         SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1604                         RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1605         SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1606                         RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1607 };
1608
1609 static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1610         SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1611                         RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1612         SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1613                         RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1614 };
1615
1616 static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1617         SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1618                         RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1619         SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1620                         RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1621 };
1622
1623 static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1624         SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1625                         RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1626         SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1627                         RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1628 };
1629
1630 static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1631         SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1632                         RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1633         SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1634                         RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1635 };
1636
1637 static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1638         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1639                         RT5665_M_ADCMIX_L_SFT, 1, 1),
1640         SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1641                         RT5665_M_DAC1_L_SFT, 1, 1),
1642 };
1643
1644 static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1645         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1646                         RT5665_M_ADCMIX_R_SFT, 1, 1),
1647         SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1648                         RT5665_M_DAC1_R_SFT, 1, 1),
1649 };
1650
1651 static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1652         SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1653                         RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1654         SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1655                         RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1656         SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1657                         RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1658         SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1659                         RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1660 };
1661
1662 static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1663         SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1664                         RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1665         SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1666                         RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1667         SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1668                         RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1669         SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1670                         RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1671 };
1672
1673 static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1674         SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1675                         RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1676         SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1677                         RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1678         SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1679                         RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1680 };
1681
1682 static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1683         SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1684                         RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1685         SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1686                         RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1687         SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1688                         RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1689 };
1690
1691 static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1692         SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1693                         RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1694         SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1695                         RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1696         SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1697                         RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1698         SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1699                         RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1700 };
1701
1702 static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1703         SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1704                         RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1705         SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1706                         RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1707         SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1708                         RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1709         SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1710                         RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1711 };
1712
1713 /* Analog Input Mixer */
1714 static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1715         SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1716                         RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1717         SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1718                         RT5665_M_INL_RM1_L_SFT, 1, 1),
1719         SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1720                         RT5665_M_INR_RM1_L_SFT, 1, 1),
1721         SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1722                         RT5665_M_BST4_RM1_L_SFT, 1, 1),
1723         SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1724                         RT5665_M_BST3_RM1_L_SFT, 1, 1),
1725         SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1726                         RT5665_M_BST2_RM1_L_SFT, 1, 1),
1727         SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1728                         RT5665_M_BST1_RM1_L_SFT, 1, 1),
1729 };
1730
1731 static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1732         SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1733                         RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1734         SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1735                         RT5665_M_INR_RM1_R_SFT, 1, 1),
1736         SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1737                         RT5665_M_BST4_RM1_R_SFT, 1, 1),
1738         SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1739                         RT5665_M_BST3_RM1_R_SFT, 1, 1),
1740         SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1741                         RT5665_M_BST2_RM1_R_SFT, 1, 1),
1742         SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1743                         RT5665_M_BST1_RM1_R_SFT, 1, 1),
1744 };
1745
1746 static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1747         SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1748                         RT5665_M_INL_RM2_L_SFT, 1, 1),
1749         SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1750                         RT5665_M_INR_RM2_L_SFT, 1, 1),
1751         SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1752                         RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1753         SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1754                         RT5665_M_BST4_RM2_L_SFT, 1, 1),
1755         SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1756                         RT5665_M_BST3_RM2_L_SFT, 1, 1),
1757         SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1758                         RT5665_M_BST2_RM2_L_SFT, 1, 1),
1759         SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1760                         RT5665_M_BST1_RM2_L_SFT, 1, 1),
1761 };
1762
1763 static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1764         SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1765                         RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1766         SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1767                         RT5665_M_INL_RM2_R_SFT, 1, 1),
1768         SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1769                         RT5665_M_INR_RM2_R_SFT, 1, 1),
1770         SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1771                         RT5665_M_BST4_RM2_R_SFT, 1, 1),
1772         SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1773                         RT5665_M_BST3_RM2_R_SFT, 1, 1),
1774         SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1775                         RT5665_M_BST2_RM2_R_SFT, 1, 1),
1776         SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1777                         RT5665_M_BST1_RM2_R_SFT, 1, 1),
1778 };
1779
1780 static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1781         SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1782                         RT5665_M_DAC_L2_MM_SFT, 1, 1),
1783         SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1784                         RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1785         SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1786                         RT5665_M_BST1_MM_SFT, 1, 1),
1787         SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1788                         RT5665_M_BST2_MM_SFT, 1, 1),
1789         SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1790                         RT5665_M_BST3_MM_SFT, 1, 1),
1791 };
1792
1793 static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1794         SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1795                         RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1796         SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1797                         RT5665_M_IN_L_OM_L_SFT, 1, 1),
1798         SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1799                         RT5665_M_BST1_OM_L_SFT, 1, 1),
1800         SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1801                         RT5665_M_BST2_OM_L_SFT, 1, 1),
1802         SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1803                         RT5665_M_BST3_OM_L_SFT, 1, 1),
1804 };
1805
1806 static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1807         SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1808                         RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1809         SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1810                         RT5665_M_IN_R_OM_R_SFT, 1, 1),
1811         SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1812                         RT5665_M_BST2_OM_R_SFT, 1, 1),
1813         SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1814                         RT5665_M_BST3_OM_R_SFT, 1, 1),
1815         SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1816                         RT5665_M_BST4_OM_R_SFT, 1, 1),
1817 };
1818
1819 static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1820         SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1821                         RT5665_M_DAC_L2_MA_SFT, 1, 1),
1822         SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1823                         RT5665_M_MONOVOL_MA_SFT, 1, 1),
1824 };
1825
1826 static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1827         SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1828                         RT5665_M_DAC_L2_LM_SFT, 1, 1),
1829         SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1830                         RT5665_M_OV_L_LM_SFT, 1, 1),
1831 };
1832
1833 static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1834         SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1835                         RT5665_M_DAC_R2_LM_SFT, 1, 1),
1836         SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1837                         RT5665_M_OV_R_LM_SFT, 1, 1),
1838 };
1839
1840 /*DAC L2, DAC R2*/
1841 /*MX-17 [6:4], MX-17 [2:0]*/
1842 static const char * const rt5665_dac2_src[] = {
1843         "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1844 };
1845
1846 static SOC_ENUM_SINGLE_DECL(
1847         rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1848         RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1849
1850 static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1851         SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1852
1853 static SOC_ENUM_SINGLE_DECL(
1854         rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1855         RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1856
1857 static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1858         SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1859
1860 /*DAC L3, DAC R3*/
1861 /*MX-1B [6:4], MX-1B [2:0]*/
1862 static const char * const rt5665_dac3_src[] = {
1863         "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1864 };
1865
1866 static SOC_ENUM_SINGLE_DECL(
1867         rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1868         RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1869
1870 static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1871         SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1872
1873 static SOC_ENUM_SINGLE_DECL(
1874         rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1875         RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1876
1877 static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1878         SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1879
1880 /* STO1 ADC1 Source */
1881 /* MX-26 [13] [5] */
1882 static const char * const rt5665_sto1_adc1_src[] = {
1883         "DD Mux", "ADC"
1884 };
1885
1886 static SOC_ENUM_SINGLE_DECL(
1887         rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1888         RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1889
1890 static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1891         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1892
1893 static SOC_ENUM_SINGLE_DECL(
1894         rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1895         RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1896
1897 static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1898         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1899
1900 /* STO1 ADC Source */
1901 /* MX-26 [11:10] [3:2] */
1902 static const char * const rt5665_sto1_adc_src[] = {
1903         "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1904 };
1905
1906 static SOC_ENUM_SINGLE_DECL(
1907         rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1908         RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1909
1910 static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1911         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1912
1913 static SOC_ENUM_SINGLE_DECL(
1914         rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1915         RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1916
1917 static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1918         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1919
1920 /* STO1 ADC2 Source */
1921 /* MX-26 [12] [4] */
1922 static const char * const rt5665_sto1_adc2_src[] = {
1923         "DAC MIX", "DMIC"
1924 };
1925
1926 static SOC_ENUM_SINGLE_DECL(
1927         rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1928         RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1929
1930 static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1931         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1932
1933 static SOC_ENUM_SINGLE_DECL(
1934         rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1935         RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1936
1937 static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1938         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1939
1940 /* STO1 DMIC Source */
1941 /* MX-26 [8] */
1942 static const char * const rt5665_sto1_dmic_src[] = {
1943         "DMIC1", "DMIC2"
1944 };
1945
1946 static SOC_ENUM_SINGLE_DECL(
1947         rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1948         RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1949
1950 static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1951         SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1952
1953 /* MX-26 [9] */
1954 static const char * const rt5665_sto1_dd_l_src[] = {
1955         "STO2 DAC", "MONO DAC"
1956 };
1957
1958 static SOC_ENUM_SINGLE_DECL(
1959         rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1960         RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1961
1962 static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1963         SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1964
1965 /* MX-26 [1:0] */
1966 static const char * const rt5665_sto1_dd_r_src[] = {
1967         "STO2 DAC", "MONO DAC", "AEC REF"
1968 };
1969
1970 static SOC_ENUM_SINGLE_DECL(
1971         rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1972         RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1973
1974 static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1975         SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1976
1977 /* MONO ADC L2 Source */
1978 /* MX-27 [12] */
1979 static const char * const rt5665_mono_adc_l2_src[] = {
1980         "DAC MIXL", "DMIC"
1981 };
1982
1983 static SOC_ENUM_SINGLE_DECL(
1984         rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1985         RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1986
1987 static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1988         SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1989
1990
1991 /* MONO ADC L1 Source */
1992 /* MX-27 [13] */
1993 static const char * const rt5665_mono_adc_l1_src[] = {
1994         "DD Mux", "ADC"
1995 };
1996
1997 static SOC_ENUM_SINGLE_DECL(
1998         rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1999         RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
2000
2001 static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
2002         SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
2003
2004 /* MX-27 [9][1]*/
2005 static const char * const rt5665_mono_dd_src[] = {
2006         "STO2 DAC", "MONO DAC"
2007 };
2008
2009 static SOC_ENUM_SINGLE_DECL(
2010         rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
2011         RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
2012
2013 static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
2014         SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
2015
2016 static SOC_ENUM_SINGLE_DECL(
2017         rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
2018         RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
2019
2020 static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
2021         SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
2022
2023 /* MONO ADC L Source, MONO ADC R Source*/
2024 /* MX-27 [11:10], MX-27 [3:2] */
2025 static const char * const rt5665_mono_adc_src[] = {
2026         "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2027 };
2028
2029 static SOC_ENUM_SINGLE_DECL(
2030         rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2031         RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2032
2033 static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2034         SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2035
2036 static SOC_ENUM_SINGLE_DECL(
2037         rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2038         RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2039
2040 static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2041         SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2042
2043 /* MONO DMIC L Source */
2044 /* MX-27 [8] */
2045 static const char * const rt5665_mono_dmic_l_src[] = {
2046         "DMIC1 L", "DMIC2 L"
2047 };
2048
2049 static SOC_ENUM_SINGLE_DECL(
2050         rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2051         RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2052
2053 static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2054         SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2055
2056 /* MONO ADC R2 Source */
2057 /* MX-27 [4] */
2058 static const char * const rt5665_mono_adc_r2_src[] = {
2059         "DAC MIXR", "DMIC"
2060 };
2061
2062 static SOC_ENUM_SINGLE_DECL(
2063         rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2064         RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2065
2066 static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2067         SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2068
2069 /* MONO ADC R1 Source */
2070 /* MX-27 [5] */
2071 static const char * const rt5665_mono_adc_r1_src[] = {
2072         "DD Mux", "ADC"
2073 };
2074
2075 static SOC_ENUM_SINGLE_DECL(
2076         rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2077         RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2078
2079 static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2080         SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2081
2082 /* MONO DMIC R Source */
2083 /* MX-27 [0] */
2084 static const char * const rt5665_mono_dmic_r_src[] = {
2085         "DMIC1 R", "DMIC2 R"
2086 };
2087
2088 static SOC_ENUM_SINGLE_DECL(
2089         rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2090         RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2091
2092 static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2093         SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2094
2095
2096 /* STO2 ADC1 Source */
2097 /* MX-28 [13] [5] */
2098 static const char * const rt5665_sto2_adc1_src[] = {
2099         "DD Mux", "ADC"
2100 };
2101
2102 static SOC_ENUM_SINGLE_DECL(
2103         rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2104         RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2105
2106 static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2107         SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2108
2109 static SOC_ENUM_SINGLE_DECL(
2110         rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2111         RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2112
2113 static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2114         SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2115
2116 /* STO2 ADC Source */
2117 /* MX-28 [11:10] [3:2] */
2118 static const char * const rt5665_sto2_adc_src[] = {
2119         "ADC1 L", "ADC1 R", "ADC2 L"
2120 };
2121
2122 static SOC_ENUM_SINGLE_DECL(
2123         rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2124         RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2125
2126 static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2127         SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2128
2129 static SOC_ENUM_SINGLE_DECL(
2130         rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2131         RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2132
2133 static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2134         SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2135
2136 /* STO2 ADC2 Source */
2137 /* MX-28 [12] [4] */
2138 static const char * const rt5665_sto2_adc2_src[] = {
2139         "DAC MIX", "DMIC"
2140 };
2141
2142 static SOC_ENUM_SINGLE_DECL(
2143         rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2144         RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2145
2146 static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2147         SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2148
2149 static SOC_ENUM_SINGLE_DECL(
2150         rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2151         RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2152
2153 static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2154         SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2155
2156 /* STO2 DMIC Source */
2157 /* MX-28 [8] */
2158 static const char * const rt5665_sto2_dmic_src[] = {
2159         "DMIC1", "DMIC2"
2160 };
2161
2162 static SOC_ENUM_SINGLE_DECL(
2163         rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2164         RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2165
2166 static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2167         SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2168
2169 /* MX-28 [9] */
2170 static const char * const rt5665_sto2_dd_l_src[] = {
2171         "STO2 DAC", "MONO DAC"
2172 };
2173
2174 static SOC_ENUM_SINGLE_DECL(
2175         rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2176         RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2177
2178 static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2179         SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2180
2181 /* MX-28 [1] */
2182 static const char * const rt5665_sto2_dd_r_src[] = {
2183         "STO2 DAC", "MONO DAC"
2184 };
2185
2186 static SOC_ENUM_SINGLE_DECL(
2187         rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2188         RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2189
2190 static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2191         SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2192
2193 /* DAC R1 Source, DAC L1 Source*/
2194 /* MX-29 [11:10], MX-29 [9:8]*/
2195 static const char * const rt5665_dac1_src[] = {
2196         "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2197 };
2198
2199 static SOC_ENUM_SINGLE_DECL(
2200         rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2201         RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2202
2203 static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2204         SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2205
2206 static SOC_ENUM_SINGLE_DECL(
2207         rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2208         RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2209
2210 static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2211         SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2212
2213 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2214 /* MX-2D [13:12], MX-2D [9:8]*/
2215 static const char * const rt5665_dig_dac_mix_src[] = {
2216         "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2217 };
2218
2219 static SOC_ENUM_SINGLE_DECL(
2220         rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2221         RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2222
2223 static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2224         SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2225
2226 static SOC_ENUM_SINGLE_DECL(
2227         rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2228         RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2229
2230 static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2231         SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2232
2233 /* Analog DAC L1 Source, Analog DAC R1 Source*/
2234 /* MX-2D [5:4], MX-2D [1:0]*/
2235 static const char * const rt5665_alg_dac1_src[] = {
2236         "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2237 };
2238
2239 static SOC_ENUM_SINGLE_DECL(
2240         rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2241         RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2242
2243 static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2244         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2245
2246 static SOC_ENUM_SINGLE_DECL(
2247         rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2248         RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2249
2250 static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2251         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2252
2253 /* Analog DAC LR Source, Analog DAC R2 Source*/
2254 /* MX-2E [5:4], MX-2E [0]*/
2255 static const char * const rt5665_alg_dac2_src[] = {
2256         "Mono DAC Mixer", "DAC2"
2257 };
2258
2259 static SOC_ENUM_SINGLE_DECL(
2260         rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2261         RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2262
2263 static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2264         SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2265
2266 static SOC_ENUM_SINGLE_DECL(
2267         rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2268         RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2269
2270 static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2271         SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2272
2273 /* Interface2 ADC Data Input*/
2274 /* MX-2F [14:12] */
2275 static const char * const rt5665_if2_1_adc_in_src[] = {
2276         "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2277         "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2278 };
2279
2280 static SOC_ENUM_SINGLE_DECL(
2281         rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2282         RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2283
2284 static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2285         SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2286
2287 /* MX-2F [6:4] */
2288 static const char * const rt5665_if2_2_adc_in_src[] = {
2289         "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2290         "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2291 };
2292
2293 static SOC_ENUM_SINGLE_DECL(
2294         rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2295         RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2296
2297 static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2298         SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2299
2300 /* Interface3 ADC Data Input*/
2301 /* MX-30 [6:4] */
2302 static const char * const rt5665_if3_adc_in_src[] = {
2303         "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2304         "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2305 };
2306
2307 static SOC_ENUM_SINGLE_DECL(
2308         rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2309         RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2310
2311 static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2312         SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2313
2314 /* PDM 1 L/R*/
2315 /* MX-31 [11:10] [9:8] */
2316 static const char * const rt5665_pdm_src[] = {
2317         "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2318 };
2319
2320 static SOC_ENUM_SINGLE_DECL(
2321         rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2322         RT5665_PDM1_L_SFT, rt5665_pdm_src);
2323
2324 static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2325         SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2326
2327 static SOC_ENUM_SINGLE_DECL(
2328         rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2329         RT5665_PDM1_R_SFT, rt5665_pdm_src);
2330
2331 static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2332         SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2333
2334
2335 /* I2S1 TDM ADCDAT Source */
2336 /* MX-7a[10] */
2337 static const char * const rt5665_if1_1_adc1_data_src[] = {
2338         "STO1 ADC", "IF2_1 DAC",
2339 };
2340
2341 static SOC_ENUM_SINGLE_DECL(
2342         rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2343         RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2344
2345 static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2346         SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2347
2348 /* MX-7a[9] */
2349 static const char * const rt5665_if1_1_adc2_data_src[] = {
2350         "STO2 ADC", "IF2_2 DAC",
2351 };
2352
2353 static SOC_ENUM_SINGLE_DECL(
2354         rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2355         RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2356
2357 static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2358         SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2359
2360 /* MX-7a[8] */
2361 static const char * const rt5665_if1_1_adc3_data_src[] = {
2362         "MONO ADC", "IF3 DAC",
2363 };
2364
2365 static SOC_ENUM_SINGLE_DECL(
2366         rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2367         RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2368
2369 static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2370         SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2371
2372 /* MX-7b[10] */
2373 static const char * const rt5665_if1_2_adc1_data_src[] = {
2374         "STO1 ADC", "IF1 DAC",
2375 };
2376
2377 static SOC_ENUM_SINGLE_DECL(
2378         rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2379         RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2380
2381 static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2382         SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2383
2384 /* MX-7b[9] */
2385 static const char * const rt5665_if1_2_adc2_data_src[] = {
2386         "STO2 ADC", "IF2_1 DAC",
2387 };
2388
2389 static SOC_ENUM_SINGLE_DECL(
2390         rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2391         RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2392
2393 static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2394         SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2395
2396 /* MX-7b[8] */
2397 static const char * const rt5665_if1_2_adc3_data_src[] = {
2398         "MONO ADC", "IF2_2 DAC",
2399 };
2400
2401 static SOC_ENUM_SINGLE_DECL(
2402         rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2403         RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2404
2405 static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2406         SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2407
2408 /* MX-7b[7] */
2409 static const char * const rt5665_if1_2_adc4_data_src[] = {
2410         "DAC1", "IF3 DAC",
2411 };
2412
2413 static SOC_ENUM_SINGLE_DECL(
2414         rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2415         RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2416
2417 static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2418         SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2419
2420 /* MX-7a[4:0] MX-7b[4:0] */
2421 static const char * const rt5665_tdm_adc_data_src[] = {
2422         "1234", "1243", "1324", "1342", "1432", "1423",
2423         "2134", "2143", "2314", "2341", "2431", "2413",
2424         "3124", "3142", "3214", "3241", "3412", "3421",
2425         "4123", "4132", "4213", "4231", "4312", "4321"
2426 };
2427
2428 static SOC_ENUM_SINGLE_DECL(
2429         rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2430         RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2431
2432 static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2433         SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2434
2435 static SOC_ENUM_SINGLE_DECL(
2436         rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2437         RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2438
2439 static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2440         SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2441
2442 /* Out Volume Switch */
2443 static const struct snd_kcontrol_new monovol_switch =
2444         SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2445
2446 static const struct snd_kcontrol_new outvol_l_switch =
2447         SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2448
2449 static const struct snd_kcontrol_new outvol_r_switch =
2450         SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2451
2452 /* Out Switch */
2453 static const struct snd_kcontrol_new mono_switch =
2454         SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2455
2456 static const struct snd_kcontrol_new hpo_switch =
2457         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2458                                         RT5665_VOL_L_SFT, 1, 0);
2459
2460 static const struct snd_kcontrol_new lout_l_switch =
2461         SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2462
2463 static const struct snd_kcontrol_new lout_r_switch =
2464         SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2465
2466 static const struct snd_kcontrol_new pdm_l_switch =
2467         SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2468                         RT5665_M_PDM1_L_SFT, 1, 1);
2469
2470 static const struct snd_kcontrol_new pdm_r_switch =
2471         SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2472                         RT5665_M_PDM1_R_SFT, 1, 1);
2473
2474 static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2475         struct snd_kcontrol *kcontrol, int event)
2476 {
2477         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2478
2479         switch (event) {
2480         case SND_SOC_DAPM_PRE_PMU:
2481                 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2482                         RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2483                 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2484                         0x0);
2485                 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2486                 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2487                 break;
2488
2489         case SND_SOC_DAPM_POST_PMD:
2490                 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2491                 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2492                 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2493                         0x40);
2494                 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2495                         RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2496                 break;
2497
2498         default:
2499                 return 0;
2500         }
2501
2502         return 0;
2503
2504 }
2505
2506 static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2507         struct snd_kcontrol *kcontrol, int event)
2508 {
2509         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2510
2511         switch (event) {
2512         case SND_SOC_DAPM_PRE_PMU:
2513                 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2514                         RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2515                 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2516                 break;
2517
2518         case SND_SOC_DAPM_POST_PMD:
2519                 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2520                 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2521                         RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2522                 break;
2523
2524         default:
2525                 return 0;
2526         }
2527
2528         return 0;
2529
2530 }
2531
2532 static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2533         struct snd_kcontrol *kcontrol, int event)
2534 {
2535         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2536
2537         switch (event) {
2538         case SND_SOC_DAPM_POST_PMU:
2539                 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2540                         RT5665_PUMP_EN, RT5665_PUMP_EN);
2541                 break;
2542
2543         case SND_SOC_DAPM_PRE_PMD:
2544                 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2545                         RT5665_PUMP_EN, 0);
2546                 break;
2547
2548         default:
2549                 return 0;
2550         }
2551
2552         return 0;
2553
2554 }
2555
2556 static int set_dmic_power(struct snd_soc_dapm_widget *w,
2557         struct snd_kcontrol *kcontrol, int event)
2558 {
2559         switch (event) {
2560         case SND_SOC_DAPM_POST_PMU:
2561                 /*Add delay to avoid pop noise*/
2562                 msleep(150);
2563                 break;
2564
2565         default:
2566                 return 0;
2567         }
2568
2569         return 0;
2570 }
2571
2572 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2573         struct snd_kcontrol *kcontrol, int event)
2574 {
2575         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2576
2577         switch (event) {
2578         case SND_SOC_DAPM_PRE_PMU:
2579                 switch (w->shift) {
2580                 case RT5665_PWR_VREF1_BIT:
2581                         snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2582                                 RT5665_PWR_FV1, 0);
2583                         break;
2584
2585                 case RT5665_PWR_VREF2_BIT:
2586                         snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2587                                 RT5665_PWR_FV2, 0);
2588                         break;
2589
2590                 case RT5665_PWR_VREF3_BIT:
2591                         snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2592                                 RT5665_PWR_FV3, 0);
2593                         break;
2594
2595                 default:
2596                         break;
2597                 }
2598                 break;
2599
2600         case SND_SOC_DAPM_POST_PMU:
2601                 usleep_range(15000, 20000);
2602                 switch (w->shift) {
2603                 case RT5665_PWR_VREF1_BIT:
2604                         snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2605                                 RT5665_PWR_FV1, RT5665_PWR_FV1);
2606                         break;
2607
2608                 case RT5665_PWR_VREF2_BIT:
2609                         snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2610                                 RT5665_PWR_FV2, RT5665_PWR_FV2);
2611                         break;
2612
2613                 case RT5665_PWR_VREF3_BIT:
2614                         snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2615                                 RT5665_PWR_FV3, RT5665_PWR_FV3);
2616                         break;
2617
2618                 default:
2619                         break;
2620                 }
2621                 break;
2622
2623         default:
2624                 return 0;
2625         }
2626
2627         return 0;
2628 }
2629
2630 static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
2631         struct snd_kcontrol *kcontrol, int event)
2632 {
2633         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2634         unsigned int val1, val2, mask1 = 0, mask2 = 0;
2635
2636         switch (w->shift) {
2637         case RT5665_PWR_I2S2_1_BIT:
2638                 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2639                         RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
2640                 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2641                         RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
2642                 break;
2643         case RT5665_PWR_I2S2_2_BIT:
2644                 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2645                         RT5665_GP8_PIN_MASK;
2646                 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2647                         RT5665_GP8_PIN_DACDAT2_2;
2648                 mask2 = RT5665_GP9_PIN_MASK;
2649                 val2 = RT5665_GP9_PIN_ADCDAT2_2;
2650                 break;
2651         case RT5665_PWR_I2S3_BIT:
2652                 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
2653                         RT5665_GP8_PIN_MASK;
2654                 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
2655                         RT5665_GP8_PIN_DACDAT3;
2656                 mask2 = RT5665_GP9_PIN_MASK;
2657                 val2 = RT5665_GP9_PIN_ADCDAT3;
2658                 break;
2659         }
2660         switch (event) {
2661         case SND_SOC_DAPM_PRE_PMU:
2662                 if (mask1)
2663                         snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1,
2664                                             mask1, val1);
2665                 if (mask2)
2666                         snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2667                                             mask2, val2);
2668                 break;
2669         case SND_SOC_DAPM_POST_PMD:
2670                 if (mask1)
2671                         snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1,
2672                                             mask1, 0);
2673                 if (mask2)
2674                         snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2675                                             mask2, 0);
2676                 break;
2677         default:
2678                 return 0;
2679         }
2680
2681         return 0;
2682 }
2683
2684 static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2685         SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2686                 NULL, 0),
2687         SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2688                 NULL, 0),
2689         SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2690                 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2691         SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2692                 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2693         SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2694                 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2695         SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2696                 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2697
2698         /* ASRC */
2699         SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2700                 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2701         SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2702                 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2703         SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2704                 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2705         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2706                 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2707         SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2708                 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2709         SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2710                 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2711         SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2712                 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2713         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2714                 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2715         SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
2716                 RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0),
2717         SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2718                 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2719         SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2720                 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2721         SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2722                 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2723         SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2724                 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2725         SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2726                 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2727         SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2728                 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2729
2730         /* Input Side */
2731         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2732                 0, NULL, 0),
2733         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2734                 0, NULL, 0),
2735         SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2736                 0, NULL, 0),
2737
2738         /* Input Lines */
2739         SND_SOC_DAPM_INPUT("DMIC L1"),
2740         SND_SOC_DAPM_INPUT("DMIC R1"),
2741         SND_SOC_DAPM_INPUT("DMIC L2"),
2742         SND_SOC_DAPM_INPUT("DMIC R2"),
2743
2744         SND_SOC_DAPM_INPUT("IN1P"),
2745         SND_SOC_DAPM_INPUT("IN1N"),
2746         SND_SOC_DAPM_INPUT("IN2P"),
2747         SND_SOC_DAPM_INPUT("IN2N"),
2748         SND_SOC_DAPM_INPUT("IN3P"),
2749         SND_SOC_DAPM_INPUT("IN3N"),
2750         SND_SOC_DAPM_INPUT("IN4P"),
2751         SND_SOC_DAPM_INPUT("IN4N"),
2752
2753         SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2754         SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2755
2756         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2757                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2758         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2759                 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2760         SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2761                 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2762
2763         /* Boost */
2764         SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2765                 0, 0, NULL, 0),
2766         SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2767                 0, 0, NULL, 0),
2768         SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2769                 0, 0, NULL, 0),
2770         SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2771                 0, 0, NULL, 0),
2772         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2773                 0, 0, NULL, 0),
2774         SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2775                 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2776         SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2777                 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2778         SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2779                 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2780         SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2781                 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2782         SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2783                 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2784         SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2785                 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2786         SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2787                 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2788         SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2789                 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2790         SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2791                 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2792
2793
2794         /* Input Volume */
2795         SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2796                 0, NULL, 0),
2797         SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2798                 0, NULL, 0),
2799
2800         /* REC Mixer */
2801         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2802                 ARRAY_SIZE(rt5665_rec1_l_mix)),
2803         SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2804                 ARRAY_SIZE(rt5665_rec1_r_mix)),
2805         SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2806                 ARRAY_SIZE(rt5665_rec2_l_mix)),
2807         SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2808                 ARRAY_SIZE(rt5665_rec2_r_mix)),
2809         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2810                 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2811         SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2812                 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2813         SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2814                 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2815         SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2816                 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2817
2818         /* ADCs */
2819         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2820         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2821         SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2822         SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2823
2824         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2825                 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2826         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2827                 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2828         SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2829                 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2830         SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2831                 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2832         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2833                 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2834         SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2835                 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2836
2837         /* ADC Mux */
2838         SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2839                 &rt5665_sto1_dmic_mux),
2840         SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2841                 &rt5665_sto1_dmic_mux),
2842         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2843                 &rt5665_sto1_adc1l_mux),
2844         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2845                 &rt5665_sto1_adc1r_mux),
2846         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2847                 &rt5665_sto1_adc2l_mux),
2848         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2849                 &rt5665_sto1_adc2r_mux),
2850         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2851                 &rt5665_sto1_adcl_mux),
2852         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2853                 &rt5665_sto1_adcr_mux),
2854         SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2855                 &rt5665_sto1_dd_l_mux),
2856         SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2857                 &rt5665_sto1_dd_r_mux),
2858         SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2859                 &rt5665_mono_adc_l2_mux),
2860         SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2861                 &rt5665_mono_adc_r2_mux),
2862         SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2863                 &rt5665_mono_adc_l1_mux),
2864         SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2865                 &rt5665_mono_adc_r1_mux),
2866         SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2867                 &rt5665_mono_dmic_l_mux),
2868         SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2869                 &rt5665_mono_dmic_r_mux),
2870         SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2871                 &rt5665_mono_adc_l_mux),
2872         SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2873                 &rt5665_mono_adc_r_mux),
2874         SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2875                 &rt5665_mono_dd_l_mux),
2876         SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2877                 &rt5665_mono_dd_r_mux),
2878         SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2879                 &rt5665_sto2_dmic_mux),
2880         SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2881                 &rt5665_sto2_dmic_mux),
2882         SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2883                 &rt5665_sto2_adc1l_mux),
2884         SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2885                 &rt5665_sto2_adc1r_mux),
2886         SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2887                 &rt5665_sto2_adc2l_mux),
2888         SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2889                 &rt5665_sto2_adc2r_mux),
2890         SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2891                 &rt5665_sto2_adcl_mux),
2892         SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2893                 &rt5665_sto2_adcr_mux),
2894         SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2895                 &rt5665_sto2_dd_l_mux),
2896         SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2897                 &rt5665_sto2_dd_r_mux),
2898         /* ADC Mixer */
2899         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2900                 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2901         SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2902                 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2903         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2904                 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2905                 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2906         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2907                 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2908                 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2909         SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2910                 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2911                 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2912         SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2913                 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2914                 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2915         SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2916                 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2917         SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2918                 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2919                 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2920         SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2921                 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2922         SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2923                 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2924                 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2925
2926         /* ADC PGA */
2927         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2928         SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2929         SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2930
2931         /* Digital Interface */
2932         SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2933                 0, NULL, 0),
2934         SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2935                 0, NULL, 0),
2936         SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2937                 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2938                 SND_SOC_DAPM_POST_PMD),
2939         SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2940                 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2941                 SND_SOC_DAPM_POST_PMD),
2942         SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2943                 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2944                 SND_SOC_DAPM_POST_PMD),
2945         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2946         SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2947         SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2948         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2949         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2950         SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2951         SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2952         SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2953         SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2954
2955         SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2956         SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2957         SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2958         SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2959         SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2960         SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2961         SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2962         SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2963
2964         SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2965         SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2966         SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2967         SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2968
2969         /* Digital Interface Select */
2970         SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2971                 &rt5665_if1_1_adc1_mux),
2972         SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2973                 &rt5665_if1_1_adc2_mux),
2974         SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2975                 &rt5665_if1_1_adc3_mux),
2976         SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2977         SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2978                 &rt5665_if1_2_adc1_mux),
2979         SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2980                 &rt5665_if1_2_adc2_mux),
2981         SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2982                 &rt5665_if1_2_adc3_mux),
2983         SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2984                 &rt5665_if1_2_adc4_mux),
2985         SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2986                 &rt5665_tdm1_adc_mux),
2987         SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2988                 &rt5665_tdm1_adc_mux),
2989         SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2990                 &rt5665_tdm1_adc_mux),
2991         SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2992                 &rt5665_tdm1_adc_mux),
2993         SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2994                 &rt5665_tdm2_adc_mux),
2995         SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2996                 &rt5665_tdm2_adc_mux),
2997         SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2998                 &rt5665_tdm2_adc_mux),
2999         SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
3000                 &rt5665_tdm2_adc_mux),
3001         SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
3002                 &rt5665_if2_1_adc_in_mux),
3003         SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
3004                 &rt5665_if2_2_adc_in_mux),
3005         SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
3006                 &rt5665_if3_adc_in_mux),
3007         SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3008                         &rt5665_if1_1_01_adc_swap_mux),
3009         SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3010                         &rt5665_if1_1_01_adc_swap_mux),
3011         SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3012                         &rt5665_if1_1_23_adc_swap_mux),
3013         SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3014                         &rt5665_if1_1_23_adc_swap_mux),
3015         SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3016                         &rt5665_if1_1_45_adc_swap_mux),
3017         SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3018                         &rt5665_if1_1_45_adc_swap_mux),
3019         SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3020                         &rt5665_if1_1_67_adc_swap_mux),
3021         SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3022                         &rt5665_if1_1_67_adc_swap_mux),
3023         SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3024                         &rt5665_if1_2_01_adc_swap_mux),
3025         SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3026                         &rt5665_if1_2_01_adc_swap_mux),
3027         SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3028                         &rt5665_if1_2_23_adc_swap_mux),
3029         SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3030                         &rt5665_if1_2_23_adc_swap_mux),
3031         SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3032                         &rt5665_if1_2_45_adc_swap_mux),
3033         SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3034                         &rt5665_if1_2_45_adc_swap_mux),
3035         SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3036                         &rt5665_if1_2_67_adc_swap_mux),
3037         SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3038                         &rt5665_if1_2_67_adc_swap_mux),
3039         SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3040                         &rt5665_if2_1_dac_swap_mux),
3041         SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3042                         &rt5665_if2_1_adc_swap_mux),
3043         SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3044                         &rt5665_if2_2_dac_swap_mux),
3045         SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3046                         &rt5665_if2_2_adc_swap_mux),
3047         SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3048                         &rt5665_if3_dac_swap_mux),
3049         SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3050                         &rt5665_if3_adc_swap_mux),
3051
3052         /* Audio Interface */
3053         SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
3054                                 0, SND_SOC_NOPM, 0, 0),
3055         SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
3056                                 1, SND_SOC_NOPM, 0, 0),
3057         SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
3058                                 2, SND_SOC_NOPM, 0, 0),
3059         SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
3060                                 3, SND_SOC_NOPM, 0, 0),
3061         SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
3062                                 4, SND_SOC_NOPM, 0, 0),
3063         SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
3064                                 5, SND_SOC_NOPM, 0, 0),
3065         SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
3066                                 6, SND_SOC_NOPM, 0, 0),
3067         SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
3068                                 7, SND_SOC_NOPM, 0, 0),
3069         SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
3070                                 0, SND_SOC_NOPM, 0, 0),
3071         SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
3072                                 1, SND_SOC_NOPM, 0, 0),
3073         SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
3074                                 2, SND_SOC_NOPM, 0, 0),
3075         SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
3076                                 3, SND_SOC_NOPM, 0, 0),
3077         SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
3078                                 4, SND_SOC_NOPM, 0, 0),
3079         SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
3080                                 5, SND_SOC_NOPM, 0, 0),
3081         SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
3082                                 6, SND_SOC_NOPM, 0, 0),
3083         SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3084                                 7, SND_SOC_NOPM, 0, 0),
3085         SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3086                                 0, SND_SOC_NOPM, 0, 0),
3087         SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3088                                 0, SND_SOC_NOPM, 0, 0),
3089         SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3090                                 0, SND_SOC_NOPM, 0, 0),
3091         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3092                                 0, SND_SOC_NOPM, 0, 0),
3093         SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3094                                 0, SND_SOC_NOPM, 0, 0),
3095         SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3096                                 0, SND_SOC_NOPM, 0, 0),
3097         SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3098                                 0, SND_SOC_NOPM, 0, 0),
3099
3100         /* Output Side */
3101         /* DAC mixer before sound effect  */
3102         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3103                 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3104         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3105                 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3106
3107         /* DAC channel Mux */
3108         SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3109         SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3110         SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3111         SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3112         SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3113         SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3114
3115         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3116                 &rt5665_alg_dac_l1_mux),
3117         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3118                 &rt5665_alg_dac_r1_mux),
3119         SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3120                 &rt5665_alg_dac_l2_mux),
3121         SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3122                 &rt5665_alg_dac_r2_mux),
3123
3124         /* DAC Mixer */
3125         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3126                 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3127         SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3128                 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3129         SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3130                 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3131         SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3132                 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3133         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3134                 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3135         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3136                 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3137         SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3138                 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3139         SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3140                 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3141         SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3142                 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3143         SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3144                 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3145         SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3146                 &rt5665_dig_dac_mixl_mux),
3147         SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3148                 &rt5665_dig_dac_mixr_mux),
3149
3150         /* DACs */
3151         SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3152         SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3153
3154         SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3155                 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3156         SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3157                 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3158         SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3159         SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3160         SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3161
3162         SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3163                 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3164         SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3165                 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3166
3167         /* OUT Mixer */
3168         SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3169                 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3170         SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3171                 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3172         SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3173                 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3174
3175         /* Output Volume */
3176         SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3177                 &monovol_switch),
3178         SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3179                 &outvol_l_switch),
3180         SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3181                 &outvol_r_switch),
3182
3183         /* MONO/HPO/LOUT */
3184         SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3185                 ARRAY_SIZE(rt5665_mono_mix)),
3186         SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3187                 ARRAY_SIZE(rt5665_lout_l_mix)),
3188         SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3189                 ARRAY_SIZE(rt5665_lout_r_mix)),
3190         SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3191                 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3192                 SND_SOC_DAPM_PRE_PMU),
3193         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3194                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3195         SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3196                 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3197                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3198                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3199
3200         SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3201                 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3202                 SND_SOC_DAPM_POST_PMD),
3203
3204         SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3205                 &mono_switch),
3206         SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3207                 &hpo_switch),
3208         SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3209                 &lout_l_switch),
3210         SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3211                 &lout_r_switch),
3212         SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3213                 &pdm_l_switch),
3214         SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3215                 &pdm_r_switch),
3216
3217         /* PDM */
3218         SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3219                 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3220         SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3221                 0, 1, &rt5665_pdm_l_mux),
3222         SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3223                 0, 1, &rt5665_pdm_r_mux),
3224
3225         /* CLK DET */
3226         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3227                 0, NULL, 0),
3228         SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3229                 0, NULL, 0),
3230         SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3231                 0, NULL, 0),
3232         SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3233                 0, NULL, 0),
3234         SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3235                 0, NULL, 0),
3236
3237         /* Output Lines */
3238         SND_SOC_DAPM_OUTPUT("HPOL"),
3239         SND_SOC_DAPM_OUTPUT("HPOR"),
3240         SND_SOC_DAPM_OUTPUT("LOUTL"),
3241         SND_SOC_DAPM_OUTPUT("LOUTR"),
3242         SND_SOC_DAPM_OUTPUT("MONOOUT"),
3243         SND_SOC_DAPM_OUTPUT("PDML"),
3244         SND_SOC_DAPM_OUTPUT("PDMR"),
3245 };
3246
3247 static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3248         /*PLL*/
3249         {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3250         {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3251         {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3252         {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3253         {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3254         {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3255         {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3256         {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3257
3258         /*ASRC*/
3259         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3260         {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
3261         {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3262         {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3263         {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3264         {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3265         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3266         {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3267         {"I2S1 ASRC", NULL, "CLKDET"},
3268         {"I2S2 ASRC", NULL, "CLKDET"},
3269         {"I2S3 ASRC", NULL, "CLKDET"},
3270
3271         /*Vref*/
3272         {"Mic Det Power", NULL, "Vref2"},
3273         {"MICBIAS1", NULL, "Vref1"},
3274         {"MICBIAS1", NULL, "Vref2"},
3275         {"MICBIAS2", NULL, "Vref1"},
3276         {"MICBIAS2", NULL, "Vref2"},
3277         {"MICBIAS3", NULL, "Vref1"},
3278         {"MICBIAS3", NULL, "Vref2"},
3279
3280         {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3281         {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3282         {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3283         {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3284         {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3285         {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3286
3287         {"I2S1_1", NULL, "I2S1 ASRC"},
3288         {"I2S1_2", NULL, "I2S1 ASRC"},
3289         {"I2S2_1", NULL, "I2S2 ASRC"},
3290         {"I2S2_2", NULL, "I2S2 ASRC"},
3291         {"I2S3", NULL, "I2S3 ASRC"},
3292
3293         {"CLKDET SYS", NULL, "CLKDET"},
3294         {"CLKDET HP", NULL, "CLKDET"},
3295         {"CLKDET MONO", NULL, "CLKDET"},
3296         {"CLKDET LOUT", NULL, "CLKDET"},
3297
3298         {"IN1P", NULL, "LDO2"},
3299         {"IN2P", NULL, "LDO2"},
3300         {"IN3P", NULL, "LDO2"},
3301         {"IN4P", NULL, "LDO2"},
3302
3303         {"DMIC1", NULL, "DMIC L1"},
3304         {"DMIC1", NULL, "DMIC R1"},
3305         {"DMIC2", NULL, "DMIC L2"},
3306         {"DMIC2", NULL, "DMIC R2"},
3307
3308         {"BST1", NULL, "IN1P"},
3309         {"BST1", NULL, "IN1N"},
3310         {"BST1", NULL, "BST1 Power"},
3311         {"BST1", NULL, "BST1P Power"},
3312         {"BST2", NULL, "IN2P"},
3313         {"BST2", NULL, "IN2N"},
3314         {"BST2", NULL, "BST2 Power"},
3315         {"BST2", NULL, "BST2P Power"},
3316         {"BST3", NULL, "IN3P"},
3317         {"BST3", NULL, "IN3N"},
3318         {"BST3", NULL, "BST3 Power"},
3319         {"BST3", NULL, "BST3P Power"},
3320         {"BST4", NULL, "IN4P"},
3321         {"BST4", NULL, "IN4N"},
3322         {"BST4", NULL, "BST4 Power"},
3323         {"BST4", NULL, "BST4P Power"},
3324         {"BST1 CBJ", NULL, "IN1P"},
3325         {"BST1 CBJ", NULL, "IN1N"},
3326         {"BST1 CBJ", NULL, "CBJ Power"},
3327         {"CBJ Power", NULL, "Vref2"},
3328
3329         {"INL VOL", NULL, "IN3P"},
3330         {"INR VOL", NULL, "IN3N"},
3331
3332         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3333         {"RECMIX1L", "INL Switch", "INL VOL"},
3334         {"RECMIX1L", "INR Switch", "INR VOL"},
3335         {"RECMIX1L", "BST4 Switch", "BST4"},
3336         {"RECMIX1L", "BST3 Switch", "BST3"},
3337         {"RECMIX1L", "BST2 Switch", "BST2"},
3338         {"RECMIX1L", "BST1 Switch", "BST1"},
3339         {"RECMIX1L", NULL, "RECMIX1L Power"},
3340
3341         {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3342         {"RECMIX1R", "INR Switch", "INR VOL"},
3343         {"RECMIX1R", "BST4 Switch", "BST4"},
3344         {"RECMIX1R", "BST3 Switch", "BST3"},
3345         {"RECMIX1R", "BST2 Switch", "BST2"},
3346         {"RECMIX1R", "BST1 Switch", "BST1"},
3347         {"RECMIX1R", NULL, "RECMIX1R Power"},
3348
3349         {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3350         {"RECMIX2L", "INL Switch", "INL VOL"},
3351         {"RECMIX2L", "INR Switch", "INR VOL"},
3352         {"RECMIX2L", "BST4 Switch", "BST4"},
3353         {"RECMIX2L", "BST3 Switch", "BST3"},
3354         {"RECMIX2L", "BST2 Switch", "BST2"},
3355         {"RECMIX2L", "BST1 Switch", "BST1"},
3356         {"RECMIX2L", NULL, "RECMIX2L Power"},
3357
3358         {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3359         {"RECMIX2R", "INL Switch", "INL VOL"},
3360         {"RECMIX2R", "INR Switch", "INR VOL"},
3361         {"RECMIX2R", "BST4 Switch", "BST4"},
3362         {"RECMIX2R", "BST3 Switch", "BST3"},
3363         {"RECMIX2R", "BST2 Switch", "BST2"},
3364         {"RECMIX2R", "BST1 Switch", "BST1"},
3365         {"RECMIX2R", NULL, "RECMIX2R Power"},
3366
3367         {"ADC1 L", NULL, "RECMIX1L"},
3368         {"ADC1 L", NULL, "ADC1 L Power"},
3369         {"ADC1 L", NULL, "ADC1 clock"},
3370         {"ADC1 R", NULL, "RECMIX1R"},
3371         {"ADC1 R", NULL, "ADC1 R Power"},
3372         {"ADC1 R", NULL, "ADC1 clock"},
3373
3374         {"ADC2 L", NULL, "RECMIX2L"},
3375         {"ADC2 L", NULL, "ADC2 L Power"},
3376         {"ADC2 L", NULL, "ADC2 clock"},
3377         {"ADC2 R", NULL, "RECMIX2R"},
3378         {"ADC2 R", NULL, "ADC2 R Power"},
3379         {"ADC2 R", NULL, "ADC2 clock"},
3380
3381         {"DMIC L1", NULL, "DMIC CLK"},
3382         {"DMIC L1", NULL, "DMIC1 Power"},
3383         {"DMIC R1", NULL, "DMIC CLK"},
3384         {"DMIC R1", NULL, "DMIC1 Power"},
3385         {"DMIC L2", NULL, "DMIC CLK"},
3386         {"DMIC L2", NULL, "DMIC2 Power"},
3387         {"DMIC R2", NULL, "DMIC CLK"},
3388         {"DMIC R2", NULL, "DMIC2 Power"},
3389
3390         {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3391         {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3392
3393         {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3394         {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3395
3396         {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3397         {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3398
3399         {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3400         {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3401
3402         {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3403         {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3404
3405         {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3406         {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3407
3408         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3409         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3410         {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3411         {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3412         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3413         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3414         {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3415         {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3416
3417         {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3418         {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3419
3420         {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3421         {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3422
3423         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3424         {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3425         {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3426         {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3427
3428         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3429         {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3430         {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3431         {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3432
3433         {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3434         {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3435         {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3436         {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3437
3438         {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3439         {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3440         {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3441         {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3442
3443         {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3444         {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3445
3446         {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3447         {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3448
3449         {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3450         {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3451         {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3452         {"Mono ADC L1 Mux", "ADC",  "Mono ADC L Mux"},
3453
3454         {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3455         {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3456         {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3457         {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3458
3459         {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3460         {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3461         {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3462         {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3463         {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3464         {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3465
3466         {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3467         {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3468
3469         {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3470         {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3471
3472         {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3473         {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3474         {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3475         {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3476
3477         {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3478         {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3479         {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3480         {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3481
3482         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3483         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3484         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3485
3486         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3487         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3488         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3489
3490         {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3491         {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3492         {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3493
3494         {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3495         {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3496         {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3497
3498         {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3499         {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3500         {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3501
3502         {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3503         {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3504         {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3505
3506         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3507         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3508         {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3509         {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3510         {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3511         {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3512
3513         {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3514         {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3515         {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3516         {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3517         {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3518         {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3519         {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3520
3521         {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3522         {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3523         {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3524         {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3525         {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3526         {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3527         {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3528         {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3529
3530         {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3531         {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3532         {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3533         {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3534         {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3535         {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3536         {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3537         {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3538         {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3539         {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3540         {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3541         {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3542         {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3543         {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3544         {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3545         {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3546         {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3547         {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3548         {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3549         {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3550         {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3551         {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3552         {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3553         {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3554         {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3555
3556         {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3557         {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3558         {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3559         {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3560         {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3561         {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3562         {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3563         {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3564         {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3565         {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3566         {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3567         {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3568         {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3569         {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3570         {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3571         {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3572         {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3573         {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3574         {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3575         {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3576         {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3577         {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3578         {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3579         {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3580         {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3581
3582         {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3583         {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3584         {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3585         {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3586         {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3587         {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3588         {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3589         {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3590         {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3591         {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3592         {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3593         {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3594         {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3595         {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3596         {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3597         {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3598         {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3599         {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3600         {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3601         {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3602         {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3603         {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3604         {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3605         {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3606         {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3607
3608         {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3609         {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3610         {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3611         {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3612         {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3613         {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3614         {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3615         {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3616         {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3617         {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3618         {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3619         {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3620         {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3621         {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3622         {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3623         {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3624         {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3625         {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3626         {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3627         {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3628         {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3629         {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3630         {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3631         {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3632         {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3633
3634
3635         {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3636         {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3637         {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3638         {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3639         {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3640         {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3641         {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3642         {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3643         {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3644         {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3645         {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3646         {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3647         {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3648         {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3649         {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3650         {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3651         {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3652         {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3653         {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3654         {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3655         {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3656         {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3657         {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3658         {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3659         {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3660
3661         {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3662         {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3663         {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3664         {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3665         {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3666         {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3667         {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3668         {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3669         {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3670         {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3671         {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3672         {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3673         {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3674         {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3675         {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3676         {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3677         {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3678         {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3679         {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3680         {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3681         {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3682         {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3683         {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3684         {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3685         {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3686
3687         {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3688         {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3689         {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3690         {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3691         {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3692         {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3693         {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3694         {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3695         {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3696         {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3697         {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3698         {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3699         {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3700         {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3701         {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3702         {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3703         {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3704         {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3705         {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3706         {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3707         {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3708         {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3709         {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3710         {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3711         {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3712
3713         {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3714         {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3715         {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3716         {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3717         {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3718         {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3719         {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3720         {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3721         {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3722         {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3723         {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3724         {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3725         {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3726         {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3727         {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3728         {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3729         {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3730         {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3731         {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3732         {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3733         {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3734         {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3735         {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3736         {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3737         {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3738
3739         {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3740         {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3741         {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3742         {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3743         {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3744         {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3745         {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3746         {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3747         {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3748         {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3749         {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3750         {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3751         {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3752         {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3753         {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3754         {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3755         {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3756         {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3757         {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3758         {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3759         {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3760         {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3761         {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3762         {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3763         {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3764         {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3765         {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3766         {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3767         {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3768         {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3769         {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3770         {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3771
3772         {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3773         {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3774         {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3775         {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3776         {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3777         {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3778         {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3779         {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3780         {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3781         {"IF2_1 ADC", NULL, "I2S2_1"},
3782
3783         {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3784         {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3785         {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3786         {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3787         {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3788         {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3789         {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3790         {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3791         {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3792         {"IF2_2 ADC", NULL, "I2S2_2"},
3793
3794         {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3795         {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3796         {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3797         {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3798         {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3799         {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3800         {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3801         {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3802         {"IF3 ADC", NULL, "IF3 ADC Mux"},
3803         {"IF3 ADC", NULL, "I2S3"},
3804
3805         {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3806         {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3807         {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3808         {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3809         {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3810         {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3811         {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3812         {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3813         {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3814         {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3815         {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3816         {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3817         {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3818         {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3819         {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3820         {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3821         {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3822         {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3823         {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3824         {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3825         {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3826         {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3827         {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3828         {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3829         {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3830         {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3831         {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3832         {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3833         {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3834         {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3835         {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3836
3837         {"IF1 DAC1", NULL, "AIF1RX"},
3838         {"IF1 DAC2", NULL, "AIF1RX"},
3839         {"IF1 DAC3", NULL, "AIF1RX"},
3840         {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3841         {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3842         {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3843         {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3844         {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3845         {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3846         {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3847         {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3848         {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3849         {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3850         {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3851         {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3852         {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3853         {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3854         {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3855
3856         {"IF1 DAC1", NULL, "I2S1_1"},
3857         {"IF1 DAC2", NULL, "I2S1_1"},
3858         {"IF1 DAC3", NULL, "I2S1_1"},
3859         {"IF2_1 DAC", NULL, "I2S2_1"},
3860         {"IF2_2 DAC", NULL, "I2S2_2"},
3861         {"IF3 DAC", NULL, "I2S3"},
3862
3863         {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3864         {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3865         {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3866         {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3867         {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3868         {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3869         {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3870         {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3871         {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3872         {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3873         {"IF3 DAC L", NULL, "IF3 DAC"},
3874         {"IF3 DAC R", NULL, "IF3 DAC"},
3875
3876         {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3877         {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3878         {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3879         {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3880         {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3881
3882         {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3883         {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3884         {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3885         {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3886         {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3887
3888         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3889         {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3890         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3891         {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3892
3893         {"DAC1 MIX", NULL, "DAC1 MIXL"},
3894         {"DAC1 MIX", NULL, "DAC1 MIXR"},
3895
3896         {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3897         {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3898         {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3899         {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3900         {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3901         {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3902
3903         {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3904         {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3905         {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3906         {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3907         {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3908         {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3909
3910         {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3911         {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3912         {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3913         {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3914         {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3915         {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3916
3917         {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3918         {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3919         {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3920         {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3921         {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3922         {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3923
3924         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3925         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3926         {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3927         {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3928
3929         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3930         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3931         {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3932         {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3933
3934         {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3935         {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3936         {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3937
3938         {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3939         {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3940         {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3941
3942         {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3943         {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3944         {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3945         {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3946         {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3947         {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3948         {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3949         {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3950
3951         {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3952         {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3953         {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3954         {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3955         {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3956         {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3957
3958         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3959         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3960         {"DAC L1 Source", "DMIC1", "DMIC L1"},
3961         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3962         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3963         {"DAC R1 Source", "DMIC1", "DMIC R1"},
3964
3965         {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3966         {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3967         {"DAC L2 Source", NULL, "DAC L2 Power"},
3968         {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3969         {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3970         {"DAC R2 Source", NULL, "DAC R2 Power"},
3971
3972         {"DAC L1", NULL, "DAC L1 Source"},
3973         {"DAC R1", NULL, "DAC R1 Source"},
3974         {"DAC L2", NULL, "DAC L2 Source"},
3975         {"DAC R2", NULL, "DAC R2 Source"},
3976
3977         {"DAC L1", NULL, "DAC 1 Clock"},
3978         {"DAC R1", NULL, "DAC 1 Clock"},
3979         {"DAC L2", NULL, "DAC 2 Clock"},
3980         {"DAC R2", NULL, "DAC 2 Clock"},
3981
3982         {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3983         {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3984         {"MONOVOL MIX", "BST1 Switch", "BST1"},
3985         {"MONOVOL MIX", "BST2 Switch", "BST2"},
3986         {"MONOVOL MIX", "BST3 Switch", "BST3"},
3987
3988         {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3989         {"OUT MIXL", "INL Switch", "INL VOL"},
3990         {"OUT MIXL", "BST1 Switch", "BST1"},
3991         {"OUT MIXL", "BST2 Switch", "BST2"},
3992         {"OUT MIXL", "BST3 Switch", "BST3"},
3993         {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3994         {"OUT MIXR", "INR Switch", "INR VOL"},
3995         {"OUT MIXR", "BST2 Switch", "BST2"},
3996         {"OUT MIXR", "BST3 Switch", "BST3"},
3997         {"OUT MIXR", "BST4 Switch", "BST4"},
3998
3999         {"MONOVOL", "Switch", "MONOVOL MIX"},
4000         {"Mono MIX", "DAC L2 Switch", "DAC L2"},
4001         {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
4002         {"Mono Amp", NULL, "Mono MIX"},
4003         {"Mono Amp", NULL, "Vref2"},
4004         {"Mono Amp", NULL, "Vref3"},
4005         {"Mono Amp", NULL, "CLKDET SYS"},
4006         {"Mono Amp", NULL, "CLKDET MONO"},
4007         {"Mono Playback", "Switch", "Mono Amp"},
4008         {"MONOOUT", NULL, "Mono Playback"},
4009
4010         {"HP Amp", NULL, "DAC L1"},
4011         {"HP Amp", NULL, "DAC R1"},
4012         {"HP Amp", NULL, "Charge Pump"},
4013         {"HP Amp", NULL, "CLKDET SYS"},
4014         {"HP Amp", NULL, "CLKDET HP"},
4015         {"HP Amp", NULL, "CBJ Power"},
4016         {"HP Amp", NULL, "Vref2"},
4017         {"HPO Playback", "Switch", "HP Amp"},
4018         {"HPOL", NULL, "HPO Playback"},
4019         {"HPOR", NULL, "HPO Playback"},
4020
4021         {"OUTVOL L", "Switch", "OUT MIXL"},
4022         {"OUTVOL R", "Switch", "OUT MIXR"},
4023         {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
4024         {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
4025         {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
4026         {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
4027         {"LOUT Amp", NULL, "LOUT L MIX"},
4028         {"LOUT Amp", NULL, "LOUT R MIX"},
4029         {"LOUT Amp", NULL, "Vref1"},
4030         {"LOUT Amp", NULL, "Vref2"},
4031         {"LOUT Amp", NULL, "CLKDET SYS"},
4032         {"LOUT Amp", NULL, "CLKDET LOUT"},
4033         {"LOUT L Playback", "Switch", "LOUT Amp"},
4034         {"LOUT R Playback", "Switch", "LOUT Amp"},
4035         {"LOUTL", NULL, "LOUT L Playback"},
4036         {"LOUTR", NULL, "LOUT R Playback"},
4037
4038         {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
4039         {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
4040         {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
4041         {"PDM L Mux", NULL, "PDM Power"},
4042         {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
4043         {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
4044         {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
4045         {"PDM R Mux", NULL, "PDM Power"},
4046         {"PDM L Playback", "Switch", "PDM L Mux"},
4047         {"PDM R Playback", "Switch", "PDM R Mux"},
4048         {"PDML", NULL, "PDM L Playback"},
4049         {"PDMR", NULL, "PDM R Playback"},
4050 };
4051
4052 static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4053                         unsigned int rx_mask, int slots, int slot_width)
4054 {
4055         struct snd_soc_codec *codec = dai->codec;
4056         unsigned int val = 0;
4057
4058         if (rx_mask || tx_mask)
4059                 val |= RT5665_I2S1_MODE_TDM;
4060
4061         switch (slots) {
4062         case 4:
4063                 val |= RT5665_TDM_IN_CH_4;
4064                 val |= RT5665_TDM_OUT_CH_4;
4065                 break;
4066         case 6:
4067                 val |= RT5665_TDM_IN_CH_6;
4068                 val |= RT5665_TDM_OUT_CH_6;
4069                 break;
4070         case 8:
4071                 val |= RT5665_TDM_IN_CH_8;
4072                 val |= RT5665_TDM_OUT_CH_8;
4073                 break;
4074         case 2:
4075                 break;
4076         default:
4077                 return -EINVAL;
4078         }
4079
4080         switch (slot_width) {
4081         case 20:
4082                 val |= RT5665_TDM_IN_LEN_20;
4083                 val |= RT5665_TDM_OUT_LEN_20;
4084                 break;
4085         case 24:
4086                 val |= RT5665_TDM_IN_LEN_24;
4087                 val |= RT5665_TDM_OUT_LEN_24;
4088                 break;
4089         case 32:
4090                 val |= RT5665_TDM_IN_LEN_32;
4091                 val |= RT5665_TDM_OUT_LEN_32;
4092                 break;
4093         case 16:
4094                 break;
4095         default:
4096                 return -EINVAL;
4097         }
4098
4099         snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4100                 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4101                 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4102                 RT5665_TDM_OUT_LEN_MASK, val);
4103
4104         return 0;
4105 }
4106
4107
4108 static int rt5665_hw_params(struct snd_pcm_substream *substream,
4109         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4110 {
4111         struct snd_soc_codec *codec = dai->codec;
4112         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4113         unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
4114         int pre_div, frame_size;
4115
4116         rt5665->lrck[dai->id] = params_rate(params);
4117         pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4118         if (pre_div < 0) {
4119                 dev_warn(codec->dev, "Force using PLL");
4120                 snd_soc_codec_set_pll(codec, 0, RT5665_PLL1_S_MCLK,
4121                         rt5665->sysclk, rt5665->lrck[dai->id] * 512);
4122                 snd_soc_codec_set_sysclk(codec, RT5665_SCLK_S_PLL1, 0,
4123                         rt5665->lrck[dai->id] * 512, 0);
4124                 pre_div = 1;
4125         }
4126         frame_size = snd_soc_params_to_frame_size(params);
4127         if (frame_size < 0) {
4128                 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4129                 return -EINVAL;
4130         }
4131
4132         dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4133                                 rt5665->lrck[dai->id], pre_div, dai->id);
4134
4135         switch (params_width(params)) {
4136         case 16:
4137                 val_bits = 0x0100;
4138                 break;
4139         case 20:
4140                 val_len |= RT5665_I2S_DL_20;
4141                 val_bits = 0x1300;
4142                 break;
4143         case 24:
4144                 val_len |= RT5665_I2S_DL_24;
4145                 val_bits = 0x2500;
4146                 break;
4147         case 8:
4148                 val_len |= RT5665_I2S_DL_8;
4149                 break;
4150         default:
4151                 return -EINVAL;
4152         }
4153
4154         switch (dai->id) {
4155         case RT5665_AIF1_1:
4156         case RT5665_AIF1_2:
4157                 if (params_channels(params) > 2)
4158                         rt5665_set_tdm_slot(dai, 0xf, 0xf,
4159                                 params_channels(params), params_width(params));
4160                 reg_clk = RT5665_ADDA_CLK_1;
4161                 mask_clk = RT5665_I2S_PD1_MASK;
4162                 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4163                 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4164                         RT5665_I2S_DL_MASK, val_len);
4165                 break;
4166         case RT5665_AIF2_1:
4167         case RT5665_AIF2_2:
4168                 reg_clk = RT5665_ADDA_CLK_2;
4169                 mask_clk = RT5665_I2S_PD2_MASK;
4170                 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4171                 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4172                         RT5665_I2S_DL_MASK, val_len);
4173                 break;
4174         case RT5665_AIF3:
4175                 reg_clk = RT5665_ADDA_CLK_2;
4176                 mask_clk = RT5665_I2S_PD3_MASK;
4177                 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4178                 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4179                         RT5665_I2S_DL_MASK, val_len);
4180                 break;
4181         default:
4182                 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4183                 return -EINVAL;
4184         }
4185
4186         snd_soc_update_bits(codec, reg_clk, mask_clk, val_clk);
4187         snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4188
4189         switch (rt5665->lrck[dai->id]) {
4190         case 192000:
4191                 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4192                         RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4193                         RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4194                 break;
4195         case 96000:
4196                 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4197                         RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4198                         RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4199                 break;
4200         default:
4201                 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4202                         RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4203                         RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4204                 break;
4205         }
4206
4207         if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
4208                 snd_soc_update_bits(codec, RT5665_I2S_M_CLK_CTRL_1,
4209                         RT5665_I2S2_M_PD_MASK, pre_div << RT5665_I2S2_M_PD_SFT);
4210         }
4211         if (rt5665->master[RT5665_AIF3]) {
4212                 snd_soc_update_bits(codec, RT5665_I2S_M_CLK_CTRL_1,
4213                         RT5665_I2S3_M_PD_MASK, pre_div << RT5665_I2S3_M_PD_SFT);
4214         }
4215
4216         return 0;
4217 }
4218
4219 static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4220 {
4221         struct snd_soc_codec *codec = dai->codec;
4222         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4223         unsigned int reg_val = 0;
4224
4225         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4226         case SND_SOC_DAIFMT_CBM_CFM:
4227                 rt5665->master[dai->id] = 1;
4228                 break;
4229         case SND_SOC_DAIFMT_CBS_CFS:
4230                 reg_val |= RT5665_I2S_MS_S;
4231                 rt5665->master[dai->id] = 0;
4232                 break;
4233         default:
4234                 return -EINVAL;
4235         }
4236
4237         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4238         case SND_SOC_DAIFMT_NB_NF:
4239                 break;
4240         case SND_SOC_DAIFMT_IB_NF:
4241                 reg_val |= RT5665_I2S_BP_INV;
4242                 break;
4243         default:
4244                 return -EINVAL;
4245         }
4246
4247         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4248         case SND_SOC_DAIFMT_I2S:
4249                 break;
4250         case SND_SOC_DAIFMT_LEFT_J:
4251                 reg_val |= RT5665_I2S_DF_LEFT;
4252                 break;
4253         case SND_SOC_DAIFMT_DSP_A:
4254                 reg_val |= RT5665_I2S_DF_PCM_A;
4255                 break;
4256         case SND_SOC_DAIFMT_DSP_B:
4257                 reg_val |= RT5665_I2S_DF_PCM_B;
4258                 break;
4259         default:
4260                 return -EINVAL;
4261         }
4262
4263         switch (dai->id) {
4264         case RT5665_AIF1_1:
4265         case RT5665_AIF1_2:
4266                 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4267                         RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4268                         RT5665_I2S_DF_MASK, reg_val);
4269                 break;
4270         case RT5665_AIF2_1:
4271         case RT5665_AIF2_2:
4272                 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4273                         RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4274                         RT5665_I2S_DF_MASK, reg_val);
4275                 break;
4276         case RT5665_AIF3:
4277                 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4278                         RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4279                         RT5665_I2S_DF_MASK, reg_val);
4280                 break;
4281         default:
4282                 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4283                 return -EINVAL;
4284         }
4285         return 0;
4286 }
4287
4288 static int rt5665_set_codec_sysclk(struct snd_soc_codec *codec, int clk_id,
4289                                    int source, unsigned int freq, int dir)
4290 {
4291         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4292         unsigned int reg_val = 0, src = 0;
4293
4294         if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4295                 return 0;
4296
4297         switch (clk_id) {
4298         case RT5665_SCLK_S_MCLK:
4299                 reg_val |= RT5665_SCLK_SRC_MCLK;
4300                 src = RT5665_CLK_SRC_MCLK;
4301                 break;
4302         case RT5665_SCLK_S_PLL1:
4303                 reg_val |= RT5665_SCLK_SRC_PLL1;
4304                 src = RT5665_CLK_SRC_PLL1;
4305                 break;
4306         case RT5665_SCLK_S_RCCLK:
4307                 reg_val |= RT5665_SCLK_SRC_RCCLK;
4308                 src = RT5665_CLK_SRC_RCCLK;
4309                 break;
4310         default:
4311                 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4312                 return -EINVAL;
4313         }
4314         snd_soc_update_bits(codec, RT5665_GLB_CLK,
4315                 RT5665_SCLK_SRC_MASK, reg_val);
4316
4317         if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
4318                 snd_soc_update_bits(codec, RT5665_I2S_M_CLK_CTRL_1,
4319                         RT5665_I2S2_SRC_MASK, src << RT5665_I2S2_SRC_SFT);
4320         }
4321         if (rt5665->master[RT5665_AIF3]) {
4322                 snd_soc_update_bits(codec, RT5665_I2S_M_CLK_CTRL_1,
4323                         RT5665_I2S3_SRC_MASK, src << RT5665_I2S3_SRC_SFT);
4324         }
4325
4326         rt5665->sysclk = freq;
4327         rt5665->sysclk_src = clk_id;
4328
4329         dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4330
4331         return 0;
4332 }
4333
4334 static int rt5665_set_codec_pll(struct snd_soc_codec *codec, int pll_id,
4335                                 int source, unsigned int freq_in,
4336                                 unsigned int freq_out)
4337 {
4338         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4339         struct rl6231_pll_code pll_code;
4340         int ret;
4341
4342         if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4343             freq_out == rt5665->pll_out)
4344                 return 0;
4345
4346         if (!freq_in || !freq_out) {
4347                 dev_dbg(codec->dev, "PLL disabled\n");
4348
4349                 rt5665->pll_in = 0;
4350                 rt5665->pll_out = 0;
4351                 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4352                         RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4353                 return 0;
4354         }
4355
4356         switch (source) {
4357         case RT5665_PLL1_S_MCLK:
4358                 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4359                         RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4360                 break;
4361         case RT5665_PLL1_S_BCLK1:
4362                 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4363                                 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4364                 break;
4365         case RT5665_PLL1_S_BCLK2:
4366                 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4367                                 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4368                 break;
4369         case RT5665_PLL1_S_BCLK3:
4370                 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4371                                 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4372                 break;
4373         default:
4374                 dev_err(codec->dev, "Unknown PLL Source %d\n", source);
4375                 return -EINVAL;
4376         }
4377
4378         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4379         if (ret < 0) {
4380                 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4381                 return ret;
4382         }
4383
4384         dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4385                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4386                 pll_code.n_code, pll_code.k_code);
4387
4388         snd_soc_write(codec, RT5665_PLL_CTRL_1,
4389                 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4390         snd_soc_write(codec, RT5665_PLL_CTRL_2,
4391                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4392                 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4393
4394         rt5665->pll_in = freq_in;
4395         rt5665->pll_out = freq_out;
4396         rt5665->pll_src = source;
4397
4398         return 0;
4399 }
4400
4401 static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4402 {
4403         struct snd_soc_codec *codec = dai->codec;
4404         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4405
4406         dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4407
4408         rt5665->bclk[dai->id] = ratio;
4409
4410         if (ratio == 64) {
4411                 switch (dai->id) {
4412                 case RT5665_AIF2_1:
4413                 case RT5665_AIF2_2:
4414                         snd_soc_update_bits(codec, RT5665_ADDA_CLK_2,
4415                                 RT5665_I2S_BCLK_MS2_MASK,
4416                                 RT5665_I2S_BCLK_MS2_64);
4417                         break;
4418                 case RT5665_AIF3:
4419                         snd_soc_update_bits(codec, RT5665_ADDA_CLK_2,
4420                                 RT5665_I2S_BCLK_MS3_MASK,
4421                                 RT5665_I2S_BCLK_MS3_64);
4422                         break;
4423                 }
4424         }
4425
4426         return 0;
4427 }
4428
4429 static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4430                         enum snd_soc_bias_level level)
4431 {
4432         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4433
4434         switch (level) {
4435         case SND_SOC_BIAS_PREPARE:
4436                 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4437                         RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4438                 break;
4439
4440         case SND_SOC_BIAS_STANDBY:
4441                 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4442                         RT5665_PWR_LDO, RT5665_PWR_LDO);
4443                 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4444                         RT5665_PWR_MB, RT5665_PWR_MB);
4445                 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4446                         RT5665_DIG_GATE_CTRL, 0);
4447                 break;
4448         case SND_SOC_BIAS_OFF:
4449                 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4450                         RT5665_PWR_LDO, 0);
4451                 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4452                         RT5665_PWR_MB, 0);
4453                 break;
4454
4455         default:
4456                 break;
4457         }
4458
4459         return 0;
4460 }
4461
4462 static int rt5665_probe(struct snd_soc_codec *codec)
4463 {
4464         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4465
4466         rt5665->codec = codec;
4467
4468         schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4469
4470         return 0;
4471 }
4472
4473 static int rt5665_remove(struct snd_soc_codec *codec)
4474 {
4475         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4476
4477         regmap_write(rt5665->regmap, RT5665_RESET, 0);
4478
4479         return 0;
4480 }
4481
4482 #ifdef CONFIG_PM
4483 static int rt5665_suspend(struct snd_soc_codec *codec)
4484 {
4485         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4486
4487         regcache_cache_only(rt5665->regmap, true);
4488         regcache_mark_dirty(rt5665->regmap);
4489         return 0;
4490 }
4491
4492 static int rt5665_resume(struct snd_soc_codec *codec)
4493 {
4494         struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4495
4496         regcache_cache_only(rt5665->regmap, false);
4497         regcache_sync(rt5665->regmap);
4498
4499         return 0;
4500 }
4501 #else
4502 #define rt5665_suspend NULL
4503 #define rt5665_resume NULL
4504 #endif
4505
4506 #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4507 #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4508                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4509
4510 static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4511         .hw_params = rt5665_hw_params,
4512         .set_fmt = rt5665_set_dai_fmt,
4513         .set_tdm_slot = rt5665_set_tdm_slot,
4514         .set_bclk_ratio = rt5665_set_bclk_ratio,
4515 };
4516
4517 static struct snd_soc_dai_driver rt5665_dai[] = {
4518         {
4519                 .name = "rt5665-aif1_1",
4520                 .id = RT5665_AIF1_1,
4521                 .playback = {
4522                         .stream_name = "AIF1 Playback",
4523                         .channels_min = 1,
4524                         .channels_max = 8,
4525                         .rates = RT5665_STEREO_RATES,
4526                         .formats = RT5665_FORMATS,
4527                 },
4528                 .capture = {
4529                         .stream_name = "AIF1_1 Capture",
4530                         .channels_min = 1,
4531                         .channels_max = 8,
4532                         .rates = RT5665_STEREO_RATES,
4533                         .formats = RT5665_FORMATS,
4534                 },
4535                 .ops = &rt5665_aif_dai_ops,
4536         },
4537         {
4538                 .name = "rt5665-aif1_2",
4539                 .id = RT5665_AIF1_2,
4540                 .capture = {
4541                         .stream_name = "AIF1_2 Capture",
4542                         .channels_min = 1,
4543                         .channels_max = 8,
4544                         .rates = RT5665_STEREO_RATES,
4545                         .formats = RT5665_FORMATS,
4546                 },
4547                 .ops = &rt5665_aif_dai_ops,
4548         },
4549         {
4550                 .name = "rt5665-aif2_1",
4551                 .id = RT5665_AIF2_1,
4552                 .playback = {
4553                         .stream_name = "AIF2_1 Playback",
4554                         .channels_min = 1,
4555                         .channels_max = 2,
4556                         .rates = RT5665_STEREO_RATES,
4557                         .formats = RT5665_FORMATS,
4558                 },
4559                 .capture = {
4560                         .stream_name = "AIF2_1 Capture",
4561                         .channels_min = 1,
4562                         .channels_max = 2,
4563                         .rates = RT5665_STEREO_RATES,
4564                         .formats = RT5665_FORMATS,
4565                 },
4566                 .ops = &rt5665_aif_dai_ops,
4567         },
4568         {
4569                 .name = "rt5665-aif2_2",
4570                 .id = RT5665_AIF2_2,
4571                 .playback = {
4572                         .stream_name = "AIF2_2 Playback",
4573                         .channels_min = 1,
4574                         .channels_max = 2,
4575                         .rates = RT5665_STEREO_RATES,
4576                         .formats = RT5665_FORMATS,
4577                 },
4578                 .capture = {
4579                         .stream_name = "AIF2_2 Capture",
4580                         .channels_min = 1,
4581                         .channels_max = 2,
4582                         .rates = RT5665_STEREO_RATES,
4583                         .formats = RT5665_FORMATS,
4584                 },
4585                 .ops = &rt5665_aif_dai_ops,
4586         },
4587         {
4588                 .name = "rt5665-aif3",
4589                 .id = RT5665_AIF3,
4590                 .playback = {
4591                         .stream_name = "AIF3 Playback",
4592                         .channels_min = 1,
4593                         .channels_max = 2,
4594                         .rates = RT5665_STEREO_RATES,
4595                         .formats = RT5665_FORMATS,
4596                 },
4597                 .capture = {
4598                         .stream_name = "AIF3 Capture",
4599                         .channels_min = 1,
4600                         .channels_max = 2,
4601                         .rates = RT5665_STEREO_RATES,
4602                         .formats = RT5665_FORMATS,
4603                 },
4604                 .ops = &rt5665_aif_dai_ops,
4605         },
4606 };
4607
4608 static const struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4609         .probe = rt5665_probe,
4610         .remove = rt5665_remove,
4611         .suspend = rt5665_suspend,
4612         .resume = rt5665_resume,
4613         .set_bias_level = rt5665_set_bias_level,
4614         .idle_bias_off = true,
4615         .component_driver = {
4616                 .controls = rt5665_snd_controls,
4617                 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4618                 .dapm_widgets = rt5665_dapm_widgets,
4619                 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4620                 .dapm_routes = rt5665_dapm_routes,
4621                 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4622         },
4623         .set_sysclk = rt5665_set_codec_sysclk,
4624         .set_pll = rt5665_set_codec_pll,
4625         .set_jack = rt5665_set_jack_detect,
4626 };
4627
4628
4629 static const struct regmap_config rt5665_regmap = {
4630         .reg_bits = 16,
4631         .val_bits = 16,
4632         .max_register = 0x0400,
4633         .volatile_reg = rt5665_volatile_register,
4634         .readable_reg = rt5665_readable_register,
4635         .cache_type = REGCACHE_RBTREE,
4636         .reg_defaults = rt5665_reg,
4637         .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4638         .use_single_rw = true,
4639 };
4640
4641 static const struct i2c_device_id rt5665_i2c_id[] = {
4642         {"rt5665", 0},
4643         {}
4644 };
4645 MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4646
4647 static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4648 {
4649         rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4650                                         "realtek,in1-differential");
4651         rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4652                                         "realtek,in2-differential");
4653         rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4654                                         "realtek,in3-differential");
4655         rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4656                                         "realtek,in4-differential");
4657
4658         of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4659                 &rt5665->pdata.dmic1_data_pin);
4660         of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4661                 &rt5665->pdata.dmic2_data_pin);
4662         of_property_read_u32(dev->of_node, "realtek,jd-src",
4663                 &rt5665->pdata.jd_src);
4664
4665         rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4666                 "realtek,ldo1-en-gpios", 0);
4667
4668         return 0;
4669 }
4670
4671 static void rt5665_calibrate(struct rt5665_priv *rt5665)
4672 {
4673         int value, count;
4674
4675         mutex_lock(&rt5665->calibrate_mutex);
4676
4677         regcache_cache_bypass(rt5665->regmap, true);
4678
4679         regmap_write(rt5665->regmap, RT5665_RESET, 0);
4680         regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4681         regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4682         regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4683         regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4684         regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4685         regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4686         regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4687         regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4688         regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4689         regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4690         regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4691         regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4692         regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4693         regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4694         regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4695         usleep_range(15000, 20000);
4696         regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4697         regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4698
4699         regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4700         count = 0;
4701         while (true) {
4702                 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4703                 if (value & 0x8000)
4704                         usleep_range(10000, 10005);
4705                 else
4706                         break;
4707
4708                 if (count > 60) {
4709                         pr_err("HP Calibration Failure\n");
4710                         regmap_write(rt5665->regmap, RT5665_RESET, 0);
4711                         regcache_cache_bypass(rt5665->regmap, false);
4712                         goto out_unlock;
4713                 }
4714
4715                 count++;
4716         }
4717
4718         regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4719         count = 0;
4720         while (true) {
4721                 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4722                 if (value & 0x8000)
4723                         usleep_range(10000, 10005);
4724                 else
4725                         break;
4726
4727                 if (count > 60) {
4728                         pr_err("MONO Calibration Failure\n");
4729                         regmap_write(rt5665->regmap, RT5665_RESET, 0);
4730                         regcache_cache_bypass(rt5665->regmap, false);
4731                         goto out_unlock;
4732                 }
4733
4734                 count++;
4735         }
4736
4737         regmap_write(rt5665->regmap, RT5665_RESET, 0);
4738         regcache_cache_bypass(rt5665->regmap, false);
4739
4740         regcache_mark_dirty(rt5665->regmap);
4741         regcache_sync(rt5665->regmap);
4742
4743         regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4744         regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4745
4746 out_unlock:
4747         rt5665->calibration_done = true;
4748         mutex_unlock(&rt5665->calibrate_mutex);
4749 }
4750
4751 static void rt5665_calibrate_handler(struct work_struct *work)
4752 {
4753         struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4754                 calibrate_work.work);
4755
4756         while (!rt5665->codec->component.card->instantiated) {
4757                 pr_debug("%s\n", __func__);
4758                 usleep_range(10000, 15000);
4759         }
4760
4761         rt5665_calibrate(rt5665);
4762 }
4763
4764 static int rt5665_i2c_probe(struct i2c_client *i2c,
4765                     const struct i2c_device_id *id)
4766 {
4767         struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4768         struct rt5665_priv *rt5665;
4769         int i, ret;
4770         unsigned int val;
4771
4772         rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4773                 GFP_KERNEL);
4774
4775         if (rt5665 == NULL)
4776                 return -ENOMEM;
4777
4778         i2c_set_clientdata(i2c, rt5665);
4779
4780         if (pdata)
4781                 rt5665->pdata = *pdata;
4782         else
4783                 rt5665_parse_dt(rt5665, &i2c->dev);
4784
4785         for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4786                 rt5665->supplies[i].supply = rt5665_supply_names[i];
4787
4788         ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4789                                       rt5665->supplies);
4790         if (ret != 0) {
4791                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4792                 return ret;
4793         }
4794
4795         ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4796                                     rt5665->supplies);
4797         if (ret != 0) {
4798                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4799                 return ret;
4800         }
4801
4802         if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
4803                 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4804                                           GPIOF_OUT_INIT_HIGH, "rt5665"))
4805                         dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
4806         }
4807
4808         /* Sleep for 300 ms miniumum */
4809         usleep_range(300000, 350000);
4810
4811         rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4812         if (IS_ERR(rt5665->regmap)) {
4813                 ret = PTR_ERR(rt5665->regmap);
4814                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4815                         ret);
4816                 return ret;
4817         }
4818
4819         regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4820         if (val != DEVICE_ID) {
4821                 dev_err(&i2c->dev,
4822                         "Device with ID register %x is not rt5665\n", val);
4823                 return -ENODEV;
4824         }
4825
4826         regmap_read(rt5665->regmap, RT5665_RESET, &val);
4827         switch (val) {
4828         case 0x0:
4829                 rt5665->id = CODEC_5666;
4830                 break;
4831         case 0x6:
4832                 rt5665->id = CODEC_5668;
4833                 break;
4834         case 0x3:
4835         default:
4836                 rt5665->id = CODEC_5665;
4837                 break;
4838         }
4839
4840         regmap_write(rt5665->regmap, RT5665_RESET, 0);
4841
4842         /* line in diff mode*/
4843         if (rt5665->pdata.in1_diff)
4844                 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4845                         RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4846         if (rt5665->pdata.in2_diff)
4847                 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4848                         RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4849         if (rt5665->pdata.in3_diff)
4850                 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4851                         RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4852         if (rt5665->pdata.in4_diff)
4853                 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4854                         RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4855
4856         /* DMIC pin*/
4857         if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4858                 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4859                 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4860                         RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4861                 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4862                                 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4863                 switch (rt5665->pdata.dmic1_data_pin) {
4864                 case RT5665_DMIC1_DATA_IN2N:
4865                         regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4866                                 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4867                         break;
4868
4869                 case RT5665_DMIC1_DATA_GPIO4:
4870                         regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4871                                 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4872                         regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4873                                 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4874                         break;
4875
4876                 default:
4877                         dev_dbg(&i2c->dev, "no DMIC1\n");
4878                         break;
4879                 }
4880
4881                 switch (rt5665->pdata.dmic2_data_pin) {
4882                 case RT5665_DMIC2_DATA_IN2P:
4883                         regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4884                                 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4885                         break;
4886
4887                 case RT5665_DMIC2_DATA_GPIO5:
4888                         regmap_update_bits(rt5665->regmap,
4889                                 RT5665_DMIC_CTRL_1,
4890                                 RT5665_DMIC_2_DP_MASK,
4891                                 RT5665_DMIC_2_DP_GPIO5);
4892                         regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4893                                 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4894                         break;
4895
4896                 default:
4897                         dev_dbg(&i2c->dev, "no DMIC2\n");
4898                         break;
4899
4900                 }
4901         }
4902
4903         regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4904         regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4905                 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
4906         /* Work around for pow_pump */
4907         regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4908                 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4909
4910         regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4911                 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4912
4913         /* Set GPIO4,8 as input for combo jack */
4914         if (rt5665->id == CODEC_5666) {
4915                 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4916                         RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4917                 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4918                         RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4919         }
4920
4921         /* Enhance performance*/
4922         regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4923                 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4924                 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
4925
4926         INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4927                                 rt5665_jack_detect_handler);
4928         INIT_DELAYED_WORK(&rt5665->calibrate_work,
4929                                 rt5665_calibrate_handler);
4930         INIT_DELAYED_WORK(&rt5665->jd_check_work,
4931                                 rt5665_jd_check_handler);
4932
4933         mutex_init(&rt5665->calibrate_mutex);
4934
4935         if (i2c->irq) {
4936                 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4937                         rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4938                         | IRQF_ONESHOT, "rt5665", rt5665);
4939                 if (ret)
4940                         dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4941
4942         }
4943
4944         return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4945                         rt5665_dai, ARRAY_SIZE(rt5665_dai));
4946 }
4947
4948 static int rt5665_i2c_remove(struct i2c_client *i2c)
4949 {
4950         snd_soc_unregister_codec(&i2c->dev);
4951
4952         return 0;
4953 }
4954
4955 static void rt5665_i2c_shutdown(struct i2c_client *client)
4956 {
4957         struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4958
4959         regmap_write(rt5665->regmap, RT5665_RESET, 0);
4960 }
4961
4962 #ifdef CONFIG_OF
4963 static const struct of_device_id rt5665_of_match[] = {
4964         {.compatible = "realtek,rt5665"},
4965         {.compatible = "realtek,rt5666"},
4966         {.compatible = "realtek,rt5668"},
4967         {},
4968 };
4969 MODULE_DEVICE_TABLE(of, rt5665_of_match);
4970 #endif
4971
4972 #ifdef CONFIG_ACPI
4973 static const struct acpi_device_id rt5665_acpi_match[] = {
4974         {"10EC5665", 0,},
4975         {"10EC5666", 0,},
4976         {"10EC5668", 0,},
4977         {},
4978 };
4979 MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4980 #endif
4981
4982 static struct i2c_driver rt5665_i2c_driver = {
4983         .driver = {
4984                 .name = "rt5665",
4985                 .of_match_table = of_match_ptr(rt5665_of_match),
4986                 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4987         },
4988         .probe = rt5665_i2c_probe,
4989         .remove = rt5665_i2c_remove,
4990         .shutdown = rt5665_i2c_shutdown,
4991         .id_table = rt5665_i2c_id,
4992 };
4993 module_i2c_driver(rt5665_i2c_driver);
4994
4995 MODULE_DESCRIPTION("ASoC RT5665 driver");
4996 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4997 MODULE_LICENSE("GPL v2");