?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / sound / soc / codecs / tlv320aic3x.c
blob06f92571eba4622a89ae808911fd0b510ec2eed2
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/of.h>
44 #include <linux/of_gpio.h>
45 #include <linux/slab.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/soc.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
53
54 #include "tlv320aic3x.h"
55
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62 };
63
64 static LIST_HEAD(reset_list);
65
66 struct aic3x_priv;
67
68 struct aic3x_disable_nb {
69 struct notifier_block nb;
70 struct aic3x_priv *aic3x;
71 };
72
73 /* codec private data */
74 struct aic3x_priv {
75 struct snd_soc_codec *codec;
76 struct regmap *regmap;
77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
79 struct aic3x_setup_data *setup;
80 unsigned int sysclk;
81 unsigned int dai_fmt;
82 unsigned int tdm_delay;
83 unsigned int slot_width;
84 struct list_head list;
85 int master;
86 int gpio_reset;
87 int power;
88 #define AIC3X_MODEL_3X 0
89 #define AIC3X_MODEL_33 1
90 #define AIC3X_MODEL_3007 2
91 #define AIC3X_MODEL_3104 3
92 u16 model;
93
94 /* Selects the micbias voltage */
95 enum aic3x_micbias_voltage micbias_vg;
96 /* Output Common-Mode Voltage */
97 u8 ocmv;
98 };
99
100 static const struct reg_default aic3x_reg[] = {
101 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
102 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
103 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
104 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
105 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
106 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
107 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
108 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
109 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
110 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
111 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
112 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
113 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
114 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
115 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
116 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
117 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
118 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
119 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
120 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
121 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
122 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
123 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
124 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
125 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
126 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
127 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
128 { 108, 0x00 }, { 109, 0x00 },
129 };
130
131 static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)
132 {
133 switch (reg) {
134 case AIC3X_RESET:
135 return true;
136 default:
137 return false;
138 }
139 }
140
141 static const struct regmap_config aic3x_regmap = {
142 .reg_bits = 8,
143 .val_bits = 8,
144
145 .max_register = DAC_ICC_ADJ,
146 .reg_defaults = aic3x_reg,
147 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
148
149 .volatile_reg = aic3x_volatile_reg,
150
151 .cache_type = REGCACHE_RBTREE,
152 };
153
154 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
155 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
156 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
157
158 /*
159 * All input lines are connected when !0xf and disconnected with 0xf bit field,
160 * so we have to use specific dapm_put call for input mixer
161 */
162 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
163 struct snd_ctl_elem_value *ucontrol)
164 {
165 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
166 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
167 struct soc_mixer_control *mc =
168 (struct soc_mixer_control *)kcontrol->private_value;
169 unsigned int reg = mc->reg;
170 unsigned int shift = mc->shift;
171 int max = mc->max;
172 unsigned int mask = (1 << fls(max)) - 1;
173 unsigned int invert = mc->invert;
174 unsigned short val;
175 struct snd_soc_dapm_update update = { 0 };
176 int connect, change;
177
178 val = (ucontrol->value.integer.value[0] & mask);
179
180 mask = 0xf;
181 if (val)
182 val = mask;
183
184 connect = !!val;
185
186 if (invert)
187 val = mask - val;
188
189 mask <<= shift;
190 val <<= shift;
191
192 change = snd_soc_test_bits(codec, reg, mask, val);
193 if (change) {
194 update.kcontrol = kcontrol;
195 update.reg = reg;
196 update.mask = mask;
197 update.val = val;
198
199 snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect,
200 &update);
201 }
202
203 return change;
204 }
205
206 /*
207 * mic bias power on/off share the same register bits with
208 * output voltage of mic bias. when power on mic bias, we
209 * need reclaim it to voltage value.
210 * 0x0 = Powered off
211 * 0x1 = MICBIAS output is powered to 2.0V,
212 * 0x2 = MICBIAS output is powered to 2.5V
213 * 0x3 = MICBIAS output is connected to AVDD
214 */
215 static int mic_bias_event(struct snd_soc_dapm_widget *w,
216 struct snd_kcontrol *kcontrol, int event)
217 {
218 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
219 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
220
221 switch (event) {
222 case SND_SOC_DAPM_POST_PMU:
223 /* change mic bias voltage to user defined */
224 snd_soc_update_bits(codec, MICBIAS_CTRL,
225 MICBIAS_LEVEL_MASK,
226 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
227 break;
228
229 case SND_SOC_DAPM_PRE_PMD:
230 snd_soc_update_bits(codec, MICBIAS_CTRL,
231 MICBIAS_LEVEL_MASK, 0);
232 break;
233 }
234 return 0;
235 }
236
237 static const char * const aic3x_left_dac_mux[] = {
238 "DAC_L1", "DAC_L3", "DAC_L2" };
239 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
240 aic3x_left_dac_mux);
241
242 static const char * const aic3x_right_dac_mux[] = {
243 "DAC_R1", "DAC_R3", "DAC_R2" };
244 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
245 aic3x_right_dac_mux);
246
247 static const char * const aic3x_left_hpcom_mux[] = {
248 "differential of HPLOUT", "constant VCM", "single-ended" };
249 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
250 aic3x_left_hpcom_mux);
251
252 static const char * const aic3x_right_hpcom_mux[] = {
253 "differential of HPROUT", "constant VCM", "single-ended",
254 "differential of HPLCOM", "external feedback" };
255 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
256 aic3x_right_hpcom_mux);
257
258 static const char * const aic3x_linein_mode_mux[] = {
259 "single-ended", "differential" };
260 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
261 aic3x_linein_mode_mux);
262 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
263 aic3x_linein_mode_mux);
264 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
265 aic3x_linein_mode_mux);
266 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
267 aic3x_linein_mode_mux);
268 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
269 aic3x_linein_mode_mux);
270 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
271 aic3x_linein_mode_mux);
272
273 static const char * const aic3x_adc_hpf[] = {
274 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
275 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
276 aic3x_adc_hpf);
277
278 static const char * const aic3x_agc_level[] = {
279 "-5.5dB", "-8dB", "-10dB", "-12dB",
280 "-14dB", "-17dB", "-20dB", "-24dB" };
281 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
282 aic3x_agc_level);
283 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
284 aic3x_agc_level);
285
286 static const char * const aic3x_agc_attack[] = {
287 "8ms", "11ms", "16ms", "20ms" };
288 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
289 aic3x_agc_attack);
290 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
291 aic3x_agc_attack);
292
293 static const char * const aic3x_agc_decay[] = {
294 "100ms", "200ms", "400ms", "500ms" };
295 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
296 aic3x_agc_decay);
297 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
298 aic3x_agc_decay);
299
300 static const char * const aic3x_poweron_time[] = {
301 "0us", "10us", "100us", "1ms", "10ms", "50ms",
302 "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
303 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
304 aic3x_poweron_time);
305
306 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
307 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2,
308 aic3x_rampup_step);
309
310 /*
311 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
312 */
313 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
314 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
315 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
316 /*
317 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
318 * Step size is approximately 0.5 dB over most of the scale but increasing
319 * near the very low levels.
320 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
321 * but having increasing dB difference below that (and where it doesn't count
322 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
323 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
324 */
325 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
326
327 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
328 /* Output */
329 SOC_DOUBLE_R_TLV("PCM Playback Volume",
330 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
331
332 /*
333 * Output controls that map to output mixer switches. Note these are
334 * only for swapped L-to-R and R-to-L routes. See below stereo controls
335 * for direct L-to-L and R-to-R routes.
336 */
337 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
338 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
340 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
341
342 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
343 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
344 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
345 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
346
347 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
348 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
349 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
350 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
351
352 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
353 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
354 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
355 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
356
357 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
358 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
359 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
360 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
361
362 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
363 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
364 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
365 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
366
367 /* Stereo output controls for direct L-to-L and R-to-R routes */
368 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
369 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
370 0, 118, 1, output_stage_tlv),
371 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
372 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
373 0, 118, 1, output_stage_tlv),
374
375 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
376 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
377 0, 118, 1, output_stage_tlv),
378 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
379 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
380 0, 118, 1, output_stage_tlv),
381
382 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
383 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
384 0, 118, 1, output_stage_tlv),
385 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
386 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
387 0, 118, 1, output_stage_tlv),
388
389 /* Output pin mute controls */
390 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
391 0x01, 0),
392 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
393 0x01, 0),
394 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
395 0x01, 0),
396
397 /*
398 * Note: enable Automatic input Gain Controller with care. It can
399 * adjust PGA to max value when ADC is on and will never go back.
400 */
401 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
402 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
403 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
404 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
405 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
406 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
407 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
408
409 /* De-emphasis */
410 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
411
412 /* Input */
413 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
414 0, 119, 0, adc_tlv),
415 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
416
417 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
418
419 /* Pop reduction */
420 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
421 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
422 };
423
424 /* For other than tlv320aic3104 */
425 static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = {
426 /*
427 * Output controls that map to output mixer switches. Note these are
428 * only for swapped L-to-R and R-to-L routes. See below stereo controls
429 * for direct L-to-L and R-to-R routes.
430 */
431 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
432 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
433
434 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
435 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
436
437 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
438 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
439
440 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
441 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
442
443 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
444 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
445
446 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
447 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
448
449 /* Stereo output controls for direct L-to-L and R-to-R routes */
450 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
451 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
452 0, 118, 1, output_stage_tlv),
453
454 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
455 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
456 0, 118, 1, output_stage_tlv),
457
458 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
459 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
460 0, 118, 1, output_stage_tlv),
461 };
462
463 static const struct snd_kcontrol_new aic3x_mono_controls[] = {
464 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
465 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
466 0, 118, 1, output_stage_tlv),
467 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
468 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
469 0, 118, 1, output_stage_tlv),
470 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
471 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
472 0, 118, 1, output_stage_tlv),
473
474 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
475 };
476
477 /*
478 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
479 */
480 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
481
482 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
483 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
484
485 /* Left DAC Mux */
486 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
487 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
488
489 /* Right DAC Mux */
490 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
491 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
492
493 /* Left HPCOM Mux */
494 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
495 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
496
497 /* Right HPCOM Mux */
498 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
499 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
500
501 /* Left Line Mixer */
502 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
503 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
504 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
505 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
506 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
507 /* Not on tlv320aic3104 */
508 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
509 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
510 };
511
512 /* Right Line Mixer */
513 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
514 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
515 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
516 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
517 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
518 /* Not on tlv320aic3104 */
519 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
520 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
521 };
522
523 /* Mono Mixer */
524 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
525 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
526 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
527 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
528 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
529 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
530 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
531 };
532
533 /* Left HP Mixer */
534 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
535 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
536 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
537 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
538 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
539 /* Not on tlv320aic3104 */
540 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
541 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
542 };
543
544 /* Right HP Mixer */
545 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
546 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
547 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
548 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
549 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
550 /* Not on tlv320aic3104 */
551 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
552 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
553 };
554
555 /* Left HPCOM Mixer */
556 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
557 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
558 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
559 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
560 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
561 /* Not on tlv320aic3104 */
562 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
563 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
564 };
565
566 /* Right HPCOM Mixer */
567 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
568 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
569 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
570 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
571 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
572 /* Not on tlv320aic3104 */
573 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
574 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
575 };
576
577 /* Left PGA Mixer */
578 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
579 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
580 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
581 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
582 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
583 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
584 };
585
586 /* Right PGA Mixer */
587 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
588 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
589 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
590 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
591 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
592 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
593 };
594
595 /* Left PGA Mixer for tlv320aic3104 */
596 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = {
597 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
598 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
599 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
600 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
601 };
602
603 /* Right PGA Mixer for tlv320aic3104 */
604 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = {
605 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
606 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
607 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
608 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
609 };
610
611 /* Left Line1 Mux */
612 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
613 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
614 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
615 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
616
617 /* Right Line1 Mux */
618 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
619 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
620 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
621 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
622
623 /* Left Line2 Mux */
624 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
625 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
626
627 /* Right Line2 Mux */
628 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
629 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
630
631 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
632 /* Left DAC to Left Outputs */
633 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
634 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
635 &aic3x_left_dac_mux_controls),
636 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
637 &aic3x_left_hpcom_mux_controls),
638 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
639 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
640 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
641
642 /* Right DAC to Right Outputs */
643 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
644 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
645 &aic3x_right_dac_mux_controls),
646 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
647 &aic3x_right_hpcom_mux_controls),
648 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
649 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
650 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
651
652 /* Inputs to Left ADC */
653 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
654 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
655 &aic3x_left_line1l_mux_controls),
656 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
657 &aic3x_left_line1r_mux_controls),
658
659 /* Inputs to Right ADC */
660 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
661 LINE1R_2_RADC_CTRL, 2, 0),
662 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
663 &aic3x_right_line1l_mux_controls),
664 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
665 &aic3x_right_line1r_mux_controls),
666
667 /* Mic Bias */
668 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
669 mic_bias_event,
670 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
671
672 SND_SOC_DAPM_OUTPUT("LLOUT"),
673 SND_SOC_DAPM_OUTPUT("RLOUT"),
674 SND_SOC_DAPM_OUTPUT("HPLOUT"),
675 SND_SOC_DAPM_OUTPUT("HPROUT"),
676 SND_SOC_DAPM_OUTPUT("HPLCOM"),
677 SND_SOC_DAPM_OUTPUT("HPRCOM"),
678
679 SND_SOC_DAPM_INPUT("LINE1L"),
680 SND_SOC_DAPM_INPUT("LINE1R"),
681
682 /*
683 * Virtual output pin to detection block inside codec. This can be
684 * used to keep codec bias on if gpio or detection features are needed.
685 * Force pin on or construct a path with an input jack and mic bias
686 * widgets.
687 */
688 SND_SOC_DAPM_OUTPUT("Detection"),
689 };
690
691 /* For other than tlv320aic3104 */
692 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = {
693 /* Inputs to Left ADC */
694 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
695 &aic3x_left_pga_mixer_controls[0],
696 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
697 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
698 &aic3x_left_line2_mux_controls),
699
700 /* Inputs to Right ADC */
701 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
702 &aic3x_right_pga_mixer_controls[0],
703 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
704 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
705 &aic3x_right_line2_mux_controls),
706
707 /*
708 * Not a real mic bias widget but similar function. This is for dynamic
709 * control of GPIO1 digital mic modulator clock output function when
710 * using digital mic.
711 */
712 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
713 AIC3X_GPIO1_REG, 4, 0xf,
714 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
715 AIC3X_GPIO1_FUNC_DISABLED),
716
717 /*
718 * Also similar function like mic bias. Selects digital mic with
719 * configurable oversampling rate instead of ADC converter.
720 */
721 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
722 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
723 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
724 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
725 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
726 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
727
728 /* Output mixers */
729 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
730 &aic3x_left_line_mixer_controls[0],
731 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
732 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
733 &aic3x_right_line_mixer_controls[0],
734 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
735 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
736 &aic3x_left_hp_mixer_controls[0],
737 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
738 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
739 &aic3x_right_hp_mixer_controls[0],
740 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
741 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
742 &aic3x_left_hpcom_mixer_controls[0],
743 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
744 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
745 &aic3x_right_hpcom_mixer_controls[0],
746 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
747
748 SND_SOC_DAPM_INPUT("MIC3L"),
749 SND_SOC_DAPM_INPUT("MIC3R"),
750 SND_SOC_DAPM_INPUT("LINE2L"),
751 SND_SOC_DAPM_INPUT("LINE2R"),
752 };
753
754 /* For tlv320aic3104 */
755 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = {
756 /* Inputs to Left ADC */
757 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
758 &aic3104_left_pga_mixer_controls[0],
759 ARRAY_SIZE(aic3104_left_pga_mixer_controls)),
760
761 /* Inputs to Right ADC */
762 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
763 &aic3104_right_pga_mixer_controls[0],
764 ARRAY_SIZE(aic3104_right_pga_mixer_controls)),
765
766 /* Output mixers */
767 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
768 &aic3x_left_line_mixer_controls[0],
769 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
770 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
771 &aic3x_right_line_mixer_controls[0],
772 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
773 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
774 &aic3x_left_hp_mixer_controls[0],
775 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
776 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
777 &aic3x_right_hp_mixer_controls[0],
778 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
779 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
780 &aic3x_left_hpcom_mixer_controls[0],
781 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
782 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
783 &aic3x_right_hpcom_mixer_controls[0],
784 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
785
786 SND_SOC_DAPM_INPUT("MIC2L"),
787 SND_SOC_DAPM_INPUT("MIC2R"),
788 };
789
790 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
791 /* Mono Output */
792 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
793
794 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
795 &aic3x_mono_mixer_controls[0],
796 ARRAY_SIZE(aic3x_mono_mixer_controls)),
797
798 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
799 };
800
801 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
802 /* Class-D outputs */
803 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
804 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
805
806 SND_SOC_DAPM_OUTPUT("SPOP"),
807 SND_SOC_DAPM_OUTPUT("SPOM"),
808 };
809
810 static const struct snd_soc_dapm_route intercon[] = {
811 /* Left Input */
812 {"Left Line1L Mux", "single-ended", "LINE1L"},
813 {"Left Line1L Mux", "differential", "LINE1L"},
814 {"Left Line1R Mux", "single-ended", "LINE1R"},
815 {"Left Line1R Mux", "differential", "LINE1R"},
816
817 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
818 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
819
820 {"Left ADC", NULL, "Left PGA Mixer"},
821
822 /* Right Input */
823 {"Right Line1R Mux", "single-ended", "LINE1R"},
824 {"Right Line1R Mux", "differential", "LINE1R"},
825 {"Right Line1L Mux", "single-ended", "LINE1L"},
826 {"Right Line1L Mux", "differential", "LINE1L"},
827
828 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
829 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
830
831 {"Right ADC", NULL, "Right PGA Mixer"},
832
833 /* Left DAC Output */
834 {"Left DAC Mux", "DAC_L1", "Left DAC"},
835 {"Left DAC Mux", "DAC_L2", "Left DAC"},
836 {"Left DAC Mux", "DAC_L3", "Left DAC"},
837
838 /* Right DAC Output */
839 {"Right DAC Mux", "DAC_R1", "Right DAC"},
840 {"Right DAC Mux", "DAC_R2", "Right DAC"},
841 {"Right DAC Mux", "DAC_R3", "Right DAC"},
842
843 /* Left Line Output */
844 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
845 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
846 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
847 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
848
849 {"Left Line Out", NULL, "Left Line Mixer"},
850 {"Left Line Out", NULL, "Left DAC Mux"},
851 {"LLOUT", NULL, "Left Line Out"},
852
853 /* Right Line Output */
854 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
855 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
856 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
857 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
858
859 {"Right Line Out", NULL, "Right Line Mixer"},
860 {"Right Line Out", NULL, "Right DAC Mux"},
861 {"RLOUT", NULL, "Right Line Out"},
862
863 /* Left HP Output */
864 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
865 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
866 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
867 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
868
869 {"Left HP Out", NULL, "Left HP Mixer"},
870 {"Left HP Out", NULL, "Left DAC Mux"},
871 {"HPLOUT", NULL, "Left HP Out"},
872
873 /* Right HP Output */
874 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
875 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
876 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
877 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
878
879 {"Right HP Out", NULL, "Right HP Mixer"},
880 {"Right HP Out", NULL, "Right DAC Mux"},
881 {"HPROUT", NULL, "Right HP Out"},
882
883 /* Left HPCOM Output */
884 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
885 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
886 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
887 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
888
889 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
890 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
891 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
892 {"Left HP Com", NULL, "Left HPCOM Mux"},
893 {"HPLCOM", NULL, "Left HP Com"},
894
895 /* Right HPCOM Output */
896 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
897 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
898 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
899 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
900
901 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
902 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
903 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
904 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
905 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
906 {"Right HP Com", NULL, "Right HPCOM Mux"},
907 {"HPRCOM", NULL, "Right HP Com"},
908 };
909
910 /* For other than tlv320aic3104 */
911 static const struct snd_soc_dapm_route intercon_extra[] = {
912 /* Left Input */
913 {"Left Line2L Mux", "single-ended", "LINE2L"},
914 {"Left Line2L Mux", "differential", "LINE2L"},
915
916 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
917 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
918 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
919
920 {"Left ADC", NULL, "GPIO1 dmic modclk"},
921
922 /* Right Input */
923 {"Right Line2R Mux", "single-ended", "LINE2R"},
924 {"Right Line2R Mux", "differential", "LINE2R"},
925
926 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
927 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
928 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
929
930 {"Right ADC", NULL, "GPIO1 dmic modclk"},
931
932 /*
933 * Logical path between digital mic enable and GPIO1 modulator clock
934 * output function
935 */
936 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
937 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
938 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
939
940 /* Left Line Output */
941 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
942 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
943
944 /* Right Line Output */
945 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
946 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
947
948 /* Left HP Output */
949 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
950 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
951
952 /* Right HP Output */
953 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
954 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
955
956 /* Left HPCOM Output */
957 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
958 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
959
960 /* Right HPCOM Output */
961 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
962 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
963 };
964
965 /* For tlv320aic3104 */
966 static const struct snd_soc_dapm_route intercon_extra_3104[] = {
967 /* Left Input */
968 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
969 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
970
971 /* Right Input */
972 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
973 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
974 };
975
976 static const struct snd_soc_dapm_route intercon_mono[] = {
977 /* Mono Output */
978 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
979 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
980 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
981 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
982 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
983 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
984 {"Mono Out", NULL, "Mono Mixer"},
985 {"MONO_LOUT", NULL, "Mono Out"},
986 };
987
988 static const struct snd_soc_dapm_route intercon_3007[] = {
989 /* Class-D outputs */
990 {"Left Class-D Out", NULL, "Left Line Out"},
991 {"Right Class-D Out", NULL, "Left Line Out"},
992 {"SPOP", NULL, "Left Class-D Out"},
993 {"SPOM", NULL, "Right Class-D Out"},
994 };
995
996 static int aic3x_add_widgets(struct snd_soc_codec *codec)
997 {
998 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
999 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1000
1001 switch (aic3x->model) {
1002 case AIC3X_MODEL_3X:
1003 case AIC3X_MODEL_33:
1004 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1005 ARRAY_SIZE(aic3x_extra_dapm_widgets));
1006 snd_soc_dapm_add_routes(dapm, intercon_extra,
1007 ARRAY_SIZE(intercon_extra));
1008 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
1009 ARRAY_SIZE(aic3x_dapm_mono_widgets));
1010 snd_soc_dapm_add_routes(dapm, intercon_mono,
1011 ARRAY_SIZE(intercon_mono));
1012 break;
1013 case AIC3X_MODEL_3007:
1014 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1015 ARRAY_SIZE(aic3x_extra_dapm_widgets));
1016 snd_soc_dapm_add_routes(dapm, intercon_extra,
1017 ARRAY_SIZE(intercon_extra));
1018 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
1019 ARRAY_SIZE(aic3007_dapm_widgets));
1020 snd_soc_dapm_add_routes(dapm, intercon_3007,
1021 ARRAY_SIZE(intercon_3007));
1022 break;
1023 case AIC3X_MODEL_3104:
1024 snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets,
1025 ARRAY_SIZE(aic3104_extra_dapm_widgets));
1026 snd_soc_dapm_add_routes(dapm, intercon_extra_3104,
1027 ARRAY_SIZE(intercon_extra_3104));
1028 break;
1029 }
1030
1031 return 0;
1032 }
1033
1034 static int aic3x_hw_params(struct snd_pcm_substream *substream,
1035 struct snd_pcm_hw_params *params,
1036 struct snd_soc_dai *dai)
1037 {
1038 struct snd_soc_codec *codec = dai->codec;
1039 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1040 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
1041 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
1042 u16 d, pll_d = 1;
1043 int clk;
1044 int width = aic3x->slot_width;
1045
1046 if (!width)
1047 width = params_width(params);
1048
1049 /* select data word length */
1050 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
1051 switch (width) {
1052 case 16:
1053 break;
1054 case 20:
1055 data |= (0x01 << 4);
1056 break;
1057 case 24:
1058 data |= (0x02 << 4);
1059 break;
1060 case 32:
1061 data |= (0x03 << 4);
1062 break;
1063 }
1064 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
1065
1066 /* Fsref can be 44100 or 48000 */
1067 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
1068
1069 /* Try to find a value for Q which allows us to bypass the PLL and
1070 * generate CODEC_CLK directly. */
1071 for (pll_q = 2; pll_q < 18; pll_q++)
1072 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1073 bypass_pll = 1;
1074 break;
1075 }
1076
1077 if (bypass_pll) {
1078 pll_q &= 0xf;
1079 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1080 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
1081 /* disable PLL if it is bypassed */
1082 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
1083
1084 } else {
1085 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
1086 /* enable PLL when it is used */
1087 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1088 PLL_ENABLE, PLL_ENABLE);
1089 }
1090
1091 /* Route Left DAC to left channel input and
1092 * right DAC to right channel input */
1093 data = (LDAC2LCH | RDAC2RCH);
1094 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1095 if (params_rate(params) >= 64000)
1096 data |= DUAL_RATE_MODE;
1097 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
1098
1099 /* codec sample rate select */
1100 data = (fsref * 20) / params_rate(params);
1101 if (params_rate(params) < 64000)
1102 data /= 2;
1103 data /= 5;
1104 data -= 2;
1105 data |= (data << 4);
1106 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
1107
1108 if (bypass_pll)
1109 return 0;
1110
1111 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
1112 * one wins the game. Try with d==0 first, next with d!=0.
1113 * Constraints for j are according to the datasheet.
1114 * The sysclk is divided by 1000 to prevent integer overflows.
1115 */
1116
1117 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1118
1119 for (r = 1; r <= 16; r++)
1120 for (p = 1; p <= 8; p++) {
1121 for (j = 4; j <= 55; j++) {
1122 /* This is actually 1000*((j+(d/10000))*r)/p
1123 * The term had to be converted to get
1124 * rid of the division by 10000; d = 0 here
1125 */
1126 int tmp_clk = (1000 * j * r) / p;
1127
1128 /* Check whether this values get closer than
1129 * the best ones we had before
1130 */
1131 if (abs(codec_clk - tmp_clk) <
1132 abs(codec_clk - last_clk)) {
1133 pll_j = j; pll_d = 0;
1134 pll_r = r; pll_p = p;
1135 last_clk = tmp_clk;
1136 }
1137
1138 /* Early exit for exact matches */
1139 if (tmp_clk == codec_clk)
1140 goto found;
1141 }
1142 }
1143
1144 /* try with d != 0 */
1145 for (p = 1; p <= 8; p++) {
1146 j = codec_clk * p / 1000;
1147
1148 if (j < 4 || j > 11)
1149 continue;
1150
1151 /* do not use codec_clk here since we'd loose precision */
1152 d = ((2048 * p * fsref) - j * aic3x->sysclk)
1153 * 100 / (aic3x->sysclk/100);
1154
1155 clk = (10000 * j + d) / (10 * p);
1156
1157 /* check whether this values get closer than the best
1158 * ones we had before */
1159 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1160 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
1161 last_clk = clk;
1162 }
1163
1164 /* Early exit for exact matches */
1165 if (clk == codec_clk)
1166 goto found;
1167 }
1168
1169 if (last_clk == 0) {
1170 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1171 return -EINVAL;
1172 }
1173
1174 found:
1175 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
1176 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1177 pll_r << PLLR_SHIFT);
1178 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1179 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
1180 (pll_d >> 6) << PLLD_MSB_SHIFT);
1181 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
1182 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1183
1184 return 0;
1185 }
1186
1187 static int aic3x_prepare(struct snd_pcm_substream *substream,
1188 struct snd_soc_dai *dai)
1189 {
1190 struct snd_soc_codec *codec = dai->codec;
1191 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1192 int delay = 0;
1193 int width = aic3x->slot_width;
1194
1195 if (!width)
1196 width = substream->runtime->sample_bits;
1197
1198 /* TDM slot selection only valid in DSP_A/_B mode */
1199 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
1200 delay += (aic3x->tdm_delay*width + 1);
1201 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
1202 delay += aic3x->tdm_delay*width;
1203
1204 /* Configure data delay */
1205 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1206
1207 return 0;
1208 }
1209
1210 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1211 {
1212 struct snd_soc_codec *codec = dai->codec;
1213 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
1214 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
1215
1216 if (mute) {
1217 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1218 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1219 } else {
1220 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1221 snd_soc_write(codec, RDAC_VOL, rdac_reg);
1222 }
1223
1224 return 0;
1225 }
1226
1227 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1228 int clk_id, unsigned int freq, int dir)
1229 {
1230 struct snd_soc_codec *codec = codec_dai->codec;
1231 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1232
1233 /* set clock on MCLK or GPIO2 or BCLK */
1234 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1235 clk_id << PLLCLK_IN_SHIFT);
1236 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1237 clk_id << CLKDIV_IN_SHIFT);
1238
1239 aic3x->sysclk = freq;
1240 return 0;
1241 }
1242
1243 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1244 unsigned int fmt)
1245 {
1246 struct snd_soc_codec *codec = codec_dai->codec;
1247 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1248 u8 iface_areg, iface_breg;
1249
1250 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1251 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1252
1253 /* set master/slave audio interface */
1254 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1255 case SND_SOC_DAIFMT_CBM_CFM:
1256 aic3x->master = 1;
1257 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1258 break;
1259 case SND_SOC_DAIFMT_CBS_CFS:
1260 aic3x->master = 0;
1261 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1262 break;
1263 default:
1264 return -EINVAL;
1265 }
1266
1267 /*
1268 * match both interface format and signal polarities since they
1269 * are fixed
1270 */
1271 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1272 SND_SOC_DAIFMT_INV_MASK)) {
1273 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1274 break;
1275 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1276 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1277 iface_breg |= (0x01 << 6);
1278 break;
1279 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1280 iface_breg |= (0x02 << 6);
1281 break;
1282 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1283 iface_breg |= (0x03 << 6);
1284 break;
1285 default:
1286 return -EINVAL;
1287 }
1288
1289 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1290
1291 /* set iface */
1292 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1293 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1294
1295 return 0;
1296 }
1297
1298 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
1299 unsigned int tx_mask, unsigned int rx_mask,
1300 int slots, int slot_width)
1301 {
1302 struct snd_soc_codec *codec = codec_dai->codec;
1303 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1304 unsigned int lsb;
1305
1306 if (tx_mask != rx_mask) {
1307 dev_err(codec->dev, "tx and rx masks must be symmetric\n");
1308 return -EINVAL;
1309 }
1310
1311 if (unlikely(!tx_mask)) {
1312 dev_err(codec->dev, "tx and rx masks need to be non 0\n");
1313 return -EINVAL;
1314 }
1315
1316 /* TDM based on DSP mode requires slots to be adjacent */
1317 lsb = __ffs(tx_mask);
1318 if ((lsb + 1) != __fls(tx_mask)) {
1319 dev_err(codec->dev, "Invalid mask, slots must be adjacent\n");
1320 return -EINVAL;
1321 }
1322
1323 switch (slot_width) {
1324 case 16:
1325 case 20:
1326 case 24:
1327 case 32:
1328 break;
1329 default:
1330 dev_err(codec->dev, "Unsupported slot width %d\n", slot_width);
1331 return -EINVAL;
1332 }
1333
1334
1335 aic3x->tdm_delay = lsb;
1336 aic3x->slot_width = slot_width;
1337
1338 /* DOUT in high-impedance on inactive bit clocks */
1339 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
1340 DOUT_TRISTATE, DOUT_TRISTATE);
1341
1342 return 0;
1343 }
1344
1345 static int aic3x_regulator_event(struct notifier_block *nb,
1346 unsigned long event, void *data)
1347 {
1348 struct aic3x_disable_nb *disable_nb =
1349 container_of(nb, struct aic3x_disable_nb, nb);
1350 struct aic3x_priv *aic3x = disable_nb->aic3x;
1351
1352 if (event & REGULATOR_EVENT_DISABLE) {
1353 /*
1354 * Put codec to reset and require cache sync as at least one
1355 * of the supplies was disabled
1356 */
1357 if (gpio_is_valid(aic3x->gpio_reset))
1358 gpio_set_value(aic3x->gpio_reset, 0);
1359 regcache_mark_dirty(aic3x->regmap);
1360 }
1361
1362 return 0;
1363 }
1364
1365 static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1366 {
1367 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1368 unsigned int pll_c, pll_d;
1369 int ret;
1370
1371 if (power) {
1372 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1373 aic3x->supplies);
1374 if (ret)
1375 goto out;
1376 aic3x->power = 1;
1377
1378 if (gpio_is_valid(aic3x->gpio_reset)) {
1379 udelay(1);
1380 gpio_set_value(aic3x->gpio_reset, 1);
1381 }
1382
1383 /* Sync reg_cache with the hardware */
1384 regcache_cache_only(aic3x->regmap, false);
1385 regcache_sync(aic3x->regmap);
1386
1387 /* Rewrite paired PLL D registers in case cached sync skipped
1388 * writing one of them and thus caused other one also not
1389 * being written
1390 */
1391 pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG);
1392 pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG);
1393 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1394 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1395 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c);
1396 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d);
1397 }
1398
1399 /*
1400 * Delay is needed to reduce pop-noise after syncing back the
1401 * registers
1402 */
1403 mdelay(50);
1404 } else {
1405 /*
1406 * Do soft reset to this codec instance in order to clear
1407 * possible VDD leakage currents in case the supply regulators
1408 * remain on
1409 */
1410 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1411 regcache_mark_dirty(aic3x->regmap);
1412 aic3x->power = 0;
1413 /* HW writes are needless when bias is off */
1414 regcache_cache_only(aic3x->regmap, true);
1415 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1416 aic3x->supplies);
1417 }
1418 out:
1419 return ret;
1420 }
1421
1422 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1423 enum snd_soc_bias_level level)
1424 {
1425 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1426
1427 switch (level) {
1428 case SND_SOC_BIAS_ON:
1429 break;
1430 case SND_SOC_BIAS_PREPARE:
1431 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY &&
1432 aic3x->master) {
1433 /* enable pll */
1434 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1435 PLL_ENABLE, PLL_ENABLE);
1436 }
1437 break;
1438 case SND_SOC_BIAS_STANDBY:
1439 if (!aic3x->power)
1440 aic3x_set_power(codec, 1);
1441 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE &&
1442 aic3x->master) {
1443 /* disable pll */
1444 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1445 PLL_ENABLE, 0);
1446 }
1447 break;
1448 case SND_SOC_BIAS_OFF:
1449 if (aic3x->power)
1450 aic3x_set_power(codec, 0);
1451 break;
1452 }
1453
1454 return 0;
1455 }
1456
1457 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1458 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1459 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1460 SNDRV_PCM_FMTBIT_S32_LE)
1461
1462 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1463 .hw_params = aic3x_hw_params,
1464 .prepare = aic3x_prepare,
1465 .digital_mute = aic3x_mute,
1466 .set_sysclk = aic3x_set_dai_sysclk,
1467 .set_fmt = aic3x_set_dai_fmt,
1468 .set_tdm_slot = aic3x_set_dai_tdm_slot,
1469 };
1470
1471 static struct snd_soc_dai_driver aic3x_dai = {
1472 .name = "tlv320aic3x-hifi",
1473 .playback = {
1474 .stream_name = "Playback",
1475 .channels_min = 2,
1476 .channels_max = 2,
1477 .rates = AIC3X_RATES,
1478 .formats = AIC3X_FORMATS,},
1479 .capture = {
1480 .stream_name = "Capture",
1481 .channels_min = 2,
1482 .channels_max = 2,
1483 .rates = AIC3X_RATES,
1484 .formats = AIC3X_FORMATS,},
1485 .ops = &aic3x_dai_ops,
1486 .symmetric_rates = 1,
1487 };
1488
1489 static void aic3x_mono_init(struct snd_soc_codec *codec)
1490 {
1491 /* DAC to Mono Line Out default volume and route to Output mixer */
1492 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1493 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1494
1495 /* unmute all outputs */
1496 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1497
1498 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1499 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1500 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1501
1502 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1503 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1504 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1505 }
1506
1507 /*
1508 * initialise the AIC3X driver
1509 * register the mixer and dsp interfaces with the kernel
1510 */
1511 static int aic3x_init(struct snd_soc_codec *codec)
1512 {
1513 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1514
1515 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1516 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1517
1518 /* DAC default volume and mute */
1519 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1520 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1521
1522 /* DAC to HP default volume and route to Output mixer */
1523 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1524 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1525 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1526 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1527 /* DAC to Line Out default volume and route to Output mixer */
1528 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1529 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1530
1531 /* unmute all outputs */
1532 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1533 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1534 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1535 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1536 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1537 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
1538
1539 /* ADC default volume and unmute */
1540 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1541 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1542 /* By default route Line1 to ADC PGA mixer */
1543 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1544 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1545
1546 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1547 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1548 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1549 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1550 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1551 /* PGA to Line Out default volume, disconnect from Output Mixer */
1552 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1553 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1554
1555 /* On tlv320aic3104, these registers are reserved and must not be written */
1556 if (aic3x->model != AIC3X_MODEL_3104) {
1557 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1558 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1559 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1560 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1561 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1562 /* Line2 Line Out default volume, disconnect from Output Mixer */
1563 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1564 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1565 }
1566
1567 switch (aic3x->model) {
1568 case AIC3X_MODEL_3X:
1569 case AIC3X_MODEL_33:
1570 aic3x_mono_init(codec);
1571 break;
1572 case AIC3X_MODEL_3007:
1573 snd_soc_write(codec, CLASSD_CTRL, 0);
1574 break;
1575 }
1576
1577 /* Output common-mode voltage = 1.5 V */
1578 snd_soc_update_bits(codec, HPOUT_SC, HPOUT_SC_OCMV_MASK,
1579 aic3x->ocmv << HPOUT_SC_OCMV_SHIFT);
1580
1581 return 0;
1582 }
1583
1584 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1585 {
1586 struct aic3x_priv *a;
1587
1588 list_for_each_entry(a, &reset_list, list) {
1589 if (gpio_is_valid(aic3x->gpio_reset) &&
1590 aic3x->gpio_reset == a->gpio_reset)
1591 return true;
1592 }
1593
1594 return false;
1595 }
1596
1597 static int aic3x_probe(struct snd_soc_codec *codec)
1598 {
1599 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1600 int ret, i;
1601
1602 INIT_LIST_HEAD(&aic3x->list);
1603 aic3x->codec = codec;
1604
1605 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1606 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1607 aic3x->disable_nb[i].aic3x = aic3x;
1608 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1609 &aic3x->disable_nb[i].nb);
1610 if (ret) {
1611 dev_err(codec->dev,
1612 "Failed to request regulator notifier: %d\n",
1613 ret);
1614 goto err_notif;
1615 }
1616 }
1617
1618 regcache_mark_dirty(aic3x->regmap);
1619 aic3x_init(codec);
1620
1621 if (aic3x->setup) {
1622 if (aic3x->model != AIC3X_MODEL_3104) {
1623 /* setup GPIO functions */
1624 snd_soc_write(codec, AIC3X_GPIO1_REG,
1625 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1626 snd_soc_write(codec, AIC3X_GPIO2_REG,
1627 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1628 } else {
1629 dev_warn(codec->dev, "GPIO functionality is not supported on tlv320aic3104\n");
1630 }
1631 }
1632
1633 switch (aic3x->model) {
1634 case AIC3X_MODEL_3X:
1635 case AIC3X_MODEL_33:
1636 snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls,
1637 ARRAY_SIZE(aic3x_extra_snd_controls));
1638 snd_soc_add_codec_controls(codec, aic3x_mono_controls,
1639 ARRAY_SIZE(aic3x_mono_controls));
1640 break;
1641 case AIC3X_MODEL_3007:
1642 snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls,
1643 ARRAY_SIZE(aic3x_extra_snd_controls));
1644 snd_soc_add_codec_controls(codec,
1645 &aic3x_classd_amp_gain_ctrl, 1);
1646 break;
1647 case AIC3X_MODEL_3104:
1648 break;
1649 }
1650
1651 /* set mic bias voltage */
1652 switch (aic3x->micbias_vg) {
1653 case AIC3X_MICBIAS_2_0V:
1654 case AIC3X_MICBIAS_2_5V:
1655 case AIC3X_MICBIAS_AVDDV:
1656 snd_soc_update_bits(codec, MICBIAS_CTRL,
1657 MICBIAS_LEVEL_MASK,
1658 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1659 break;
1660 case AIC3X_MICBIAS_OFF:
1661 /*
1662 * noting to do. target won't enter here. This is just to avoid
1663 * compile time warning "warning: enumeration value
1664 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1665 */
1666 break;
1667 }
1668
1669 aic3x_add_widgets(codec);
1670
1671 return 0;
1672
1673 err_notif:
1674 while (i--)
1675 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1676 &aic3x->disable_nb[i].nb);
1677 return ret;
1678 }
1679
1680 static int aic3x_remove(struct snd_soc_codec *codec)
1681 {
1682 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1683 int i;
1684
1685 list_del(&aic3x->list);
1686 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1687 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1688 &aic3x->disable_nb[i].nb);
1689
1690 return 0;
1691 }
1692
1693 static const struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1694 .set_bias_level = aic3x_set_bias_level,
1695 .idle_bias_off = true,
1696 .probe = aic3x_probe,
1697 .remove = aic3x_remove,
1698 .component_driver = {
1699 .controls = aic3x_snd_controls,
1700 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
1701 .dapm_widgets = aic3x_dapm_widgets,
1702 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1703 .dapm_routes = intercon,
1704 .num_dapm_routes = ARRAY_SIZE(intercon),
1705 },
1706 };
1707
1708 static void aic3x_configure_ocmv(struct i2c_client *client)
1709 {
1710 struct device_node *np = client->dev.of_node;
1711 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1712 u32 value;
1713 int dvdd, avdd;
1714
1715 if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) {
1716 /* OCMV setting is forced by DT */
1717 if (value <= 3) {
1718 aic3x->ocmv = value;
1719 return;
1720 }
1721 }
1722
1723 dvdd = regulator_get_voltage(aic3x->supplies[1].consumer);
1724 avdd = regulator_get_voltage(aic3x->supplies[2].consumer);
1725
1726 if (avdd > 3600000 || dvdd > 1950000) {
1727 dev_warn(&client->dev,
1728 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
1729 avdd, dvdd);
1730 } else if (avdd == 3600000 && dvdd == 1950000) {
1731 aic3x->ocmv = HPOUT_SC_OCMV_1_8V;
1732 } else if (avdd > 3300000 && dvdd > 1800000) {
1733 aic3x->ocmv = HPOUT_SC_OCMV_1_65V;
1734 } else if (avdd > 3000000 && dvdd > 1650000) {
1735 aic3x->ocmv = HPOUT_SC_OCMV_1_5V;
1736 } else if (avdd >= 2700000 && dvdd >= 1525000) {
1737 aic3x->ocmv = HPOUT_SC_OCMV_1_35V;
1738 } else {
1739 dev_warn(&client->dev,
1740 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
1741 avdd, dvdd);
1742 }
1743 }
1744
1745 /*
1746 * AIC3X 2 wire address can be up to 4 devices with device addresses
1747 * 0x18, 0x19, 0x1A, 0x1B
1748 */
1749
1750 static const struct i2c_device_id aic3x_i2c_id[] = {
1751 { "tlv320aic3x", AIC3X_MODEL_3X },
1752 { "tlv320aic33", AIC3X_MODEL_33 },
1753 { "tlv320aic3007", AIC3X_MODEL_3007 },
1754 { "tlv320aic3106", AIC3X_MODEL_3X },
1755 { "tlv320aic3104", AIC3X_MODEL_3104 },
1756 { }
1757 };
1758 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1759
1760 static const struct reg_sequence aic3007_class_d[] = {
1761 /* Class-D speaker driver init; datasheet p. 46 */
1762 { AIC3X_PAGE_SELECT, 0x0D },
1763 { 0xD, 0x0D },
1764 { 0x8, 0x5C },
1765 { 0x8, 0x5D },
1766 { 0x8, 0x5C },
1767 { AIC3X_PAGE_SELECT, 0x00 },
1768 };
1769
1770 /*
1771 * If the i2c layer weren't so broken, we could pass this kind of data
1772 * around
1773 */
1774 static int aic3x_i2c_probe(struct i2c_client *i2c,
1775 const struct i2c_device_id *id)
1776 {
1777 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1778 struct aic3x_priv *aic3x;
1779 struct aic3x_setup_data *ai3x_setup;
1780 struct device_node *np = i2c->dev.of_node;
1781 int ret, i;
1782 u32 value;
1783
1784 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1785 if (!aic3x)
1786 return -ENOMEM;
1787
1788 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1789 if (IS_ERR(aic3x->regmap)) {
1790 ret = PTR_ERR(aic3x->regmap);
1791 return ret;
1792 }
1793
1794 regcache_cache_only(aic3x->regmap, true);
1795
1796 i2c_set_clientdata(i2c, aic3x);
1797 if (pdata) {
1798 aic3x->gpio_reset = pdata->gpio_reset;
1799 aic3x->setup = pdata->setup;
1800 aic3x->micbias_vg = pdata->micbias_vg;
1801 } else if (np) {
1802 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1803 GFP_KERNEL);
1804 if (!ai3x_setup)
1805 return -ENOMEM;
1806
1807 ret = of_get_named_gpio(np, "gpio-reset", 0);
1808 if (ret >= 0)
1809 aic3x->gpio_reset = ret;
1810 else
1811 aic3x->gpio_reset = -1;
1812
1813 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1814 ai3x_setup->gpio_func, 2) >= 0) {
1815 aic3x->setup = ai3x_setup;
1816 }
1817
1818 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1819 switch (value) {
1820 case 1 :
1821 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1822 break;
1823 case 2 :
1824 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1825 break;
1826 case 3 :
1827 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1828 break;
1829 default :
1830 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1831 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1832 "found in DT\n");
1833 }
1834 } else {
1835 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1836 }
1837
1838 } else {
1839 aic3x->gpio_reset = -1;
1840 }
1841
1842 aic3x->model = id->driver_data;
1843
1844 if (gpio_is_valid(aic3x->gpio_reset) &&
1845 !aic3x_is_shared_reset(aic3x)) {
1846 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1847 if (ret != 0)
1848 goto err;
1849 gpio_direction_output(aic3x->gpio_reset, 0);
1850 }
1851
1852 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1853 aic3x->supplies[i].supply = aic3x_supply_names[i];
1854
1855 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1856 aic3x->supplies);
1857 if (ret != 0) {
1858 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1859 goto err_gpio;
1860 }
1861
1862 aic3x_configure_ocmv(i2c);
1863
1864 if (aic3x->model == AIC3X_MODEL_3007) {
1865 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1866 ARRAY_SIZE(aic3007_class_d));
1867 if (ret != 0)
1868 dev_err(&i2c->dev, "Failed to init class D: %d\n",
1869 ret);
1870 }
1871
1872 ret = snd_soc_register_codec(&i2c->dev,
1873 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1874
1875 if (ret != 0)
1876 goto err_gpio;
1877
1878 list_add(&aic3x->list, &reset_list);
1879
1880 return 0;
1881
1882 err_gpio:
1883 if (gpio_is_valid(aic3x->gpio_reset) &&
1884 !aic3x_is_shared_reset(aic3x))
1885 gpio_free(aic3x->gpio_reset);
1886 err:
1887 return ret;
1888 }
1889
1890 static int aic3x_i2c_remove(struct i2c_client *client)
1891 {
1892 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1893
1894 snd_soc_unregister_codec(&client->dev);
1895 if (gpio_is_valid(aic3x->gpio_reset) &&
1896 !aic3x_is_shared_reset(aic3x)) {
1897 gpio_set_value(aic3x->gpio_reset, 0);
1898 gpio_free(aic3x->gpio_reset);
1899 }
1900 return 0;
1901 }
1902
1903 #if defined(CONFIG_OF)
1904 static const struct of_device_id tlv320aic3x_of_match[] = {
1905 { .compatible = "ti,tlv320aic3x", },
1906 { .compatible = "ti,tlv320aic33" },
1907 { .compatible = "ti,tlv320aic3007" },
1908 { .compatible = "ti,tlv320aic3106" },
1909 { .compatible = "ti,tlv320aic3104" },
1910 {},
1911 };
1912 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1913 #endif
1914
1915 /* machine i2c codec control layer */
1916 static struct i2c_driver aic3x_i2c_driver = {
1917 .driver = {
1918 .name = "tlv320aic3x-codec",
1919 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
1920 },
1921 .probe = aic3x_i2c_probe,
1922 .remove = aic3x_i2c_remove,
1923 .id_table = aic3x_i2c_id,
1924 };
1925
1926 module_i2c_driver(aic3x_i2c_driver);
1927
1928 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1929 MODULE_AUTHOR("Vladimir Barinov");
1930 MODULE_LICENSE("GPL");
Linux with added FPC-III support