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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / sound / soc / codecs / wm8985.c
blob05344f974ff31b7f3d9879d4fafa335ac8996cfb
1 /*
2 * wm8985.c -- WM8985 / WM8758 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
6 *
7 * WM8758 support:
8 * Copyright: 2016 Barix AG
9 * Author: Petr Kulhavy <petr@barix.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * TODO:
16 * o Add OUT3/OUT4 mixer controls.
17 */
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/pm.h>
24 #include <linux/i2c.h>
25 #include <linux/regmap.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/spi/spi.h>
28 #include <linux/slab.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
35
36 #include "wm8985.h"
37
38 #define WM8985_NUM_SUPPLIES 4
39 static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
40 "DCVDD",
41 "DBVDD",
42 "AVDD1",
43 "AVDD2"
44 };
45
46 enum wm8985_type {
47 WM8985,
48 WM8758,
49 };
50
51 static const struct reg_default wm8985_reg_defaults[] = {
52 { 1, 0x0000 }, /* R1 - Power management 1 */
53 { 2, 0x0000 }, /* R2 - Power management 2 */
54 { 3, 0x0000 }, /* R3 - Power management 3 */
55 { 4, 0x0050 }, /* R4 - Audio Interface */
56 { 5, 0x0000 }, /* R5 - Companding control */
57 { 6, 0x0140 }, /* R6 - Clock Gen control */
58 { 7, 0x0000 }, /* R7 - Additional control */
59 { 8, 0x0000 }, /* R8 - GPIO Control */
60 { 9, 0x0000 }, /* R9 - Jack Detect Control 1 */
61 { 10, 0x0000 }, /* R10 - DAC Control */
62 { 11, 0x00FF }, /* R11 - Left DAC digital Vol */
63 { 12, 0x00FF }, /* R12 - Right DAC digital vol */
64 { 13, 0x0000 }, /* R13 - Jack Detect Control 2 */
65 { 14, 0x0100 }, /* R14 - ADC Control */
66 { 15, 0x00FF }, /* R15 - Left ADC Digital Vol */
67 { 16, 0x00FF }, /* R16 - Right ADC Digital Vol */
68 { 18, 0x012C }, /* R18 - EQ1 - low shelf */
69 { 19, 0x002C }, /* R19 - EQ2 - peak 1 */
70 { 20, 0x002C }, /* R20 - EQ3 - peak 2 */
71 { 21, 0x002C }, /* R21 - EQ4 - peak 3 */
72 { 22, 0x002C }, /* R22 - EQ5 - high shelf */
73 { 24, 0x0032 }, /* R24 - DAC Limiter 1 */
74 { 25, 0x0000 }, /* R25 - DAC Limiter 2 */
75 { 27, 0x0000 }, /* R27 - Notch Filter 1 */
76 { 28, 0x0000 }, /* R28 - Notch Filter 2 */
77 { 29, 0x0000 }, /* R29 - Notch Filter 3 */
78 { 30, 0x0000 }, /* R30 - Notch Filter 4 */
79 { 32, 0x0038 }, /* R32 - ALC control 1 */
80 { 33, 0x000B }, /* R33 - ALC control 2 */
81 { 34, 0x0032 }, /* R34 - ALC control 3 */
82 { 35, 0x0000 }, /* R35 - Noise Gate */
83 { 36, 0x0008 }, /* R36 - PLL N */
84 { 37, 0x000C }, /* R37 - PLL K 1 */
85 { 38, 0x0093 }, /* R38 - PLL K 2 */
86 { 39, 0x00E9 }, /* R39 - PLL K 3 */
87 { 41, 0x0000 }, /* R41 - 3D control */
88 { 42, 0x0000 }, /* R42 - OUT4 to ADC */
89 { 43, 0x0000 }, /* R43 - Beep control */
90 { 44, 0x0033 }, /* R44 - Input ctrl */
91 { 45, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
92 { 46, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
93 { 47, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
94 { 48, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
95 { 49, 0x0002 }, /* R49 - Output ctrl */
96 { 50, 0x0001 }, /* R50 - Left mixer ctrl */
97 { 51, 0x0001 }, /* R51 - Right mixer ctrl */
98 { 52, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
99 { 53, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
100 { 54, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
101 { 55, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
102 { 56, 0x0001 }, /* R56 - OUT3 mixer ctrl */
103 { 57, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
104 { 60, 0x0004 }, /* R60 - OUTPUT ctrl */
105 { 61, 0x0000 }, /* R61 - BIAS CTRL */
106 };
107
108 static bool wm8985_writeable(struct device *dev, unsigned int reg)
109 {
110 switch (reg) {
111 case WM8985_SOFTWARE_RESET:
112 case WM8985_POWER_MANAGEMENT_1:
113 case WM8985_POWER_MANAGEMENT_2:
114 case WM8985_POWER_MANAGEMENT_3:
115 case WM8985_AUDIO_INTERFACE:
116 case WM8985_COMPANDING_CONTROL:
117 case WM8985_CLOCK_GEN_CONTROL:
118 case WM8985_ADDITIONAL_CONTROL:
119 case WM8985_GPIO_CONTROL:
120 case WM8985_JACK_DETECT_CONTROL_1:
121 case WM8985_DAC_CONTROL:
122 case WM8985_LEFT_DAC_DIGITAL_VOL:
123 case WM8985_RIGHT_DAC_DIGITAL_VOL:
124 case WM8985_JACK_DETECT_CONTROL_2:
125 case WM8985_ADC_CONTROL:
126 case WM8985_LEFT_ADC_DIGITAL_VOL:
127 case WM8985_RIGHT_ADC_DIGITAL_VOL:
128 case WM8985_EQ1_LOW_SHELF:
129 case WM8985_EQ2_PEAK_1:
130 case WM8985_EQ3_PEAK_2:
131 case WM8985_EQ4_PEAK_3:
132 case WM8985_EQ5_HIGH_SHELF:
133 case WM8985_DAC_LIMITER_1:
134 case WM8985_DAC_LIMITER_2:
135 case WM8985_NOTCH_FILTER_1:
136 case WM8985_NOTCH_FILTER_2:
137 case WM8985_NOTCH_FILTER_3:
138 case WM8985_NOTCH_FILTER_4:
139 case WM8985_ALC_CONTROL_1:
140 case WM8985_ALC_CONTROL_2:
141 case WM8985_ALC_CONTROL_3:
142 case WM8985_NOISE_GATE:
143 case WM8985_PLL_N:
144 case WM8985_PLL_K_1:
145 case WM8985_PLL_K_2:
146 case WM8985_PLL_K_3:
147 case WM8985_3D_CONTROL:
148 case WM8985_OUT4_TO_ADC:
149 case WM8985_BEEP_CONTROL:
150 case WM8985_INPUT_CTRL:
151 case WM8985_LEFT_INP_PGA_GAIN_CTRL:
152 case WM8985_RIGHT_INP_PGA_GAIN_CTRL:
153 case WM8985_LEFT_ADC_BOOST_CTRL:
154 case WM8985_RIGHT_ADC_BOOST_CTRL:
155 case WM8985_OUTPUT_CTRL0:
156 case WM8985_LEFT_MIXER_CTRL:
157 case WM8985_RIGHT_MIXER_CTRL:
158 case WM8985_LOUT1_HP_VOLUME_CTRL:
159 case WM8985_ROUT1_HP_VOLUME_CTRL:
160 case WM8985_LOUT2_SPK_VOLUME_CTRL:
161 case WM8985_ROUT2_SPK_VOLUME_CTRL:
162 case WM8985_OUT3_MIXER_CTRL:
163 case WM8985_OUT4_MONO_MIX_CTRL:
164 case WM8985_OUTPUT_CTRL1:
165 case WM8985_BIAS_CTRL:
166 return true;
167 default:
168 return false;
169 }
170 }
171
172 /*
173 * latch bit 8 of these registers to ensure instant
174 * volume updates
175 */
176 static const int volume_update_regs[] = {
177 WM8985_LEFT_DAC_DIGITAL_VOL,
178 WM8985_RIGHT_DAC_DIGITAL_VOL,
179 WM8985_LEFT_ADC_DIGITAL_VOL,
180 WM8985_RIGHT_ADC_DIGITAL_VOL,
181 WM8985_LOUT2_SPK_VOLUME_CTRL,
182 WM8985_ROUT2_SPK_VOLUME_CTRL,
183 WM8985_LOUT1_HP_VOLUME_CTRL,
184 WM8985_ROUT1_HP_VOLUME_CTRL,
185 WM8985_LEFT_INP_PGA_GAIN_CTRL,
186 WM8985_RIGHT_INP_PGA_GAIN_CTRL
187 };
188
189 struct wm8985_priv {
190 struct regmap *regmap;
191 struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
192 enum wm8985_type dev_type;
193 unsigned int sysclk;
194 unsigned int bclk;
195 };
196
197 static const struct {
198 int div;
199 int ratio;
200 } fs_ratios[] = {
201 { 10, 128 },
202 { 15, 192 },
203 { 20, 256 },
204 { 30, 384 },
205 { 40, 512 },
206 { 60, 768 },
207 { 80, 1024 },
208 { 120, 1536 }
209 };
210
211 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
212
213 static const int bclk_divs[] = {
214 1, 2, 4, 8, 16, 32
215 };
216
217 static int eqmode_get(struct snd_kcontrol *kcontrol,
218 struct snd_ctl_elem_value *ucontrol);
219 static int eqmode_put(struct snd_kcontrol *kcontrol,
220 struct snd_ctl_elem_value *ucontrol);
221
222 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
223 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
224 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
225 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
226 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
227 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
228 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
229 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
230 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
231 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
232 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
233 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
234 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
235 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
236
237 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
238 static SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7, alc_sel_text);
239
240 static const char *alc_mode_text[] = { "ALC", "Limiter" };
241 static SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8, alc_mode_text);
242
243 static const char *filter_mode_text[] = { "Audio", "Application" };
244 static SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
245 filter_mode_text);
246
247 static const char *eq_bw_text[] = { "Narrow", "Wide" };
248 static const char *eqmode_text[] = { "Capture", "Playback" };
249 static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
250
251 static const char *eq1_cutoff_text[] = {
252 "80Hz", "105Hz", "135Hz", "175Hz"
253 };
254 static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
255 eq1_cutoff_text);
256 static const char *eq2_cutoff_text[] = {
257 "230Hz", "300Hz", "385Hz", "500Hz"
258 };
259 static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
260 static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5, eq2_cutoff_text);
261 static const char *eq3_cutoff_text[] = {
262 "650Hz", "850Hz", "1.1kHz", "1.4kHz"
263 };
264 static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
265 static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
266 eq3_cutoff_text);
267 static const char *eq4_cutoff_text[] = {
268 "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
269 };
270 static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
271 static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5, eq4_cutoff_text);
272 static const char *eq5_cutoff_text[] = {
273 "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
274 };
275 static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
276 eq5_cutoff_text);
277
278 static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
279 static SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
280
281 static const char *depth_3d_text[] = {
282 "Off",
283 "6.67%",
284 "13.3%",
285 "20%",
286 "26.7%",
287 "33.3%",
288 "40%",
289 "46.6%",
290 "53.3%",
291 "60%",
292 "66.7%",
293 "73.3%",
294 "80%",
295 "86.7%",
296 "93.3%",
297 "100%"
298 };
299 static SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0, depth_3d_text);
300
301 static const struct snd_kcontrol_new wm8985_common_snd_controls[] = {
302 SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
303 0, 1, 0),
304
305 SOC_ENUM("ALC Capture Function", alc_sel),
306 SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
307 3, 7, 0, alc_max_tlv),
308 SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
309 0, 7, 0, alc_min_tlv),
310 SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
311 0, 15, 0, alc_tar_tlv),
312 SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
313 SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
314 SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
315 SOC_ENUM("ALC Mode", alc_mode),
316 SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
317 3, 1, 0),
318 SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
319 0, 7, 1),
320
321 SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
322 WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
323 SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
324 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
325 SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
326 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
327
328 SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
329 WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
330 8, 1, 0, pga_boost_tlv),
331
332 SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
333 SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
334
335 SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
336 WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
337
338 SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
339 SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
340 SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
341 SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
342 4, 7, 1, lim_thresh_tlv),
343 SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
344 0, 12, 0, lim_boost_tlv),
345 SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
346 SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
347 SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
348
349 SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
350 WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
351 SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
352 WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
353 SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
354 WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
355
356 SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
357 WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
358 SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
359 WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
360 SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
361 WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
362
363 SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
364 SOC_ENUM("High Pass Filter Mode", filter_mode),
365 SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
366
367 SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
368 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
369 bypass_tlv),
370
371 SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
372 SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
373 SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
374 SOC_ENUM("EQ2 Bandwidth", eq2_bw),
375 SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
376 SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
377 SOC_ENUM("EQ3 Bandwidth", eq3_bw),
378 SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
379 SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
380 SOC_ENUM("EQ4 Bandwidth", eq4_bw),
381 SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
382 SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
383 SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
384 SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
385
386 SOC_ENUM("3D Depth", depth_3d),
387 };
388
389 static const struct snd_kcontrol_new wm8985_specific_snd_controls[] = {
390 SOC_DOUBLE_R_TLV("Aux Bypass Volume",
391 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
392 aux_tlv),
393
394 SOC_ENUM("Speaker Mode", speaker_mode)
395 };
396
397 static const struct snd_kcontrol_new left_out_mixer[] = {
398 SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
399 SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
400
401 /* --- WM8985 only --- */
402 SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
403 };
404
405 static const struct snd_kcontrol_new right_out_mixer[] = {
406 SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
407 SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
408
409 /* --- WM8985 only --- */
410 SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
411 };
412
413 static const struct snd_kcontrol_new left_input_mixer[] = {
414 SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
415 SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
416 SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
417 };
418
419 static const struct snd_kcontrol_new right_input_mixer[] = {
420 SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
421 SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
422 SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
423 };
424
425 static const struct snd_kcontrol_new left_boost_mixer[] = {
426 SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
427 4, 7, 0, boost_tlv),
428
429 /* --- WM8985 only --- */
430 SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
431 0, 7, 0, boost_tlv)
432 };
433
434 static const struct snd_kcontrol_new right_boost_mixer[] = {
435 SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
436 4, 7, 0, boost_tlv),
437
438 /* --- WM8985 only --- */
439 SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
440 0, 7, 0, boost_tlv)
441 };
442
443 static const struct snd_soc_dapm_widget wm8985_common_dapm_widgets[] = {
444 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
445 0, 0),
446 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
447 1, 0),
448 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
449 0, 0),
450 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
451 1, 0),
452
453 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
454 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
455 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
456 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
457
458 SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
459 6, 1, NULL, 0),
460 SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
461 6, 1, NULL, 0),
462
463 SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
464 7, 0, NULL, 0),
465 SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
466 8, 0, NULL, 0),
467
468 SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
469 5, 0, NULL, 0),
470 SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
471 6, 0, NULL, 0),
472
473 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
474 NULL, 0),
475
476 SND_SOC_DAPM_INPUT("LIN"),
477 SND_SOC_DAPM_INPUT("LIP"),
478 SND_SOC_DAPM_INPUT("RIN"),
479 SND_SOC_DAPM_INPUT("RIP"),
480 SND_SOC_DAPM_INPUT("L2"),
481 SND_SOC_DAPM_INPUT("R2"),
482 SND_SOC_DAPM_OUTPUT("HPL"),
483 SND_SOC_DAPM_OUTPUT("HPR"),
484 SND_SOC_DAPM_OUTPUT("SPKL"),
485 SND_SOC_DAPM_OUTPUT("SPKR")
486 };
487
488 static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
489 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
490 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
491 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
492 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
493
494 SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
495 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
496 SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
497 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
498
499 SND_SOC_DAPM_INPUT("AUXL"),
500 SND_SOC_DAPM_INPUT("AUXR"),
501 };
502
503 static const struct snd_soc_dapm_widget wm8758_dapm_widgets[] = {
504 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
505 2, 0, left_out_mixer,
506 ARRAY_SIZE(left_out_mixer) - 1),
507 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
508 3, 0, right_out_mixer,
509 ARRAY_SIZE(right_out_mixer) - 1),
510
511 SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
512 4, 0, left_boost_mixer,
513 ARRAY_SIZE(left_boost_mixer) - 1),
514 SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
515 5, 0, right_boost_mixer,
516 ARRAY_SIZE(right_boost_mixer) - 1),
517 };
518
519 static const struct snd_soc_dapm_route wm8985_common_dapm_routes[] = {
520 { "Right Output Mixer", "PCM Switch", "Right DAC" },
521 { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
522
523 { "Left Output Mixer", "PCM Switch", "Left DAC" },
524 { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
525
526 { "Right Headphone Out", NULL, "Right Output Mixer" },
527 { "HPR", NULL, "Right Headphone Out" },
528
529 { "Left Headphone Out", NULL, "Left Output Mixer" },
530 { "HPL", NULL, "Left Headphone Out" },
531
532 { "Right Speaker Out", NULL, "Right Output Mixer" },
533 { "SPKR", NULL, "Right Speaker Out" },
534
535 { "Left Speaker Out", NULL, "Left Output Mixer" },
536 { "SPKL", NULL, "Left Speaker Out" },
537
538 { "Right ADC", NULL, "Right Boost Mixer" },
539
540 { "Right Boost Mixer", NULL, "Right Capture PGA" },
541 { "Right Boost Mixer", "R2 Volume", "R2" },
542
543 { "Left ADC", NULL, "Left Boost Mixer" },
544
545 { "Left Boost Mixer", NULL, "Left Capture PGA" },
546 { "Left Boost Mixer", "L2 Volume", "L2" },
547
548 { "Right Capture PGA", NULL, "Right Input Mixer" },
549 { "Left Capture PGA", NULL, "Left Input Mixer" },
550
551 { "Right Input Mixer", "R2 Switch", "R2" },
552 { "Right Input Mixer", "MicN Switch", "RIN" },
553 { "Right Input Mixer", "MicP Switch", "RIP" },
554
555 { "Left Input Mixer", "L2 Switch", "L2" },
556 { "Left Input Mixer", "MicN Switch", "LIN" },
557 { "Left Input Mixer", "MicP Switch", "LIP" },
558 };
559 static const struct snd_soc_dapm_route wm8985_aux_dapm_routes[] = {
560 { "Right Output Mixer", "Aux Switch", "AUXR" },
561 { "Left Output Mixer", "Aux Switch", "AUXL" },
562
563 { "Right Boost Mixer", "AUXR Volume", "AUXR" },
564 { "Left Boost Mixer", "AUXL Volume", "AUXL" },
565 };
566
567 static int wm8985_add_widgets(struct snd_soc_codec *codec)
568 {
569 struct wm8985_priv *wm8985 = snd_soc_codec_get_drvdata(codec);
570 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
571
572 switch (wm8985->dev_type) {
573 case WM8758:
574 snd_soc_dapm_new_controls(dapm, wm8758_dapm_widgets,
575 ARRAY_SIZE(wm8758_dapm_widgets));
576 break;
577
578 case WM8985:
579 snd_soc_add_codec_controls(codec, wm8985_specific_snd_controls,
580 ARRAY_SIZE(wm8985_specific_snd_controls));
581
582 snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
583 ARRAY_SIZE(wm8985_dapm_widgets));
584 snd_soc_dapm_add_routes(dapm, wm8985_aux_dapm_routes,
585 ARRAY_SIZE(wm8985_aux_dapm_routes));
586 break;
587 }
588
589 return 0;
590 }
591
592 static int eqmode_get(struct snd_kcontrol *kcontrol,
593 struct snd_ctl_elem_value *ucontrol)
594 {
595 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
596 unsigned int reg;
597
598 reg = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
599 if (reg & WM8985_EQ3DMODE)
600 ucontrol->value.enumerated.item[0] = 1;
601 else
602 ucontrol->value.enumerated.item[0] = 0;
603
604 return 0;
605 }
606
607 static int eqmode_put(struct snd_kcontrol *kcontrol,
608 struct snd_ctl_elem_value *ucontrol)
609 {
610 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
611 unsigned int regpwr2, regpwr3;
612 unsigned int reg_eq;
613
614 if (ucontrol->value.enumerated.item[0] != 0
615 && ucontrol->value.enumerated.item[0] != 1)
616 return -EINVAL;
617
618 reg_eq = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
619 switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
620 case 0:
621 if (!ucontrol->value.enumerated.item[0])
622 return 0;
623 break;
624 case 1:
625 if (ucontrol->value.enumerated.item[0])
626 return 0;
627 break;
628 }
629
630 regpwr2 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_2);
631 regpwr3 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_3);
632 /* disable the DACs and ADCs */
633 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_2,
634 WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
635 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_3,
636 WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
637 snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
638 WM8985_M128ENB_MASK, WM8985_M128ENB);
639 /* set the desired eqmode */
640 snd_soc_update_bits(codec, WM8985_EQ1_LOW_SHELF,
641 WM8985_EQ3DMODE_MASK,
642 ucontrol->value.enumerated.item[0]
643 << WM8985_EQ3DMODE_SHIFT);
644 /* restore DAC/ADC configuration */
645 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, regpwr2);
646 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, regpwr3);
647 return 0;
648 }
649
650 static int wm8985_reset(struct snd_soc_codec *codec)
651 {
652 return snd_soc_write(codec, WM8985_SOFTWARE_RESET, 0x0);
653 }
654
655 static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute)
656 {
657 struct snd_soc_codec *codec = dai->codec;
658
659 return snd_soc_update_bits(codec, WM8985_DAC_CONTROL,
660 WM8985_SOFTMUTE_MASK,
661 !!mute << WM8985_SOFTMUTE_SHIFT);
662 }
663
664 static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
665 {
666 struct snd_soc_codec *codec;
667 u16 format, master, bcp, lrp;
668
669 codec = dai->codec;
670
671 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
672 case SND_SOC_DAIFMT_I2S:
673 format = 0x2;
674 break;
675 case SND_SOC_DAIFMT_RIGHT_J:
676 format = 0x0;
677 break;
678 case SND_SOC_DAIFMT_LEFT_J:
679 format = 0x1;
680 break;
681 case SND_SOC_DAIFMT_DSP_A:
682 case SND_SOC_DAIFMT_DSP_B:
683 format = 0x3;
684 break;
685 default:
686 dev_err(dai->dev, "Unknown dai format\n");
687 return -EINVAL;
688 }
689
690 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
691 WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
692
693 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
694 case SND_SOC_DAIFMT_CBM_CFM:
695 master = 1;
696 break;
697 case SND_SOC_DAIFMT_CBS_CFS:
698 master = 0;
699 break;
700 default:
701 dev_err(dai->dev, "Unknown master/slave configuration\n");
702 return -EINVAL;
703 }
704
705 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
706 WM8985_MS_MASK, master << WM8985_MS_SHIFT);
707
708 /* frame inversion is not valid for dsp modes */
709 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
710 case SND_SOC_DAIFMT_DSP_A:
711 case SND_SOC_DAIFMT_DSP_B:
712 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
713 case SND_SOC_DAIFMT_IB_IF:
714 case SND_SOC_DAIFMT_NB_IF:
715 return -EINVAL;
716 default:
717 break;
718 }
719 break;
720 default:
721 break;
722 }
723
724 bcp = lrp = 0;
725 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
726 case SND_SOC_DAIFMT_NB_NF:
727 break;
728 case SND_SOC_DAIFMT_IB_IF:
729 bcp = lrp = 1;
730 break;
731 case SND_SOC_DAIFMT_IB_NF:
732 bcp = 1;
733 break;
734 case SND_SOC_DAIFMT_NB_IF:
735 lrp = 1;
736 break;
737 default:
738 dev_err(dai->dev, "Unknown polarity configuration\n");
739 return -EINVAL;
740 }
741
742 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
743 WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
744 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
745 WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
746 return 0;
747 }
748
749 static int wm8985_hw_params(struct snd_pcm_substream *substream,
750 struct snd_pcm_hw_params *params,
751 struct snd_soc_dai *dai)
752 {
753 int i;
754 struct snd_soc_codec *codec;
755 struct wm8985_priv *wm8985;
756 u16 blen, srate_idx;
757 unsigned int tmp;
758 int srate_best;
759
760 codec = dai->codec;
761 wm8985 = snd_soc_codec_get_drvdata(codec);
762
763 wm8985->bclk = snd_soc_params_to_bclk(params);
764 if ((int)wm8985->bclk < 0)
765 return wm8985->bclk;
766
767 switch (params_width(params)) {
768 case 16:
769 blen = 0x0;
770 break;
771 case 20:
772 blen = 0x1;
773 break;
774 case 24:
775 blen = 0x2;
776 break;
777 case 32:
778 blen = 0x3;
779 break;
780 default:
781 dev_err(dai->dev, "Unsupported word length %u\n",
782 params_width(params));
783 return -EINVAL;
784 }
785
786 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
787 WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
788
789 /*
790 * match to the nearest possible sample rate and rely
791 * on the array index to configure the SR register
792 */
793 srate_idx = 0;
794 srate_best = abs(srates[0] - params_rate(params));
795 for (i = 1; i < ARRAY_SIZE(srates); ++i) {
796 if (abs(srates[i] - params_rate(params)) >= srate_best)
797 continue;
798 srate_idx = i;
799 srate_best = abs(srates[i] - params_rate(params));
800 }
801
802 dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
803 snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
804 WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
805
806 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
807 dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
808
809 for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
810 if (wm8985->sysclk / params_rate(params)
811 == fs_ratios[i].ratio)
812 break;
813 }
814
815 if (i == ARRAY_SIZE(fs_ratios)) {
816 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
817 wm8985->sysclk, params_rate(params));
818 return -EINVAL;
819 }
820
821 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
822 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
823 WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
824
825 /* select the appropriate bclk divider */
826 tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
827 for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
828 if (wm8985->bclk == tmp / bclk_divs[i])
829 break;
830 }
831
832 if (i == ARRAY_SIZE(bclk_divs)) {
833 dev_err(dai->dev, "No matching BCLK divider found\n");
834 return -EINVAL;
835 }
836
837 dev_dbg(dai->dev, "BCLK div = %d\n", i);
838 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
839 WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
840 return 0;
841 }
842
843 struct pll_div {
844 u32 div2:1;
845 u32 n:4;
846 u32 k:24;
847 };
848
849 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
850 static int pll_factors(struct pll_div *pll_div, unsigned int target,
851 unsigned int source)
852 {
853 u64 Kpart;
854 unsigned long int K, Ndiv, Nmod;
855
856 pll_div->div2 = 0;
857 Ndiv = target / source;
858 if (Ndiv < 6) {
859 source >>= 1;
860 pll_div->div2 = 1;
861 Ndiv = target / source;
862 }
863
864 if (Ndiv < 6 || Ndiv > 12) {
865 printk(KERN_ERR "%s: WM8985 N value is not within"
866 " the recommended range: %lu\n", __func__, Ndiv);
867 return -EINVAL;
868 }
869 pll_div->n = Ndiv;
870
871 Nmod = target % source;
872 Kpart = FIXED_PLL_SIZE * (u64)Nmod;
873
874 do_div(Kpart, source);
875
876 K = Kpart & 0xffffffff;
877 if ((K % 10) >= 5)
878 K += 5;
879 K /= 10;
880 pll_div->k = K;
881
882 return 0;
883 }
884
885 static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
886 int source, unsigned int freq_in,
887 unsigned int freq_out)
888 {
889 int ret;
890 struct snd_soc_codec *codec;
891 struct pll_div pll_div;
892
893 codec = dai->codec;
894 if (!freq_in || !freq_out) {
895 /* disable the PLL */
896 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
897 WM8985_PLLEN_MASK, 0);
898 } else {
899 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
900 if (ret)
901 return ret;
902
903 /* set PLLN and PRESCALE */
904 snd_soc_write(codec, WM8985_PLL_N,
905 (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
906 | pll_div.n);
907 /* set PLLK */
908 snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff);
909 snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
910 snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18));
911 /* set the source of the clock to be the PLL */
912 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
913 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
914 /* enable the PLL */
915 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
916 WM8985_PLLEN_MASK, WM8985_PLLEN);
917 }
918 return 0;
919 }
920
921 static int wm8985_set_sysclk(struct snd_soc_dai *dai,
922 int clk_id, unsigned int freq, int dir)
923 {
924 struct snd_soc_codec *codec;
925 struct wm8985_priv *wm8985;
926
927 codec = dai->codec;
928 wm8985 = snd_soc_codec_get_drvdata(codec);
929
930 switch (clk_id) {
931 case WM8985_CLKSRC_MCLK:
932 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
933 WM8985_CLKSEL_MASK, 0);
934 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
935 WM8985_PLLEN_MASK, 0);
936 break;
937 case WM8985_CLKSRC_PLL:
938 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
939 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
940 break;
941 default:
942 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
943 return -EINVAL;
944 }
945
946 wm8985->sysclk = freq;
947 return 0;
948 }
949
950 static int wm8985_set_bias_level(struct snd_soc_codec *codec,
951 enum snd_soc_bias_level level)
952 {
953 int ret;
954 struct wm8985_priv *wm8985;
955
956 wm8985 = snd_soc_codec_get_drvdata(codec);
957 switch (level) {
958 case SND_SOC_BIAS_ON:
959 case SND_SOC_BIAS_PREPARE:
960 /* VMID at 75k */
961 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
962 WM8985_VMIDSEL_MASK,
963 1 << WM8985_VMIDSEL_SHIFT);
964 break;
965 case SND_SOC_BIAS_STANDBY:
966 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
967 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
968 wm8985->supplies);
969 if (ret) {
970 dev_err(codec->dev,
971 "Failed to enable supplies: %d\n",
972 ret);
973 return ret;
974 }
975
976 regcache_sync(wm8985->regmap);
977
978 /* enable anti-pop features */
979 snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
980 WM8985_POBCTRL_MASK,
981 WM8985_POBCTRL);
982 /* enable thermal shutdown */
983 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
984 WM8985_TSDEN_MASK, WM8985_TSDEN);
985 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
986 WM8985_TSOPCTRL_MASK,
987 WM8985_TSOPCTRL);
988 /* enable BIASEN */
989 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
990 WM8985_BIASEN_MASK, WM8985_BIASEN);
991 /* VMID at 75k */
992 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
993 WM8985_VMIDSEL_MASK,
994 1 << WM8985_VMIDSEL_SHIFT);
995 msleep(500);
996 /* disable anti-pop features */
997 snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
998 WM8985_POBCTRL_MASK, 0);
999 }
1000 /* VMID at 300k */
1001 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
1002 WM8985_VMIDSEL_MASK,
1003 2 << WM8985_VMIDSEL_SHIFT);
1004 break;
1005 case SND_SOC_BIAS_OFF:
1006 /* disable thermal shutdown */
1007 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
1008 WM8985_TSOPCTRL_MASK, 0);
1009 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
1010 WM8985_TSDEN_MASK, 0);
1011 /* disable VMIDSEL and BIASEN */
1012 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
1013 WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
1014 0);
1015 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_1, 0);
1016 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, 0);
1017 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, 0);
1018
1019 regcache_mark_dirty(wm8985->regmap);
1020
1021 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
1022 wm8985->supplies);
1023 break;
1024 }
1025
1026 return 0;
1027 }
1028
1029 static int wm8985_probe(struct snd_soc_codec *codec)
1030 {
1031 size_t i;
1032 struct wm8985_priv *wm8985;
1033 int ret;
1034
1035 wm8985 = snd_soc_codec_get_drvdata(codec);
1036
1037 for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
1038 wm8985->supplies[i].supply = wm8985_supply_names[i];
1039
1040 ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8985->supplies),
1041 wm8985->supplies);
1042 if (ret) {
1043 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1044 return ret;
1045 }
1046
1047 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
1048 wm8985->supplies);
1049 if (ret) {
1050 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1051 return ret;
1052 }
1053
1054 ret = wm8985_reset(codec);
1055 if (ret < 0) {
1056 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1057 goto err_reg_enable;
1058 }
1059
1060 /* latch volume update bits */
1061 for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
1062 snd_soc_update_bits(codec, volume_update_regs[i],
1063 0x100, 0x100);
1064 /* enable BIASCUT */
1065 snd_soc_update_bits(codec, WM8985_BIAS_CTRL, WM8985_BIASCUT,
1066 WM8985_BIASCUT);
1067
1068 wm8985_add_widgets(codec);
1069
1070 return 0;
1071
1072 err_reg_enable:
1073 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1074 return ret;
1075 }
1076
1077 static const struct snd_soc_dai_ops wm8985_dai_ops = {
1078 .digital_mute = wm8985_dac_mute,
1079 .hw_params = wm8985_hw_params,
1080 .set_fmt = wm8985_set_fmt,
1081 .set_sysclk = wm8985_set_sysclk,
1082 .set_pll = wm8985_set_pll
1083 };
1084
1085 #define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1086 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1087
1088 static struct snd_soc_dai_driver wm8985_dai = {
1089 .name = "wm8985-hifi",
1090 .playback = {
1091 .stream_name = "Playback",
1092 .channels_min = 2,
1093 .channels_max = 2,
1094 .rates = SNDRV_PCM_RATE_8000_48000,
1095 .formats = WM8985_FORMATS,
1096 },
1097 .capture = {
1098 .stream_name = "Capture",
1099 .channels_min = 2,
1100 .channels_max = 2,
1101 .rates = SNDRV_PCM_RATE_8000_48000,
1102 .formats = WM8985_FORMATS,
1103 },
1104 .ops = &wm8985_dai_ops,
1105 .symmetric_rates = 1
1106 };
1107
1108 static const struct snd_soc_codec_driver soc_codec_dev_wm8985 = {
1109 .probe = wm8985_probe,
1110 .set_bias_level = wm8985_set_bias_level,
1111 .suspend_bias_off = true,
1112
1113 .component_driver = {
1114 .controls = wm8985_common_snd_controls,
1115 .num_controls = ARRAY_SIZE(wm8985_common_snd_controls),
1116 .dapm_widgets = wm8985_common_dapm_widgets,
1117 .num_dapm_widgets = ARRAY_SIZE(wm8985_common_dapm_widgets),
1118 .dapm_routes = wm8985_common_dapm_routes,
1119 .num_dapm_routes = ARRAY_SIZE(wm8985_common_dapm_routes),
1120 },
1121 };
1122
1123 static const struct regmap_config wm8985_regmap = {
1124 .reg_bits = 7,
1125 .val_bits = 9,
1126
1127 .max_register = WM8985_MAX_REGISTER,
1128 .writeable_reg = wm8985_writeable,
1129
1130 .cache_type = REGCACHE_RBTREE,
1131 .reg_defaults = wm8985_reg_defaults,
1132 .num_reg_defaults = ARRAY_SIZE(wm8985_reg_defaults),
1133 };
1134
1135 #if defined(CONFIG_SPI_MASTER)
1136 static int wm8985_spi_probe(struct spi_device *spi)
1137 {
1138 struct wm8985_priv *wm8985;
1139 int ret;
1140
1141 wm8985 = devm_kzalloc(&spi->dev, sizeof *wm8985, GFP_KERNEL);
1142 if (!wm8985)
1143 return -ENOMEM;
1144
1145 spi_set_drvdata(spi, wm8985);
1146
1147 wm8985->dev_type = WM8985;
1148
1149 wm8985->regmap = devm_regmap_init_spi(spi, &wm8985_regmap);
1150 if (IS_ERR(wm8985->regmap)) {
1151 ret = PTR_ERR(wm8985->regmap);
1152 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1153 ret);
1154 return ret;
1155 }
1156
1157 ret = snd_soc_register_codec(&spi->dev,
1158 &soc_codec_dev_wm8985, &wm8985_dai, 1);
1159 return ret;
1160 }
1161
1162 static int wm8985_spi_remove(struct spi_device *spi)
1163 {
1164 snd_soc_unregister_codec(&spi->dev);
1165 return 0;
1166 }
1167
1168 static struct spi_driver wm8985_spi_driver = {
1169 .driver = {
1170 .name = "wm8985",
1171 },
1172 .probe = wm8985_spi_probe,
1173 .remove = wm8985_spi_remove
1174 };
1175 #endif
1176
1177 #if IS_ENABLED(CONFIG_I2C)
1178 static int wm8985_i2c_probe(struct i2c_client *i2c,
1179 const struct i2c_device_id *id)
1180 {
1181 struct wm8985_priv *wm8985;
1182 int ret;
1183
1184 wm8985 = devm_kzalloc(&i2c->dev, sizeof *wm8985, GFP_KERNEL);
1185 if (!wm8985)
1186 return -ENOMEM;
1187
1188 i2c_set_clientdata(i2c, wm8985);
1189
1190 wm8985->dev_type = id->driver_data;
1191
1192 wm8985->regmap = devm_regmap_init_i2c(i2c, &wm8985_regmap);
1193 if (IS_ERR(wm8985->regmap)) {
1194 ret = PTR_ERR(wm8985->regmap);
1195 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1196 ret);
1197 return ret;
1198 }
1199
1200 ret = snd_soc_register_codec(&i2c->dev,
1201 &soc_codec_dev_wm8985, &wm8985_dai, 1);
1202 return ret;
1203 }
1204
1205 static int wm8985_i2c_remove(struct i2c_client *i2c)
1206 {
1207 snd_soc_unregister_codec(&i2c->dev);
1208 return 0;
1209 }
1210
1211 static const struct i2c_device_id wm8985_i2c_id[] = {
1212 { "wm8985", WM8985 },
1213 { "wm8758", WM8758 },
1214 { }
1215 };
1216 MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
1217
1218 static struct i2c_driver wm8985_i2c_driver = {
1219 .driver = {
1220 .name = "wm8985",
1221 },
1222 .probe = wm8985_i2c_probe,
1223 .remove = wm8985_i2c_remove,
1224 .id_table = wm8985_i2c_id
1225 };
1226 #endif
1227
1228 static int __init wm8985_modinit(void)
1229 {
1230 int ret = 0;
1231
1232 #if IS_ENABLED(CONFIG_I2C)
1233 ret = i2c_add_driver(&wm8985_i2c_driver);
1234 if (ret) {
1235 printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
1236 ret);
1237 }
1238 #endif
1239 #if defined(CONFIG_SPI_MASTER)
1240 ret = spi_register_driver(&wm8985_spi_driver);
1241 if (ret != 0) {
1242 printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
1243 ret);
1244 }
1245 #endif
1246 return ret;
1247 }
1248 module_init(wm8985_modinit);
1249
1250 static void __exit wm8985_exit(void)
1251 {
1252 #if IS_ENABLED(CONFIG_I2C)
1253 i2c_del_driver(&wm8985_i2c_driver);
1254 #endif
1255 #if defined(CONFIG_SPI_MASTER)
1256 spi_unregister_driver(&wm8985_spi_driver);
1257 #endif
1258 }
1259 module_exit(wm8985_exit);
1260
1261 MODULE_DESCRIPTION("ASoC WM8985 / WM8758 driver");
1262 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1263 MODULE_LICENSE("GPL");
Linux with added FPC-III support