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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / sound / soc / codecs / wm_adsp.c
blobd632a0511d62ac7a35da520748b3fc35eccd316b
1 /*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/list.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/workqueue.h>
26 #include <linux/debugfs.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/jack.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
34
35 #include "wm_adsp.h"
36
37 #define adsp_crit(_dsp, fmt, ...) \
38 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39 #define adsp_err(_dsp, fmt, ...) \
40 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41 #define adsp_warn(_dsp, fmt, ...) \
42 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43 #define adsp_info(_dsp, fmt, ...) \
44 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45 #define adsp_dbg(_dsp, fmt, ...) \
46 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47
48 #define ADSP1_CONTROL_1 0x00
49 #define ADSP1_CONTROL_2 0x02
50 #define ADSP1_CONTROL_3 0x03
51 #define ADSP1_CONTROL_4 0x04
52 #define ADSP1_CONTROL_5 0x06
53 #define ADSP1_CONTROL_6 0x07
54 #define ADSP1_CONTROL_7 0x08
55 #define ADSP1_CONTROL_8 0x09
56 #define ADSP1_CONTROL_9 0x0A
57 #define ADSP1_CONTROL_10 0x0B
58 #define ADSP1_CONTROL_11 0x0C
59 #define ADSP1_CONTROL_12 0x0D
60 #define ADSP1_CONTROL_13 0x0F
61 #define ADSP1_CONTROL_14 0x10
62 #define ADSP1_CONTROL_15 0x11
63 #define ADSP1_CONTROL_16 0x12
64 #define ADSP1_CONTROL_17 0x13
65 #define ADSP1_CONTROL_18 0x14
66 #define ADSP1_CONTROL_19 0x16
67 #define ADSP1_CONTROL_20 0x17
68 #define ADSP1_CONTROL_21 0x18
69 #define ADSP1_CONTROL_22 0x1A
70 #define ADSP1_CONTROL_23 0x1B
71 #define ADSP1_CONTROL_24 0x1C
72 #define ADSP1_CONTROL_25 0x1E
73 #define ADSP1_CONTROL_26 0x20
74 #define ADSP1_CONTROL_27 0x21
75 #define ADSP1_CONTROL_28 0x22
76 #define ADSP1_CONTROL_29 0x23
77 #define ADSP1_CONTROL_30 0x24
78 #define ADSP1_CONTROL_31 0x26
79
80 /*
81 * ADSP1 Control 19
82 */
83 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86
87
88 /*
89 * ADSP1 Control 30
90 */
91 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
92 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
93 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
94 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
95 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
96 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
97 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
98 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
99 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
100 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
101 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
102 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
103 #define ADSP1_START 0x0001 /* DSP1_START */
104 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
105 #define ADSP1_START_SHIFT 0 /* DSP1_START */
106 #define ADSP1_START_WIDTH 1 /* DSP1_START */
107
108 /*
109 * ADSP1 Control 31
110 */
111 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
112 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
113 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
114
115 #define ADSP2_CONTROL 0x0
116 #define ADSP2_CLOCKING 0x1
117 #define ADSP2V2_CLOCKING 0x2
118 #define ADSP2_STATUS1 0x4
119 #define ADSP2_WDMA_CONFIG_1 0x30
120 #define ADSP2_WDMA_CONFIG_2 0x31
121 #define ADSP2V2_WDMA_CONFIG_2 0x32
122 #define ADSP2_RDMA_CONFIG_1 0x34
123
124 #define ADSP2_SCRATCH0 0x40
125 #define ADSP2_SCRATCH1 0x41
126 #define ADSP2_SCRATCH2 0x42
127 #define ADSP2_SCRATCH3 0x43
128
129 #define ADSP2V2_SCRATCH0_1 0x40
130 #define ADSP2V2_SCRATCH2_3 0x42
131
132 /*
133 * ADSP2 Control
134 */
135
136 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
137 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
138 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
139 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
140 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
141 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
142 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
143 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
144 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
145 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
146 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
147 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
148 #define ADSP2_START 0x0001 /* DSP1_START */
149 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
150 #define ADSP2_START_SHIFT 0 /* DSP1_START */
151 #define ADSP2_START_WIDTH 1 /* DSP1_START */
152
153 /*
154 * ADSP2 clocking
155 */
156 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
157 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
158 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
159
160 /*
161 * ADSP2V2 clocking
162 */
163 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
164 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
165 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
166
167 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
168 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
169 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
170
171 /*
172 * ADSP2 Status 1
173 */
174 #define ADSP2_RAM_RDY 0x0001
175 #define ADSP2_RAM_RDY_MASK 0x0001
176 #define ADSP2_RAM_RDY_SHIFT 0
177 #define ADSP2_RAM_RDY_WIDTH 1
178
179 /*
180 * ADSP2 Lock support
181 */
182 #define ADSP2_LOCK_CODE_0 0x5555
183 #define ADSP2_LOCK_CODE_1 0xAAAA
184
185 #define ADSP2_WATCHDOG 0x0A
186 #define ADSP2_BUS_ERR_ADDR 0x52
187 #define ADSP2_REGION_LOCK_STATUS 0x64
188 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
189 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
190 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
191 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
192 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
193 #define ADSP2_LOCK_REGION_CTRL 0x7A
194 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
195
196 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000
197 #define ADSP2_SLAVE_ERR_MASK 0x4000
198 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
199 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
200 #define ADSP2_CTRL_ERR_EINT 0x0001
201
202 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
203 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
204 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
205 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16
206 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
207
208 #define ADSP2_LOCK_REGION_SHIFT 16
209
210 #define ADSP_MAX_STD_CTRL_SIZE 512
211
212 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
213 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
214 #define WM_ADSP_ACKED_CTL_MIN_VALUE 0
215 #define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
216
217 /*
218 * Event control messages
219 */
220 #define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
221
222 struct wm_adsp_buf {
223 struct list_head list;
224 void *buf;
225 };
226
227 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
228 struct list_head *list)
229 {
230 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
231
232 if (buf == NULL)
233 return NULL;
234
235 buf->buf = vmalloc(len);
236 if (!buf->buf) {
237 kfree(buf);
238 return NULL;
239 }
240 memcpy(buf->buf, src, len);
241
242 if (list)
243 list_add_tail(&buf->list, list);
244
245 return buf;
246 }
247
248 static void wm_adsp_buf_free(struct list_head *list)
249 {
250 while (!list_empty(list)) {
251 struct wm_adsp_buf *buf = list_first_entry(list,
252 struct wm_adsp_buf,
253 list);
254 list_del(&buf->list);
255 vfree(buf->buf);
256 kfree(buf);
257 }
258 }
259
260 #define WM_ADSP_FW_MBC_VSS 0
261 #define WM_ADSP_FW_HIFI 1
262 #define WM_ADSP_FW_TX 2
263 #define WM_ADSP_FW_TX_SPK 3
264 #define WM_ADSP_FW_RX 4
265 #define WM_ADSP_FW_RX_ANC 5
266 #define WM_ADSP_FW_CTRL 6
267 #define WM_ADSP_FW_ASR 7
268 #define WM_ADSP_FW_TRACE 8
269 #define WM_ADSP_FW_SPK_PROT 9
270 #define WM_ADSP_FW_MISC 10
271
272 #define WM_ADSP_NUM_FW 11
273
274 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
275 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
276 [WM_ADSP_FW_HIFI] = "MasterHiFi",
277 [WM_ADSP_FW_TX] = "Tx",
278 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
279 [WM_ADSP_FW_RX] = "Rx",
280 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
281 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
282 [WM_ADSP_FW_ASR] = "ASR Assist",
283 [WM_ADSP_FW_TRACE] = "Dbg Trace",
284 [WM_ADSP_FW_SPK_PROT] = "Protection",
285 [WM_ADSP_FW_MISC] = "Misc",
286 };
287
288 struct wm_adsp_system_config_xm_hdr {
289 __be32 sys_enable;
290 __be32 fw_id;
291 __be32 fw_rev;
292 __be32 boot_status;
293 __be32 watchdog;
294 __be32 dma_buffer_size;
295 __be32 rdma[6];
296 __be32 wdma[8];
297 __be32 build_job_name[3];
298 __be32 build_job_number;
299 };
300
301 struct wm_adsp_alg_xm_struct {
302 __be32 magic;
303 __be32 smoothing;
304 __be32 threshold;
305 __be32 host_buf_ptr;
306 __be32 start_seq;
307 __be32 high_water_mark;
308 __be32 low_water_mark;
309 __be64 smoothed_power;
310 };
311
312 struct wm_adsp_buffer {
313 __be32 X_buf_base; /* XM base addr of first X area */
314 __be32 X_buf_size; /* Size of 1st X area in words */
315 __be32 X_buf_base2; /* XM base addr of 2nd X area */
316 __be32 X_buf_brk; /* Total X size in words */
317 __be32 Y_buf_base; /* YM base addr of Y area */
318 __be32 wrap; /* Total size X and Y in words */
319 __be32 high_water_mark; /* Point at which IRQ is asserted */
320 __be32 irq_count; /* bits 1-31 count IRQ assertions */
321 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
322 __be32 next_write_index; /* word index of next write */
323 __be32 next_read_index; /* word index of next read */
324 __be32 error; /* error if any */
325 __be32 oldest_block_index; /* word index of oldest surviving */
326 __be32 requested_rewind; /* how many blocks rewind was done */
327 __be32 reserved_space; /* internal */
328 __be32 min_free; /* min free space since stream start */
329 __be32 blocks_written[2]; /* total blocks written (64 bit) */
330 __be32 words_written[2]; /* total words written (64 bit) */
331 };
332
333 struct wm_adsp_compr;
334
335 struct wm_adsp_compr_buf {
336 struct wm_adsp *dsp;
337 struct wm_adsp_compr *compr;
338
339 struct wm_adsp_buffer_region *regions;
340 u32 host_buf_ptr;
341
342 u32 error;
343 u32 irq_count;
344 int read_index;
345 int avail;
346 };
347
348 struct wm_adsp_compr {
349 struct wm_adsp *dsp;
350 struct wm_adsp_compr_buf *buf;
351
352 struct snd_compr_stream *stream;
353 struct snd_compressed_buffer size;
354
355 u32 *raw_buf;
356 unsigned int copied_total;
357
358 unsigned int sample_rate;
359 };
360
361 #define WM_ADSP_DATA_WORD_SIZE 3
362
363 #define WM_ADSP_MIN_FRAGMENTS 1
364 #define WM_ADSP_MAX_FRAGMENTS 256
365 #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
366 #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
367
368 #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
369
370 #define HOST_BUFFER_FIELD(field) \
371 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
372
373 #define ALG_XM_FIELD(field) \
374 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
375
376 static int wm_adsp_buffer_init(struct wm_adsp *dsp);
377 static int wm_adsp_buffer_free(struct wm_adsp *dsp);
378
379 struct wm_adsp_buffer_region {
380 unsigned int offset;
381 unsigned int cumulative_size;
382 unsigned int mem_type;
383 unsigned int base_addr;
384 };
385
386 struct wm_adsp_buffer_region_def {
387 unsigned int mem_type;
388 unsigned int base_offset;
389 unsigned int size_offset;
390 };
391
392 static const struct wm_adsp_buffer_region_def default_regions[] = {
393 {
394 .mem_type = WMFW_ADSP2_XM,
395 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
396 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
397 },
398 {
399 .mem_type = WMFW_ADSP2_XM,
400 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
401 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
402 },
403 {
404 .mem_type = WMFW_ADSP2_YM,
405 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
406 .size_offset = HOST_BUFFER_FIELD(wrap),
407 },
408 };
409
410 struct wm_adsp_fw_caps {
411 u32 id;
412 struct snd_codec_desc desc;
413 int num_regions;
414 const struct wm_adsp_buffer_region_def *region_defs;
415 };
416
417 static const struct wm_adsp_fw_caps ctrl_caps[] = {
418 {
419 .id = SND_AUDIOCODEC_BESPOKE,
420 .desc = {
421 .max_ch = 1,
422 .sample_rates = { 16000 },
423 .num_sample_rates = 1,
424 .formats = SNDRV_PCM_FMTBIT_S16_LE,
425 },
426 .num_regions = ARRAY_SIZE(default_regions),
427 .region_defs = default_regions,
428 },
429 };
430
431 static const struct wm_adsp_fw_caps trace_caps[] = {
432 {
433 .id = SND_AUDIOCODEC_BESPOKE,
434 .desc = {
435 .max_ch = 8,
436 .sample_rates = {
437 4000, 8000, 11025, 12000, 16000, 22050,
438 24000, 32000, 44100, 48000, 64000, 88200,
439 96000, 176400, 192000
440 },
441 .num_sample_rates = 15,
442 .formats = SNDRV_PCM_FMTBIT_S16_LE,
443 },
444 .num_regions = ARRAY_SIZE(default_regions),
445 .region_defs = default_regions,
446 },
447 };
448
449 static const struct {
450 const char *file;
451 int compr_direction;
452 int num_caps;
453 const struct wm_adsp_fw_caps *caps;
454 bool voice_trigger;
455 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
456 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
457 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
458 [WM_ADSP_FW_TX] = { .file = "tx" },
459 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
460 [WM_ADSP_FW_RX] = { .file = "rx" },
461 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
462 [WM_ADSP_FW_CTRL] = {
463 .file = "ctrl",
464 .compr_direction = SND_COMPRESS_CAPTURE,
465 .num_caps = ARRAY_SIZE(ctrl_caps),
466 .caps = ctrl_caps,
467 .voice_trigger = true,
468 },
469 [WM_ADSP_FW_ASR] = { .file = "asr" },
470 [WM_ADSP_FW_TRACE] = {
471 .file = "trace",
472 .compr_direction = SND_COMPRESS_CAPTURE,
473 .num_caps = ARRAY_SIZE(trace_caps),
474 .caps = trace_caps,
475 },
476 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
477 [WM_ADSP_FW_MISC] = { .file = "misc" },
478 };
479
480 struct wm_coeff_ctl_ops {
481 int (*xget)(struct snd_kcontrol *kcontrol,
482 struct snd_ctl_elem_value *ucontrol);
483 int (*xput)(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_elem_value *ucontrol);
485 };
486
487 struct wm_coeff_ctl {
488 const char *name;
489 const char *fw_name;
490 struct wm_adsp_alg_region alg_region;
491 struct wm_coeff_ctl_ops ops;
492 struct wm_adsp *dsp;
493 unsigned int enabled:1;
494 struct list_head list;
495 void *cache;
496 unsigned int offset;
497 size_t len;
498 unsigned int set:1;
499 struct soc_bytes_ext bytes_ext;
500 unsigned int flags;
501 unsigned int type;
502 };
503
504 static const char *wm_adsp_mem_region_name(unsigned int type)
505 {
506 switch (type) {
507 case WMFW_ADSP1_PM:
508 return "PM";
509 case WMFW_ADSP1_DM:
510 return "DM";
511 case WMFW_ADSP2_XM:
512 return "XM";
513 case WMFW_ADSP2_YM:
514 return "YM";
515 case WMFW_ADSP1_ZM:
516 return "ZM";
517 default:
518 return NULL;
519 }
520 }
521
522 #ifdef CONFIG_DEBUG_FS
523 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
524 {
525 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
526
527 kfree(dsp->wmfw_file_name);
528 dsp->wmfw_file_name = tmp;
529 }
530
531 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
532 {
533 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
534
535 kfree(dsp->bin_file_name);
536 dsp->bin_file_name = tmp;
537 }
538
539 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
540 {
541 kfree(dsp->wmfw_file_name);
542 kfree(dsp->bin_file_name);
543 dsp->wmfw_file_name = NULL;
544 dsp->bin_file_name = NULL;
545 }
546
547 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
548 char __user *user_buf,
549 size_t count, loff_t *ppos)
550 {
551 struct wm_adsp *dsp = file->private_data;
552 ssize_t ret;
553
554 mutex_lock(&dsp->pwr_lock);
555
556 if (!dsp->wmfw_file_name || !dsp->booted)
557 ret = 0;
558 else
559 ret = simple_read_from_buffer(user_buf, count, ppos,
560 dsp->wmfw_file_name,
561 strlen(dsp->wmfw_file_name));
562
563 mutex_unlock(&dsp->pwr_lock);
564 return ret;
565 }
566
567 static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
568 char __user *user_buf,
569 size_t count, loff_t *ppos)
570 {
571 struct wm_adsp *dsp = file->private_data;
572 ssize_t ret;
573
574 mutex_lock(&dsp->pwr_lock);
575
576 if (!dsp->bin_file_name || !dsp->booted)
577 ret = 0;
578 else
579 ret = simple_read_from_buffer(user_buf, count, ppos,
580 dsp->bin_file_name,
581 strlen(dsp->bin_file_name));
582
583 mutex_unlock(&dsp->pwr_lock);
584 return ret;
585 }
586
587 static const struct {
588 const char *name;
589 const struct file_operations fops;
590 } wm_adsp_debugfs_fops[] = {
591 {
592 .name = "wmfw_file_name",
593 .fops = {
594 .open = simple_open,
595 .read = wm_adsp_debugfs_wmfw_read,
596 },
597 },
598 {
599 .name = "bin_file_name",
600 .fops = {
601 .open = simple_open,
602 .read = wm_adsp_debugfs_bin_read,
603 },
604 },
605 };
606
607 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
608 struct snd_soc_codec *codec)
609 {
610 struct dentry *root = NULL;
611 char *root_name;
612 int i;
613
614 if (!codec->component.debugfs_root) {
615 adsp_err(dsp, "No codec debugfs root\n");
616 goto err;
617 }
618
619 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
620 if (!root_name)
621 goto err;
622
623 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
624 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
625 kfree(root_name);
626
627 if (!root)
628 goto err;
629
630 if (!debugfs_create_bool("booted", S_IRUGO, root, &dsp->booted))
631 goto err;
632
633 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
634 goto err;
635
636 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
637 goto err;
638
639 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
640 &dsp->fw_id_version))
641 goto err;
642
643 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
644 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
645 S_IRUGO, root, dsp,
646 &wm_adsp_debugfs_fops[i].fops))
647 goto err;
648 }
649
650 dsp->debugfs_root = root;
651 return;
652
653 err:
654 debugfs_remove_recursive(root);
655 adsp_err(dsp, "Failed to create debugfs\n");
656 }
657
658 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
659 {
660 wm_adsp_debugfs_clear(dsp);
661 debugfs_remove_recursive(dsp->debugfs_root);
662 }
663 #else
664 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
665 struct snd_soc_codec *codec)
666 {
667 }
668
669 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
670 {
671 }
672
673 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
674 const char *s)
675 {
676 }
677
678 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
679 const char *s)
680 {
681 }
682
683 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
684 {
685 }
686 #endif
687
688 static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
689 struct snd_ctl_elem_value *ucontrol)
690 {
691 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
692 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
693 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
694
695 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
696
697 return 0;
698 }
699
700 static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
701 struct snd_ctl_elem_value *ucontrol)
702 {
703 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
704 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
705 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
706 int ret = 0;
707
708 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
709 return 0;
710
711 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
712 return -EINVAL;
713
714 mutex_lock(&dsp[e->shift_l].pwr_lock);
715
716 if (dsp[e->shift_l].booted || dsp[e->shift_l].compr)
717 ret = -EBUSY;
718 else
719 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
720
721 mutex_unlock(&dsp[e->shift_l].pwr_lock);
722
723 return ret;
724 }
725
726 static const struct soc_enum wm_adsp_fw_enum[] = {
727 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
728 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
729 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
730 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
731 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
732 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
733 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
734 };
735
736 const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
737 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
738 wm_adsp_fw_get, wm_adsp_fw_put),
739 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
740 wm_adsp_fw_get, wm_adsp_fw_put),
741 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
742 wm_adsp_fw_get, wm_adsp_fw_put),
743 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
744 wm_adsp_fw_get, wm_adsp_fw_put),
745 SOC_ENUM_EXT("DSP5 Firmware", wm_adsp_fw_enum[4],
746 wm_adsp_fw_get, wm_adsp_fw_put),
747 SOC_ENUM_EXT("DSP6 Firmware", wm_adsp_fw_enum[5],
748 wm_adsp_fw_get, wm_adsp_fw_put),
749 SOC_ENUM_EXT("DSP7 Firmware", wm_adsp_fw_enum[6],
750 wm_adsp_fw_get, wm_adsp_fw_put),
751 };
752 EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
753
754 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
755 int type)
756 {
757 int i;
758
759 for (i = 0; i < dsp->num_mems; i++)
760 if (dsp->mem[i].type == type)
761 return &dsp->mem[i];
762
763 return NULL;
764 }
765
766 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
767 unsigned int offset)
768 {
769 if (WARN_ON(!mem))
770 return offset;
771 switch (mem->type) {
772 case WMFW_ADSP1_PM:
773 return mem->base + (offset * 3);
774 case WMFW_ADSP1_DM:
775 return mem->base + (offset * 2);
776 case WMFW_ADSP2_XM:
777 return mem->base + (offset * 2);
778 case WMFW_ADSP2_YM:
779 return mem->base + (offset * 2);
780 case WMFW_ADSP1_ZM:
781 return mem->base + (offset * 2);
782 default:
783 WARN(1, "Unknown memory region type");
784 return offset;
785 }
786 }
787
788 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
789 {
790 unsigned int scratch[4];
791 unsigned int addr = dsp->base + ADSP2_SCRATCH0;
792 unsigned int i;
793 int ret;
794
795 for (i = 0; i < ARRAY_SIZE(scratch); ++i) {
796 ret = regmap_read(dsp->regmap, addr + i, &scratch[i]);
797 if (ret) {
798 adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret);
799 return;
800 }
801 }
802
803 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
804 scratch[0], scratch[1], scratch[2], scratch[3]);
805 }
806
807 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
808 {
809 unsigned int scratch[2];
810 int ret;
811
812 ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1,
813 &scratch[0]);
814 if (ret) {
815 adsp_err(dsp, "Failed to read SCRATCH0_1: %d\n", ret);
816 return;
817 }
818
819 ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH2_3,
820 &scratch[1]);
821 if (ret) {
822 adsp_err(dsp, "Failed to read SCRATCH2_3: %d\n", ret);
823 return;
824 }
825
826 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
827 scratch[0] & 0xFFFF,
828 scratch[0] >> 16,
829 scratch[1] & 0xFFFF,
830 scratch[1] >> 16);
831 }
832
833 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
834 {
835 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
836 }
837
838 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
839 {
840 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
841 struct wm_adsp *dsp = ctl->dsp;
842 const struct wm_adsp_region *mem;
843
844 mem = wm_adsp_find_region(dsp, alg_region->type);
845 if (!mem) {
846 adsp_err(dsp, "No base for region %x\n",
847 alg_region->type);
848 return -EINVAL;
849 }
850
851 *reg = wm_adsp_region_to_reg(mem, ctl->alg_region.base + ctl->offset);
852
853 return 0;
854 }
855
856 static int wm_coeff_info(struct snd_kcontrol *kctl,
857 struct snd_ctl_elem_info *uinfo)
858 {
859 struct soc_bytes_ext *bytes_ext =
860 (struct soc_bytes_ext *)kctl->private_value;
861 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
862
863 switch (ctl->type) {
864 case WMFW_CTL_TYPE_ACKED:
865 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
866 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
867 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
868 uinfo->value.integer.step = 1;
869 uinfo->count = 1;
870 break;
871 default:
872 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
873 uinfo->count = ctl->len;
874 break;
875 }
876
877 return 0;
878 }
879
880 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
881 unsigned int event_id)
882 {
883 struct wm_adsp *dsp = ctl->dsp;
884 u32 val = cpu_to_be32(event_id);
885 unsigned int reg;
886 int i, ret;
887
888 ret = wm_coeff_base_reg(ctl, &reg);
889 if (ret)
890 return ret;
891
892 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
893 event_id, ctl->alg_region.alg,
894 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
895
896 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
897 if (ret) {
898 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
899 return ret;
900 }
901
902 /*
903 * Poll for ack, we initially poll at ~1ms intervals for firmwares
904 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
905 * to ack instantly so we do the first 1ms delay before reading the
906 * control to avoid a pointless bus transaction
907 */
908 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
909 switch (i) {
910 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
911 usleep_range(1000, 2000);
912 i++;
913 break;
914 default:
915 usleep_range(10000, 20000);
916 i += 10;
917 break;
918 }
919
920 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
921 if (ret) {
922 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
923 return ret;
924 }
925
926 if (val == 0) {
927 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
928 return 0;
929 }
930 }
931
932 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
933 reg, ctl->alg_region.alg,
934 wm_adsp_mem_region_name(ctl->alg_region.type),
935 ctl->offset);
936
937 return -ETIMEDOUT;
938 }
939
940 static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
941 const void *buf, size_t len)
942 {
943 struct wm_adsp *dsp = ctl->dsp;
944 void *scratch;
945 int ret;
946 unsigned int reg;
947
948 ret = wm_coeff_base_reg(ctl, &reg);
949 if (ret)
950 return ret;
951
952 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
953 if (!scratch)
954 return -ENOMEM;
955
956 ret = regmap_raw_write(dsp->regmap, reg, scratch,
957 len);
958 if (ret) {
959 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
960 len, reg, ret);
961 kfree(scratch);
962 return ret;
963 }
964 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
965
966 kfree(scratch);
967
968 return 0;
969 }
970
971 static int wm_coeff_put(struct snd_kcontrol *kctl,
972 struct snd_ctl_elem_value *ucontrol)
973 {
974 struct soc_bytes_ext *bytes_ext =
975 (struct soc_bytes_ext *)kctl->private_value;
976 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
977 char *p = ucontrol->value.bytes.data;
978 int ret = 0;
979
980 mutex_lock(&ctl->dsp->pwr_lock);
981
982 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
983 ret = -EPERM;
984 else
985 memcpy(ctl->cache, p, ctl->len);
986
987 ctl->set = 1;
988 if (ctl->enabled && ctl->dsp->running)
989 ret = wm_coeff_write_control(ctl, p, ctl->len);
990
991 mutex_unlock(&ctl->dsp->pwr_lock);
992
993 return ret;
994 }
995
996 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
997 const unsigned int __user *bytes, unsigned int size)
998 {
999 struct soc_bytes_ext *bytes_ext =
1000 (struct soc_bytes_ext *)kctl->private_value;
1001 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1002 int ret = 0;
1003
1004 mutex_lock(&ctl->dsp->pwr_lock);
1005
1006 if (copy_from_user(ctl->cache, bytes, size)) {
1007 ret = -EFAULT;
1008 } else {
1009 ctl->set = 1;
1010 if (ctl->enabled && ctl->dsp->running)
1011 ret = wm_coeff_write_control(ctl, ctl->cache, size);
1012 else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1013 ret = -EPERM;
1014 }
1015
1016 mutex_unlock(&ctl->dsp->pwr_lock);
1017
1018 return ret;
1019 }
1020
1021 static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1022 struct snd_ctl_elem_value *ucontrol)
1023 {
1024 struct soc_bytes_ext *bytes_ext =
1025 (struct soc_bytes_ext *)kctl->private_value;
1026 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1027 unsigned int val = ucontrol->value.integer.value[0];
1028 int ret;
1029
1030 if (val == 0)
1031 return 0; /* 0 means no event */
1032
1033 mutex_lock(&ctl->dsp->pwr_lock);
1034
1035 if (ctl->enabled && ctl->dsp->running)
1036 ret = wm_coeff_write_acked_control(ctl, val);
1037 else
1038 ret = -EPERM;
1039
1040 mutex_unlock(&ctl->dsp->pwr_lock);
1041
1042 return ret;
1043 }
1044
1045 static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
1046 void *buf, size_t len)
1047 {
1048 struct wm_adsp *dsp = ctl->dsp;
1049 void *scratch;
1050 int ret;
1051 unsigned int reg;
1052
1053 ret = wm_coeff_base_reg(ctl, &reg);
1054 if (ret)
1055 return ret;
1056
1057 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
1058 if (!scratch)
1059 return -ENOMEM;
1060
1061 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
1062 if (ret) {
1063 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
1064 len, reg, ret);
1065 kfree(scratch);
1066 return ret;
1067 }
1068 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
1069
1070 memcpy(buf, scratch, len);
1071 kfree(scratch);
1072
1073 return 0;
1074 }
1075
1076 static int wm_coeff_get(struct snd_kcontrol *kctl,
1077 struct snd_ctl_elem_value *ucontrol)
1078 {
1079 struct soc_bytes_ext *bytes_ext =
1080 (struct soc_bytes_ext *)kctl->private_value;
1081 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1082 char *p = ucontrol->value.bytes.data;
1083 int ret = 0;
1084
1085 mutex_lock(&ctl->dsp->pwr_lock);
1086
1087 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1088 if (ctl->enabled && ctl->dsp->running)
1089 ret = wm_coeff_read_control(ctl, p, ctl->len);
1090 else
1091 ret = -EPERM;
1092 } else {
1093 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1094 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1095
1096 memcpy(p, ctl->cache, ctl->len);
1097 }
1098
1099 mutex_unlock(&ctl->dsp->pwr_lock);
1100
1101 return ret;
1102 }
1103
1104 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1105 unsigned int __user *bytes, unsigned int size)
1106 {
1107 struct soc_bytes_ext *bytes_ext =
1108 (struct soc_bytes_ext *)kctl->private_value;
1109 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1110 int ret = 0;
1111
1112 mutex_lock(&ctl->dsp->pwr_lock);
1113
1114 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1115 if (ctl->enabled && ctl->dsp->running)
1116 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1117 else
1118 ret = -EPERM;
1119 } else {
1120 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1121 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1122 }
1123
1124 if (!ret && copy_to_user(bytes, ctl->cache, size))
1125 ret = -EFAULT;
1126
1127 mutex_unlock(&ctl->dsp->pwr_lock);
1128
1129 return ret;
1130 }
1131
1132 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1133 struct snd_ctl_elem_value *ucontrol)
1134 {
1135 /*
1136 * Although it's not useful to read an acked control, we must satisfy
1137 * user-side assumptions that all controls are readable and that a
1138 * write of the same value should be filtered out (it's valid to send
1139 * the same event number again to the firmware). We therefore return 0,
1140 * meaning "no event" so valid event numbers will always be a change
1141 */
1142 ucontrol->value.integer.value[0] = 0;
1143
1144 return 0;
1145 }
1146
1147 struct wmfw_ctl_work {
1148 struct wm_adsp *dsp;
1149 struct wm_coeff_ctl *ctl;
1150 struct work_struct work;
1151 };
1152
1153 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1154 {
1155 unsigned int out, rd, wr, vol;
1156
1157 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1158 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1159 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1160 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1161
1162 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1163 } else {
1164 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1165 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1166 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1167
1168 out = 0;
1169 }
1170
1171 if (in) {
1172 if (in & WMFW_CTL_FLAG_READABLE)
1173 out |= rd;
1174 if (in & WMFW_CTL_FLAG_WRITEABLE)
1175 out |= wr;
1176 if (in & WMFW_CTL_FLAG_VOLATILE)
1177 out |= vol;
1178 } else {
1179 out |= rd | wr | vol;
1180 }
1181
1182 return out;
1183 }
1184
1185 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
1186 {
1187 struct snd_kcontrol_new *kcontrol;
1188 int ret;
1189
1190 if (!ctl || !ctl->name)
1191 return -EINVAL;
1192
1193 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1194 if (!kcontrol)
1195 return -ENOMEM;
1196
1197 kcontrol->name = ctl->name;
1198 kcontrol->info = wm_coeff_info;
1199 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1200 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1201 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
1202 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
1203
1204 switch (ctl->type) {
1205 case WMFW_CTL_TYPE_ACKED:
1206 kcontrol->get = wm_coeff_get_acked;
1207 kcontrol->put = wm_coeff_put_acked;
1208 break;
1209 default:
1210 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1211 ctl->bytes_ext.max = ctl->len;
1212 ctl->bytes_ext.get = wm_coeff_tlv_get;
1213 ctl->bytes_ext.put = wm_coeff_tlv_put;
1214 } else {
1215 kcontrol->get = wm_coeff_get;
1216 kcontrol->put = wm_coeff_put;
1217 }
1218 break;
1219 }
1220
1221 ret = snd_soc_add_codec_controls(dsp->codec, kcontrol, 1);
1222 if (ret < 0)
1223 goto err_kcontrol;
1224
1225 kfree(kcontrol);
1226
1227 return 0;
1228
1229 err_kcontrol:
1230 kfree(kcontrol);
1231 return ret;
1232 }
1233
1234 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1235 {
1236 struct wm_coeff_ctl *ctl;
1237 int ret;
1238
1239 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1240 if (!ctl->enabled || ctl->set)
1241 continue;
1242 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1243 continue;
1244
1245 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1246 if (ret < 0)
1247 return ret;
1248 }
1249
1250 return 0;
1251 }
1252
1253 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1254 {
1255 struct wm_coeff_ctl *ctl;
1256 int ret;
1257
1258 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1259 if (!ctl->enabled)
1260 continue;
1261 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
1262 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
1263 if (ret < 0)
1264 return ret;
1265 }
1266 }
1267
1268 return 0;
1269 }
1270
1271 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1272 unsigned int event)
1273 {
1274 struct wm_coeff_ctl *ctl;
1275 int ret;
1276
1277 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1278 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1279 continue;
1280
1281 if (!ctl->enabled)
1282 continue;
1283
1284 ret = wm_coeff_write_acked_control(ctl, event);
1285 if (ret)
1286 adsp_warn(dsp,
1287 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1288 event, ctl->alg_region.alg, ret);
1289 }
1290 }
1291
1292 static void wm_adsp_ctl_work(struct work_struct *work)
1293 {
1294 struct wmfw_ctl_work *ctl_work = container_of(work,
1295 struct wmfw_ctl_work,
1296 work);
1297
1298 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1299 kfree(ctl_work);
1300 }
1301
1302 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1303 {
1304 kfree(ctl->cache);
1305 kfree(ctl->name);
1306 kfree(ctl);
1307 }
1308
1309 static int wm_adsp_create_control(struct wm_adsp *dsp,
1310 const struct wm_adsp_alg_region *alg_region,
1311 unsigned int offset, unsigned int len,
1312 const char *subname, unsigned int subname_len,
1313 unsigned int flags, unsigned int type)
1314 {
1315 struct wm_coeff_ctl *ctl;
1316 struct wmfw_ctl_work *ctl_work;
1317 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1318 const char *region_name;
1319 int ret;
1320
1321 region_name = wm_adsp_mem_region_name(alg_region->type);
1322 if (!region_name) {
1323 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
1324 return -EINVAL;
1325 }
1326
1327 switch (dsp->fw_ver) {
1328 case 0:
1329 case 1:
1330 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
1331 dsp->num, region_name, alg_region->alg);
1332 break;
1333 default:
1334 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1335 "DSP%d%c %.12s %x", dsp->num, *region_name,
1336 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1337
1338 /* Truncate the subname from the start if it is too long */
1339 if (subname) {
1340 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1341 int skip = 0;
1342
1343 if (subname_len > avail)
1344 skip = subname_len - avail;
1345
1346 snprintf(name + ret,
1347 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1348 subname_len - skip, subname + skip);
1349 }
1350 break;
1351 }
1352
1353 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1354 if (!strcmp(ctl->name, name)) {
1355 if (!ctl->enabled)
1356 ctl->enabled = 1;
1357 return 0;
1358 }
1359 }
1360
1361 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1362 if (!ctl)
1363 return -ENOMEM;
1364 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
1365 ctl->alg_region = *alg_region;
1366 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1367 if (!ctl->name) {
1368 ret = -ENOMEM;
1369 goto err_ctl;
1370 }
1371 ctl->enabled = 1;
1372 ctl->set = 0;
1373 ctl->ops.xget = wm_coeff_get;
1374 ctl->ops.xput = wm_coeff_put;
1375 ctl->dsp = dsp;
1376
1377 ctl->flags = flags;
1378 ctl->type = type;
1379 ctl->offset = offset;
1380 ctl->len = len;
1381 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1382 if (!ctl->cache) {
1383 ret = -ENOMEM;
1384 goto err_ctl_name;
1385 }
1386
1387 list_add(&ctl->list, &dsp->ctl_list);
1388
1389 if (flags & WMFW_CTL_FLAG_SYS)
1390 return 0;
1391
1392 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1393 if (!ctl_work) {
1394 ret = -ENOMEM;
1395 goto err_ctl_cache;
1396 }
1397
1398 ctl_work->dsp = dsp;
1399 ctl_work->ctl = ctl;
1400 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1401 schedule_work(&ctl_work->work);
1402
1403 return 0;
1404
1405 err_ctl_cache:
1406 kfree(ctl->cache);
1407 err_ctl_name:
1408 kfree(ctl->name);
1409 err_ctl:
1410 kfree(ctl);
1411
1412 return ret;
1413 }
1414
1415 struct wm_coeff_parsed_alg {
1416 int id;
1417 const u8 *name;
1418 int name_len;
1419 int ncoeff;
1420 };
1421
1422 struct wm_coeff_parsed_coeff {
1423 int offset;
1424 int mem_type;
1425 const u8 *name;
1426 int name_len;
1427 int ctl_type;
1428 int flags;
1429 int len;
1430 };
1431
1432 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1433 {
1434 int length;
1435
1436 switch (bytes) {
1437 case 1:
1438 length = **pos;
1439 break;
1440 case 2:
1441 length = le16_to_cpu(*((__le16 *)*pos));
1442 break;
1443 default:
1444 return 0;
1445 }
1446
1447 if (str)
1448 *str = *pos + bytes;
1449
1450 *pos += ((length + bytes) + 3) & ~0x03;
1451
1452 return length;
1453 }
1454
1455 static int wm_coeff_parse_int(int bytes, const u8 **pos)
1456 {
1457 int val = 0;
1458
1459 switch (bytes) {
1460 case 2:
1461 val = le16_to_cpu(*((__le16 *)*pos));
1462 break;
1463 case 4:
1464 val = le32_to_cpu(*((__le32 *)*pos));
1465 break;
1466 default:
1467 break;
1468 }
1469
1470 *pos += bytes;
1471
1472 return val;
1473 }
1474
1475 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1476 struct wm_coeff_parsed_alg *blk)
1477 {
1478 const struct wmfw_adsp_alg_data *raw;
1479
1480 switch (dsp->fw_ver) {
1481 case 0:
1482 case 1:
1483 raw = (const struct wmfw_adsp_alg_data *)*data;
1484 *data = raw->data;
1485
1486 blk->id = le32_to_cpu(raw->id);
1487 blk->name = raw->name;
1488 blk->name_len = strlen(raw->name);
1489 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1490 break;
1491 default:
1492 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1493 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1494 &blk->name);
1495 wm_coeff_parse_string(sizeof(u16), data, NULL);
1496 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1497 break;
1498 }
1499
1500 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1501 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1502 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1503 }
1504
1505 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1506 struct wm_coeff_parsed_coeff *blk)
1507 {
1508 const struct wmfw_adsp_coeff_data *raw;
1509 const u8 *tmp;
1510 int length;
1511
1512 switch (dsp->fw_ver) {
1513 case 0:
1514 case 1:
1515 raw = (const struct wmfw_adsp_coeff_data *)*data;
1516 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1517
1518 blk->offset = le16_to_cpu(raw->hdr.offset);
1519 blk->mem_type = le16_to_cpu(raw->hdr.type);
1520 blk->name = raw->name;
1521 blk->name_len = strlen(raw->name);
1522 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1523 blk->flags = le16_to_cpu(raw->flags);
1524 blk->len = le32_to_cpu(raw->len);
1525 break;
1526 default:
1527 tmp = *data;
1528 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1529 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1530 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1531 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1532 &blk->name);
1533 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1534 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1535 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1536 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1537 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1538
1539 *data = *data + sizeof(raw->hdr) + length;
1540 break;
1541 }
1542
1543 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1544 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1545 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1546 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1547 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1548 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1549 }
1550
1551 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1552 const struct wm_coeff_parsed_coeff *coeff_blk,
1553 unsigned int f_required,
1554 unsigned int f_illegal)
1555 {
1556 if ((coeff_blk->flags & f_illegal) ||
1557 ((coeff_blk->flags & f_required) != f_required)) {
1558 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1559 coeff_blk->flags, coeff_blk->ctl_type);
1560 return -EINVAL;
1561 }
1562
1563 return 0;
1564 }
1565
1566 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1567 const struct wmfw_region *region)
1568 {
1569 struct wm_adsp_alg_region alg_region = {};
1570 struct wm_coeff_parsed_alg alg_blk;
1571 struct wm_coeff_parsed_coeff coeff_blk;
1572 const u8 *data = region->data;
1573 int i, ret;
1574
1575 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1576 for (i = 0; i < alg_blk.ncoeff; i++) {
1577 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1578
1579 switch (coeff_blk.ctl_type) {
1580 case SNDRV_CTL_ELEM_TYPE_BYTES:
1581 break;
1582 case WMFW_CTL_TYPE_ACKED:
1583 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1584 continue; /* ignore */
1585
1586 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1587 WMFW_CTL_FLAG_VOLATILE |
1588 WMFW_CTL_FLAG_WRITEABLE |
1589 WMFW_CTL_FLAG_READABLE,
1590 0);
1591 if (ret)
1592 return -EINVAL;
1593 break;
1594 case WMFW_CTL_TYPE_HOSTEVENT:
1595 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1596 WMFW_CTL_FLAG_SYS |
1597 WMFW_CTL_FLAG_VOLATILE |
1598 WMFW_CTL_FLAG_WRITEABLE |
1599 WMFW_CTL_FLAG_READABLE,
1600 0);
1601 if (ret)
1602 return -EINVAL;
1603 break;
1604 default:
1605 adsp_err(dsp, "Unknown control type: %d\n",
1606 coeff_blk.ctl_type);
1607 return -EINVAL;
1608 }
1609
1610 alg_region.type = coeff_blk.mem_type;
1611 alg_region.alg = alg_blk.id;
1612
1613 ret = wm_adsp_create_control(dsp, &alg_region,
1614 coeff_blk.offset,
1615 coeff_blk.len,
1616 coeff_blk.name,
1617 coeff_blk.name_len,
1618 coeff_blk.flags,
1619 coeff_blk.ctl_type);
1620 if (ret < 0)
1621 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1622 coeff_blk.name_len, coeff_blk.name, ret);
1623 }
1624
1625 return 0;
1626 }
1627
1628 static int wm_adsp_load(struct wm_adsp *dsp)
1629 {
1630 LIST_HEAD(buf_list);
1631 const struct firmware *firmware;
1632 struct regmap *regmap = dsp->regmap;
1633 unsigned int pos = 0;
1634 const struct wmfw_header *header;
1635 const struct wmfw_adsp1_sizes *adsp1_sizes;
1636 const struct wmfw_adsp2_sizes *adsp2_sizes;
1637 const struct wmfw_footer *footer;
1638 const struct wmfw_region *region;
1639 const struct wm_adsp_region *mem;
1640 const char *region_name;
1641 char *file, *text = NULL;
1642 struct wm_adsp_buf *buf;
1643 unsigned int reg;
1644 int regions = 0;
1645 int ret, offset, type, sizes;
1646
1647 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1648 if (file == NULL)
1649 return -ENOMEM;
1650
1651 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1652 wm_adsp_fw[dsp->fw].file);
1653 file[PAGE_SIZE - 1] = '\0';
1654
1655 ret = request_firmware(&firmware, file, dsp->dev);
1656 if (ret != 0) {
1657 adsp_err(dsp, "Failed to request '%s'\n", file);
1658 goto out;
1659 }
1660 ret = -EINVAL;
1661
1662 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1663 if (pos >= firmware->size) {
1664 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1665 file, firmware->size);
1666 goto out_fw;
1667 }
1668
1669 header = (void *)&firmware->data[0];
1670
1671 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1672 adsp_err(dsp, "%s: invalid magic\n", file);
1673 goto out_fw;
1674 }
1675
1676 switch (header->ver) {
1677 case 0:
1678 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1679 file, header->ver);
1680 break;
1681 case 1:
1682 case 2:
1683 break;
1684 default:
1685 adsp_err(dsp, "%s: unknown file format %d\n",
1686 file, header->ver);
1687 goto out_fw;
1688 }
1689
1690 adsp_info(dsp, "Firmware version: %d\n", header->ver);
1691 dsp->fw_ver = header->ver;
1692
1693 if (header->core != dsp->type) {
1694 adsp_err(dsp, "%s: invalid core %d != %d\n",
1695 file, header->core, dsp->type);
1696 goto out_fw;
1697 }
1698
1699 switch (dsp->type) {
1700 case WMFW_ADSP1:
1701 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1702 adsp1_sizes = (void *)&(header[1]);
1703 footer = (void *)&(adsp1_sizes[1]);
1704 sizes = sizeof(*adsp1_sizes);
1705
1706 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1707 file, le32_to_cpu(adsp1_sizes->dm),
1708 le32_to_cpu(adsp1_sizes->pm),
1709 le32_to_cpu(adsp1_sizes->zm));
1710 break;
1711
1712 case WMFW_ADSP2:
1713 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1714 adsp2_sizes = (void *)&(header[1]);
1715 footer = (void *)&(adsp2_sizes[1]);
1716 sizes = sizeof(*adsp2_sizes);
1717
1718 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1719 file, le32_to_cpu(adsp2_sizes->xm),
1720 le32_to_cpu(adsp2_sizes->ym),
1721 le32_to_cpu(adsp2_sizes->pm),
1722 le32_to_cpu(adsp2_sizes->zm));
1723 break;
1724
1725 default:
1726 WARN(1, "Unknown DSP type");
1727 goto out_fw;
1728 }
1729
1730 if (le32_to_cpu(header->len) != sizeof(*header) +
1731 sizes + sizeof(*footer)) {
1732 adsp_err(dsp, "%s: unexpected header length %d\n",
1733 file, le32_to_cpu(header->len));
1734 goto out_fw;
1735 }
1736
1737 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1738 le64_to_cpu(footer->timestamp));
1739
1740 while (pos < firmware->size &&
1741 sizeof(*region) < firmware->size - pos) {
1742 region = (void *)&(firmware->data[pos]);
1743 region_name = "Unknown";
1744 reg = 0;
1745 text = NULL;
1746 offset = le32_to_cpu(region->offset) & 0xffffff;
1747 type = be32_to_cpu(region->type) & 0xff;
1748 mem = wm_adsp_find_region(dsp, type);
1749
1750 switch (type) {
1751 case WMFW_NAME_TEXT:
1752 region_name = "Firmware name";
1753 text = kzalloc(le32_to_cpu(region->len) + 1,
1754 GFP_KERNEL);
1755 break;
1756 case WMFW_ALGORITHM_DATA:
1757 region_name = "Algorithm";
1758 ret = wm_adsp_parse_coeff(dsp, region);
1759 if (ret != 0)
1760 goto out_fw;
1761 break;
1762 case WMFW_INFO_TEXT:
1763 region_name = "Information";
1764 text = kzalloc(le32_to_cpu(region->len) + 1,
1765 GFP_KERNEL);
1766 break;
1767 case WMFW_ABSOLUTE:
1768 region_name = "Absolute";
1769 reg = offset;
1770 break;
1771 case WMFW_ADSP1_PM:
1772 case WMFW_ADSP1_DM:
1773 case WMFW_ADSP2_XM:
1774 case WMFW_ADSP2_YM:
1775 case WMFW_ADSP1_ZM:
1776 region_name = wm_adsp_mem_region_name(type);
1777 reg = wm_adsp_region_to_reg(mem, offset);
1778 break;
1779 default:
1780 adsp_warn(dsp,
1781 "%s.%d: Unknown region type %x at %d(%x)\n",
1782 file, regions, type, pos, pos);
1783 break;
1784 }
1785
1786 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1787 regions, le32_to_cpu(region->len), offset,
1788 region_name);
1789
1790 if (le32_to_cpu(region->len) >
1791 firmware->size - pos - sizeof(*region)) {
1792 adsp_err(dsp,
1793 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1794 file, regions, region_name,
1795 le32_to_cpu(region->len), firmware->size);
1796 ret = -EINVAL;
1797 goto out_fw;
1798 }
1799
1800 if (text) {
1801 memcpy(text, region->data, le32_to_cpu(region->len));
1802 adsp_info(dsp, "%s: %s\n", file, text);
1803 kfree(text);
1804 text = NULL;
1805 }
1806
1807 if (reg) {
1808 buf = wm_adsp_buf_alloc(region->data,
1809 le32_to_cpu(region->len),
1810 &buf_list);
1811 if (!buf) {
1812 adsp_err(dsp, "Out of memory\n");
1813 ret = -ENOMEM;
1814 goto out_fw;
1815 }
1816
1817 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1818 le32_to_cpu(region->len));
1819 if (ret != 0) {
1820 adsp_err(dsp,
1821 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1822 file, regions,
1823 le32_to_cpu(region->len), offset,
1824 region_name, ret);
1825 goto out_fw;
1826 }
1827 }
1828
1829 pos += le32_to_cpu(region->len) + sizeof(*region);
1830 regions++;
1831 }
1832
1833 ret = regmap_async_complete(regmap);
1834 if (ret != 0) {
1835 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1836 goto out_fw;
1837 }
1838
1839 if (pos > firmware->size)
1840 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1841 file, regions, pos - firmware->size);
1842
1843 wm_adsp_debugfs_save_wmfwname(dsp, file);
1844
1845 out_fw:
1846 regmap_async_complete(regmap);
1847 wm_adsp_buf_free(&buf_list);
1848 release_firmware(firmware);
1849 kfree(text);
1850 out:
1851 kfree(file);
1852
1853 return ret;
1854 }
1855
1856 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1857 const struct wm_adsp_alg_region *alg_region)
1858 {
1859 struct wm_coeff_ctl *ctl;
1860
1861 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1862 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1863 alg_region->alg == ctl->alg_region.alg &&
1864 alg_region->type == ctl->alg_region.type) {
1865 ctl->alg_region.base = alg_region->base;
1866 }
1867 }
1868 }
1869
1870 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
1871 unsigned int pos, unsigned int len)
1872 {
1873 void *alg;
1874 int ret;
1875 __be32 val;
1876
1877 if (n_algs == 0) {
1878 adsp_err(dsp, "No algorithms\n");
1879 return ERR_PTR(-EINVAL);
1880 }
1881
1882 if (n_algs > 1024) {
1883 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
1884 return ERR_PTR(-EINVAL);
1885 }
1886
1887 /* Read the terminator first to validate the length */
1888 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1889 if (ret != 0) {
1890 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1891 ret);
1892 return ERR_PTR(ret);
1893 }
1894
1895 if (be32_to_cpu(val) != 0xbedead)
1896 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
1897 pos + len, be32_to_cpu(val));
1898
1899 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1900 if (!alg)
1901 return ERR_PTR(-ENOMEM);
1902
1903 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1904 if (ret != 0) {
1905 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
1906 kfree(alg);
1907 return ERR_PTR(ret);
1908 }
1909
1910 return alg;
1911 }
1912
1913 static struct wm_adsp_alg_region *
1914 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1915 {
1916 struct wm_adsp_alg_region *alg_region;
1917
1918 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1919 if (id == alg_region->alg && type == alg_region->type)
1920 return alg_region;
1921 }
1922
1923 return NULL;
1924 }
1925
1926 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1927 int type, __be32 id,
1928 __be32 base)
1929 {
1930 struct wm_adsp_alg_region *alg_region;
1931
1932 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1933 if (!alg_region)
1934 return ERR_PTR(-ENOMEM);
1935
1936 alg_region->type = type;
1937 alg_region->alg = be32_to_cpu(id);
1938 alg_region->base = be32_to_cpu(base);
1939
1940 list_add_tail(&alg_region->list, &dsp->alg_regions);
1941
1942 if (dsp->fw_ver > 0)
1943 wm_adsp_ctl_fixup_base(dsp, alg_region);
1944
1945 return alg_region;
1946 }
1947
1948 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
1949 {
1950 struct wm_adsp_alg_region *alg_region;
1951
1952 while (!list_empty(&dsp->alg_regions)) {
1953 alg_region = list_first_entry(&dsp->alg_regions,
1954 struct wm_adsp_alg_region,
1955 list);
1956 list_del(&alg_region->list);
1957 kfree(alg_region);
1958 }
1959 }
1960
1961 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1962 {
1963 struct wmfw_adsp1_id_hdr adsp1_id;
1964 struct wmfw_adsp1_alg_hdr *adsp1_alg;
1965 struct wm_adsp_alg_region *alg_region;
1966 const struct wm_adsp_region *mem;
1967 unsigned int pos, len;
1968 size_t n_algs;
1969 int i, ret;
1970
1971 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1972 if (WARN_ON(!mem))
1973 return -EINVAL;
1974
1975 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1976 sizeof(adsp1_id));
1977 if (ret != 0) {
1978 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1979 ret);
1980 return ret;
1981 }
1982
1983 n_algs = be32_to_cpu(adsp1_id.n_algs);
1984 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1985 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1986 dsp->fw_id,
1987 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1988 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1989 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
1990 n_algs);
1991
1992 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1993 adsp1_id.fw.id, adsp1_id.zm);
1994 if (IS_ERR(alg_region))
1995 return PTR_ERR(alg_region);
1996
1997 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1998 adsp1_id.fw.id, adsp1_id.dm);
1999 if (IS_ERR(alg_region))
2000 return PTR_ERR(alg_region);
2001
2002 pos = sizeof(adsp1_id) / 2;
2003 len = (sizeof(*adsp1_alg) * n_algs) / 2;
2004
2005 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
2006 if (IS_ERR(adsp1_alg))
2007 return PTR_ERR(adsp1_alg);
2008
2009 for (i = 0; i < n_algs; i++) {
2010 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2011 i, be32_to_cpu(adsp1_alg[i].alg.id),
2012 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2013 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2014 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2015 be32_to_cpu(adsp1_alg[i].dm),
2016 be32_to_cpu(adsp1_alg[i].zm));
2017
2018 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2019 adsp1_alg[i].alg.id,
2020 adsp1_alg[i].dm);
2021 if (IS_ERR(alg_region)) {
2022 ret = PTR_ERR(alg_region);
2023 goto out;
2024 }
2025 if (dsp->fw_ver == 0) {
2026 if (i + 1 < n_algs) {
2027 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2028 len -= be32_to_cpu(adsp1_alg[i].dm);
2029 len *= 4;
2030 wm_adsp_create_control(dsp, alg_region, 0,
2031 len, NULL, 0, 0,
2032 SNDRV_CTL_ELEM_TYPE_BYTES);
2033 } else {
2034 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2035 be32_to_cpu(adsp1_alg[i].alg.id));
2036 }
2037 }
2038
2039 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2040 adsp1_alg[i].alg.id,
2041 adsp1_alg[i].zm);
2042 if (IS_ERR(alg_region)) {
2043 ret = PTR_ERR(alg_region);
2044 goto out;
2045 }
2046 if (dsp->fw_ver == 0) {
2047 if (i + 1 < n_algs) {
2048 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2049 len -= be32_to_cpu(adsp1_alg[i].zm);
2050 len *= 4;
2051 wm_adsp_create_control(dsp, alg_region, 0,
2052 len, NULL, 0, 0,
2053 SNDRV_CTL_ELEM_TYPE_BYTES);
2054 } else {
2055 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2056 be32_to_cpu(adsp1_alg[i].alg.id));
2057 }
2058 }
2059 }
2060
2061 out:
2062 kfree(adsp1_alg);
2063 return ret;
2064 }
2065
2066 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2067 {
2068 struct wmfw_adsp2_id_hdr adsp2_id;
2069 struct wmfw_adsp2_alg_hdr *adsp2_alg;
2070 struct wm_adsp_alg_region *alg_region;
2071 const struct wm_adsp_region *mem;
2072 unsigned int pos, len;
2073 size_t n_algs;
2074 int i, ret;
2075
2076 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2077 if (WARN_ON(!mem))
2078 return -EINVAL;
2079
2080 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2081 sizeof(adsp2_id));
2082 if (ret != 0) {
2083 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2084 ret);
2085 return ret;
2086 }
2087
2088 n_algs = be32_to_cpu(adsp2_id.n_algs);
2089 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
2090 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
2091 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
2092 dsp->fw_id,
2093 (dsp->fw_id_version & 0xff0000) >> 16,
2094 (dsp->fw_id_version & 0xff00) >> 8,
2095 dsp->fw_id_version & 0xff,
2096 n_algs);
2097
2098 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2099 adsp2_id.fw.id, adsp2_id.xm);
2100 if (IS_ERR(alg_region))
2101 return PTR_ERR(alg_region);
2102
2103 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2104 adsp2_id.fw.id, adsp2_id.ym);
2105 if (IS_ERR(alg_region))
2106 return PTR_ERR(alg_region);
2107
2108 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2109 adsp2_id.fw.id, adsp2_id.zm);
2110 if (IS_ERR(alg_region))
2111 return PTR_ERR(alg_region);
2112
2113 pos = sizeof(adsp2_id) / 2;
2114 len = (sizeof(*adsp2_alg) * n_algs) / 2;
2115
2116 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
2117 if (IS_ERR(adsp2_alg))
2118 return PTR_ERR(adsp2_alg);
2119
2120 for (i = 0; i < n_algs; i++) {
2121 adsp_info(dsp,
2122 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2123 i, be32_to_cpu(adsp2_alg[i].alg.id),
2124 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2125 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2126 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2127 be32_to_cpu(adsp2_alg[i].xm),
2128 be32_to_cpu(adsp2_alg[i].ym),
2129 be32_to_cpu(adsp2_alg[i].zm));
2130
2131 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2132 adsp2_alg[i].alg.id,
2133 adsp2_alg[i].xm);
2134 if (IS_ERR(alg_region)) {
2135 ret = PTR_ERR(alg_region);
2136 goto out;
2137 }
2138 if (dsp->fw_ver == 0) {
2139 if (i + 1 < n_algs) {
2140 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2141 len -= be32_to_cpu(adsp2_alg[i].xm);
2142 len *= 4;
2143 wm_adsp_create_control(dsp, alg_region, 0,
2144 len, NULL, 0, 0,
2145 SNDRV_CTL_ELEM_TYPE_BYTES);
2146 } else {
2147 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2148 be32_to_cpu(adsp2_alg[i].alg.id));
2149 }
2150 }
2151
2152 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2153 adsp2_alg[i].alg.id,
2154 adsp2_alg[i].ym);
2155 if (IS_ERR(alg_region)) {
2156 ret = PTR_ERR(alg_region);
2157 goto out;
2158 }
2159 if (dsp->fw_ver == 0) {
2160 if (i + 1 < n_algs) {
2161 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2162 len -= be32_to_cpu(adsp2_alg[i].ym);
2163 len *= 4;
2164 wm_adsp_create_control(dsp, alg_region, 0,
2165 len, NULL, 0, 0,
2166 SNDRV_CTL_ELEM_TYPE_BYTES);
2167 } else {
2168 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2169 be32_to_cpu(adsp2_alg[i].alg.id));
2170 }
2171 }
2172
2173 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2174 adsp2_alg[i].alg.id,
2175 adsp2_alg[i].zm);
2176 if (IS_ERR(alg_region)) {
2177 ret = PTR_ERR(alg_region);
2178 goto out;
2179 }
2180 if (dsp->fw_ver == 0) {
2181 if (i + 1 < n_algs) {
2182 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2183 len -= be32_to_cpu(adsp2_alg[i].zm);
2184 len *= 4;
2185 wm_adsp_create_control(dsp, alg_region, 0,
2186 len, NULL, 0, 0,
2187 SNDRV_CTL_ELEM_TYPE_BYTES);
2188 } else {
2189 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2190 be32_to_cpu(adsp2_alg[i].alg.id));
2191 }
2192 }
2193 }
2194
2195 out:
2196 kfree(adsp2_alg);
2197 return ret;
2198 }
2199
2200 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2201 {
2202 LIST_HEAD(buf_list);
2203 struct regmap *regmap = dsp->regmap;
2204 struct wmfw_coeff_hdr *hdr;
2205 struct wmfw_coeff_item *blk;
2206 const struct firmware *firmware;
2207 const struct wm_adsp_region *mem;
2208 struct wm_adsp_alg_region *alg_region;
2209 const char *region_name;
2210 int ret, pos, blocks, type, offset, reg;
2211 char *file;
2212 struct wm_adsp_buf *buf;
2213
2214 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2215 if (file == NULL)
2216 return -ENOMEM;
2217
2218 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
2219 wm_adsp_fw[dsp->fw].file);
2220 file[PAGE_SIZE - 1] = '\0';
2221
2222 ret = request_firmware(&firmware, file, dsp->dev);
2223 if (ret != 0) {
2224 adsp_warn(dsp, "Failed to request '%s'\n", file);
2225 ret = 0;
2226 goto out;
2227 }
2228 ret = -EINVAL;
2229
2230 if (sizeof(*hdr) >= firmware->size) {
2231 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2232 file, firmware->size);
2233 goto out_fw;
2234 }
2235
2236 hdr = (void *)&firmware->data[0];
2237 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2238 adsp_err(dsp, "%s: invalid magic\n", file);
2239 goto out_fw;
2240 }
2241
2242 switch (be32_to_cpu(hdr->rev) & 0xff) {
2243 case 1:
2244 break;
2245 default:
2246 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2247 file, be32_to_cpu(hdr->rev) & 0xff);
2248 ret = -EINVAL;
2249 goto out_fw;
2250 }
2251
2252 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2253 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2254 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2255 le32_to_cpu(hdr->ver) & 0xff);
2256
2257 pos = le32_to_cpu(hdr->len);
2258
2259 blocks = 0;
2260 while (pos < firmware->size &&
2261 sizeof(*blk) < firmware->size - pos) {
2262 blk = (void *)(&firmware->data[pos]);
2263
2264 type = le16_to_cpu(blk->type);
2265 offset = le16_to_cpu(blk->offset);
2266
2267 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2268 file, blocks, le32_to_cpu(blk->id),
2269 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2270 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2271 le32_to_cpu(blk->ver) & 0xff);
2272 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2273 file, blocks, le32_to_cpu(blk->len), offset, type);
2274
2275 reg = 0;
2276 region_name = "Unknown";
2277 switch (type) {
2278 case (WMFW_NAME_TEXT << 8):
2279 case (WMFW_INFO_TEXT << 8):
2280 break;
2281 case (WMFW_ABSOLUTE << 8):
2282 /*
2283 * Old files may use this for global
2284 * coefficients.
2285 */
2286 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2287 offset == 0) {
2288 region_name = "global coefficients";
2289 mem = wm_adsp_find_region(dsp, type);
2290 if (!mem) {
2291 adsp_err(dsp, "No ZM\n");
2292 break;
2293 }
2294 reg = wm_adsp_region_to_reg(mem, 0);
2295
2296 } else {
2297 region_name = "register";
2298 reg = offset;
2299 }
2300 break;
2301
2302 case WMFW_ADSP1_DM:
2303 case WMFW_ADSP1_ZM:
2304 case WMFW_ADSP2_XM:
2305 case WMFW_ADSP2_YM:
2306 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2307 file, blocks, le32_to_cpu(blk->len),
2308 type, le32_to_cpu(blk->id));
2309
2310 mem = wm_adsp_find_region(dsp, type);
2311 if (!mem) {
2312 adsp_err(dsp, "No base for region %x\n", type);
2313 break;
2314 }
2315
2316 alg_region = wm_adsp_find_alg_region(dsp, type,
2317 le32_to_cpu(blk->id));
2318 if (alg_region) {
2319 reg = alg_region->base;
2320 reg = wm_adsp_region_to_reg(mem, reg);
2321 reg += offset;
2322 } else {
2323 adsp_err(dsp, "No %x for algorithm %x\n",
2324 type, le32_to_cpu(blk->id));
2325 }
2326 break;
2327
2328 default:
2329 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2330 file, blocks, type, pos);
2331 break;
2332 }
2333
2334 if (reg) {
2335 if (le32_to_cpu(blk->len) >
2336 firmware->size - pos - sizeof(*blk)) {
2337 adsp_err(dsp,
2338 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2339 file, blocks, region_name,
2340 le32_to_cpu(blk->len),
2341 firmware->size);
2342 ret = -EINVAL;
2343 goto out_fw;
2344 }
2345
2346 buf = wm_adsp_buf_alloc(blk->data,
2347 le32_to_cpu(blk->len),
2348 &buf_list);
2349 if (!buf) {
2350 adsp_err(dsp, "Out of memory\n");
2351 ret = -ENOMEM;
2352 goto out_fw;
2353 }
2354
2355 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2356 file, blocks, le32_to_cpu(blk->len),
2357 reg);
2358 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2359 le32_to_cpu(blk->len));
2360 if (ret != 0) {
2361 adsp_err(dsp,
2362 "%s.%d: Failed to write to %x in %s: %d\n",
2363 file, blocks, reg, region_name, ret);
2364 }
2365 }
2366
2367 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2368 blocks++;
2369 }
2370
2371 ret = regmap_async_complete(regmap);
2372 if (ret != 0)
2373 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2374
2375 if (pos > firmware->size)
2376 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2377 file, blocks, pos - firmware->size);
2378
2379 wm_adsp_debugfs_save_binname(dsp, file);
2380
2381 out_fw:
2382 regmap_async_complete(regmap);
2383 release_firmware(firmware);
2384 wm_adsp_buf_free(&buf_list);
2385 out:
2386 kfree(file);
2387 return ret;
2388 }
2389
2390 int wm_adsp1_init(struct wm_adsp *dsp)
2391 {
2392 INIT_LIST_HEAD(&dsp->alg_regions);
2393
2394 mutex_init(&dsp->pwr_lock);
2395
2396 return 0;
2397 }
2398 EXPORT_SYMBOL_GPL(wm_adsp1_init);
2399
2400 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2401 struct snd_kcontrol *kcontrol,
2402 int event)
2403 {
2404 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2405 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2406 struct wm_adsp *dsp = &dsps[w->shift];
2407 struct wm_coeff_ctl *ctl;
2408 int ret;
2409 unsigned int val;
2410
2411 dsp->codec = codec;
2412
2413 mutex_lock(&dsp->pwr_lock);
2414
2415 switch (event) {
2416 case SND_SOC_DAPM_POST_PMU:
2417 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2418 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2419
2420 /*
2421 * For simplicity set the DSP clock rate to be the
2422 * SYSCLK rate rather than making it configurable.
2423 */
2424 if (dsp->sysclk_reg) {
2425 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2426 if (ret != 0) {
2427 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2428 ret);
2429 goto err_mutex;
2430 }
2431
2432 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2433
2434 ret = regmap_update_bits(dsp->regmap,
2435 dsp->base + ADSP1_CONTROL_31,
2436 ADSP1_CLK_SEL_MASK, val);
2437 if (ret != 0) {
2438 adsp_err(dsp, "Failed to set clock rate: %d\n",
2439 ret);
2440 goto err_mutex;
2441 }
2442 }
2443
2444 ret = wm_adsp_load(dsp);
2445 if (ret != 0)
2446 goto err_ena;
2447
2448 ret = wm_adsp1_setup_algs(dsp);
2449 if (ret != 0)
2450 goto err_ena;
2451
2452 ret = wm_adsp_load_coeff(dsp);
2453 if (ret != 0)
2454 goto err_ena;
2455
2456 /* Initialize caches for enabled and unset controls */
2457 ret = wm_coeff_init_control_caches(dsp);
2458 if (ret != 0)
2459 goto err_ena;
2460
2461 /* Sync set controls */
2462 ret = wm_coeff_sync_controls(dsp);
2463 if (ret != 0)
2464 goto err_ena;
2465
2466 dsp->booted = true;
2467
2468 /* Start the core running */
2469 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2470 ADSP1_CORE_ENA | ADSP1_START,
2471 ADSP1_CORE_ENA | ADSP1_START);
2472
2473 dsp->running = true;
2474 break;
2475
2476 case SND_SOC_DAPM_PRE_PMD:
2477 dsp->running = false;
2478 dsp->booted = false;
2479
2480 /* Halt the core */
2481 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2482 ADSP1_CORE_ENA | ADSP1_START, 0);
2483
2484 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2485 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2486
2487 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2488 ADSP1_SYS_ENA, 0);
2489
2490 list_for_each_entry(ctl, &dsp->ctl_list, list)
2491 ctl->enabled = 0;
2492
2493
2494 wm_adsp_free_alg_regions(dsp);
2495 break;
2496
2497 default:
2498 break;
2499 }
2500
2501 mutex_unlock(&dsp->pwr_lock);
2502
2503 return 0;
2504
2505 err_ena:
2506 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2507 ADSP1_SYS_ENA, 0);
2508 err_mutex:
2509 mutex_unlock(&dsp->pwr_lock);
2510
2511 return ret;
2512 }
2513 EXPORT_SYMBOL_GPL(wm_adsp1_event);
2514
2515 static int wm_adsp2_ena(struct wm_adsp *dsp)
2516 {
2517 unsigned int val;
2518 int ret, count;
2519
2520 switch (dsp->rev) {
2521 case 0:
2522 ret = regmap_update_bits_async(dsp->regmap,
2523 dsp->base + ADSP2_CONTROL,
2524 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2525 if (ret != 0)
2526 return ret;
2527 break;
2528 default:
2529 break;
2530 }
2531
2532 /* Wait for the RAM to start, should be near instantaneous */
2533 for (count = 0; count < 10; ++count) {
2534 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2535 if (ret != 0)
2536 return ret;
2537
2538 if (val & ADSP2_RAM_RDY)
2539 break;
2540
2541 usleep_range(250, 500);
2542 }
2543
2544 if (!(val & ADSP2_RAM_RDY)) {
2545 adsp_err(dsp, "Failed to start DSP RAM\n");
2546 return -EBUSY;
2547 }
2548
2549 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2550
2551 return 0;
2552 }
2553
2554 static void wm_adsp2_boot_work(struct work_struct *work)
2555 {
2556 struct wm_adsp *dsp = container_of(work,
2557 struct wm_adsp,
2558 boot_work);
2559 int ret;
2560
2561 mutex_lock(&dsp->pwr_lock);
2562
2563 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2564 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2565 if (ret != 0)
2566 goto err_mutex;
2567
2568 ret = wm_adsp2_ena(dsp);
2569 if (ret != 0)
2570 goto err_mem;
2571
2572 ret = wm_adsp_load(dsp);
2573 if (ret != 0)
2574 goto err_ena;
2575
2576 ret = wm_adsp2_setup_algs(dsp);
2577 if (ret != 0)
2578 goto err_ena;
2579
2580 ret = wm_adsp_load_coeff(dsp);
2581 if (ret != 0)
2582 goto err_ena;
2583
2584 /* Initialize caches for enabled and unset controls */
2585 ret = wm_coeff_init_control_caches(dsp);
2586 if (ret != 0)
2587 goto err_ena;
2588
2589 switch (dsp->rev) {
2590 case 0:
2591 /* Turn DSP back off until we are ready to run */
2592 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2593 ADSP2_SYS_ENA, 0);
2594 if (ret != 0)
2595 goto err_ena;
2596 break;
2597 default:
2598 break;
2599 }
2600
2601 dsp->booted = true;
2602
2603 mutex_unlock(&dsp->pwr_lock);
2604
2605 return;
2606
2607 err_ena:
2608 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2609 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2610 err_mem:
2611 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2612 ADSP2_MEM_ENA, 0);
2613 err_mutex:
2614 mutex_unlock(&dsp->pwr_lock);
2615 }
2616
2617 static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2618 {
2619 int ret;
2620
2621 switch (dsp->rev) {
2622 case 0:
2623 ret = regmap_update_bits_async(dsp->regmap,
2624 dsp->base + ADSP2_CLOCKING,
2625 ADSP2_CLK_SEL_MASK,
2626 freq << ADSP2_CLK_SEL_SHIFT);
2627 if (ret) {
2628 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2629 return;
2630 }
2631 break;
2632 default:
2633 /* clock is handled by parent codec driver */
2634 break;
2635 }
2636 }
2637
2638 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
2639 struct snd_ctl_elem_value *ucontrol)
2640 {
2641 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2642 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
2643
2644 ucontrol->value.integer.value[0] = dsp->preloaded;
2645
2646 return 0;
2647 }
2648 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
2649
2650 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
2651 struct snd_ctl_elem_value *ucontrol)
2652 {
2653 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2654 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
2655 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2656 struct soc_mixer_control *mc =
2657 (struct soc_mixer_control *)kcontrol->private_value;
2658 char preload[32];
2659
2660 snprintf(preload, ARRAY_SIZE(preload), "DSP%u Preload", mc->shift);
2661
2662 dsp->preloaded = ucontrol->value.integer.value[0];
2663
2664 if (ucontrol->value.integer.value[0])
2665 snd_soc_dapm_force_enable_pin(dapm, preload);
2666 else
2667 snd_soc_dapm_disable_pin(dapm, preload);
2668
2669 snd_soc_dapm_sync(dapm);
2670
2671 return 0;
2672 }
2673 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
2674
2675 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
2676 {
2677 switch (dsp->rev) {
2678 case 0:
2679 case 1:
2680 return;
2681 default:
2682 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
2683 ADSP2_WDT_ENA_MASK, 0);
2684 }
2685 }
2686
2687 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
2688 struct snd_kcontrol *kcontrol, int event,
2689 unsigned int freq)
2690 {
2691 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2692 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2693 struct wm_adsp *dsp = &dsps[w->shift];
2694 struct wm_coeff_ctl *ctl;
2695
2696 switch (event) {
2697 case SND_SOC_DAPM_PRE_PMU:
2698 wm_adsp2_set_dspclk(dsp, freq);
2699 queue_work(system_unbound_wq, &dsp->boot_work);
2700 break;
2701 case SND_SOC_DAPM_PRE_PMD:
2702 mutex_lock(&dsp->pwr_lock);
2703
2704 wm_adsp_debugfs_clear(dsp);
2705
2706 dsp->fw_id = 0;
2707 dsp->fw_id_version = 0;
2708
2709 dsp->booted = false;
2710
2711 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2712 ADSP2_MEM_ENA, 0);
2713
2714 list_for_each_entry(ctl, &dsp->ctl_list, list)
2715 ctl->enabled = 0;
2716
2717 wm_adsp_free_alg_regions(dsp);
2718
2719 mutex_unlock(&dsp->pwr_lock);
2720
2721 adsp_dbg(dsp, "Shutdown complete\n");
2722 break;
2723 default:
2724 break;
2725 }
2726
2727 return 0;
2728 }
2729 EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2730
2731 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2732 struct snd_kcontrol *kcontrol, int event)
2733 {
2734 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2735 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2736 struct wm_adsp *dsp = &dsps[w->shift];
2737 int ret;
2738
2739 switch (event) {
2740 case SND_SOC_DAPM_POST_PMU:
2741 flush_work(&dsp->boot_work);
2742
2743 mutex_lock(&dsp->pwr_lock);
2744
2745 if (!dsp->booted) {
2746 ret = -EIO;
2747 goto err;
2748 }
2749
2750 ret = wm_adsp2_ena(dsp);
2751 if (ret != 0)
2752 goto err;
2753
2754 /* Sync set controls */
2755 ret = wm_coeff_sync_controls(dsp);
2756 if (ret != 0)
2757 goto err;
2758
2759 wm_adsp2_lock(dsp, dsp->lock_regions);
2760
2761 ret = regmap_update_bits(dsp->regmap,
2762 dsp->base + ADSP2_CONTROL,
2763 ADSP2_CORE_ENA | ADSP2_START,
2764 ADSP2_CORE_ENA | ADSP2_START);
2765 if (ret != 0)
2766 goto err;
2767
2768 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
2769 ret = wm_adsp_buffer_init(dsp);
2770 if (ret < 0)
2771 goto err;
2772 }
2773
2774 dsp->running = true;
2775
2776 mutex_unlock(&dsp->pwr_lock);
2777
2778 break;
2779
2780 case SND_SOC_DAPM_PRE_PMD:
2781 /* Tell the firmware to cleanup */
2782 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
2783
2784 wm_adsp_stop_watchdog(dsp);
2785
2786 /* Log firmware state, it can be useful for analysis */
2787 switch (dsp->rev) {
2788 case 0:
2789 wm_adsp2_show_fw_status(dsp);
2790 break;
2791 default:
2792 wm_adsp2v2_show_fw_status(dsp);
2793 break;
2794 }
2795
2796 mutex_lock(&dsp->pwr_lock);
2797
2798 dsp->running = false;
2799
2800 regmap_update_bits(dsp->regmap,
2801 dsp->base + ADSP2_CONTROL,
2802 ADSP2_CORE_ENA | ADSP2_START, 0);
2803
2804 /* Make sure DMAs are quiesced */
2805 switch (dsp->rev) {
2806 case 0:
2807 regmap_write(dsp->regmap,
2808 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2809 regmap_write(dsp->regmap,
2810 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2811 regmap_write(dsp->regmap,
2812 dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2813
2814 regmap_update_bits(dsp->regmap,
2815 dsp->base + ADSP2_CONTROL,
2816 ADSP2_SYS_ENA, 0);
2817 break;
2818 default:
2819 regmap_write(dsp->regmap,
2820 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2821 regmap_write(dsp->regmap,
2822 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2823 regmap_write(dsp->regmap,
2824 dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2825 break;
2826 }
2827
2828 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2829 wm_adsp_buffer_free(dsp);
2830
2831 mutex_unlock(&dsp->pwr_lock);
2832
2833 adsp_dbg(dsp, "Execution stopped\n");
2834 break;
2835
2836 default:
2837 break;
2838 }
2839
2840 return 0;
2841 err:
2842 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2843 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2844 mutex_unlock(&dsp->pwr_lock);
2845 return ret;
2846 }
2847 EXPORT_SYMBOL_GPL(wm_adsp2_event);
2848
2849 int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2850 {
2851 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2852 char preload[32];
2853
2854 snprintf(preload, ARRAY_SIZE(preload), "DSP%d Preload", dsp->num);
2855 snd_soc_dapm_disable_pin(dapm, preload);
2856
2857 wm_adsp2_init_debugfs(dsp, codec);
2858
2859 dsp->codec = codec;
2860
2861 return snd_soc_add_codec_controls(codec,
2862 &wm_adsp_fw_controls[dsp->num - 1],
2863 1);
2864 }
2865 EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2866
2867 int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2868 {
2869 wm_adsp2_cleanup_debugfs(dsp);
2870
2871 return 0;
2872 }
2873 EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2874
2875 int wm_adsp2_init(struct wm_adsp *dsp)
2876 {
2877 int ret;
2878
2879 switch (dsp->rev) {
2880 case 0:
2881 /*
2882 * Disable the DSP memory by default when in reset for a small
2883 * power saving.
2884 */
2885 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2886 ADSP2_MEM_ENA, 0);
2887 if (ret) {
2888 adsp_err(dsp,
2889 "Failed to clear memory retention: %d\n", ret);
2890 return ret;
2891 }
2892 break;
2893 default:
2894 break;
2895 }
2896
2897 INIT_LIST_HEAD(&dsp->alg_regions);
2898 INIT_LIST_HEAD(&dsp->ctl_list);
2899 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
2900
2901 mutex_init(&dsp->pwr_lock);
2902
2903 return 0;
2904 }
2905 EXPORT_SYMBOL_GPL(wm_adsp2_init);
2906
2907 void wm_adsp2_remove(struct wm_adsp *dsp)
2908 {
2909 struct wm_coeff_ctl *ctl;
2910
2911 while (!list_empty(&dsp->ctl_list)) {
2912 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2913 list);
2914 list_del(&ctl->list);
2915 wm_adsp_free_ctl_blk(ctl);
2916 }
2917 }
2918 EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2919
2920 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2921 {
2922 return compr->buf != NULL;
2923 }
2924
2925 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2926 {
2927 /*
2928 * Note this will be more complex once each DSP can support multiple
2929 * streams
2930 */
2931 if (!compr->dsp->buffer)
2932 return -EINVAL;
2933
2934 compr->buf = compr->dsp->buffer;
2935 compr->buf->compr = compr;
2936
2937 return 0;
2938 }
2939
2940 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
2941 {
2942 if (!compr)
2943 return;
2944
2945 /* Wake the poll so it can see buffer is no longer attached */
2946 if (compr->stream)
2947 snd_compr_fragment_elapsed(compr->stream);
2948
2949 if (wm_adsp_compr_attached(compr)) {
2950 compr->buf->compr = NULL;
2951 compr->buf = NULL;
2952 }
2953 }
2954
2955 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2956 {
2957 struct wm_adsp_compr *compr;
2958 int ret = 0;
2959
2960 mutex_lock(&dsp->pwr_lock);
2961
2962 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2963 adsp_err(dsp, "Firmware does not support compressed API\n");
2964 ret = -ENXIO;
2965 goto out;
2966 }
2967
2968 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2969 adsp_err(dsp, "Firmware does not support stream direction\n");
2970 ret = -EINVAL;
2971 goto out;
2972 }
2973
2974 if (dsp->compr) {
2975 /* It is expect this limitation will be removed in future */
2976 adsp_err(dsp, "Only a single stream supported per DSP\n");
2977 ret = -EBUSY;
2978 goto out;
2979 }
2980
2981 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
2982 if (!compr) {
2983 ret = -ENOMEM;
2984 goto out;
2985 }
2986
2987 compr->dsp = dsp;
2988 compr->stream = stream;
2989
2990 dsp->compr = compr;
2991
2992 stream->runtime->private_data = compr;
2993
2994 out:
2995 mutex_unlock(&dsp->pwr_lock);
2996
2997 return ret;
2998 }
2999 EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3000
3001 int wm_adsp_compr_free(struct snd_compr_stream *stream)
3002 {
3003 struct wm_adsp_compr *compr = stream->runtime->private_data;
3004 struct wm_adsp *dsp = compr->dsp;
3005
3006 mutex_lock(&dsp->pwr_lock);
3007
3008 wm_adsp_compr_detach(compr);
3009 dsp->compr = NULL;
3010
3011 kfree(compr->raw_buf);
3012 kfree(compr);
3013
3014 mutex_unlock(&dsp->pwr_lock);
3015
3016 return 0;
3017 }
3018 EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3019
3020 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3021 struct snd_compr_params *params)
3022 {
3023 struct wm_adsp_compr *compr = stream->runtime->private_data;
3024 struct wm_adsp *dsp = compr->dsp;
3025 const struct wm_adsp_fw_caps *caps;
3026 const struct snd_codec_desc *desc;
3027 int i, j;
3028
3029 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3030 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3031 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3032 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3033 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3034 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
3035 params->buffer.fragment_size,
3036 params->buffer.fragments);
3037
3038 return -EINVAL;
3039 }
3040
3041 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3042 caps = &wm_adsp_fw[dsp->fw].caps[i];
3043 desc = &caps->desc;
3044
3045 if (caps->id != params->codec.id)
3046 continue;
3047
3048 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3049 if (desc->max_ch < params->codec.ch_out)
3050 continue;
3051 } else {
3052 if (desc->max_ch < params->codec.ch_in)
3053 continue;
3054 }
3055
3056 if (!(desc->formats & (1 << params->codec.format)))
3057 continue;
3058
3059 for (j = 0; j < desc->num_sample_rates; ++j)
3060 if (desc->sample_rates[j] == params->codec.sample_rate)
3061 return 0;
3062 }
3063
3064 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3065 params->codec.id, params->codec.ch_in, params->codec.ch_out,
3066 params->codec.sample_rate, params->codec.format);
3067 return -EINVAL;
3068 }
3069
3070 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3071 {
3072 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3073 }
3074
3075 int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
3076 struct snd_compr_params *params)
3077 {
3078 struct wm_adsp_compr *compr = stream->runtime->private_data;
3079 unsigned int size;
3080 int ret;
3081
3082 ret = wm_adsp_compr_check_params(stream, params);
3083 if (ret)
3084 return ret;
3085
3086 compr->size = params->buffer;
3087
3088 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
3089 compr->size.fragment_size, compr->size.fragments);
3090
3091 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3092 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3093 if (!compr->raw_buf)
3094 return -ENOMEM;
3095
3096 compr->sample_rate = params->codec.sample_rate;
3097
3098 return 0;
3099 }
3100 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3101
3102 int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
3103 struct snd_compr_caps *caps)
3104 {
3105 struct wm_adsp_compr *compr = stream->runtime->private_data;
3106 int fw = compr->dsp->fw;
3107 int i;
3108
3109 if (wm_adsp_fw[fw].caps) {
3110 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3111 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3112
3113 caps->num_codecs = i;
3114 caps->direction = wm_adsp_fw[fw].compr_direction;
3115
3116 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3117 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3118 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3119 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3120 }
3121
3122 return 0;
3123 }
3124 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3125
3126 static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
3127 unsigned int mem_addr,
3128 unsigned int num_words, u32 *data)
3129 {
3130 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3131 unsigned int i, reg;
3132 int ret;
3133
3134 if (!mem)
3135 return -EINVAL;
3136
3137 reg = wm_adsp_region_to_reg(mem, mem_addr);
3138
3139 ret = regmap_raw_read(dsp->regmap, reg, data,
3140 sizeof(*data) * num_words);
3141 if (ret < 0)
3142 return ret;
3143
3144 for (i = 0; i < num_words; ++i)
3145 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
3146
3147 return 0;
3148 }
3149
3150 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3151 unsigned int mem_addr, u32 *data)
3152 {
3153 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
3154 }
3155
3156 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3157 unsigned int mem_addr, u32 data)
3158 {
3159 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3160 unsigned int reg;
3161
3162 if (!mem)
3163 return -EINVAL;
3164
3165 reg = wm_adsp_region_to_reg(mem, mem_addr);
3166
3167 data = cpu_to_be32(data & 0x00ffffffu);
3168
3169 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
3170 }
3171
3172 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3173 unsigned int field_offset, u32 *data)
3174 {
3175 return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
3176 buf->host_buf_ptr + field_offset, data);
3177 }
3178
3179 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3180 unsigned int field_offset, u32 data)
3181 {
3182 return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
3183 buf->host_buf_ptr + field_offset, data);
3184 }
3185
3186 static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
3187 {
3188 struct wm_adsp_alg_region *alg_region;
3189 struct wm_adsp *dsp = buf->dsp;
3190 u32 xmalg, addr, magic;
3191 int i, ret;
3192
3193 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3194 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
3195
3196 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3197 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3198 if (ret < 0)
3199 return ret;
3200
3201 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3202 return -EINVAL;
3203
3204 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3205 for (i = 0; i < 5; ++i) {
3206 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3207 &buf->host_buf_ptr);
3208 if (ret < 0)
3209 return ret;
3210
3211 if (buf->host_buf_ptr)
3212 break;
3213
3214 usleep_range(1000, 2000);
3215 }
3216
3217 if (!buf->host_buf_ptr)
3218 return -EIO;
3219
3220 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3221
3222 return 0;
3223 }
3224
3225 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3226 {
3227 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3228 struct wm_adsp_buffer_region *region;
3229 u32 offset = 0;
3230 int i, ret;
3231
3232 for (i = 0; i < caps->num_regions; ++i) {
3233 region = &buf->regions[i];
3234
3235 region->offset = offset;
3236 region->mem_type = caps->region_defs[i].mem_type;
3237
3238 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3239 &region->base_addr);
3240 if (ret < 0)
3241 return ret;
3242
3243 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3244 &offset);
3245 if (ret < 0)
3246 return ret;
3247
3248 region->cumulative_size = offset;
3249
3250 adsp_dbg(buf->dsp,
3251 "region=%d type=%d base=%04x off=%04x size=%04x\n",
3252 i, region->mem_type, region->base_addr,
3253 region->offset, region->cumulative_size);
3254 }
3255
3256 return 0;
3257 }
3258
3259 static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3260 {
3261 struct wm_adsp_compr_buf *buf;
3262 int ret;
3263
3264 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3265 if (!buf)
3266 return -ENOMEM;
3267
3268 buf->dsp = dsp;
3269 buf->read_index = -1;
3270 buf->irq_count = 0xFFFFFFFF;
3271
3272 ret = wm_adsp_buffer_locate(buf);
3273 if (ret < 0) {
3274 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
3275 goto err_buffer;
3276 }
3277
3278 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
3279 sizeof(*buf->regions), GFP_KERNEL);
3280 if (!buf->regions) {
3281 ret = -ENOMEM;
3282 goto err_buffer;
3283 }
3284
3285 ret = wm_adsp_buffer_populate(buf);
3286 if (ret < 0) {
3287 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
3288 goto err_regions;
3289 }
3290
3291 dsp->buffer = buf;
3292
3293 return 0;
3294
3295 err_regions:
3296 kfree(buf->regions);
3297 err_buffer:
3298 kfree(buf);
3299 return ret;
3300 }
3301
3302 static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3303 {
3304 if (dsp->buffer) {
3305 wm_adsp_compr_detach(dsp->buffer->compr);
3306
3307 kfree(dsp->buffer->regions);
3308 kfree(dsp->buffer);
3309
3310 dsp->buffer = NULL;
3311 }
3312
3313 return 0;
3314 }
3315
3316 int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3317 {
3318 struct wm_adsp_compr *compr = stream->runtime->private_data;
3319 struct wm_adsp *dsp = compr->dsp;
3320 int ret = 0;
3321
3322 adsp_dbg(dsp, "Trigger: %d\n", cmd);
3323
3324 mutex_lock(&dsp->pwr_lock);
3325
3326 switch (cmd) {
3327 case SNDRV_PCM_TRIGGER_START:
3328 if (wm_adsp_compr_attached(compr))
3329 break;
3330
3331 ret = wm_adsp_compr_attach(compr);
3332 if (ret < 0) {
3333 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
3334 ret);
3335 break;
3336 }
3337
3338 /* Trigger the IRQ at one fragment of data */
3339 ret = wm_adsp_buffer_write(compr->buf,
3340 HOST_BUFFER_FIELD(high_water_mark),
3341 wm_adsp_compr_frag_words(compr));
3342 if (ret < 0) {
3343 adsp_err(dsp, "Failed to set high water mark: %d\n",
3344 ret);
3345 break;
3346 }
3347 break;
3348 case SNDRV_PCM_TRIGGER_STOP:
3349 break;
3350 default:
3351 ret = -EINVAL;
3352 break;
3353 }
3354
3355 mutex_unlock(&dsp->pwr_lock);
3356
3357 return ret;
3358 }
3359 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
3360
3361 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
3362 {
3363 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
3364
3365 return buf->regions[last_region].cumulative_size;
3366 }
3367
3368 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
3369 {
3370 u32 next_read_index, next_write_index;
3371 int write_index, read_index, avail;
3372 int ret;
3373
3374 /* Only sync read index if we haven't already read a valid index */
3375 if (buf->read_index < 0) {
3376 ret = wm_adsp_buffer_read(buf,
3377 HOST_BUFFER_FIELD(next_read_index),
3378 &next_read_index);
3379 if (ret < 0)
3380 return ret;
3381
3382 read_index = sign_extend32(next_read_index, 23);
3383
3384 if (read_index < 0) {
3385 adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
3386 return 0;
3387 }
3388
3389 buf->read_index = read_index;
3390 }
3391
3392 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
3393 &next_write_index);
3394 if (ret < 0)
3395 return ret;
3396
3397 write_index = sign_extend32(next_write_index, 23);
3398
3399 avail = write_index - buf->read_index;
3400 if (avail < 0)
3401 avail += wm_adsp_buffer_size(buf);
3402
3403 adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
3404 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
3405
3406 buf->avail = avail;
3407
3408 return 0;
3409 }
3410
3411 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3412 {
3413 int ret;
3414
3415 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3416 if (ret < 0) {
3417 adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret);
3418 return ret;
3419 }
3420 if (buf->error != 0) {
3421 adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error);
3422 return -EIO;
3423 }
3424
3425 return 0;
3426 }
3427
3428 int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
3429 {
3430 struct wm_adsp_compr_buf *buf;
3431 struct wm_adsp_compr *compr;
3432 int ret = 0;
3433
3434 mutex_lock(&dsp->pwr_lock);
3435
3436 buf = dsp->buffer;
3437 compr = dsp->compr;
3438
3439 if (!buf) {
3440 ret = -ENODEV;
3441 goto out;
3442 }
3443
3444 adsp_dbg(dsp, "Handling buffer IRQ\n");
3445
3446 ret = wm_adsp_buffer_get_error(buf);
3447 if (ret < 0)
3448 goto out_notify; /* Wake poll to report error */
3449
3450 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
3451 &buf->irq_count);
3452 if (ret < 0) {
3453 adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
3454 goto out;
3455 }
3456
3457 ret = wm_adsp_buffer_update_avail(buf);
3458 if (ret < 0) {
3459 adsp_err(dsp, "Error reading avail: %d\n", ret);
3460 goto out;
3461 }
3462
3463 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
3464 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
3465
3466 out_notify:
3467 if (compr && compr->stream)
3468 snd_compr_fragment_elapsed(compr->stream);
3469
3470 out:
3471 mutex_unlock(&dsp->pwr_lock);
3472
3473 return ret;
3474 }
3475 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
3476
3477 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
3478 {
3479 if (buf->irq_count & 0x01)
3480 return 0;
3481
3482 adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
3483 buf->irq_count);
3484
3485 buf->irq_count |= 0x01;
3486
3487 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
3488 buf->irq_count);
3489 }
3490
3491 int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
3492 struct snd_compr_tstamp *tstamp)
3493 {
3494 struct wm_adsp_compr *compr = stream->runtime->private_data;
3495 struct wm_adsp *dsp = compr->dsp;
3496 struct wm_adsp_compr_buf *buf;
3497 int ret = 0;
3498
3499 adsp_dbg(dsp, "Pointer request\n");
3500
3501 mutex_lock(&dsp->pwr_lock);
3502
3503 buf = compr->buf;
3504
3505 if (!compr->buf || compr->buf->error) {
3506 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
3507 ret = -EIO;
3508 goto out;
3509 }
3510
3511 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3512 ret = wm_adsp_buffer_update_avail(buf);
3513 if (ret < 0) {
3514 adsp_err(dsp, "Error reading avail: %d\n", ret);
3515 goto out;
3516 }
3517
3518 /*
3519 * If we really have less than 1 fragment available tell the
3520 * DSP to inform us once a whole fragment is available.
3521 */
3522 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3523 ret = wm_adsp_buffer_get_error(buf);
3524 if (ret < 0) {
3525 if (compr->buf->error)
3526 snd_compr_stop_error(stream,
3527 SNDRV_PCM_STATE_XRUN);
3528 goto out;
3529 }
3530
3531 ret = wm_adsp_buffer_reenable_irq(buf);
3532 if (ret < 0) {
3533 adsp_err(dsp,
3534 "Failed to re-enable buffer IRQ: %d\n",
3535 ret);
3536 goto out;
3537 }
3538 }
3539 }
3540
3541 tstamp->copied_total = compr->copied_total;
3542 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
3543 tstamp->sampling_rate = compr->sample_rate;
3544
3545 out:
3546 mutex_unlock(&dsp->pwr_lock);
3547
3548 return ret;
3549 }
3550 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
3551
3552 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
3553 {
3554 struct wm_adsp_compr_buf *buf = compr->buf;
3555 u8 *pack_in = (u8 *)compr->raw_buf;
3556 u8 *pack_out = (u8 *)compr->raw_buf;
3557 unsigned int adsp_addr;
3558 int mem_type, nwords, max_read;
3559 int i, j, ret;
3560
3561 /* Calculate read parameters */
3562 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
3563 if (buf->read_index < buf->regions[i].cumulative_size)
3564 break;
3565
3566 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
3567 return -EINVAL;
3568
3569 mem_type = buf->regions[i].mem_type;
3570 adsp_addr = buf->regions[i].base_addr +
3571 (buf->read_index - buf->regions[i].offset);
3572
3573 max_read = wm_adsp_compr_frag_words(compr);
3574 nwords = buf->regions[i].cumulative_size - buf->read_index;
3575
3576 if (nwords > target)
3577 nwords = target;
3578 if (nwords > buf->avail)
3579 nwords = buf->avail;
3580 if (nwords > max_read)
3581 nwords = max_read;
3582 if (!nwords)
3583 return 0;
3584
3585 /* Read data from DSP */
3586 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
3587 nwords, compr->raw_buf);
3588 if (ret < 0)
3589 return ret;
3590
3591 /* Remove the padding bytes from the data read from the DSP */
3592 for (i = 0; i < nwords; i++) {
3593 for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
3594 *pack_out++ = *pack_in++;
3595
3596 pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
3597 }
3598
3599 /* update read index to account for words read */
3600 buf->read_index += nwords;
3601 if (buf->read_index == wm_adsp_buffer_size(buf))
3602 buf->read_index = 0;
3603
3604 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
3605 buf->read_index);
3606 if (ret < 0)
3607 return ret;
3608
3609 /* update avail to account for words read */
3610 buf->avail -= nwords;
3611
3612 return nwords;
3613 }
3614
3615 static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
3616 char __user *buf, size_t count)
3617 {
3618 struct wm_adsp *dsp = compr->dsp;
3619 int ntotal = 0;
3620 int nwords, nbytes;
3621
3622 adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
3623
3624 if (!compr->buf || compr->buf->error) {
3625 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
3626 return -EIO;
3627 }
3628
3629 count /= WM_ADSP_DATA_WORD_SIZE;
3630
3631 do {
3632 nwords = wm_adsp_buffer_capture_block(compr, count);
3633 if (nwords < 0) {
3634 adsp_err(dsp, "Failed to capture block: %d\n", nwords);
3635 return nwords;
3636 }
3637
3638 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
3639
3640 adsp_dbg(dsp, "Read %d bytes\n", nbytes);
3641
3642 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
3643 adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
3644 ntotal, nbytes);
3645 return -EFAULT;
3646 }
3647
3648 count -= nwords;
3649 ntotal += nbytes;
3650 } while (nwords > 0 && count > 0);
3651
3652 compr->copied_total += ntotal;
3653
3654 return ntotal;
3655 }
3656
3657 int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
3658 size_t count)
3659 {
3660 struct wm_adsp_compr *compr = stream->runtime->private_data;
3661 struct wm_adsp *dsp = compr->dsp;
3662 int ret;
3663
3664 mutex_lock(&dsp->pwr_lock);
3665
3666 if (stream->direction == SND_COMPRESS_CAPTURE)
3667 ret = wm_adsp_compr_read(compr, buf, count);
3668 else
3669 ret = -ENOTSUPP;
3670
3671 mutex_unlock(&dsp->pwr_lock);
3672
3673 return ret;
3674 }
3675 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
3676
3677 int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
3678 {
3679 struct regmap *regmap = dsp->regmap;
3680 unsigned int code0, code1, lock_reg;
3681
3682 if (!(lock_regions & WM_ADSP2_REGION_ALL))
3683 return 0;
3684
3685 lock_regions &= WM_ADSP2_REGION_ALL;
3686 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
3687
3688 while (lock_regions) {
3689 code0 = code1 = 0;
3690 if (lock_regions & BIT(0)) {
3691 code0 = ADSP2_LOCK_CODE_0;
3692 code1 = ADSP2_LOCK_CODE_1;
3693 }
3694 if (lock_regions & BIT(1)) {
3695 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
3696 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
3697 }
3698 regmap_write(regmap, lock_reg, code0);
3699 regmap_write(regmap, lock_reg, code1);
3700 lock_regions >>= 2;
3701 lock_reg += 2;
3702 }
3703
3704 return 0;
3705 }
3706 EXPORT_SYMBOL_GPL(wm_adsp2_lock);
3707
3708 irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp)
3709 {
3710 unsigned int val;
3711 struct regmap *regmap = dsp->regmap;
3712 int ret = 0;
3713
3714 mutex_lock(&dsp->pwr_lock);
3715
3716 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
3717 if (ret) {
3718 adsp_err(dsp,
3719 "Failed to read Region Lock Ctrl register: %d\n", ret);
3720 goto error;
3721 }
3722
3723 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
3724 adsp_err(dsp, "watchdog timeout error\n");
3725 wm_adsp_stop_watchdog(dsp);
3726 }
3727
3728 if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
3729 if (val & ADSP2_SLAVE_ERR_MASK)
3730 adsp_err(dsp, "bus error: slave error\n");
3731 else
3732 adsp_err(dsp, "bus error: region lock error\n");
3733
3734 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
3735 if (ret) {
3736 adsp_err(dsp,
3737 "Failed to read Bus Err Addr register: %d\n",
3738 ret);
3739 goto error;
3740 }
3741
3742 adsp_err(dsp, "bus error address = 0x%x\n",
3743 val & ADSP2_BUS_ERR_ADDR_MASK);
3744
3745 ret = regmap_read(regmap,
3746 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
3747 &val);
3748 if (ret) {
3749 adsp_err(dsp,
3750 "Failed to read Pmem Xmem Err Addr register: %d\n",
3751 ret);
3752 goto error;
3753 }
3754
3755 adsp_err(dsp, "xmem error address = 0x%x\n",
3756 val & ADSP2_XMEM_ERR_ADDR_MASK);
3757 adsp_err(dsp, "pmem error address = 0x%x\n",
3758 (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
3759 ADSP2_PMEM_ERR_ADDR_SHIFT);
3760 }
3761
3762 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
3763 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
3764
3765 error:
3766 mutex_unlock(&dsp->pwr_lock);
3767
3768 return IRQ_HANDLED;
3769 }
3770 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
3771
3772 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support