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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / sound / soc / sh / rcar / adg.c
blobeb7879bcc6a795d44798d14474ea4a88061ea19d
1 /*
2 * Helper routines for R-Car sound ADG.
3 *
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/clk-provider.h>
11 #include "rsnd.h"
12
13 #define CLKA 0
14 #define CLKB 1
15 #define CLKC 2
16 #define CLKI 3
17 #define CLKMAX 4
18
19 #define CLKOUT 0
20 #define CLKOUT1 1
21 #define CLKOUT2 2
22 #define CLKOUT3 3
23 #define CLKOUTMAX 4
24
25 #define BRRx_MASK(x) (0x3FF & x)
26
27 static struct rsnd_mod_ops adg_ops = {
28 .name = "adg",
29 };
30
31 struct rsnd_adg {
32 struct clk *clk[CLKMAX];
33 struct clk *clkout[CLKOUTMAX];
34 struct clk_onecell_data onecell;
35 struct rsnd_mod mod;
36 u32 flags;
37 u32 ckr;
38 u32 rbga;
39 u32 rbgb;
40
41 int rbga_rate_for_441khz; /* RBGA */
42 int rbgb_rate_for_48khz; /* RBGB */
43 };
44
45 #define LRCLK_ASYNC (1 << 0)
46 #define AUDIO_OUT_48 (1 << 1)
47 #define adg_mode_flags(adg) (adg->flags)
48
49 #define for_each_rsnd_clk(pos, adg, i) \
50 for (i = 0; \
51 (i < CLKMAX) && \
52 ((pos) = adg->clk[i]); \
53 i++)
54 #define for_each_rsnd_clkout(pos, adg, i) \
55 for (i = 0; \
56 (i < CLKOUTMAX) && \
57 ((pos) = adg->clkout[i]); \
58 i++)
59 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
60
61 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
62 {
63 int i, ratio;
64
65 if (!div)
66 return 0;
67
68 for (i = 3; i >= 0; i--) {
69 ratio = 2 << (i * 2);
70 if (0 == (div % ratio))
71 return (u32)((i << 8) | ((div / ratio) - 1));
72 }
73
74 return ~0;
75 }
76
77 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
78 {
79 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
80 int id = rsnd_mod_id(ssi_mod);
81 int ws = id;
82
83 if (rsnd_ssi_is_pin_sharing(io)) {
84 switch (id) {
85 case 1:
86 case 2:
87 ws = 0;
88 break;
89 case 4:
90 ws = 3;
91 break;
92 case 8:
93 ws = 7;
94 break;
95 }
96 }
97
98 return (0x6 + ws) << 8;
99 }
100
101 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
102 struct rsnd_dai_stream *io,
103 unsigned int target_rate,
104 unsigned int *target_val,
105 unsigned int *target_en)
106 {
107 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
108 struct device *dev = rsnd_priv_to_dev(priv);
109 int idx, sel, div, step;
110 unsigned int val, en;
111 unsigned int min, diff;
112 unsigned int sel_rate[] = {
113 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
114 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
115 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
116 adg->rbga_rate_for_441khz, /* 0011: RBGA */
117 adg->rbgb_rate_for_48khz, /* 0100: RBGB */
118 };
119
120 min = ~0;
121 val = 0;
122 en = 0;
123 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
124 idx = 0;
125 step = 2;
126
127 if (!sel_rate[sel])
128 continue;
129
130 for (div = 2; div <= 98304; div += step) {
131 diff = abs(target_rate - sel_rate[sel] / div);
132 if (min > diff) {
133 val = (sel << 8) | idx;
134 min = diff;
135 en = 1 << (sel + 1); /* fixme */
136 }
137
138 /*
139 * step of 0_0000 / 0_0001 / 0_1101
140 * are out of order
141 */
142 if ((idx > 2) && (idx % 2))
143 step *= 2;
144 if (idx == 0x1c) {
145 div += step;
146 step *= 2;
147 }
148 idx++;
149 }
150 }
151
152 if (min == ~0) {
153 dev_err(dev, "no Input clock\n");
154 return;
155 }
156
157 *target_val = val;
158 if (target_en)
159 *target_en = en;
160 }
161
162 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
163 struct rsnd_dai_stream *io,
164 unsigned int in_rate,
165 unsigned int out_rate,
166 u32 *in, u32 *out, u32 *en)
167 {
168 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
169 unsigned int target_rate;
170 u32 *target_val;
171 u32 _in;
172 u32 _out;
173 u32 _en;
174
175 /* default = SSI WS */
176 _in =
177 _out = rsnd_adg_ssi_ws_timing_gen2(io);
178
179 target_rate = 0;
180 target_val = NULL;
181 _en = 0;
182 if (runtime->rate != in_rate) {
183 target_rate = out_rate;
184 target_val = &_out;
185 } else if (runtime->rate != out_rate) {
186 target_rate = in_rate;
187 target_val = &_in;
188 }
189
190 if (target_rate)
191 __rsnd_adg_get_timesel_ratio(priv, io,
192 target_rate,
193 target_val, &_en);
194
195 if (in)
196 *in = _in;
197 if (out)
198 *out = _out;
199 if (en)
200 *en = _en;
201 }
202
203 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
204 struct rsnd_dai_stream *io)
205 {
206 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
207 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
208 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
209 int id = rsnd_mod_id(cmd_mod);
210 int shift = (id % 2) ? 16 : 0;
211 u32 mask, val;
212
213 rsnd_adg_get_timesel_ratio(priv, io,
214 rsnd_src_get_in_rate(priv, io),
215 rsnd_src_get_out_rate(priv, io),
216 NULL, &val, NULL);
217
218 val = val << shift;
219 mask = 0x0f1f << shift;
220
221 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
222
223 return 0;
224 }
225
226 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
227 struct rsnd_dai_stream *io,
228 unsigned int in_rate,
229 unsigned int out_rate)
230 {
231 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
232 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
233 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
234 u32 in, out;
235 u32 mask, en;
236 int id = rsnd_mod_id(src_mod);
237 int shift = (id % 2) ? 16 : 0;
238
239 rsnd_mod_confirm_src(src_mod);
240
241 rsnd_adg_get_timesel_ratio(priv, io,
242 in_rate, out_rate,
243 &in, &out, &en);
244
245 in = in << shift;
246 out = out << shift;
247 mask = 0x0f1f << shift;
248
249 switch (id / 2) {
250 case 0:
251 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
252 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
253 break;
254 case 1:
255 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
256 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
257 break;
258 case 2:
259 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
260 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
261 break;
262 case 3:
263 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
264 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
265 break;
266 case 4:
267 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
268 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
269 break;
270 }
271
272 if (en)
273 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
274
275 return 0;
276 }
277
278 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
279 {
280 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
281 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
282 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
283 int id = rsnd_mod_id(ssi_mod);
284 int shift = (id % 4) * 8;
285 u32 mask = 0xFF << shift;
286
287 rsnd_mod_confirm_ssi(ssi_mod);
288
289 val = val << shift;
290
291 /*
292 * SSI 8 is not connected to ADG.
293 * it works with SSI 7
294 */
295 if (id == 8)
296 return;
297
298 switch (id / 4) {
299 case 0:
300 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
301 break;
302 case 1:
303 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
304 break;
305 case 2:
306 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
307 break;
308 }
309 }
310
311 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
312 {
313 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
314 struct device *dev = rsnd_priv_to_dev(priv);
315 struct clk *clk;
316 int i;
317 int sel_table[] = {
318 [CLKA] = 0x1,
319 [CLKB] = 0x2,
320 [CLKC] = 0x3,
321 [CLKI] = 0x0,
322 };
323
324 dev_dbg(dev, "request clock = %d\n", rate);
325
326 /*
327 * find suitable clock from
328 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
329 */
330 for_each_rsnd_clk(clk, adg, i) {
331 if (rate == clk_get_rate(clk))
332 return sel_table[i];
333 }
334
335 /*
336 * find divided clock from BRGA/BRGB
337 */
338 if (rate == adg->rbga_rate_for_441khz)
339 return 0x10;
340
341 if (rate == adg->rbgb_rate_for_48khz)
342 return 0x20;
343
344 return -EIO;
345 }
346
347 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
348 {
349 rsnd_adg_set_ssi_clk(ssi_mod, 0);
350
351 return 0;
352 }
353
354 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
355 {
356 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
357 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
358 struct device *dev = rsnd_priv_to_dev(priv);
359 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
360 int data;
361 u32 ckr = 0;
362
363 data = rsnd_adg_clk_query(priv, rate);
364 if (data < 0)
365 return data;
366
367 rsnd_adg_set_ssi_clk(ssi_mod, data);
368
369 if (adg_mode_flags(adg) & LRCLK_ASYNC) {
370 if (adg_mode_flags(adg) & AUDIO_OUT_48)
371 ckr = 0x80000000;
372 } else {
373 if (0 == (rate % 8000))
374 ckr = 0x80000000;
375 }
376
377 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
378 rsnd_mod_write(adg_mod, BRRA, adg->rbga);
379 rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
380
381 dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
382 rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
383 data, rate);
384
385 return 0;
386 }
387
388 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
389 {
390 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
391 struct device *dev = rsnd_priv_to_dev(priv);
392 struct clk *clk;
393 int i, ret;
394
395 for_each_rsnd_clk(clk, adg, i) {
396 ret = 0;
397 if (enable)
398 ret = clk_prepare_enable(clk);
399 else
400 clk_disable_unprepare(clk);
401
402 if (ret < 0)
403 dev_warn(dev, "can't use clk %d\n", i);
404 }
405 }
406
407 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
408 struct rsnd_adg *adg)
409 {
410 struct device *dev = rsnd_priv_to_dev(priv);
411 struct clk *clk;
412 static const char * const clk_name[] = {
413 [CLKA] = "clk_a",
414 [CLKB] = "clk_b",
415 [CLKC] = "clk_c",
416 [CLKI] = "clk_i",
417 };
418 int i;
419
420 for (i = 0; i < CLKMAX; i++) {
421 clk = devm_clk_get(dev, clk_name[i]);
422 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
423 }
424
425 for_each_rsnd_clk(clk, adg, i)
426 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
427 }
428
429 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
430 struct rsnd_adg *adg)
431 {
432 struct clk *clk;
433 struct device *dev = rsnd_priv_to_dev(priv);
434 struct device_node *np = dev->of_node;
435 struct property *prop;
436 u32 ckr, rbgx, rbga, rbgb;
437 u32 rate, div;
438 #define REQ_SIZE 2
439 u32 req_rate[REQ_SIZE] = {};
440 uint32_t count = 0;
441 unsigned long req_48kHz_rate, req_441kHz_rate;
442 int i, req_size;
443 const char *parent_clk_name = NULL;
444 static const char * const clkout_name[] = {
445 [CLKOUT] = "audio_clkout",
446 [CLKOUT1] = "audio_clkout1",
447 [CLKOUT2] = "audio_clkout2",
448 [CLKOUT3] = "audio_clkout3",
449 };
450 int brg_table[] = {
451 [CLKA] = 0x0,
452 [CLKB] = 0x1,
453 [CLKC] = 0x4,
454 [CLKI] = 0x2,
455 };
456
457 ckr = 0;
458 rbga = 2; /* default 1/6 */
459 rbgb = 2; /* default 1/6 */
460
461 /*
462 * ADG supports BRRA/BRRB output only
463 * this means all clkout0/1/2/3 will be same rate
464 */
465 prop = of_find_property(np, "clock-frequency", NULL);
466 if (!prop)
467 goto rsnd_adg_get_clkout_end;
468
469 req_size = prop->length / sizeof(u32);
470 if (req_size > REQ_SIZE) {
471 dev_err(dev,
472 "too many clock-frequency, use top %d\n", REQ_SIZE);
473 req_size = REQ_SIZE;
474 }
475
476 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
477 req_48kHz_rate = 0;
478 req_441kHz_rate = 0;
479 for (i = 0; i < req_size; i++) {
480 if (0 == (req_rate[i] % 44100))
481 req_441kHz_rate = req_rate[i];
482 if (0 == (req_rate[i] % 48000))
483 req_48kHz_rate = req_rate[i];
484 }
485
486 if (req_rate[0] % 48000 == 0)
487 adg->flags |= AUDIO_OUT_48;
488
489 if (of_get_property(np, "clkout-lr-asynchronous", NULL))
490 adg->flags |= LRCLK_ASYNC;
491
492 /*
493 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
494 * have 44.1kHz or 48kHz base clocks for now.
495 *
496 * SSI itself can divide parent clock by 1/1 - 1/16
497 * see
498 * rsnd_adg_ssi_clk_try_start()
499 * rsnd_ssi_master_clk_start()
500 */
501 adg->rbga_rate_for_441khz = 0;
502 adg->rbgb_rate_for_48khz = 0;
503 for_each_rsnd_clk(clk, adg, i) {
504 rate = clk_get_rate(clk);
505
506 if (0 == rate) /* not used */
507 continue;
508
509 /* RBGA */
510 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
511 div = 6;
512 if (req_441kHz_rate)
513 div = rate / req_441kHz_rate;
514 rbgx = rsnd_adg_calculate_rbgx(div);
515 if (BRRx_MASK(rbgx) == rbgx) {
516 rbga = rbgx;
517 adg->rbga_rate_for_441khz = rate / div;
518 ckr |= brg_table[i] << 20;
519 if (req_441kHz_rate &&
520 !(adg_mode_flags(adg) & AUDIO_OUT_48))
521 parent_clk_name = __clk_get_name(clk);
522 }
523 }
524
525 /* RBGB */
526 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
527 div = 6;
528 if (req_48kHz_rate)
529 div = rate / req_48kHz_rate;
530 rbgx = rsnd_adg_calculate_rbgx(div);
531 if (BRRx_MASK(rbgx) == rbgx) {
532 rbgb = rbgx;
533 adg->rbgb_rate_for_48khz = rate / div;
534 ckr |= brg_table[i] << 16;
535 if (req_48kHz_rate &&
536 (adg_mode_flags(adg) & AUDIO_OUT_48))
537 parent_clk_name = __clk_get_name(clk);
538 }
539 }
540 }
541
542 /*
543 * ADG supports BRRA/BRRB output only.
544 * this means all clkout0/1/2/3 will be * same rate
545 */
546
547 of_property_read_u32(np, "#clock-cells", &count);
548 /*
549 * for clkout
550 */
551 if (!count) {
552 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
553 parent_clk_name, 0, req_rate[0]);
554 if (!IS_ERR(clk)) {
555 adg->clkout[CLKOUT] = clk;
556 of_clk_add_provider(np, of_clk_src_simple_get, clk);
557 }
558 }
559 /*
560 * for clkout0/1/2/3
561 */
562 else {
563 for (i = 0; i < CLKOUTMAX; i++) {
564 clk = clk_register_fixed_rate(dev, clkout_name[i],
565 parent_clk_name, 0,
566 req_rate[0]);
567 if (!IS_ERR(clk))
568 adg->clkout[i] = clk;
569 }
570 adg->onecell.clks = adg->clkout;
571 adg->onecell.clk_num = CLKOUTMAX;
572 of_clk_add_provider(np, of_clk_src_onecell_get,
573 &adg->onecell);
574 }
575
576 rsnd_adg_get_clkout_end:
577 adg->ckr = ckr;
578 adg->rbga = rbga;
579 adg->rbgb = rbgb;
580
581 for_each_rsnd_clkout(clk, adg, i)
582 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
583 dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
584 ckr, rbga, rbgb);
585 }
586
587 int rsnd_adg_probe(struct rsnd_priv *priv)
588 {
589 struct rsnd_adg *adg;
590 struct device *dev = rsnd_priv_to_dev(priv);
591 int ret;
592
593 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
594 if (!adg)
595 return -ENOMEM;
596
597 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
598 NULL, NULL, 0, 0);
599 if (ret)
600 return ret;
601
602 rsnd_adg_get_clkin(priv, adg);
603 rsnd_adg_get_clkout(priv, adg);
604
605 priv->adg = adg;
606
607 rsnd_adg_clk_enable(priv);
608
609 return 0;
610 }
611
612 void rsnd_adg_remove(struct rsnd_priv *priv)
613 {
614 struct device *dev = rsnd_priv_to_dev(priv);
615 struct device_node *np = dev->of_node;
616 struct rsnd_adg *adg = priv->adg;
617 struct clk *clk;
618 int i;
619
620 for_each_rsnd_clkout(clk, adg, i)
621 if (adg->clkout[i])
622 clk_unregister_fixed_rate(adg->clkout[i]);
623
624 of_clk_del_provider(np);
625
626 rsnd_adg_clk_disable(priv);
627 }
Linux with added FPC-III support