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x86/speculation/mds: Fix documentation typo
[linux/fpc-iii.git] / sound / soc / sunxi / sun8i-codec.c
blob7a312168f8647acd364e9d0d97c9ef7801f51289
1 /*
2 * This driver supports the digital controls for the internal codec
3 * found in Allwinner's A33 SoCs.
4 *
5 * (C) Copyright 2010-2016
6 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
7 * huangxin <huangxin@Reuuimllatech.com>
8 * Mylène Josserand <mylene.josserand@free-electrons.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/io.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regmap.h>
27
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31
32 #define SUN8I_SYSCLK_CTL 0x00c
33 #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11
34 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL 9
35 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC 8
36 #define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3
37 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
38 #define SUN8I_MOD_CLK_ENA 0x010
39 #define SUN8I_MOD_CLK_ENA_AIF1 15
40 #define SUN8I_MOD_CLK_ENA_DAC 2
41 #define SUN8I_MOD_RST_CTL 0x014
42 #define SUN8I_MOD_RST_CTL_AIF1 15
43 #define SUN8I_MOD_RST_CTL_DAC 2
44 #define SUN8I_SYS_SR_CTRL 0x018
45 #define SUN8I_SYS_SR_CTRL_AIF1_FS 12
46 #define SUN8I_SYS_SR_CTRL_AIF2_FS 8
47 #define SUN8I_AIF1CLK_CTRL 0x040
48 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15
49 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14
50 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13
51 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9
52 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6
53 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16 (1 << 6)
54 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
55 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4)
56 #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
57 #define SUN8I_AIF1_DACDAT_CTRL 0x048
58 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
59 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
60 #define SUN8I_DAC_DIG_CTRL 0x120
61 #define SUN8I_DAC_DIG_CTRL_ENDA 15
62 #define SUN8I_DAC_MXR_SRC 0x130
63 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
64 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
65 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
66 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12
67 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
68 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
69 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
70 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
71
72 #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
73 #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
74 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4)
75 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
76 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
77
78 struct sun8i_codec {
79 struct device *dev;
80 struct regmap *regmap;
81 struct clk *clk_module;
82 struct clk *clk_bus;
83 };
84
85 static int sun8i_codec_runtime_resume(struct device *dev)
86 {
87 struct sun8i_codec *scodec = dev_get_drvdata(dev);
88 int ret;
89
90 ret = clk_prepare_enable(scodec->clk_module);
91 if (ret) {
92 dev_err(dev, "Failed to enable the module clock\n");
93 return ret;
94 }
95
96 ret = clk_prepare_enable(scodec->clk_bus);
97 if (ret) {
98 dev_err(dev, "Failed to enable the bus clock\n");
99 goto err_disable_modclk;
100 }
101
102 regcache_cache_only(scodec->regmap, false);
103
104 ret = regcache_sync(scodec->regmap);
105 if (ret) {
106 dev_err(dev, "Failed to sync regmap cache\n");
107 goto err_disable_clk;
108 }
109
110 return 0;
111
112 err_disable_clk:
113 clk_disable_unprepare(scodec->clk_bus);
114
115 err_disable_modclk:
116 clk_disable_unprepare(scodec->clk_module);
117
118 return ret;
119 }
120
121 static int sun8i_codec_runtime_suspend(struct device *dev)
122 {
123 struct sun8i_codec *scodec = dev_get_drvdata(dev);
124
125 regcache_cache_only(scodec->regmap, true);
126 regcache_mark_dirty(scodec->regmap);
127
128 clk_disable_unprepare(scodec->clk_module);
129 clk_disable_unprepare(scodec->clk_bus);
130
131 return 0;
132 }
133
134 static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
135 {
136 unsigned int rate = params_rate(params);
137
138 switch (rate) {
139 case 8000:
140 case 7350:
141 return 0x0;
142 case 11025:
143 return 0x1;
144 case 12000:
145 return 0x2;
146 case 16000:
147 return 0x3;
148 case 22050:
149 return 0x4;
150 case 24000:
151 return 0x5;
152 case 32000:
153 return 0x6;
154 case 44100:
155 return 0x7;
156 case 48000:
157 return 0x8;
158 case 96000:
159 return 0x9;
160 case 192000:
161 return 0xa;
162 default:
163 return -EINVAL;
164 }
165 }
166
167 static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
168 {
169 struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
170 u32 value;
171
172 /* clock masters */
173 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
174 case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */
175 value = 0x1;
176 break;
177 case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */
178 value = 0x0;
179 break;
180 default:
181 return -EINVAL;
182 }
183 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
184 BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
185 value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
186
187 /* clock inversion */
188 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
189 case SND_SOC_DAIFMT_NB_NF: /* Normal */
190 value = 0x0;
191 break;
192 case SND_SOC_DAIFMT_IB_IF: /* Inversion */
193 value = 0x1;
194 break;
195 default:
196 return -EINVAL;
197 }
198 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
199 BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
200 value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
201 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
202 BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
203 !value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
204
205 /* DAI format */
206 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
207 case SND_SOC_DAIFMT_I2S:
208 value = 0x0;
209 break;
210 case SND_SOC_DAIFMT_LEFT_J:
211 value = 0x1;
212 break;
213 case SND_SOC_DAIFMT_RIGHT_J:
214 value = 0x2;
215 break;
216 case SND_SOC_DAIFMT_DSP_A:
217 case SND_SOC_DAIFMT_DSP_B:
218 value = 0x3;
219 break;
220 default:
221 return -EINVAL;
222 }
223 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
224 BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT),
225 value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
226
227 return 0;
228 }
229
230 struct sun8i_codec_clk_div {
231 u8 div;
232 u8 val;
233 };
234
235 static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = {
236 { .div = 1, .val = 0 },
237 { .div = 2, .val = 1 },
238 { .div = 4, .val = 2 },
239 { .div = 6, .val = 3 },
240 { .div = 8, .val = 4 },
241 { .div = 12, .val = 5 },
242 { .div = 16, .val = 6 },
243 { .div = 24, .val = 7 },
244 { .div = 32, .val = 8 },
245 { .div = 48, .val = 9 },
246 { .div = 64, .val = 10 },
247 { .div = 96, .val = 11 },
248 { .div = 128, .val = 12 },
249 { .div = 192, .val = 13 },
250 };
251
252 static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec,
253 unsigned int rate,
254 unsigned int word_size)
255 {
256 unsigned long clk_rate = clk_get_rate(scodec->clk_module);
257 unsigned int div = clk_rate / rate / word_size / 2;
258 unsigned int best_val = 0, best_diff = ~0;
259 int i;
260
261 for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) {
262 const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i];
263 unsigned int diff = abs(bdiv->div - div);
264
265 if (diff < best_diff) {
266 best_diff = diff;
267 best_val = bdiv->val;
268 }
269 }
270
271 return best_val;
272 }
273
274 static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
275 struct snd_pcm_hw_params *params,
276 struct snd_soc_dai *dai)
277 {
278 struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
279 int sample_rate;
280 u8 bclk_div;
281
282 /*
283 * The CPU DAI handles only a sample of 16 bits. Configure the
284 * codec to handle this type of sample resolution.
285 */
286 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
287 SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
288 SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);
289
290 bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16);
291 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
292 SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK,
293 bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
294
295 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
296 SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
297 SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
298
299 sample_rate = sun8i_codec_get_hw_rate(params);
300 if (sample_rate < 0)
301 return sample_rate;
302
303 regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
304 SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
305 sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
306 regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
307 SUN8I_SYS_SR_CTRL_AIF2_FS_MASK,
308 sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS);
309
310 return 0;
311 }
312
313 static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
314 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
315 SUN8I_DAC_MXR_SRC,
316 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
317 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
318 SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
319 SUN8I_DAC_MXR_SRC,
320 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
321 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
322 SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
323 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
324 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
325 SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
326 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
327 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
328 };
329
330 static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
331 /* Digital parts of the DACs */
332 SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
333 0, NULL, 0),
334
335 /* Analog DAC AIF */
336 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
337 SUN8I_AIF1_DACDAT_CTRL,
338 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
339 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
340 SUN8I_AIF1_DACDAT_CTRL,
341 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
342
343 /* DAC Mixers */
344 SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
345 sun8i_dac_mixer_controls),
346 SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
347 sun8i_dac_mixer_controls),
348
349 /* Clocks */
350 SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
351 SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
352 SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
353 SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
354 SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
355 SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
356 SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
357 SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
358
359 SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL,
360 SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0),
361 /* Inversion as 0=AIF1, 1=AIF2 */
362 SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL,
363 SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),
364
365 /* Module reset */
366 SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL,
367 SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
368 SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
369 SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
370 };
371
372 static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
373 /* Clock Routes */
374 { "AIF1", NULL, "SYSCLK AIF1" },
375 { "AIF1 PLL", NULL, "AIF1" },
376 { "RST AIF1", NULL, "AIF1 PLL" },
377 { "MODCLK AFI1", NULL, "RST AIF1" },
378 { "DAC", NULL, "MODCLK AFI1" },
379
380 { "RST DAC", NULL, "SYSCLK" },
381 { "MODCLK DAC", NULL, "RST DAC" },
382 { "DAC", NULL, "MODCLK DAC" },
383
384 /* DAC Routes */
385 { "AIF1 Slot 0 Right", NULL, "DAC" },
386 { "AIF1 Slot 0 Left", NULL, "DAC" },
387
388 /* DAC Mixer Routes */
389 { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
390 "AIF1 Slot 0 Left"},
391 { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
392 "AIF1 Slot 0 Right"},
393 };
394
395 static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
396 .hw_params = sun8i_codec_hw_params,
397 .set_fmt = sun8i_set_fmt,
398 };
399
400 static struct snd_soc_dai_driver sun8i_codec_dai = {
401 .name = "sun8i",
402 /* playback capabilities */
403 .playback = {
404 .stream_name = "Playback",
405 .channels_min = 1,
406 .channels_max = 2,
407 .rates = SNDRV_PCM_RATE_8000_192000,
408 .formats = SNDRV_PCM_FMTBIT_S16_LE,
409 },
410 /* pcm operations */
411 .ops = &sun8i_codec_dai_ops,
412 };
413
414 static const struct snd_soc_codec_driver sun8i_soc_codec = {
415 .component_driver = {
416 .dapm_widgets = sun8i_codec_dapm_widgets,
417 .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets),
418 .dapm_routes = sun8i_codec_dapm_routes,
419 .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes),
420 },
421 };
422
423 static const struct regmap_config sun8i_codec_regmap_config = {
424 .reg_bits = 32,
425 .reg_stride = 4,
426 .val_bits = 32,
427 .max_register = SUN8I_DAC_MXR_SRC,
428
429 .cache_type = REGCACHE_FLAT,
430 };
431
432 static int sun8i_codec_probe(struct platform_device *pdev)
433 {
434 struct resource *res_base;
435 struct sun8i_codec *scodec;
436 void __iomem *base;
437 int ret;
438
439 scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
440 if (!scodec)
441 return -ENOMEM;
442
443 scodec->dev = &pdev->dev;
444
445 scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
446 if (IS_ERR(scodec->clk_module)) {
447 dev_err(&pdev->dev, "Failed to get the module clock\n");
448 return PTR_ERR(scodec->clk_module);
449 }
450
451 scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
452 if (IS_ERR(scodec->clk_bus)) {
453 dev_err(&pdev->dev, "Failed to get the bus clock\n");
454 return PTR_ERR(scodec->clk_bus);
455 }
456
457 res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
458 base = devm_ioremap_resource(&pdev->dev, res_base);
459 if (IS_ERR(base)) {
460 dev_err(&pdev->dev, "Failed to map the registers\n");
461 return PTR_ERR(base);
462 }
463
464 scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
465 &sun8i_codec_regmap_config);
466 if (IS_ERR(scodec->regmap)) {
467 dev_err(&pdev->dev, "Failed to create our regmap\n");
468 return PTR_ERR(scodec->regmap);
469 }
470
471 platform_set_drvdata(pdev, scodec);
472
473 pm_runtime_enable(&pdev->dev);
474 if (!pm_runtime_enabled(&pdev->dev)) {
475 ret = sun8i_codec_runtime_resume(&pdev->dev);
476 if (ret)
477 goto err_pm_disable;
478 }
479
480 ret = snd_soc_register_codec(&pdev->dev, &sun8i_soc_codec,
481 &sun8i_codec_dai, 1);
482 if (ret) {
483 dev_err(&pdev->dev, "Failed to register codec\n");
484 goto err_suspend;
485 }
486
487 return ret;
488
489 err_suspend:
490 if (!pm_runtime_status_suspended(&pdev->dev))
491 sun8i_codec_runtime_suspend(&pdev->dev);
492
493 err_pm_disable:
494 pm_runtime_disable(&pdev->dev);
495
496 return ret;
497 }
498
499 static int sun8i_codec_remove(struct platform_device *pdev)
500 {
501 struct snd_soc_card *card = platform_get_drvdata(pdev);
502 struct sun8i_codec *scodec = snd_soc_card_get_drvdata(card);
503
504 pm_runtime_disable(&pdev->dev);
505 if (!pm_runtime_status_suspended(&pdev->dev))
506 sun8i_codec_runtime_suspend(&pdev->dev);
507
508 snd_soc_unregister_codec(&pdev->dev);
509 clk_disable_unprepare(scodec->clk_module);
510 clk_disable_unprepare(scodec->clk_bus);
511
512 return 0;
513 }
514
515 static const struct of_device_id sun8i_codec_of_match[] = {
516 { .compatible = "allwinner,sun8i-a33-codec" },
517 {}
518 };
519 MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
520
521 static const struct dev_pm_ops sun8i_codec_pm_ops = {
522 SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
523 sun8i_codec_runtime_resume, NULL)
524 };
525
526 static struct platform_driver sun8i_codec_driver = {
527 .driver = {
528 .name = "sun8i-codec",
529 .of_match_table = sun8i_codec_of_match,
530 .pm = &sun8i_codec_pm_ops,
531 },
532 .probe = sun8i_codec_probe,
533 .remove = sun8i_codec_remove,
534 };
535 module_platform_driver(sun8i_codec_driver);
536
537 MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
538 MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>");
539 MODULE_LICENSE("GPL");
540 MODULE_ALIAS("platform:sun8i-codec");
Linux with added FPC-III support