drivers/gpio/gpio-mxs.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #include <linux/err.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqdomain.h>
  29 #include <linux/of.h>
  30 #include <linux/of_address.h>
  31 #include <linux/of_device.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/driver.h>
  35 /* FIXME: for gpio_get_value(), replace this by direct register read */
  36 #include <linux/gpio.h>
  37 #include <linux/module.h>
  38
  39 #define MXS_SET         0x4
  40 #define MXS_CLR         0x8
  41
  42 #define PINCTRL_DOUT(p)         ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
  43 #define PINCTRL_DIN(p)          ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
  44 #define PINCTRL_DOE(p)          ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
  45 #define PINCTRL_PIN2IRQ(p)      ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
  46 #define PINCTRL_IRQEN(p)        ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
  47 #define PINCTRL_IRQLEV(p)       ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
  48 #define PINCTRL_IRQPOL(p)       ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
  49 #define PINCTRL_IRQSTAT(p)      ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
  50
  51 #define GPIO_INT_FALL_EDGE      0x0
  52 #define GPIO_INT_LOW_LEV        0x1
  53 #define GPIO_INT_RISE_EDGE      0x2
  54 #define GPIO_INT_HIGH_LEV       0x3
  55 #define GPIO_INT_LEV_MASK       (1 << 0)
  56 #define GPIO_INT_POL_MASK       (1 << 1)
  57
  58 enum mxs_gpio_id {
  59         IMX23_GPIO,
  60         IMX28_GPIO,
  61 };
  62
  63 struct mxs_gpio_port {
  64         void __iomem *base;
  65         int id;
  66         int irq;
  67         struct irq_domain *domain;
  68         struct gpio_chip gc;
  69         enum mxs_gpio_id devid;
  70         u32 both_edges;
  71 };
  72
  73 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
  74 {
  75         return port->devid == IMX23_GPIO;
  76 }
  77
  78 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
  79 {
  80         return port->devid == IMX28_GPIO;
  81 }
  82
  83 /* Note: This driver assumes 32 GPIOs are handled in one register */
  84
  85 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  86 {
  87         u32 val;
  88         u32 pin_mask = 1 << d->hwirq;
  89         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  90         struct mxs_gpio_port *port = gc->private;
  91         void __iomem *pin_addr;
  92         int edge;
  93
  94         port->both_edges &= ~pin_mask;
  95         switch (type) {
  96         case IRQ_TYPE_EDGE_BOTH:
  97                 val = gpio_get_value(port->gc.base + d->hwirq);
  98                 if (val)
  99                         edge = GPIO_INT_FALL_EDGE;
 100                 else
 101                         edge = GPIO_INT_RISE_EDGE;
 102                 port->both_edges |= pin_mask;
 103                 break;
 104         case IRQ_TYPE_EDGE_RISING:
 105                 edge = GPIO_INT_RISE_EDGE;
 106                 break;
 107         case IRQ_TYPE_EDGE_FALLING:
 108                 edge = GPIO_INT_FALL_EDGE;
 109                 break;
 110         case IRQ_TYPE_LEVEL_LOW:
 111                 edge = GPIO_INT_LOW_LEV;
 112                 break;
 113         case IRQ_TYPE_LEVEL_HIGH:
 114                 edge = GPIO_INT_HIGH_LEV;
 115                 break;
 116         default:
 117                 return -EINVAL;
 118         }
 119
 120         /* set level or edge */
 121         pin_addr = port->base + PINCTRL_IRQLEV(port);
 122         if (edge & GPIO_INT_LEV_MASK)
 123                 writel(pin_mask, pin_addr + MXS_SET);
 124         else
 125                 writel(pin_mask, pin_addr + MXS_CLR);
 126
 127         /* set polarity */
 128         pin_addr = port->base + PINCTRL_IRQPOL(port);
 129         if (edge & GPIO_INT_POL_MASK)
 130                 writel(pin_mask, pin_addr + MXS_SET);
 131         else
 132                 writel(pin_mask, pin_addr + MXS_CLR);
 133
 134         writel(pin_mask,
 135                port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 136
 137         return 0;
 138 }
 139
 140 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
 141 {
 142         u32 bit, val, edge;
 143         void __iomem *pin_addr;
 144
 145         bit = 1 << gpio;
 146
 147         pin_addr = port->base + PINCTRL_IRQPOL(port);
 148         val = readl(pin_addr);
 149         edge = val & bit;
 150
 151         if (edge)
 152                 writel(bit, pin_addr + MXS_CLR);
 153         else
 154                 writel(bit, pin_addr + MXS_SET);
 155 }
 156
 157 /* MXS has one interrupt *per* gpio port */
 158 static void mxs_gpio_irq_handler(struct irq_desc *desc)
 159 {
 160         u32 irq_stat;
 161         struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
 162
 163         desc->irq_data.chip->irq_ack(&desc->irq_data);
 164
 165         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
 166                         readl(port->base + PINCTRL_IRQEN(port));
 167
 168         while (irq_stat != 0) {
 169                 int irqoffset = fls(irq_stat) - 1;
 170                 if (port->both_edges & (1 << irqoffset))
 171                         mxs_flip_edge(port, irqoffset);
 172
 173                 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 174                 irq_stat &= ~(1 << irqoffset);
 175         }
 176 }
 177
 178 /*
 179  * Set interrupt number "irq" in the GPIO as a wake-up source.
 180  * While system is running, all registered GPIO interrupts need to have
 181  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 182  * need to have wake-up enabled.
 183  * @param  irq          interrupt source number
 184  * @param  enable       enable as wake-up if equal to non-zero
 185  * @return       This function returns 0 on success.
 186  */
 187 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 188 {
 189         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 190         struct mxs_gpio_port *port = gc->private;
 191
 192         if (enable)
 193                 enable_irq_wake(port->irq);
 194         else
 195                 disable_irq_wake(port->irq);
 196
 197         return 0;
 198 }
 199
 200 static int __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
 201 {
 202         struct irq_chip_generic *gc;
 203         struct irq_chip_type *ct;
 204
 205         gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
 206                                     port->base, handle_level_irq);
 207         if (!gc)
 208                 return -ENOMEM;
 209
 210         gc->private = port;
 211
 212         ct = gc->chip_types;
 213         ct->chip.irq_ack = irq_gc_ack_set_bit;
 214         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 215         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 216         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 217         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 218         ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
 219         ct->regs.mask = PINCTRL_IRQEN(port);
 220
 221         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
 222                                IRQ_NOREQUEST, 0);
 223
 224         return 0;
 225 }
 226
 227 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 228 {
 229         struct mxs_gpio_port *port = gpiochip_get_data(gc);
 230
 231         return irq_find_mapping(port->domain, offset);
 232 }
 233
 234 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
 235 {
 236         struct mxs_gpio_port *port = gpiochip_get_data(gc);
 237         u32 mask = 1 << offset;
 238         u32 dir;
 239
 240         dir = readl(port->base + PINCTRL_DOE(port));
 241         return !(dir & mask);
 242 }
 243
 244 static const struct platform_device_id mxs_gpio_ids[] = {
 245         {
 246                 .name = "imx23-gpio",
 247                 .driver_data = IMX23_GPIO,
 248         }, {
 249                 .name = "imx28-gpio",
 250                 .driver_data = IMX28_GPIO,
 251         }, {
 252                 /* sentinel */
 253         }
 254 };
 255 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
 256
 257 static const struct of_device_id mxs_gpio_dt_ids[] = {
 258         { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
 259         { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
 260         { /* sentinel */ }
 261 };
 262 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
 263
 264 static int mxs_gpio_probe(struct platform_device *pdev)
 265 {
 266         const struct of_device_id *of_id =
 267                         of_match_device(mxs_gpio_dt_ids, &pdev->dev);
 268         struct device_node *np = pdev->dev.of_node;
 269         struct device_node *parent;
 270         static void __iomem *base;
 271         struct mxs_gpio_port *port;
 272         int irq_base;
 273         int err;
 274
 275         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 276         if (!port)
 277                 return -ENOMEM;
 278
 279         port->id = of_alias_get_id(np, "gpio");
 280         if (port->id < 0)
 281                 return port->id;
 282         port->devid = (enum mxs_gpio_id) of_id->data;
 283         port->irq = platform_get_irq(pdev, 0);
 284         if (port->irq < 0)
 285                 return port->irq;
 286
 287         /*
 288          * map memory region only once, as all the gpio ports
 289          * share the same one
 290          */
 291         if (!base) {
 292                 parent = of_get_parent(np);
 293                 base = of_iomap(parent, 0);
 294                 of_node_put(parent);
 295                 if (!base)
 296                         return -EADDRNOTAVAIL;
 297         }
 298         port->base = base;
 299
 300         /*
 301          * select the pin interrupt functionality but initially
 302          * disable the interrupts
 303          */
 304         writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
 305         writel(0, port->base + PINCTRL_IRQEN(port));
 306
 307         /* clear address has to be used to clear IRQSTAT bits */
 308         writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 309
 310         irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
 311         if (irq_base < 0) {
 312                 err = irq_base;
 313                 goto out_iounmap;
 314         }
 315
 316         port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
 317                                              &irq_domain_simple_ops, NULL);
 318         if (!port->domain) {
 319                 err = -ENODEV;
 320                 goto out_irqdesc_free;
 321         }
 322
 323         /* gpio-mxs can be a generic irq chip */
 324         err = mxs_gpio_init_gc(port, irq_base);
 325         if (err < 0)
 326                 goto out_irqdomain_remove;
 327
 328         /* setup one handler for each entry */
 329         irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
 330                                          port);
 331
 332         err = bgpio_init(&port->gc, &pdev->dev, 4,
 333                          port->base + PINCTRL_DIN(port),
 334                          port->base + PINCTRL_DOUT(port) + MXS_SET,
 335                          port->base + PINCTRL_DOUT(port) + MXS_CLR,
 336                          port->base + PINCTRL_DOE(port), NULL, 0);
 337         if (err)
 338                 goto out_irqdomain_remove;
 339
 340         port->gc.to_irq = mxs_gpio_to_irq;
 341         port->gc.get_direction = mxs_gpio_get_direction;
 342         port->gc.base = port->id * 32;
 343
 344         err = gpiochip_add_data(&port->gc, port);
 345         if (err)
 346                 goto out_irqdomain_remove;
 347
 348         return 0;
 349
 350 out_irqdomain_remove:
 351         irq_domain_remove(port->domain);
 352 out_irqdesc_free:
 353         irq_free_descs(irq_base, 32);
 354 out_iounmap:
 355         iounmap(port->base);
 356         return err;
 357 }
 358
 359 static struct platform_driver mxs_gpio_driver = {
 360         .driver         = {
 361                 .name   = "gpio-mxs",
 362                 .of_match_table = mxs_gpio_dt_ids,
 363         },
 364         .probe          = mxs_gpio_probe,
 365         .id_table       = mxs_gpio_ids,
 366 };
 367
 368 static int __init mxs_gpio_init(void)
 369 {
 370         return platform_driver_register(&mxs_gpio_driver);
 371 }
 372 postcore_initcall(mxs_gpio_init);
 373
 374 MODULE_AUTHOR("Freescale Semiconductor, "
 375               "Daniel Mack <danielncaiaq.de>, "
 376               "Juergen Beisert <kernel@pengutronix.de>");
 377 MODULE_DESCRIPTION("Freescale MXS GPIO");
 378 MODULE_LICENSE("GPL");