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hfs: get rid of hfs_sync_super
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
blobe5b84ff89ca58234b5c7e0d30fa8e97583d6357d
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 intel_emit_post_sync_nonzero_flush(ring);
223
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
226 * impact.
227 */
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
233 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
234 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
235
236 ret = intel_ring_begin(ring, 6);
237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, flags);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
243 intel_ring_emit(ring, 0); /* lower dword */
244 intel_ring_emit(ring, 0); /* uppwer dword */
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249 }
250
251 static void ring_write_tail(struct intel_ring_buffer *ring,
252 u32 value)
253 {
254 drm_i915_private_t *dev_priv = ring->dev->dev_private;
255 I915_WRITE_TAIL(ring, value);
256 }
257
258 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
259 {
260 drm_i915_private_t *dev_priv = ring->dev->dev_private;
261 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
262 RING_ACTHD(ring->mmio_base) : ACTHD;
263
264 return I915_READ(acthd_reg);
265 }
266
267 static int init_ring_common(struct intel_ring_buffer *ring)
268 {
269 struct drm_device *dev = ring->dev;
270 drm_i915_private_t *dev_priv = dev->dev_private;
271 struct drm_i915_gem_object *obj = ring->obj;
272 int ret = 0;
273 u32 head;
274
275 if (HAS_FORCE_WAKE(dev))
276 gen6_gt_force_wake_get(dev_priv);
277
278 /* Stop the ring if it's running. */
279 I915_WRITE_CTL(ring, 0);
280 I915_WRITE_HEAD(ring, 0);
281 ring->write_tail(ring, 0);
282
283 /* Initialize the ring. */
284 I915_WRITE_START(ring, obj->gtt_offset);
285 head = I915_READ_HEAD(ring) & HEAD_ADDR;
286
287 /* G45 ring initialization fails to reset head to zero */
288 if (head != 0) {
289 DRM_DEBUG_KMS("%s head not reset to zero "
290 "ctl %08x head %08x tail %08x start %08x\n",
291 ring->name,
292 I915_READ_CTL(ring),
293 I915_READ_HEAD(ring),
294 I915_READ_TAIL(ring),
295 I915_READ_START(ring));
296
297 I915_WRITE_HEAD(ring, 0);
298
299 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
300 DRM_ERROR("failed to set %s head to zero "
301 "ctl %08x head %08x tail %08x start %08x\n",
302 ring->name,
303 I915_READ_CTL(ring),
304 I915_READ_HEAD(ring),
305 I915_READ_TAIL(ring),
306 I915_READ_START(ring));
307 }
308 }
309
310 I915_WRITE_CTL(ring,
311 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
312 | RING_VALID);
313
314 /* If the head is still not zero, the ring is dead */
315 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
316 I915_READ_START(ring) == obj->gtt_offset &&
317 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
318 DRM_ERROR("%s initialization failed "
319 "ctl %08x head %08x tail %08x start %08x\n",
320 ring->name,
321 I915_READ_CTL(ring),
322 I915_READ_HEAD(ring),
323 I915_READ_TAIL(ring),
324 I915_READ_START(ring));
325 ret = -EIO;
326 goto out;
327 }
328
329 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
330 i915_kernel_lost_context(ring->dev);
331 else {
332 ring->head = I915_READ_HEAD(ring);
333 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
334 ring->space = ring_space(ring);
335 ring->last_retired_head = -1;
336 }
337
338 out:
339 if (HAS_FORCE_WAKE(dev))
340 gen6_gt_force_wake_put(dev_priv);
341
342 return ret;
343 }
344
345 static int
346 init_pipe_control(struct intel_ring_buffer *ring)
347 {
348 struct pipe_control *pc;
349 struct drm_i915_gem_object *obj;
350 int ret;
351
352 if (ring->private)
353 return 0;
354
355 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
356 if (!pc)
357 return -ENOMEM;
358
359 obj = i915_gem_alloc_object(ring->dev, 4096);
360 if (obj == NULL) {
361 DRM_ERROR("Failed to allocate seqno page\n");
362 ret = -ENOMEM;
363 goto err;
364 }
365
366 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
367
368 ret = i915_gem_object_pin(obj, 4096, true);
369 if (ret)
370 goto err_unref;
371
372 pc->gtt_offset = obj->gtt_offset;
373 pc->cpu_page = kmap(obj->pages[0]);
374 if (pc->cpu_page == NULL)
375 goto err_unpin;
376
377 pc->obj = obj;
378 ring->private = pc;
379 return 0;
380
381 err_unpin:
382 i915_gem_object_unpin(obj);
383 err_unref:
384 drm_gem_object_unreference(&obj->base);
385 err:
386 kfree(pc);
387 return ret;
388 }
389
390 static void
391 cleanup_pipe_control(struct intel_ring_buffer *ring)
392 {
393 struct pipe_control *pc = ring->private;
394 struct drm_i915_gem_object *obj;
395
396 if (!ring->private)
397 return;
398
399 obj = pc->obj;
400 kunmap(obj->pages[0]);
401 i915_gem_object_unpin(obj);
402 drm_gem_object_unreference(&obj->base);
403
404 kfree(pc);
405 ring->private = NULL;
406 }
407
408 static int init_render_ring(struct intel_ring_buffer *ring)
409 {
410 struct drm_device *dev = ring->dev;
411 struct drm_i915_private *dev_priv = dev->dev_private;
412 int ret = init_ring_common(ring);
413
414 if (INTEL_INFO(dev)->gen > 3) {
415 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
416 if (IS_GEN7(dev))
417 I915_WRITE(GFX_MODE_GEN7,
418 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
419 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
420 }
421
422 if (INTEL_INFO(dev)->gen >= 5) {
423 ret = init_pipe_control(ring);
424 if (ret)
425 return ret;
426 }
427
428 if (IS_GEN6(dev)) {
429 /* From the Sandybridge PRM, volume 1 part 3, page 24:
430 * "If this bit is set, STCunit will have LRA as replacement
431 * policy. [...] This bit must be reset. LRA replacement
432 * policy is not supported."
433 */
434 I915_WRITE(CACHE_MODE_0,
435 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
436 }
437
438 if (INTEL_INFO(dev)->gen >= 6)
439 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
440
441 return ret;
442 }
443
444 static void render_ring_cleanup(struct intel_ring_buffer *ring)
445 {
446 if (!ring->private)
447 return;
448
449 cleanup_pipe_control(ring);
450 }
451
452 static void
453 update_mboxes(struct intel_ring_buffer *ring,
454 u32 seqno,
455 u32 mmio_offset)
456 {
457 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
458 MI_SEMAPHORE_GLOBAL_GTT |
459 MI_SEMAPHORE_REGISTER |
460 MI_SEMAPHORE_UPDATE);
461 intel_ring_emit(ring, seqno);
462 intel_ring_emit(ring, mmio_offset);
463 }
464
465 /**
466 * gen6_add_request - Update the semaphore mailbox registers
467 *
468 * @ring - ring that is adding a request
469 * @seqno - return seqno stuck into the ring
470 *
471 * Update the mailbox registers in the *other* rings with the current seqno.
472 * This acts like a signal in the canonical semaphore.
473 */
474 static int
475 gen6_add_request(struct intel_ring_buffer *ring,
476 u32 *seqno)
477 {
478 u32 mbox1_reg;
479 u32 mbox2_reg;
480 int ret;
481
482 ret = intel_ring_begin(ring, 10);
483 if (ret)
484 return ret;
485
486 mbox1_reg = ring->signal_mbox[0];
487 mbox2_reg = ring->signal_mbox[1];
488
489 *seqno = i915_gem_next_request_seqno(ring);
490
491 update_mboxes(ring, *seqno, mbox1_reg);
492 update_mboxes(ring, *seqno, mbox2_reg);
493 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
494 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
495 intel_ring_emit(ring, *seqno);
496 intel_ring_emit(ring, MI_USER_INTERRUPT);
497 intel_ring_advance(ring);
498
499 return 0;
500 }
501
502 /**
503 * intel_ring_sync - sync the waiter to the signaller on seqno
504 *
505 * @waiter - ring that is waiting
506 * @signaller - ring which has, or will signal
507 * @seqno - seqno which the waiter will block on
508 */
509 static int
510 gen6_ring_sync(struct intel_ring_buffer *waiter,
511 struct intel_ring_buffer *signaller,
512 u32 seqno)
513 {
514 int ret;
515 u32 dw1 = MI_SEMAPHORE_MBOX |
516 MI_SEMAPHORE_COMPARE |
517 MI_SEMAPHORE_REGISTER;
518
519 /* Throughout all of the GEM code, seqno passed implies our current
520 * seqno is >= the last seqno executed. However for hardware the
521 * comparison is strictly greater than.
522 */
523 seqno -= 1;
524
525 WARN_ON(signaller->semaphore_register[waiter->id] ==
526 MI_SEMAPHORE_SYNC_INVALID);
527
528 ret = intel_ring_begin(waiter, 4);
529 if (ret)
530 return ret;
531
532 intel_ring_emit(waiter,
533 dw1 | signaller->semaphore_register[waiter->id]);
534 intel_ring_emit(waiter, seqno);
535 intel_ring_emit(waiter, 0);
536 intel_ring_emit(waiter, MI_NOOP);
537 intel_ring_advance(waiter);
538
539 return 0;
540 }
541
542 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
543 do { \
544 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
545 PIPE_CONTROL_DEPTH_STALL); \
546 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
547 intel_ring_emit(ring__, 0); \
548 intel_ring_emit(ring__, 0); \
549 } while (0)
550
551 static int
552 pc_render_add_request(struct intel_ring_buffer *ring,
553 u32 *result)
554 {
555 u32 seqno = i915_gem_next_request_seqno(ring);
556 struct pipe_control *pc = ring->private;
557 u32 scratch_addr = pc->gtt_offset + 128;
558 int ret;
559
560 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
561 * incoherent with writes to memory, i.e. completely fubar,
562 * so we need to use PIPE_NOTIFY instead.
563 *
564 * However, we also need to workaround the qword write
565 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
566 * memory before requesting an interrupt.
567 */
568 ret = intel_ring_begin(ring, 32);
569 if (ret)
570 return ret;
571
572 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
573 PIPE_CONTROL_WRITE_FLUSH |
574 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
575 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
576 intel_ring_emit(ring, seqno);
577 intel_ring_emit(ring, 0);
578 PIPE_CONTROL_FLUSH(ring, scratch_addr);
579 scratch_addr += 128; /* write to separate cachelines */
580 PIPE_CONTROL_FLUSH(ring, scratch_addr);
581 scratch_addr += 128;
582 PIPE_CONTROL_FLUSH(ring, scratch_addr);
583 scratch_addr += 128;
584 PIPE_CONTROL_FLUSH(ring, scratch_addr);
585 scratch_addr += 128;
586 PIPE_CONTROL_FLUSH(ring, scratch_addr);
587 scratch_addr += 128;
588 PIPE_CONTROL_FLUSH(ring, scratch_addr);
589
590 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
591 PIPE_CONTROL_WRITE_FLUSH |
592 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
593 PIPE_CONTROL_NOTIFY);
594 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
595 intel_ring_emit(ring, seqno);
596 intel_ring_emit(ring, 0);
597 intel_ring_advance(ring);
598
599 *result = seqno;
600 return 0;
601 }
602
603 static u32
604 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
605 {
606 struct drm_device *dev = ring->dev;
607
608 /* Workaround to force correct ordering between irq and seqno writes on
609 * ivb (and maybe also on snb) by reading from a CS register (like
610 * ACTHD) before reading the status page. */
611 if (IS_GEN6(dev) || IS_GEN7(dev))
612 intel_ring_get_active_head(ring);
613 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
614 }
615
616 static u32
617 ring_get_seqno(struct intel_ring_buffer *ring)
618 {
619 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
620 }
621
622 static u32
623 pc_render_get_seqno(struct intel_ring_buffer *ring)
624 {
625 struct pipe_control *pc = ring->private;
626 return pc->cpu_page[0];
627 }
628
629 static bool
630 gen5_ring_get_irq(struct intel_ring_buffer *ring)
631 {
632 struct drm_device *dev = ring->dev;
633 drm_i915_private_t *dev_priv = dev->dev_private;
634 unsigned long flags;
635
636 if (!dev->irq_enabled)
637 return false;
638
639 spin_lock_irqsave(&dev_priv->irq_lock, flags);
640 if (ring->irq_refcount++ == 0) {
641 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
642 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
643 POSTING_READ(GTIMR);
644 }
645 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
646
647 return true;
648 }
649
650 static void
651 gen5_ring_put_irq(struct intel_ring_buffer *ring)
652 {
653 struct drm_device *dev = ring->dev;
654 drm_i915_private_t *dev_priv = dev->dev_private;
655 unsigned long flags;
656
657 spin_lock_irqsave(&dev_priv->irq_lock, flags);
658 if (--ring->irq_refcount == 0) {
659 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
660 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
661 POSTING_READ(GTIMR);
662 }
663 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
664 }
665
666 static bool
667 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
668 {
669 struct drm_device *dev = ring->dev;
670 drm_i915_private_t *dev_priv = dev->dev_private;
671 unsigned long flags;
672
673 if (!dev->irq_enabled)
674 return false;
675
676 spin_lock_irqsave(&dev_priv->irq_lock, flags);
677 if (ring->irq_refcount++ == 0) {
678 dev_priv->irq_mask &= ~ring->irq_enable_mask;
679 I915_WRITE(IMR, dev_priv->irq_mask);
680 POSTING_READ(IMR);
681 }
682 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
683
684 return true;
685 }
686
687 static void
688 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
689 {
690 struct drm_device *dev = ring->dev;
691 drm_i915_private_t *dev_priv = dev->dev_private;
692 unsigned long flags;
693
694 spin_lock_irqsave(&dev_priv->irq_lock, flags);
695 if (--ring->irq_refcount == 0) {
696 dev_priv->irq_mask |= ring->irq_enable_mask;
697 I915_WRITE(IMR, dev_priv->irq_mask);
698 POSTING_READ(IMR);
699 }
700 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
701 }
702
703 static bool
704 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
705 {
706 struct drm_device *dev = ring->dev;
707 drm_i915_private_t *dev_priv = dev->dev_private;
708 unsigned long flags;
709
710 if (!dev->irq_enabled)
711 return false;
712
713 spin_lock_irqsave(&dev_priv->irq_lock, flags);
714 if (ring->irq_refcount++ == 0) {
715 dev_priv->irq_mask &= ~ring->irq_enable_mask;
716 I915_WRITE16(IMR, dev_priv->irq_mask);
717 POSTING_READ16(IMR);
718 }
719 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
720
721 return true;
722 }
723
724 static void
725 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
726 {
727 struct drm_device *dev = ring->dev;
728 drm_i915_private_t *dev_priv = dev->dev_private;
729 unsigned long flags;
730
731 spin_lock_irqsave(&dev_priv->irq_lock, flags);
732 if (--ring->irq_refcount == 0) {
733 dev_priv->irq_mask |= ring->irq_enable_mask;
734 I915_WRITE16(IMR, dev_priv->irq_mask);
735 POSTING_READ16(IMR);
736 }
737 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
738 }
739
740 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
741 {
742 struct drm_device *dev = ring->dev;
743 drm_i915_private_t *dev_priv = ring->dev->dev_private;
744 u32 mmio = 0;
745
746 /* The ring status page addresses are no longer next to the rest of
747 * the ring registers as of gen7.
748 */
749 if (IS_GEN7(dev)) {
750 switch (ring->id) {
751 case RCS:
752 mmio = RENDER_HWS_PGA_GEN7;
753 break;
754 case BCS:
755 mmio = BLT_HWS_PGA_GEN7;
756 break;
757 case VCS:
758 mmio = BSD_HWS_PGA_GEN7;
759 break;
760 }
761 } else if (IS_GEN6(ring->dev)) {
762 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
763 } else {
764 mmio = RING_HWS_PGA(ring->mmio_base);
765 }
766
767 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
768 POSTING_READ(mmio);
769 }
770
771 static int
772 bsd_ring_flush(struct intel_ring_buffer *ring,
773 u32 invalidate_domains,
774 u32 flush_domains)
775 {
776 int ret;
777
778 ret = intel_ring_begin(ring, 2);
779 if (ret)
780 return ret;
781
782 intel_ring_emit(ring, MI_FLUSH);
783 intel_ring_emit(ring, MI_NOOP);
784 intel_ring_advance(ring);
785 return 0;
786 }
787
788 static int
789 i9xx_add_request(struct intel_ring_buffer *ring,
790 u32 *result)
791 {
792 u32 seqno;
793 int ret;
794
795 ret = intel_ring_begin(ring, 4);
796 if (ret)
797 return ret;
798
799 seqno = i915_gem_next_request_seqno(ring);
800
801 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
802 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
803 intel_ring_emit(ring, seqno);
804 intel_ring_emit(ring, MI_USER_INTERRUPT);
805 intel_ring_advance(ring);
806
807 *result = seqno;
808 return 0;
809 }
810
811 static bool
812 gen6_ring_get_irq(struct intel_ring_buffer *ring)
813 {
814 struct drm_device *dev = ring->dev;
815 drm_i915_private_t *dev_priv = dev->dev_private;
816 unsigned long flags;
817
818 if (!dev->irq_enabled)
819 return false;
820
821 /* It looks like we need to prevent the gt from suspending while waiting
822 * for an notifiy irq, otherwise irqs seem to get lost on at least the
823 * blt/bsd rings on ivb. */
824 gen6_gt_force_wake_get(dev_priv);
825
826 spin_lock_irqsave(&dev_priv->irq_lock, flags);
827 if (ring->irq_refcount++ == 0) {
828 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
829 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
830 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
831 POSTING_READ(GTIMR);
832 }
833 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
834
835 return true;
836 }
837
838 static void
839 gen6_ring_put_irq(struct intel_ring_buffer *ring)
840 {
841 struct drm_device *dev = ring->dev;
842 drm_i915_private_t *dev_priv = dev->dev_private;
843 unsigned long flags;
844
845 spin_lock_irqsave(&dev_priv->irq_lock, flags);
846 if (--ring->irq_refcount == 0) {
847 I915_WRITE_IMR(ring, ~0);
848 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
849 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
850 POSTING_READ(GTIMR);
851 }
852 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
853
854 gen6_gt_force_wake_put(dev_priv);
855 }
856
857 static int
858 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
859 {
860 int ret;
861
862 ret = intel_ring_begin(ring, 2);
863 if (ret)
864 return ret;
865
866 intel_ring_emit(ring,
867 MI_BATCH_BUFFER_START |
868 MI_BATCH_GTT |
869 MI_BATCH_NON_SECURE_I965);
870 intel_ring_emit(ring, offset);
871 intel_ring_advance(ring);
872
873 return 0;
874 }
875
876 static int
877 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
878 u32 offset, u32 len)
879 {
880 int ret;
881
882 ret = intel_ring_begin(ring, 4);
883 if (ret)
884 return ret;
885
886 intel_ring_emit(ring, MI_BATCH_BUFFER);
887 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
888 intel_ring_emit(ring, offset + len - 8);
889 intel_ring_emit(ring, 0);
890 intel_ring_advance(ring);
891
892 return 0;
893 }
894
895 static int
896 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
897 u32 offset, u32 len)
898 {
899 int ret;
900
901 ret = intel_ring_begin(ring, 2);
902 if (ret)
903 return ret;
904
905 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
906 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
907 intel_ring_advance(ring);
908
909 return 0;
910 }
911
912 static void cleanup_status_page(struct intel_ring_buffer *ring)
913 {
914 struct drm_i915_gem_object *obj;
915
916 obj = ring->status_page.obj;
917 if (obj == NULL)
918 return;
919
920 kunmap(obj->pages[0]);
921 i915_gem_object_unpin(obj);
922 drm_gem_object_unreference(&obj->base);
923 ring->status_page.obj = NULL;
924 }
925
926 static int init_status_page(struct intel_ring_buffer *ring)
927 {
928 struct drm_device *dev = ring->dev;
929 struct drm_i915_gem_object *obj;
930 int ret;
931
932 obj = i915_gem_alloc_object(dev, 4096);
933 if (obj == NULL) {
934 DRM_ERROR("Failed to allocate status page\n");
935 ret = -ENOMEM;
936 goto err;
937 }
938
939 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
940
941 ret = i915_gem_object_pin(obj, 4096, true);
942 if (ret != 0) {
943 goto err_unref;
944 }
945
946 ring->status_page.gfx_addr = obj->gtt_offset;
947 ring->status_page.page_addr = kmap(obj->pages[0]);
948 if (ring->status_page.page_addr == NULL) {
949 goto err_unpin;
950 }
951 ring->status_page.obj = obj;
952 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
953
954 intel_ring_setup_status_page(ring);
955 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
956 ring->name, ring->status_page.gfx_addr);
957
958 return 0;
959
960 err_unpin:
961 i915_gem_object_unpin(obj);
962 err_unref:
963 drm_gem_object_unreference(&obj->base);
964 err:
965 return ret;
966 }
967
968 static int intel_init_ring_buffer(struct drm_device *dev,
969 struct intel_ring_buffer *ring)
970 {
971 struct drm_i915_gem_object *obj;
972 int ret;
973
974 ring->dev = dev;
975 INIT_LIST_HEAD(&ring->active_list);
976 INIT_LIST_HEAD(&ring->request_list);
977 INIT_LIST_HEAD(&ring->gpu_write_list);
978 ring->size = 32 * PAGE_SIZE;
979
980 init_waitqueue_head(&ring->irq_queue);
981
982 if (I915_NEED_GFX_HWS(dev)) {
983 ret = init_status_page(ring);
984 if (ret)
985 return ret;
986 }
987
988 obj = i915_gem_alloc_object(dev, ring->size);
989 if (obj == NULL) {
990 DRM_ERROR("Failed to allocate ringbuffer\n");
991 ret = -ENOMEM;
992 goto err_hws;
993 }
994
995 ring->obj = obj;
996
997 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
998 if (ret)
999 goto err_unref;
1000
1001 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1002 if (ret)
1003 goto err_unpin;
1004
1005 ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
1006 ring->size);
1007 if (ring->virtual_start == NULL) {
1008 DRM_ERROR("Failed to map ringbuffer.\n");
1009 ret = -EINVAL;
1010 goto err_unpin;
1011 }
1012
1013 ret = ring->init(ring);
1014 if (ret)
1015 goto err_unmap;
1016
1017 /* Workaround an erratum on the i830 which causes a hang if
1018 * the TAIL pointer points to within the last 2 cachelines
1019 * of the buffer.
1020 */
1021 ring->effective_size = ring->size;
1022 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1023 ring->effective_size -= 128;
1024
1025 return 0;
1026
1027 err_unmap:
1028 iounmap(ring->virtual_start);
1029 err_unpin:
1030 i915_gem_object_unpin(obj);
1031 err_unref:
1032 drm_gem_object_unreference(&obj->base);
1033 ring->obj = NULL;
1034 err_hws:
1035 cleanup_status_page(ring);
1036 return ret;
1037 }
1038
1039 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1040 {
1041 struct drm_i915_private *dev_priv;
1042 int ret;
1043
1044 if (ring->obj == NULL)
1045 return;
1046
1047 /* Disable the ring buffer. The ring must be idle at this point */
1048 dev_priv = ring->dev->dev_private;
1049 ret = intel_wait_ring_idle(ring);
1050 if (ret)
1051 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1052 ring->name, ret);
1053
1054 I915_WRITE_CTL(ring, 0);
1055
1056 iounmap(ring->virtual_start);
1057
1058 i915_gem_object_unpin(ring->obj);
1059 drm_gem_object_unreference(&ring->obj->base);
1060 ring->obj = NULL;
1061
1062 if (ring->cleanup)
1063 ring->cleanup(ring);
1064
1065 cleanup_status_page(ring);
1066 }
1067
1068 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1069 {
1070 uint32_t __iomem *virt;
1071 int rem = ring->size - ring->tail;
1072
1073 if (ring->space < rem) {
1074 int ret = intel_wait_ring_buffer(ring, rem);
1075 if (ret)
1076 return ret;
1077 }
1078
1079 virt = ring->virtual_start + ring->tail;
1080 rem /= 4;
1081 while (rem--)
1082 iowrite32(MI_NOOP, virt++);
1083
1084 ring->tail = 0;
1085 ring->space = ring_space(ring);
1086
1087 return 0;
1088 }
1089
1090 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1091 {
1092 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1093 bool was_interruptible;
1094 int ret;
1095
1096 /* XXX As we have not yet audited all the paths to check that
1097 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1098 * allow us to be interruptible by a signal.
1099 */
1100 was_interruptible = dev_priv->mm.interruptible;
1101 dev_priv->mm.interruptible = false;
1102
1103 ret = i915_wait_request(ring, seqno);
1104
1105 dev_priv->mm.interruptible = was_interruptible;
1106 if (!ret)
1107 i915_gem_retire_requests_ring(ring);
1108
1109 return ret;
1110 }
1111
1112 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1113 {
1114 struct drm_i915_gem_request *request;
1115 u32 seqno = 0;
1116 int ret;
1117
1118 i915_gem_retire_requests_ring(ring);
1119
1120 if (ring->last_retired_head != -1) {
1121 ring->head = ring->last_retired_head;
1122 ring->last_retired_head = -1;
1123 ring->space = ring_space(ring);
1124 if (ring->space >= n)
1125 return 0;
1126 }
1127
1128 list_for_each_entry(request, &ring->request_list, list) {
1129 int space;
1130
1131 if (request->tail == -1)
1132 continue;
1133
1134 space = request->tail - (ring->tail + 8);
1135 if (space < 0)
1136 space += ring->size;
1137 if (space >= n) {
1138 seqno = request->seqno;
1139 break;
1140 }
1141
1142 /* Consume this request in case we need more space than
1143 * is available and so need to prevent a race between
1144 * updating last_retired_head and direct reads of
1145 * I915_RING_HEAD. It also provides a nice sanity check.
1146 */
1147 request->tail = -1;
1148 }
1149
1150 if (seqno == 0)
1151 return -ENOSPC;
1152
1153 ret = intel_ring_wait_seqno(ring, seqno);
1154 if (ret)
1155 return ret;
1156
1157 if (WARN_ON(ring->last_retired_head == -1))
1158 return -ENOSPC;
1159
1160 ring->head = ring->last_retired_head;
1161 ring->last_retired_head = -1;
1162 ring->space = ring_space(ring);
1163 if (WARN_ON(ring->space < n))
1164 return -ENOSPC;
1165
1166 return 0;
1167 }
1168
1169 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1170 {
1171 struct drm_device *dev = ring->dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 unsigned long end;
1174 int ret;
1175
1176 ret = intel_ring_wait_request(ring, n);
1177 if (ret != -ENOSPC)
1178 return ret;
1179
1180 trace_i915_ring_wait_begin(ring);
1181 /* With GEM the hangcheck timer should kick us out of the loop,
1182 * leaving it early runs the risk of corrupting GEM state (due
1183 * to running on almost untested codepaths). But on resume
1184 * timers don't work yet, so prevent a complete hang in that
1185 * case by choosing an insanely large timeout. */
1186 end = jiffies + 60 * HZ;
1187
1188 do {
1189 ring->head = I915_READ_HEAD(ring);
1190 ring->space = ring_space(ring);
1191 if (ring->space >= n) {
1192 trace_i915_ring_wait_end(ring);
1193 return 0;
1194 }
1195
1196 if (dev->primary->master) {
1197 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1198 if (master_priv->sarea_priv)
1199 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1200 }
1201
1202 msleep(1);
1203 if (atomic_read(&dev_priv->mm.wedged))
1204 return -EAGAIN;
1205 } while (!time_after(jiffies, end));
1206 trace_i915_ring_wait_end(ring);
1207 return -EBUSY;
1208 }
1209
1210 int intel_ring_begin(struct intel_ring_buffer *ring,
1211 int num_dwords)
1212 {
1213 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1214 int n = 4*num_dwords;
1215 int ret;
1216
1217 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1218 return -EIO;
1219
1220 if (unlikely(ring->tail + n > ring->effective_size)) {
1221 ret = intel_wrap_ring_buffer(ring);
1222 if (unlikely(ret))
1223 return ret;
1224 }
1225
1226 if (unlikely(ring->space < n)) {
1227 ret = intel_wait_ring_buffer(ring, n);
1228 if (unlikely(ret))
1229 return ret;
1230 }
1231
1232 ring->space -= n;
1233 return 0;
1234 }
1235
1236 void intel_ring_advance(struct intel_ring_buffer *ring)
1237 {
1238 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1239
1240 ring->tail &= ring->size - 1;
1241 if (dev_priv->stop_rings & intel_ring_flag(ring))
1242 return;
1243 ring->write_tail(ring, ring->tail);
1244 }
1245
1246
1247 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1248 u32 value)
1249 {
1250 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1251
1252 /* Every tail move must follow the sequence below */
1253 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1254 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1255 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1256 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1257
1258 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1259 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1260 50))
1261 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1262
1263 I915_WRITE_TAIL(ring, value);
1264 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1265 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1266 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1267 }
1268
1269 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1270 u32 invalidate, u32 flush)
1271 {
1272 uint32_t cmd;
1273 int ret;
1274
1275 ret = intel_ring_begin(ring, 4);
1276 if (ret)
1277 return ret;
1278
1279 cmd = MI_FLUSH_DW;
1280 if (invalidate & I915_GEM_GPU_DOMAINS)
1281 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1282 intel_ring_emit(ring, cmd);
1283 intel_ring_emit(ring, 0);
1284 intel_ring_emit(ring, 0);
1285 intel_ring_emit(ring, MI_NOOP);
1286 intel_ring_advance(ring);
1287 return 0;
1288 }
1289
1290 static int
1291 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1292 u32 offset, u32 len)
1293 {
1294 int ret;
1295
1296 ret = intel_ring_begin(ring, 2);
1297 if (ret)
1298 return ret;
1299
1300 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1301 /* bit0-7 is the length on GEN6+ */
1302 intel_ring_emit(ring, offset);
1303 intel_ring_advance(ring);
1304
1305 return 0;
1306 }
1307
1308 /* Blitter support (SandyBridge+) */
1309
1310 static int blt_ring_flush(struct intel_ring_buffer *ring,
1311 u32 invalidate, u32 flush)
1312 {
1313 uint32_t cmd;
1314 int ret;
1315
1316 ret = intel_ring_begin(ring, 4);
1317 if (ret)
1318 return ret;
1319
1320 cmd = MI_FLUSH_DW;
1321 if (invalidate & I915_GEM_DOMAIN_RENDER)
1322 cmd |= MI_INVALIDATE_TLB;
1323 intel_ring_emit(ring, cmd);
1324 intel_ring_emit(ring, 0);
1325 intel_ring_emit(ring, 0);
1326 intel_ring_emit(ring, MI_NOOP);
1327 intel_ring_advance(ring);
1328 return 0;
1329 }
1330
1331 int intel_init_render_ring_buffer(struct drm_device *dev)
1332 {
1333 drm_i915_private_t *dev_priv = dev->dev_private;
1334 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1335
1336 ring->name = "render ring";
1337 ring->id = RCS;
1338 ring->mmio_base = RENDER_RING_BASE;
1339
1340 if (INTEL_INFO(dev)->gen >= 6) {
1341 ring->add_request = gen6_add_request;
1342 ring->flush = gen6_render_ring_flush;
1343 ring->irq_get = gen6_ring_get_irq;
1344 ring->irq_put = gen6_ring_put_irq;
1345 ring->irq_enable_mask = GT_USER_INTERRUPT;
1346 ring->get_seqno = gen6_ring_get_seqno;
1347 ring->sync_to = gen6_ring_sync;
1348 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1349 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1350 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1351 ring->signal_mbox[0] = GEN6_VRSYNC;
1352 ring->signal_mbox[1] = GEN6_BRSYNC;
1353 } else if (IS_GEN5(dev)) {
1354 ring->add_request = pc_render_add_request;
1355 ring->flush = gen4_render_ring_flush;
1356 ring->get_seqno = pc_render_get_seqno;
1357 ring->irq_get = gen5_ring_get_irq;
1358 ring->irq_put = gen5_ring_put_irq;
1359 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1360 } else {
1361 ring->add_request = i9xx_add_request;
1362 if (INTEL_INFO(dev)->gen < 4)
1363 ring->flush = gen2_render_ring_flush;
1364 else
1365 ring->flush = gen4_render_ring_flush;
1366 ring->get_seqno = ring_get_seqno;
1367 if (IS_GEN2(dev)) {
1368 ring->irq_get = i8xx_ring_get_irq;
1369 ring->irq_put = i8xx_ring_put_irq;
1370 } else {
1371 ring->irq_get = i9xx_ring_get_irq;
1372 ring->irq_put = i9xx_ring_put_irq;
1373 }
1374 ring->irq_enable_mask = I915_USER_INTERRUPT;
1375 }
1376 ring->write_tail = ring_write_tail;
1377 if (INTEL_INFO(dev)->gen >= 6)
1378 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1379 else if (INTEL_INFO(dev)->gen >= 4)
1380 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1381 else if (IS_I830(dev) || IS_845G(dev))
1382 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1383 else
1384 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1385 ring->init = init_render_ring;
1386 ring->cleanup = render_ring_cleanup;
1387
1388
1389 if (!I915_NEED_GFX_HWS(dev)) {
1390 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1391 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1392 }
1393
1394 return intel_init_ring_buffer(dev, ring);
1395 }
1396
1397 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1398 {
1399 drm_i915_private_t *dev_priv = dev->dev_private;
1400 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1401
1402 ring->name = "render ring";
1403 ring->id = RCS;
1404 ring->mmio_base = RENDER_RING_BASE;
1405
1406 if (INTEL_INFO(dev)->gen >= 6) {
1407 /* non-kms not supported on gen6+ */
1408 return -ENODEV;
1409 }
1410
1411 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1412 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1413 * the special gen5 functions. */
1414 ring->add_request = i9xx_add_request;
1415 if (INTEL_INFO(dev)->gen < 4)
1416 ring->flush = gen2_render_ring_flush;
1417 else
1418 ring->flush = gen4_render_ring_flush;
1419 ring->get_seqno = ring_get_seqno;
1420 if (IS_GEN2(dev)) {
1421 ring->irq_get = i8xx_ring_get_irq;
1422 ring->irq_put = i8xx_ring_put_irq;
1423 } else {
1424 ring->irq_get = i9xx_ring_get_irq;
1425 ring->irq_put = i9xx_ring_put_irq;
1426 }
1427 ring->irq_enable_mask = I915_USER_INTERRUPT;
1428 ring->write_tail = ring_write_tail;
1429 if (INTEL_INFO(dev)->gen >= 4)
1430 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1431 else if (IS_I830(dev) || IS_845G(dev))
1432 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1433 else
1434 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1435 ring->init = init_render_ring;
1436 ring->cleanup = render_ring_cleanup;
1437
1438 if (!I915_NEED_GFX_HWS(dev))
1439 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1440
1441 ring->dev = dev;
1442 INIT_LIST_HEAD(&ring->active_list);
1443 INIT_LIST_HEAD(&ring->request_list);
1444 INIT_LIST_HEAD(&ring->gpu_write_list);
1445
1446 ring->size = size;
1447 ring->effective_size = ring->size;
1448 if (IS_I830(ring->dev))
1449 ring->effective_size -= 128;
1450
1451 ring->virtual_start = ioremap_wc(start, size);
1452 if (ring->virtual_start == NULL) {
1453 DRM_ERROR("can not ioremap virtual address for"
1454 " ring buffer\n");
1455 return -ENOMEM;
1456 }
1457
1458 return 0;
1459 }
1460
1461 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1462 {
1463 drm_i915_private_t *dev_priv = dev->dev_private;
1464 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1465
1466 ring->name = "bsd ring";
1467 ring->id = VCS;
1468
1469 ring->write_tail = ring_write_tail;
1470 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1471 ring->mmio_base = GEN6_BSD_RING_BASE;
1472 /* gen6 bsd needs a special wa for tail updates */
1473 if (IS_GEN6(dev))
1474 ring->write_tail = gen6_bsd_ring_write_tail;
1475 ring->flush = gen6_ring_flush;
1476 ring->add_request = gen6_add_request;
1477 ring->get_seqno = gen6_ring_get_seqno;
1478 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1479 ring->irq_get = gen6_ring_get_irq;
1480 ring->irq_put = gen6_ring_put_irq;
1481 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1482 ring->sync_to = gen6_ring_sync;
1483 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1484 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1485 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1486 ring->signal_mbox[0] = GEN6_RVSYNC;
1487 ring->signal_mbox[1] = GEN6_BVSYNC;
1488 } else {
1489 ring->mmio_base = BSD_RING_BASE;
1490 ring->flush = bsd_ring_flush;
1491 ring->add_request = i9xx_add_request;
1492 ring->get_seqno = ring_get_seqno;
1493 if (IS_GEN5(dev)) {
1494 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1495 ring->irq_get = gen5_ring_get_irq;
1496 ring->irq_put = gen5_ring_put_irq;
1497 } else {
1498 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1499 ring->irq_get = i9xx_ring_get_irq;
1500 ring->irq_put = i9xx_ring_put_irq;
1501 }
1502 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1503 }
1504 ring->init = init_ring_common;
1505
1506
1507 return intel_init_ring_buffer(dev, ring);
1508 }
1509
1510 int intel_init_blt_ring_buffer(struct drm_device *dev)
1511 {
1512 drm_i915_private_t *dev_priv = dev->dev_private;
1513 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1514
1515 ring->name = "blitter ring";
1516 ring->id = BCS;
1517
1518 ring->mmio_base = BLT_RING_BASE;
1519 ring->write_tail = ring_write_tail;
1520 ring->flush = blt_ring_flush;
1521 ring->add_request = gen6_add_request;
1522 ring->get_seqno = gen6_ring_get_seqno;
1523 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1524 ring->irq_get = gen6_ring_get_irq;
1525 ring->irq_put = gen6_ring_put_irq;
1526 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1527 ring->sync_to = gen6_ring_sync;
1528 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1529 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1530 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1531 ring->signal_mbox[0] = GEN6_RBSYNC;
1532 ring->signal_mbox[1] = GEN6_VBSYNC;
1533 ring->init = init_ring_common;
1534
1535 return intel_init_ring_buffer(dev, ring);
1536 }
Linux with added FPC-III support