?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hfs: get rid of hfs_sync_super
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_asic.c
blobf533df5f7d508a671d5f35c505d6af7327569b66
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/console.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "atom.h"
39
40 /*
41 * Registers accessors functions.
42 */
43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
44 {
45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
46 BUG_ON(1);
47 return 0;
48 }
49
50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
51 {
52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
53 reg, v);
54 BUG_ON(1);
55 }
56
57 static void radeon_register_accessor_init(struct radeon_device *rdev)
58 {
59 rdev->mc_rreg = &radeon_invalid_rreg;
60 rdev->mc_wreg = &radeon_invalid_wreg;
61 rdev->pll_rreg = &radeon_invalid_rreg;
62 rdev->pll_wreg = &radeon_invalid_wreg;
63 rdev->pciep_rreg = &radeon_invalid_rreg;
64 rdev->pciep_wreg = &radeon_invalid_wreg;
65
66 /* Don't change order as we are overridding accessor. */
67 if (rdev->family < CHIP_RV515) {
68 rdev->pcie_reg_mask = 0xff;
69 } else {
70 rdev->pcie_reg_mask = 0x7ff;
71 }
72 /* FIXME: not sure here */
73 if (rdev->family <= CHIP_R580) {
74 rdev->pll_rreg = &r100_pll_rreg;
75 rdev->pll_wreg = &r100_pll_wreg;
76 }
77 if (rdev->family >= CHIP_R420) {
78 rdev->mc_rreg = &r420_mc_rreg;
79 rdev->mc_wreg = &r420_mc_wreg;
80 }
81 if (rdev->family >= CHIP_RV515) {
82 rdev->mc_rreg = &rv515_mc_rreg;
83 rdev->mc_wreg = &rv515_mc_wreg;
84 }
85 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
86 rdev->mc_rreg = &rs400_mc_rreg;
87 rdev->mc_wreg = &rs400_mc_wreg;
88 }
89 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
90 rdev->mc_rreg = &rs690_mc_rreg;
91 rdev->mc_wreg = &rs690_mc_wreg;
92 }
93 if (rdev->family == CHIP_RS600) {
94 rdev->mc_rreg = &rs600_mc_rreg;
95 rdev->mc_wreg = &rs600_mc_wreg;
96 }
97 if (rdev->family >= CHIP_R600) {
98 rdev->pciep_rreg = &r600_pciep_rreg;
99 rdev->pciep_wreg = &r600_pciep_wreg;
100 }
101 }
102
103
104 /* helper to disable agp */
105 void radeon_agp_disable(struct radeon_device *rdev)
106 {
107 rdev->flags &= ~RADEON_IS_AGP;
108 if (rdev->family >= CHIP_R600) {
109 DRM_INFO("Forcing AGP to PCIE mode\n");
110 rdev->flags |= RADEON_IS_PCIE;
111 } else if (rdev->family >= CHIP_RV515 ||
112 rdev->family == CHIP_RV380 ||
113 rdev->family == CHIP_RV410 ||
114 rdev->family == CHIP_R423) {
115 DRM_INFO("Forcing AGP to PCIE mode\n");
116 rdev->flags |= RADEON_IS_PCIE;
117 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
118 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
119 } else {
120 DRM_INFO("Forcing AGP to PCI mode\n");
121 rdev->flags |= RADEON_IS_PCI;
122 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
123 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
124 }
125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126 }
127
128 /*
129 * ASIC
130 */
131 static struct radeon_asic r100_asic = {
132 .init = &r100_init,
133 .fini = &r100_fini,
134 .suspend = &r100_suspend,
135 .resume = &r100_resume,
136 .vga_set_state = &r100_vga_set_state,
137 .asic_reset = &r100_asic_reset,
138 .ioctl_wait_idle = NULL,
139 .gui_idle = &r100_gui_idle,
140 .mc_wait_for_idle = &r100_mc_wait_for_idle,
141 .gart = {
142 .tlb_flush = &r100_pci_gart_tlb_flush,
143 .set_page = &r100_pci_gart_set_page,
144 },
145 .ring = {
146 [RADEON_RING_TYPE_GFX_INDEX] = {
147 .ib_execute = &r100_ring_ib_execute,
148 .emit_fence = &r100_fence_ring_emit,
149 .emit_semaphore = &r100_semaphore_ring_emit,
150 .cs_parse = &r100_cs_parse,
151 .ring_start = &r100_ring_start,
152 .ring_test = &r100_ring_test,
153 .ib_test = &r100_ib_test,
154 .is_lockup = &r100_gpu_is_lockup,
155 }
156 },
157 .irq = {
158 .set = &r100_irq_set,
159 .process = &r100_irq_process,
160 },
161 .display = {
162 .bandwidth_update = &r100_bandwidth_update,
163 .get_vblank_counter = &r100_get_vblank_counter,
164 .wait_for_vblank = &r100_wait_for_vblank,
165 },
166 .copy = {
167 .blit = &r100_copy_blit,
168 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
169 .dma = NULL,
170 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
171 .copy = &r100_copy_blit,
172 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
173 },
174 .surface = {
175 .set_reg = r100_set_surface_reg,
176 .clear_reg = r100_clear_surface_reg,
177 },
178 .hpd = {
179 .init = &r100_hpd_init,
180 .fini = &r100_hpd_fini,
181 .sense = &r100_hpd_sense,
182 .set_polarity = &r100_hpd_set_polarity,
183 },
184 .pm = {
185 .misc = &r100_pm_misc,
186 .prepare = &r100_pm_prepare,
187 .finish = &r100_pm_finish,
188 .init_profile = &r100_pm_init_profile,
189 .get_dynpm_state = &r100_pm_get_dynpm_state,
190 .get_engine_clock = &radeon_legacy_get_engine_clock,
191 .set_engine_clock = &radeon_legacy_set_engine_clock,
192 .get_memory_clock = &radeon_legacy_get_memory_clock,
193 .set_memory_clock = NULL,
194 .get_pcie_lanes = NULL,
195 .set_pcie_lanes = NULL,
196 .set_clock_gating = &radeon_legacy_set_clock_gating,
197 },
198 .pflip = {
199 .pre_page_flip = &r100_pre_page_flip,
200 .page_flip = &r100_page_flip,
201 .post_page_flip = &r100_post_page_flip,
202 },
203 };
204
205 static struct radeon_asic r200_asic = {
206 .init = &r100_init,
207 .fini = &r100_fini,
208 .suspend = &r100_suspend,
209 .resume = &r100_resume,
210 .vga_set_state = &r100_vga_set_state,
211 .asic_reset = &r100_asic_reset,
212 .ioctl_wait_idle = NULL,
213 .gui_idle = &r100_gui_idle,
214 .mc_wait_for_idle = &r100_mc_wait_for_idle,
215 .gart = {
216 .tlb_flush = &r100_pci_gart_tlb_flush,
217 .set_page = &r100_pci_gart_set_page,
218 },
219 .ring = {
220 [RADEON_RING_TYPE_GFX_INDEX] = {
221 .ib_execute = &r100_ring_ib_execute,
222 .emit_fence = &r100_fence_ring_emit,
223 .emit_semaphore = &r100_semaphore_ring_emit,
224 .cs_parse = &r100_cs_parse,
225 .ring_start = &r100_ring_start,
226 .ring_test = &r100_ring_test,
227 .ib_test = &r100_ib_test,
228 .is_lockup = &r100_gpu_is_lockup,
229 }
230 },
231 .irq = {
232 .set = &r100_irq_set,
233 .process = &r100_irq_process,
234 },
235 .display = {
236 .bandwidth_update = &r100_bandwidth_update,
237 .get_vblank_counter = &r100_get_vblank_counter,
238 .wait_for_vblank = &r100_wait_for_vblank,
239 },
240 .copy = {
241 .blit = &r100_copy_blit,
242 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
243 .dma = &r200_copy_dma,
244 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
245 .copy = &r100_copy_blit,
246 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
247 },
248 .surface = {
249 .set_reg = r100_set_surface_reg,
250 .clear_reg = r100_clear_surface_reg,
251 },
252 .hpd = {
253 .init = &r100_hpd_init,
254 .fini = &r100_hpd_fini,
255 .sense = &r100_hpd_sense,
256 .set_polarity = &r100_hpd_set_polarity,
257 },
258 .pm = {
259 .misc = &r100_pm_misc,
260 .prepare = &r100_pm_prepare,
261 .finish = &r100_pm_finish,
262 .init_profile = &r100_pm_init_profile,
263 .get_dynpm_state = &r100_pm_get_dynpm_state,
264 .get_engine_clock = &radeon_legacy_get_engine_clock,
265 .set_engine_clock = &radeon_legacy_set_engine_clock,
266 .get_memory_clock = &radeon_legacy_get_memory_clock,
267 .set_memory_clock = NULL,
268 .get_pcie_lanes = NULL,
269 .set_pcie_lanes = NULL,
270 .set_clock_gating = &radeon_legacy_set_clock_gating,
271 },
272 .pflip = {
273 .pre_page_flip = &r100_pre_page_flip,
274 .page_flip = &r100_page_flip,
275 .post_page_flip = &r100_post_page_flip,
276 },
277 };
278
279 static struct radeon_asic r300_asic = {
280 .init = &r300_init,
281 .fini = &r300_fini,
282 .suspend = &r300_suspend,
283 .resume = &r300_resume,
284 .vga_set_state = &r100_vga_set_state,
285 .asic_reset = &r300_asic_reset,
286 .ioctl_wait_idle = NULL,
287 .gui_idle = &r100_gui_idle,
288 .mc_wait_for_idle = &r300_mc_wait_for_idle,
289 .gart = {
290 .tlb_flush = &r100_pci_gart_tlb_flush,
291 .set_page = &r100_pci_gart_set_page,
292 },
293 .ring = {
294 [RADEON_RING_TYPE_GFX_INDEX] = {
295 .ib_execute = &r100_ring_ib_execute,
296 .emit_fence = &r300_fence_ring_emit,
297 .emit_semaphore = &r100_semaphore_ring_emit,
298 .cs_parse = &r300_cs_parse,
299 .ring_start = &r300_ring_start,
300 .ring_test = &r100_ring_test,
301 .ib_test = &r100_ib_test,
302 .is_lockup = &r100_gpu_is_lockup,
303 }
304 },
305 .irq = {
306 .set = &r100_irq_set,
307 .process = &r100_irq_process,
308 },
309 .display = {
310 .bandwidth_update = &r100_bandwidth_update,
311 .get_vblank_counter = &r100_get_vblank_counter,
312 .wait_for_vblank = &r100_wait_for_vblank,
313 },
314 .copy = {
315 .blit = &r100_copy_blit,
316 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
317 .dma = &r200_copy_dma,
318 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
319 .copy = &r100_copy_blit,
320 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
321 },
322 .surface = {
323 .set_reg = r100_set_surface_reg,
324 .clear_reg = r100_clear_surface_reg,
325 },
326 .hpd = {
327 .init = &r100_hpd_init,
328 .fini = &r100_hpd_fini,
329 .sense = &r100_hpd_sense,
330 .set_polarity = &r100_hpd_set_polarity,
331 },
332 .pm = {
333 .misc = &r100_pm_misc,
334 .prepare = &r100_pm_prepare,
335 .finish = &r100_pm_finish,
336 .init_profile = &r100_pm_init_profile,
337 .get_dynpm_state = &r100_pm_get_dynpm_state,
338 .get_engine_clock = &radeon_legacy_get_engine_clock,
339 .set_engine_clock = &radeon_legacy_set_engine_clock,
340 .get_memory_clock = &radeon_legacy_get_memory_clock,
341 .set_memory_clock = NULL,
342 .get_pcie_lanes = &rv370_get_pcie_lanes,
343 .set_pcie_lanes = &rv370_set_pcie_lanes,
344 .set_clock_gating = &radeon_legacy_set_clock_gating,
345 },
346 .pflip = {
347 .pre_page_flip = &r100_pre_page_flip,
348 .page_flip = &r100_page_flip,
349 .post_page_flip = &r100_post_page_flip,
350 },
351 };
352
353 static struct radeon_asic r300_asic_pcie = {
354 .init = &r300_init,
355 .fini = &r300_fini,
356 .suspend = &r300_suspend,
357 .resume = &r300_resume,
358 .vga_set_state = &r100_vga_set_state,
359 .asic_reset = &r300_asic_reset,
360 .ioctl_wait_idle = NULL,
361 .gui_idle = &r100_gui_idle,
362 .mc_wait_for_idle = &r300_mc_wait_for_idle,
363 .gart = {
364 .tlb_flush = &rv370_pcie_gart_tlb_flush,
365 .set_page = &rv370_pcie_gart_set_page,
366 },
367 .ring = {
368 [RADEON_RING_TYPE_GFX_INDEX] = {
369 .ib_execute = &r100_ring_ib_execute,
370 .emit_fence = &r300_fence_ring_emit,
371 .emit_semaphore = &r100_semaphore_ring_emit,
372 .cs_parse = &r300_cs_parse,
373 .ring_start = &r300_ring_start,
374 .ring_test = &r100_ring_test,
375 .ib_test = &r100_ib_test,
376 .is_lockup = &r100_gpu_is_lockup,
377 }
378 },
379 .irq = {
380 .set = &r100_irq_set,
381 .process = &r100_irq_process,
382 },
383 .display = {
384 .bandwidth_update = &r100_bandwidth_update,
385 .get_vblank_counter = &r100_get_vblank_counter,
386 .wait_for_vblank = &r100_wait_for_vblank,
387 },
388 .copy = {
389 .blit = &r100_copy_blit,
390 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
391 .dma = &r200_copy_dma,
392 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
393 .copy = &r100_copy_blit,
394 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
395 },
396 .surface = {
397 .set_reg = r100_set_surface_reg,
398 .clear_reg = r100_clear_surface_reg,
399 },
400 .hpd = {
401 .init = &r100_hpd_init,
402 .fini = &r100_hpd_fini,
403 .sense = &r100_hpd_sense,
404 .set_polarity = &r100_hpd_set_polarity,
405 },
406 .pm = {
407 .misc = &r100_pm_misc,
408 .prepare = &r100_pm_prepare,
409 .finish = &r100_pm_finish,
410 .init_profile = &r100_pm_init_profile,
411 .get_dynpm_state = &r100_pm_get_dynpm_state,
412 .get_engine_clock = &radeon_legacy_get_engine_clock,
413 .set_engine_clock = &radeon_legacy_set_engine_clock,
414 .get_memory_clock = &radeon_legacy_get_memory_clock,
415 .set_memory_clock = NULL,
416 .get_pcie_lanes = &rv370_get_pcie_lanes,
417 .set_pcie_lanes = &rv370_set_pcie_lanes,
418 .set_clock_gating = &radeon_legacy_set_clock_gating,
419 },
420 .pflip = {
421 .pre_page_flip = &r100_pre_page_flip,
422 .page_flip = &r100_page_flip,
423 .post_page_flip = &r100_post_page_flip,
424 },
425 };
426
427 static struct radeon_asic r420_asic = {
428 .init = &r420_init,
429 .fini = &r420_fini,
430 .suspend = &r420_suspend,
431 .resume = &r420_resume,
432 .vga_set_state = &r100_vga_set_state,
433 .asic_reset = &r300_asic_reset,
434 .ioctl_wait_idle = NULL,
435 .gui_idle = &r100_gui_idle,
436 .mc_wait_for_idle = &r300_mc_wait_for_idle,
437 .gart = {
438 .tlb_flush = &rv370_pcie_gart_tlb_flush,
439 .set_page = &rv370_pcie_gart_set_page,
440 },
441 .ring = {
442 [RADEON_RING_TYPE_GFX_INDEX] = {
443 .ib_execute = &r100_ring_ib_execute,
444 .emit_fence = &r300_fence_ring_emit,
445 .emit_semaphore = &r100_semaphore_ring_emit,
446 .cs_parse = &r300_cs_parse,
447 .ring_start = &r300_ring_start,
448 .ring_test = &r100_ring_test,
449 .ib_test = &r100_ib_test,
450 .is_lockup = &r100_gpu_is_lockup,
451 }
452 },
453 .irq = {
454 .set = &r100_irq_set,
455 .process = &r100_irq_process,
456 },
457 .display = {
458 .bandwidth_update = &r100_bandwidth_update,
459 .get_vblank_counter = &r100_get_vblank_counter,
460 .wait_for_vblank = &r100_wait_for_vblank,
461 },
462 .copy = {
463 .blit = &r100_copy_blit,
464 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
465 .dma = &r200_copy_dma,
466 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
467 .copy = &r100_copy_blit,
468 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
469 },
470 .surface = {
471 .set_reg = r100_set_surface_reg,
472 .clear_reg = r100_clear_surface_reg,
473 },
474 .hpd = {
475 .init = &r100_hpd_init,
476 .fini = &r100_hpd_fini,
477 .sense = &r100_hpd_sense,
478 .set_polarity = &r100_hpd_set_polarity,
479 },
480 .pm = {
481 .misc = &r100_pm_misc,
482 .prepare = &r100_pm_prepare,
483 .finish = &r100_pm_finish,
484 .init_profile = &r420_pm_init_profile,
485 .get_dynpm_state = &r100_pm_get_dynpm_state,
486 .get_engine_clock = &radeon_atom_get_engine_clock,
487 .set_engine_clock = &radeon_atom_set_engine_clock,
488 .get_memory_clock = &radeon_atom_get_memory_clock,
489 .set_memory_clock = &radeon_atom_set_memory_clock,
490 .get_pcie_lanes = &rv370_get_pcie_lanes,
491 .set_pcie_lanes = &rv370_set_pcie_lanes,
492 .set_clock_gating = &radeon_atom_set_clock_gating,
493 },
494 .pflip = {
495 .pre_page_flip = &r100_pre_page_flip,
496 .page_flip = &r100_page_flip,
497 .post_page_flip = &r100_post_page_flip,
498 },
499 };
500
501 static struct radeon_asic rs400_asic = {
502 .init = &rs400_init,
503 .fini = &rs400_fini,
504 .suspend = &rs400_suspend,
505 .resume = &rs400_resume,
506 .vga_set_state = &r100_vga_set_state,
507 .asic_reset = &r300_asic_reset,
508 .ioctl_wait_idle = NULL,
509 .gui_idle = &r100_gui_idle,
510 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
511 .gart = {
512 .tlb_flush = &rs400_gart_tlb_flush,
513 .set_page = &rs400_gart_set_page,
514 },
515 .ring = {
516 [RADEON_RING_TYPE_GFX_INDEX] = {
517 .ib_execute = &r100_ring_ib_execute,
518 .emit_fence = &r300_fence_ring_emit,
519 .emit_semaphore = &r100_semaphore_ring_emit,
520 .cs_parse = &r300_cs_parse,
521 .ring_start = &r300_ring_start,
522 .ring_test = &r100_ring_test,
523 .ib_test = &r100_ib_test,
524 .is_lockup = &r100_gpu_is_lockup,
525 }
526 },
527 .irq = {
528 .set = &r100_irq_set,
529 .process = &r100_irq_process,
530 },
531 .display = {
532 .bandwidth_update = &r100_bandwidth_update,
533 .get_vblank_counter = &r100_get_vblank_counter,
534 .wait_for_vblank = &r100_wait_for_vblank,
535 },
536 .copy = {
537 .blit = &r100_copy_blit,
538 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
539 .dma = &r200_copy_dma,
540 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
541 .copy = &r100_copy_blit,
542 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
543 },
544 .surface = {
545 .set_reg = r100_set_surface_reg,
546 .clear_reg = r100_clear_surface_reg,
547 },
548 .hpd = {
549 .init = &r100_hpd_init,
550 .fini = &r100_hpd_fini,
551 .sense = &r100_hpd_sense,
552 .set_polarity = &r100_hpd_set_polarity,
553 },
554 .pm = {
555 .misc = &r100_pm_misc,
556 .prepare = &r100_pm_prepare,
557 .finish = &r100_pm_finish,
558 .init_profile = &r100_pm_init_profile,
559 .get_dynpm_state = &r100_pm_get_dynpm_state,
560 .get_engine_clock = &radeon_legacy_get_engine_clock,
561 .set_engine_clock = &radeon_legacy_set_engine_clock,
562 .get_memory_clock = &radeon_legacy_get_memory_clock,
563 .set_memory_clock = NULL,
564 .get_pcie_lanes = NULL,
565 .set_pcie_lanes = NULL,
566 .set_clock_gating = &radeon_legacy_set_clock_gating,
567 },
568 .pflip = {
569 .pre_page_flip = &r100_pre_page_flip,
570 .page_flip = &r100_page_flip,
571 .post_page_flip = &r100_post_page_flip,
572 },
573 };
574
575 static struct radeon_asic rs600_asic = {
576 .init = &rs600_init,
577 .fini = &rs600_fini,
578 .suspend = &rs600_suspend,
579 .resume = &rs600_resume,
580 .vga_set_state = &r100_vga_set_state,
581 .asic_reset = &rs600_asic_reset,
582 .ioctl_wait_idle = NULL,
583 .gui_idle = &r100_gui_idle,
584 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
585 .gart = {
586 .tlb_flush = &rs600_gart_tlb_flush,
587 .set_page = &rs600_gart_set_page,
588 },
589 .ring = {
590 [RADEON_RING_TYPE_GFX_INDEX] = {
591 .ib_execute = &r100_ring_ib_execute,
592 .emit_fence = &r300_fence_ring_emit,
593 .emit_semaphore = &r100_semaphore_ring_emit,
594 .cs_parse = &r300_cs_parse,
595 .ring_start = &r300_ring_start,
596 .ring_test = &r100_ring_test,
597 .ib_test = &r100_ib_test,
598 .is_lockup = &r100_gpu_is_lockup,
599 }
600 },
601 .irq = {
602 .set = &rs600_irq_set,
603 .process = &rs600_irq_process,
604 },
605 .display = {
606 .bandwidth_update = &rs600_bandwidth_update,
607 .get_vblank_counter = &rs600_get_vblank_counter,
608 .wait_for_vblank = &avivo_wait_for_vblank,
609 },
610 .copy = {
611 .blit = &r100_copy_blit,
612 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
613 .dma = &r200_copy_dma,
614 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
615 .copy = &r100_copy_blit,
616 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
617 },
618 .surface = {
619 .set_reg = r100_set_surface_reg,
620 .clear_reg = r100_clear_surface_reg,
621 },
622 .hpd = {
623 .init = &rs600_hpd_init,
624 .fini = &rs600_hpd_fini,
625 .sense = &rs600_hpd_sense,
626 .set_polarity = &rs600_hpd_set_polarity,
627 },
628 .pm = {
629 .misc = &rs600_pm_misc,
630 .prepare = &rs600_pm_prepare,
631 .finish = &rs600_pm_finish,
632 .init_profile = &r420_pm_init_profile,
633 .get_dynpm_state = &r100_pm_get_dynpm_state,
634 .get_engine_clock = &radeon_atom_get_engine_clock,
635 .set_engine_clock = &radeon_atom_set_engine_clock,
636 .get_memory_clock = &radeon_atom_get_memory_clock,
637 .set_memory_clock = &radeon_atom_set_memory_clock,
638 .get_pcie_lanes = NULL,
639 .set_pcie_lanes = NULL,
640 .set_clock_gating = &radeon_atom_set_clock_gating,
641 },
642 .pflip = {
643 .pre_page_flip = &rs600_pre_page_flip,
644 .page_flip = &rs600_page_flip,
645 .post_page_flip = &rs600_post_page_flip,
646 },
647 };
648
649 static struct radeon_asic rs690_asic = {
650 .init = &rs690_init,
651 .fini = &rs690_fini,
652 .suspend = &rs690_suspend,
653 .resume = &rs690_resume,
654 .vga_set_state = &r100_vga_set_state,
655 .asic_reset = &rs600_asic_reset,
656 .ioctl_wait_idle = NULL,
657 .gui_idle = &r100_gui_idle,
658 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
659 .gart = {
660 .tlb_flush = &rs400_gart_tlb_flush,
661 .set_page = &rs400_gart_set_page,
662 },
663 .ring = {
664 [RADEON_RING_TYPE_GFX_INDEX] = {
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
668 .cs_parse = &r300_cs_parse,
669 .ring_start = &r300_ring_start,
670 .ring_test = &r100_ring_test,
671 .ib_test = &r100_ib_test,
672 .is_lockup = &r100_gpu_is_lockup,
673 }
674 },
675 .irq = {
676 .set = &rs600_irq_set,
677 .process = &rs600_irq_process,
678 },
679 .display = {
680 .get_vblank_counter = &rs600_get_vblank_counter,
681 .bandwidth_update = &rs690_bandwidth_update,
682 .wait_for_vblank = &avivo_wait_for_vblank,
683 },
684 .copy = {
685 .blit = &r100_copy_blit,
686 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
687 .dma = &r200_copy_dma,
688 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
689 .copy = &r200_copy_dma,
690 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
691 },
692 .surface = {
693 .set_reg = r100_set_surface_reg,
694 .clear_reg = r100_clear_surface_reg,
695 },
696 .hpd = {
697 .init = &rs600_hpd_init,
698 .fini = &rs600_hpd_fini,
699 .sense = &rs600_hpd_sense,
700 .set_polarity = &rs600_hpd_set_polarity,
701 },
702 .pm = {
703 .misc = &rs600_pm_misc,
704 .prepare = &rs600_pm_prepare,
705 .finish = &rs600_pm_finish,
706 .init_profile = &r420_pm_init_profile,
707 .get_dynpm_state = &r100_pm_get_dynpm_state,
708 .get_engine_clock = &radeon_atom_get_engine_clock,
709 .set_engine_clock = &radeon_atom_set_engine_clock,
710 .get_memory_clock = &radeon_atom_get_memory_clock,
711 .set_memory_clock = &radeon_atom_set_memory_clock,
712 .get_pcie_lanes = NULL,
713 .set_pcie_lanes = NULL,
714 .set_clock_gating = &radeon_atom_set_clock_gating,
715 },
716 .pflip = {
717 .pre_page_flip = &rs600_pre_page_flip,
718 .page_flip = &rs600_page_flip,
719 .post_page_flip = &rs600_post_page_flip,
720 },
721 };
722
723 static struct radeon_asic rv515_asic = {
724 .init = &rv515_init,
725 .fini = &rv515_fini,
726 .suspend = &rv515_suspend,
727 .resume = &rv515_resume,
728 .vga_set_state = &r100_vga_set_state,
729 .asic_reset = &rs600_asic_reset,
730 .ioctl_wait_idle = NULL,
731 .gui_idle = &r100_gui_idle,
732 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
733 .gart = {
734 .tlb_flush = &rv370_pcie_gart_tlb_flush,
735 .set_page = &rv370_pcie_gart_set_page,
736 },
737 .ring = {
738 [RADEON_RING_TYPE_GFX_INDEX] = {
739 .ib_execute = &r100_ring_ib_execute,
740 .emit_fence = &r300_fence_ring_emit,
741 .emit_semaphore = &r100_semaphore_ring_emit,
742 .cs_parse = &r300_cs_parse,
743 .ring_start = &rv515_ring_start,
744 .ring_test = &r100_ring_test,
745 .ib_test = &r100_ib_test,
746 .is_lockup = &r100_gpu_is_lockup,
747 }
748 },
749 .irq = {
750 .set = &rs600_irq_set,
751 .process = &rs600_irq_process,
752 },
753 .display = {
754 .get_vblank_counter = &rs600_get_vblank_counter,
755 .bandwidth_update = &rv515_bandwidth_update,
756 .wait_for_vblank = &avivo_wait_for_vblank,
757 },
758 .copy = {
759 .blit = &r100_copy_blit,
760 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
761 .dma = &r200_copy_dma,
762 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
763 .copy = &r100_copy_blit,
764 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
765 },
766 .surface = {
767 .set_reg = r100_set_surface_reg,
768 .clear_reg = r100_clear_surface_reg,
769 },
770 .hpd = {
771 .init = &rs600_hpd_init,
772 .fini = &rs600_hpd_fini,
773 .sense = &rs600_hpd_sense,
774 .set_polarity = &rs600_hpd_set_polarity,
775 },
776 .pm = {
777 .misc = &rs600_pm_misc,
778 .prepare = &rs600_pm_prepare,
779 .finish = &rs600_pm_finish,
780 .init_profile = &r420_pm_init_profile,
781 .get_dynpm_state = &r100_pm_get_dynpm_state,
782 .get_engine_clock = &radeon_atom_get_engine_clock,
783 .set_engine_clock = &radeon_atom_set_engine_clock,
784 .get_memory_clock = &radeon_atom_get_memory_clock,
785 .set_memory_clock = &radeon_atom_set_memory_clock,
786 .get_pcie_lanes = &rv370_get_pcie_lanes,
787 .set_pcie_lanes = &rv370_set_pcie_lanes,
788 .set_clock_gating = &radeon_atom_set_clock_gating,
789 },
790 .pflip = {
791 .pre_page_flip = &rs600_pre_page_flip,
792 .page_flip = &rs600_page_flip,
793 .post_page_flip = &rs600_post_page_flip,
794 },
795 };
796
797 static struct radeon_asic r520_asic = {
798 .init = &r520_init,
799 .fini = &rv515_fini,
800 .suspend = &rv515_suspend,
801 .resume = &r520_resume,
802 .vga_set_state = &r100_vga_set_state,
803 .asic_reset = &rs600_asic_reset,
804 .ioctl_wait_idle = NULL,
805 .gui_idle = &r100_gui_idle,
806 .mc_wait_for_idle = &r520_mc_wait_for_idle,
807 .gart = {
808 .tlb_flush = &rv370_pcie_gart_tlb_flush,
809 .set_page = &rv370_pcie_gart_set_page,
810 },
811 .ring = {
812 [RADEON_RING_TYPE_GFX_INDEX] = {
813 .ib_execute = &r100_ring_ib_execute,
814 .emit_fence = &r300_fence_ring_emit,
815 .emit_semaphore = &r100_semaphore_ring_emit,
816 .cs_parse = &r300_cs_parse,
817 .ring_start = &rv515_ring_start,
818 .ring_test = &r100_ring_test,
819 .ib_test = &r100_ib_test,
820 .is_lockup = &r100_gpu_is_lockup,
821 }
822 },
823 .irq = {
824 .set = &rs600_irq_set,
825 .process = &rs600_irq_process,
826 },
827 .display = {
828 .bandwidth_update = &rv515_bandwidth_update,
829 .get_vblank_counter = &rs600_get_vblank_counter,
830 .wait_for_vblank = &avivo_wait_for_vblank,
831 },
832 .copy = {
833 .blit = &r100_copy_blit,
834 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
835 .dma = &r200_copy_dma,
836 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
837 .copy = &r100_copy_blit,
838 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
839 },
840 .surface = {
841 .set_reg = r100_set_surface_reg,
842 .clear_reg = r100_clear_surface_reg,
843 },
844 .hpd = {
845 .init = &rs600_hpd_init,
846 .fini = &rs600_hpd_fini,
847 .sense = &rs600_hpd_sense,
848 .set_polarity = &rs600_hpd_set_polarity,
849 },
850 .pm = {
851 .misc = &rs600_pm_misc,
852 .prepare = &rs600_pm_prepare,
853 .finish = &rs600_pm_finish,
854 .init_profile = &r420_pm_init_profile,
855 .get_dynpm_state = &r100_pm_get_dynpm_state,
856 .get_engine_clock = &radeon_atom_get_engine_clock,
857 .set_engine_clock = &radeon_atom_set_engine_clock,
858 .get_memory_clock = &radeon_atom_get_memory_clock,
859 .set_memory_clock = &radeon_atom_set_memory_clock,
860 .get_pcie_lanes = &rv370_get_pcie_lanes,
861 .set_pcie_lanes = &rv370_set_pcie_lanes,
862 .set_clock_gating = &radeon_atom_set_clock_gating,
863 },
864 .pflip = {
865 .pre_page_flip = &rs600_pre_page_flip,
866 .page_flip = &rs600_page_flip,
867 .post_page_flip = &rs600_post_page_flip,
868 },
869 };
870
871 static struct radeon_asic r600_asic = {
872 .init = &r600_init,
873 .fini = &r600_fini,
874 .suspend = &r600_suspend,
875 .resume = &r600_resume,
876 .vga_set_state = &r600_vga_set_state,
877 .asic_reset = &r600_asic_reset,
878 .ioctl_wait_idle = r600_ioctl_wait_idle,
879 .gui_idle = &r600_gui_idle,
880 .mc_wait_for_idle = &r600_mc_wait_for_idle,
881 .gart = {
882 .tlb_flush = &r600_pcie_gart_tlb_flush,
883 .set_page = &rs600_gart_set_page,
884 },
885 .ring = {
886 [RADEON_RING_TYPE_GFX_INDEX] = {
887 .ib_execute = &r600_ring_ib_execute,
888 .emit_fence = &r600_fence_ring_emit,
889 .emit_semaphore = &r600_semaphore_ring_emit,
890 .cs_parse = &r600_cs_parse,
891 .ring_test = &r600_ring_test,
892 .ib_test = &r600_ib_test,
893 .is_lockup = &r600_gpu_is_lockup,
894 }
895 },
896 .irq = {
897 .set = &r600_irq_set,
898 .process = &r600_irq_process,
899 },
900 .display = {
901 .bandwidth_update = &rv515_bandwidth_update,
902 .get_vblank_counter = &rs600_get_vblank_counter,
903 .wait_for_vblank = &avivo_wait_for_vblank,
904 },
905 .copy = {
906 .blit = &r600_copy_blit,
907 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
908 .dma = NULL,
909 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
910 .copy = &r600_copy_blit,
911 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
912 },
913 .surface = {
914 .set_reg = r600_set_surface_reg,
915 .clear_reg = r600_clear_surface_reg,
916 },
917 .hpd = {
918 .init = &r600_hpd_init,
919 .fini = &r600_hpd_fini,
920 .sense = &r600_hpd_sense,
921 .set_polarity = &r600_hpd_set_polarity,
922 },
923 .pm = {
924 .misc = &r600_pm_misc,
925 .prepare = &rs600_pm_prepare,
926 .finish = &rs600_pm_finish,
927 .init_profile = &r600_pm_init_profile,
928 .get_dynpm_state = &r600_pm_get_dynpm_state,
929 .get_engine_clock = &radeon_atom_get_engine_clock,
930 .set_engine_clock = &radeon_atom_set_engine_clock,
931 .get_memory_clock = &radeon_atom_get_memory_clock,
932 .set_memory_clock = &radeon_atom_set_memory_clock,
933 .get_pcie_lanes = &r600_get_pcie_lanes,
934 .set_pcie_lanes = &r600_set_pcie_lanes,
935 .set_clock_gating = NULL,
936 },
937 .pflip = {
938 .pre_page_flip = &rs600_pre_page_flip,
939 .page_flip = &rs600_page_flip,
940 .post_page_flip = &rs600_post_page_flip,
941 },
942 };
943
944 static struct radeon_asic rs780_asic = {
945 .init = &r600_init,
946 .fini = &r600_fini,
947 .suspend = &r600_suspend,
948 .resume = &r600_resume,
949 .vga_set_state = &r600_vga_set_state,
950 .asic_reset = &r600_asic_reset,
951 .ioctl_wait_idle = r600_ioctl_wait_idle,
952 .gui_idle = &r600_gui_idle,
953 .mc_wait_for_idle = &r600_mc_wait_for_idle,
954 .gart = {
955 .tlb_flush = &r600_pcie_gart_tlb_flush,
956 .set_page = &rs600_gart_set_page,
957 },
958 .ring = {
959 [RADEON_RING_TYPE_GFX_INDEX] = {
960 .ib_execute = &r600_ring_ib_execute,
961 .emit_fence = &r600_fence_ring_emit,
962 .emit_semaphore = &r600_semaphore_ring_emit,
963 .cs_parse = &r600_cs_parse,
964 .ring_test = &r600_ring_test,
965 .ib_test = &r600_ib_test,
966 .is_lockup = &r600_gpu_is_lockup,
967 }
968 },
969 .irq = {
970 .set = &r600_irq_set,
971 .process = &r600_irq_process,
972 },
973 .display = {
974 .bandwidth_update = &rs690_bandwidth_update,
975 .get_vblank_counter = &rs600_get_vblank_counter,
976 .wait_for_vblank = &avivo_wait_for_vblank,
977 },
978 .copy = {
979 .blit = &r600_copy_blit,
980 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
981 .dma = NULL,
982 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
983 .copy = &r600_copy_blit,
984 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
985 },
986 .surface = {
987 .set_reg = r600_set_surface_reg,
988 .clear_reg = r600_clear_surface_reg,
989 },
990 .hpd = {
991 .init = &r600_hpd_init,
992 .fini = &r600_hpd_fini,
993 .sense = &r600_hpd_sense,
994 .set_polarity = &r600_hpd_set_polarity,
995 },
996 .pm = {
997 .misc = &r600_pm_misc,
998 .prepare = &rs600_pm_prepare,
999 .finish = &rs600_pm_finish,
1000 .init_profile = &rs780_pm_init_profile,
1001 .get_dynpm_state = &r600_pm_get_dynpm_state,
1002 .get_engine_clock = &radeon_atom_get_engine_clock,
1003 .set_engine_clock = &radeon_atom_set_engine_clock,
1004 .get_memory_clock = NULL,
1005 .set_memory_clock = NULL,
1006 .get_pcie_lanes = NULL,
1007 .set_pcie_lanes = NULL,
1008 .set_clock_gating = NULL,
1009 },
1010 .pflip = {
1011 .pre_page_flip = &rs600_pre_page_flip,
1012 .page_flip = &rs600_page_flip,
1013 .post_page_flip = &rs600_post_page_flip,
1014 },
1015 };
1016
1017 static struct radeon_asic rv770_asic = {
1018 .init = &rv770_init,
1019 .fini = &rv770_fini,
1020 .suspend = &rv770_suspend,
1021 .resume = &rv770_resume,
1022 .asic_reset = &r600_asic_reset,
1023 .vga_set_state = &r600_vga_set_state,
1024 .ioctl_wait_idle = r600_ioctl_wait_idle,
1025 .gui_idle = &r600_gui_idle,
1026 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1027 .gart = {
1028 .tlb_flush = &r600_pcie_gart_tlb_flush,
1029 .set_page = &rs600_gart_set_page,
1030 },
1031 .ring = {
1032 [RADEON_RING_TYPE_GFX_INDEX] = {
1033 .ib_execute = &r600_ring_ib_execute,
1034 .emit_fence = &r600_fence_ring_emit,
1035 .emit_semaphore = &r600_semaphore_ring_emit,
1036 .cs_parse = &r600_cs_parse,
1037 .ring_test = &r600_ring_test,
1038 .ib_test = &r600_ib_test,
1039 .is_lockup = &r600_gpu_is_lockup,
1040 }
1041 },
1042 .irq = {
1043 .set = &r600_irq_set,
1044 .process = &r600_irq_process,
1045 },
1046 .display = {
1047 .bandwidth_update = &rv515_bandwidth_update,
1048 .get_vblank_counter = &rs600_get_vblank_counter,
1049 .wait_for_vblank = &avivo_wait_for_vblank,
1050 },
1051 .copy = {
1052 .blit = &r600_copy_blit,
1053 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1054 .dma = NULL,
1055 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1056 .copy = &r600_copy_blit,
1057 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1058 },
1059 .surface = {
1060 .set_reg = r600_set_surface_reg,
1061 .clear_reg = r600_clear_surface_reg,
1062 },
1063 .hpd = {
1064 .init = &r600_hpd_init,
1065 .fini = &r600_hpd_fini,
1066 .sense = &r600_hpd_sense,
1067 .set_polarity = &r600_hpd_set_polarity,
1068 },
1069 .pm = {
1070 .misc = &rv770_pm_misc,
1071 .prepare = &rs600_pm_prepare,
1072 .finish = &rs600_pm_finish,
1073 .init_profile = &r600_pm_init_profile,
1074 .get_dynpm_state = &r600_pm_get_dynpm_state,
1075 .get_engine_clock = &radeon_atom_get_engine_clock,
1076 .set_engine_clock = &radeon_atom_set_engine_clock,
1077 .get_memory_clock = &radeon_atom_get_memory_clock,
1078 .set_memory_clock = &radeon_atom_set_memory_clock,
1079 .get_pcie_lanes = &r600_get_pcie_lanes,
1080 .set_pcie_lanes = &r600_set_pcie_lanes,
1081 .set_clock_gating = &radeon_atom_set_clock_gating,
1082 },
1083 .pflip = {
1084 .pre_page_flip = &rs600_pre_page_flip,
1085 .page_flip = &rv770_page_flip,
1086 .post_page_flip = &rs600_post_page_flip,
1087 },
1088 };
1089
1090 static struct radeon_asic evergreen_asic = {
1091 .init = &evergreen_init,
1092 .fini = &evergreen_fini,
1093 .suspend = &evergreen_suspend,
1094 .resume = &evergreen_resume,
1095 .asic_reset = &evergreen_asic_reset,
1096 .vga_set_state = &r600_vga_set_state,
1097 .ioctl_wait_idle = r600_ioctl_wait_idle,
1098 .gui_idle = &r600_gui_idle,
1099 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1100 .gart = {
1101 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1102 .set_page = &rs600_gart_set_page,
1103 },
1104 .ring = {
1105 [RADEON_RING_TYPE_GFX_INDEX] = {
1106 .ib_execute = &evergreen_ring_ib_execute,
1107 .emit_fence = &r600_fence_ring_emit,
1108 .emit_semaphore = &r600_semaphore_ring_emit,
1109 .cs_parse = &evergreen_cs_parse,
1110 .ring_test = &r600_ring_test,
1111 .ib_test = &r600_ib_test,
1112 .is_lockup = &evergreen_gpu_is_lockup,
1113 }
1114 },
1115 .irq = {
1116 .set = &evergreen_irq_set,
1117 .process = &evergreen_irq_process,
1118 },
1119 .display = {
1120 .bandwidth_update = &evergreen_bandwidth_update,
1121 .get_vblank_counter = &evergreen_get_vblank_counter,
1122 .wait_for_vblank = &dce4_wait_for_vblank,
1123 },
1124 .copy = {
1125 .blit = &r600_copy_blit,
1126 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1127 .dma = NULL,
1128 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1129 .copy = &r600_copy_blit,
1130 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1131 },
1132 .surface = {
1133 .set_reg = r600_set_surface_reg,
1134 .clear_reg = r600_clear_surface_reg,
1135 },
1136 .hpd = {
1137 .init = &evergreen_hpd_init,
1138 .fini = &evergreen_hpd_fini,
1139 .sense = &evergreen_hpd_sense,
1140 .set_polarity = &evergreen_hpd_set_polarity,
1141 },
1142 .pm = {
1143 .misc = &evergreen_pm_misc,
1144 .prepare = &evergreen_pm_prepare,
1145 .finish = &evergreen_pm_finish,
1146 .init_profile = &r600_pm_init_profile,
1147 .get_dynpm_state = &r600_pm_get_dynpm_state,
1148 .get_engine_clock = &radeon_atom_get_engine_clock,
1149 .set_engine_clock = &radeon_atom_set_engine_clock,
1150 .get_memory_clock = &radeon_atom_get_memory_clock,
1151 .set_memory_clock = &radeon_atom_set_memory_clock,
1152 .get_pcie_lanes = &r600_get_pcie_lanes,
1153 .set_pcie_lanes = &r600_set_pcie_lanes,
1154 .set_clock_gating = NULL,
1155 },
1156 .pflip = {
1157 .pre_page_flip = &evergreen_pre_page_flip,
1158 .page_flip = &evergreen_page_flip,
1159 .post_page_flip = &evergreen_post_page_flip,
1160 },
1161 };
1162
1163 static struct radeon_asic sumo_asic = {
1164 .init = &evergreen_init,
1165 .fini = &evergreen_fini,
1166 .suspend = &evergreen_suspend,
1167 .resume = &evergreen_resume,
1168 .asic_reset = &evergreen_asic_reset,
1169 .vga_set_state = &r600_vga_set_state,
1170 .ioctl_wait_idle = r600_ioctl_wait_idle,
1171 .gui_idle = &r600_gui_idle,
1172 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1173 .gart = {
1174 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1175 .set_page = &rs600_gart_set_page,
1176 },
1177 .ring = {
1178 [RADEON_RING_TYPE_GFX_INDEX] = {
1179 .ib_execute = &evergreen_ring_ib_execute,
1180 .emit_fence = &r600_fence_ring_emit,
1181 .emit_semaphore = &r600_semaphore_ring_emit,
1182 .cs_parse = &evergreen_cs_parse,
1183 .ring_test = &r600_ring_test,
1184 .ib_test = &r600_ib_test,
1185 .is_lockup = &evergreen_gpu_is_lockup,
1186 },
1187 },
1188 .irq = {
1189 .set = &evergreen_irq_set,
1190 .process = &evergreen_irq_process,
1191 },
1192 .display = {
1193 .bandwidth_update = &evergreen_bandwidth_update,
1194 .get_vblank_counter = &evergreen_get_vblank_counter,
1195 .wait_for_vblank = &dce4_wait_for_vblank,
1196 },
1197 .copy = {
1198 .blit = &r600_copy_blit,
1199 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1200 .dma = NULL,
1201 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1202 .copy = &r600_copy_blit,
1203 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1204 },
1205 .surface = {
1206 .set_reg = r600_set_surface_reg,
1207 .clear_reg = r600_clear_surface_reg,
1208 },
1209 .hpd = {
1210 .init = &evergreen_hpd_init,
1211 .fini = &evergreen_hpd_fini,
1212 .sense = &evergreen_hpd_sense,
1213 .set_polarity = &evergreen_hpd_set_polarity,
1214 },
1215 .pm = {
1216 .misc = &evergreen_pm_misc,
1217 .prepare = &evergreen_pm_prepare,
1218 .finish = &evergreen_pm_finish,
1219 .init_profile = &sumo_pm_init_profile,
1220 .get_dynpm_state = &r600_pm_get_dynpm_state,
1221 .get_engine_clock = &radeon_atom_get_engine_clock,
1222 .set_engine_clock = &radeon_atom_set_engine_clock,
1223 .get_memory_clock = NULL,
1224 .set_memory_clock = NULL,
1225 .get_pcie_lanes = NULL,
1226 .set_pcie_lanes = NULL,
1227 .set_clock_gating = NULL,
1228 },
1229 .pflip = {
1230 .pre_page_flip = &evergreen_pre_page_flip,
1231 .page_flip = &evergreen_page_flip,
1232 .post_page_flip = &evergreen_post_page_flip,
1233 },
1234 };
1235
1236 static struct radeon_asic btc_asic = {
1237 .init = &evergreen_init,
1238 .fini = &evergreen_fini,
1239 .suspend = &evergreen_suspend,
1240 .resume = &evergreen_resume,
1241 .asic_reset = &evergreen_asic_reset,
1242 .vga_set_state = &r600_vga_set_state,
1243 .ioctl_wait_idle = r600_ioctl_wait_idle,
1244 .gui_idle = &r600_gui_idle,
1245 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1246 .gart = {
1247 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1248 .set_page = &rs600_gart_set_page,
1249 },
1250 .ring = {
1251 [RADEON_RING_TYPE_GFX_INDEX] = {
1252 .ib_execute = &evergreen_ring_ib_execute,
1253 .emit_fence = &r600_fence_ring_emit,
1254 .emit_semaphore = &r600_semaphore_ring_emit,
1255 .cs_parse = &evergreen_cs_parse,
1256 .ring_test = &r600_ring_test,
1257 .ib_test = &r600_ib_test,
1258 .is_lockup = &evergreen_gpu_is_lockup,
1259 }
1260 },
1261 .irq = {
1262 .set = &evergreen_irq_set,
1263 .process = &evergreen_irq_process,
1264 },
1265 .display = {
1266 .bandwidth_update = &evergreen_bandwidth_update,
1267 .get_vblank_counter = &evergreen_get_vblank_counter,
1268 .wait_for_vblank = &dce4_wait_for_vblank,
1269 },
1270 .copy = {
1271 .blit = &r600_copy_blit,
1272 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1273 .dma = NULL,
1274 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1275 .copy = &r600_copy_blit,
1276 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1277 },
1278 .surface = {
1279 .set_reg = r600_set_surface_reg,
1280 .clear_reg = r600_clear_surface_reg,
1281 },
1282 .hpd = {
1283 .init = &evergreen_hpd_init,
1284 .fini = &evergreen_hpd_fini,
1285 .sense = &evergreen_hpd_sense,
1286 .set_polarity = &evergreen_hpd_set_polarity,
1287 },
1288 .pm = {
1289 .misc = &evergreen_pm_misc,
1290 .prepare = &evergreen_pm_prepare,
1291 .finish = &evergreen_pm_finish,
1292 .init_profile = &r600_pm_init_profile,
1293 .get_dynpm_state = &r600_pm_get_dynpm_state,
1294 .get_engine_clock = &radeon_atom_get_engine_clock,
1295 .set_engine_clock = &radeon_atom_set_engine_clock,
1296 .get_memory_clock = &radeon_atom_get_memory_clock,
1297 .set_memory_clock = &radeon_atom_set_memory_clock,
1298 .get_pcie_lanes = NULL,
1299 .set_pcie_lanes = NULL,
1300 .set_clock_gating = NULL,
1301 },
1302 .pflip = {
1303 .pre_page_flip = &evergreen_pre_page_flip,
1304 .page_flip = &evergreen_page_flip,
1305 .post_page_flip = &evergreen_post_page_flip,
1306 },
1307 };
1308
1309 static const struct radeon_vm_funcs cayman_vm_funcs = {
1310 .init = &cayman_vm_init,
1311 .fini = &cayman_vm_fini,
1312 .bind = &cayman_vm_bind,
1313 .unbind = &cayman_vm_unbind,
1314 .tlb_flush = &cayman_vm_tlb_flush,
1315 .page_flags = &cayman_vm_page_flags,
1316 .set_page = &cayman_vm_set_page,
1317 };
1318
1319 static struct radeon_asic cayman_asic = {
1320 .init = &cayman_init,
1321 .fini = &cayman_fini,
1322 .suspend = &cayman_suspend,
1323 .resume = &cayman_resume,
1324 .asic_reset = &cayman_asic_reset,
1325 .vga_set_state = &r600_vga_set_state,
1326 .ioctl_wait_idle = r600_ioctl_wait_idle,
1327 .gui_idle = &r600_gui_idle,
1328 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1329 .gart = {
1330 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1331 .set_page = &rs600_gart_set_page,
1332 },
1333 .ring = {
1334 [RADEON_RING_TYPE_GFX_INDEX] = {
1335 .ib_execute = &cayman_ring_ib_execute,
1336 .ib_parse = &evergreen_ib_parse,
1337 .emit_fence = &cayman_fence_ring_emit,
1338 .emit_semaphore = &r600_semaphore_ring_emit,
1339 .cs_parse = &evergreen_cs_parse,
1340 .ring_test = &r600_ring_test,
1341 .ib_test = &r600_ib_test,
1342 .is_lockup = &evergreen_gpu_is_lockup,
1343 },
1344 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1345 .ib_execute = &cayman_ring_ib_execute,
1346 .ib_parse = &evergreen_ib_parse,
1347 .emit_fence = &cayman_fence_ring_emit,
1348 .emit_semaphore = &r600_semaphore_ring_emit,
1349 .cs_parse = &evergreen_cs_parse,
1350 .ring_test = &r600_ring_test,
1351 .ib_test = &r600_ib_test,
1352 .is_lockup = &evergreen_gpu_is_lockup,
1353 },
1354 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1355 .ib_execute = &cayman_ring_ib_execute,
1356 .ib_parse = &evergreen_ib_parse,
1357 .emit_fence = &cayman_fence_ring_emit,
1358 .emit_semaphore = &r600_semaphore_ring_emit,
1359 .cs_parse = &evergreen_cs_parse,
1360 .ring_test = &r600_ring_test,
1361 .ib_test = &r600_ib_test,
1362 .is_lockup = &evergreen_gpu_is_lockup,
1363 }
1364 },
1365 .irq = {
1366 .set = &evergreen_irq_set,
1367 .process = &evergreen_irq_process,
1368 },
1369 .display = {
1370 .bandwidth_update = &evergreen_bandwidth_update,
1371 .get_vblank_counter = &evergreen_get_vblank_counter,
1372 .wait_for_vblank = &dce4_wait_for_vblank,
1373 },
1374 .copy = {
1375 .blit = &r600_copy_blit,
1376 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1377 .dma = NULL,
1378 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1379 .copy = &r600_copy_blit,
1380 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1381 },
1382 .surface = {
1383 .set_reg = r600_set_surface_reg,
1384 .clear_reg = r600_clear_surface_reg,
1385 },
1386 .hpd = {
1387 .init = &evergreen_hpd_init,
1388 .fini = &evergreen_hpd_fini,
1389 .sense = &evergreen_hpd_sense,
1390 .set_polarity = &evergreen_hpd_set_polarity,
1391 },
1392 .pm = {
1393 .misc = &evergreen_pm_misc,
1394 .prepare = &evergreen_pm_prepare,
1395 .finish = &evergreen_pm_finish,
1396 .init_profile = &r600_pm_init_profile,
1397 .get_dynpm_state = &r600_pm_get_dynpm_state,
1398 .get_engine_clock = &radeon_atom_get_engine_clock,
1399 .set_engine_clock = &radeon_atom_set_engine_clock,
1400 .get_memory_clock = &radeon_atom_get_memory_clock,
1401 .set_memory_clock = &radeon_atom_set_memory_clock,
1402 .get_pcie_lanes = NULL,
1403 .set_pcie_lanes = NULL,
1404 .set_clock_gating = NULL,
1405 },
1406 .pflip = {
1407 .pre_page_flip = &evergreen_pre_page_flip,
1408 .page_flip = &evergreen_page_flip,
1409 .post_page_flip = &evergreen_post_page_flip,
1410 },
1411 };
1412
1413 static struct radeon_asic trinity_asic = {
1414 .init = &cayman_init,
1415 .fini = &cayman_fini,
1416 .suspend = &cayman_suspend,
1417 .resume = &cayman_resume,
1418 .asic_reset = &cayman_asic_reset,
1419 .vga_set_state = &r600_vga_set_state,
1420 .ioctl_wait_idle = r600_ioctl_wait_idle,
1421 .gui_idle = &r600_gui_idle,
1422 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1423 .gart = {
1424 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1425 .set_page = &rs600_gart_set_page,
1426 },
1427 .ring = {
1428 [RADEON_RING_TYPE_GFX_INDEX] = {
1429 .ib_execute = &cayman_ring_ib_execute,
1430 .ib_parse = &evergreen_ib_parse,
1431 .emit_fence = &cayman_fence_ring_emit,
1432 .emit_semaphore = &r600_semaphore_ring_emit,
1433 .cs_parse = &evergreen_cs_parse,
1434 .ring_test = &r600_ring_test,
1435 .ib_test = &r600_ib_test,
1436 .is_lockup = &evergreen_gpu_is_lockup,
1437 },
1438 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1439 .ib_execute = &cayman_ring_ib_execute,
1440 .ib_parse = &evergreen_ib_parse,
1441 .emit_fence = &cayman_fence_ring_emit,
1442 .emit_semaphore = &r600_semaphore_ring_emit,
1443 .cs_parse = &evergreen_cs_parse,
1444 .ring_test = &r600_ring_test,
1445 .ib_test = &r600_ib_test,
1446 .is_lockup = &evergreen_gpu_is_lockup,
1447 },
1448 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1449 .ib_execute = &cayman_ring_ib_execute,
1450 .ib_parse = &evergreen_ib_parse,
1451 .emit_fence = &cayman_fence_ring_emit,
1452 .emit_semaphore = &r600_semaphore_ring_emit,
1453 .cs_parse = &evergreen_cs_parse,
1454 .ring_test = &r600_ring_test,
1455 .ib_test = &r600_ib_test,
1456 .is_lockup = &evergreen_gpu_is_lockup,
1457 }
1458 },
1459 .irq = {
1460 .set = &evergreen_irq_set,
1461 .process = &evergreen_irq_process,
1462 },
1463 .display = {
1464 .bandwidth_update = &dce6_bandwidth_update,
1465 .get_vblank_counter = &evergreen_get_vblank_counter,
1466 .wait_for_vblank = &dce4_wait_for_vblank,
1467 },
1468 .copy = {
1469 .blit = &r600_copy_blit,
1470 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1471 .dma = NULL,
1472 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1473 .copy = &r600_copy_blit,
1474 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1475 },
1476 .surface = {
1477 .set_reg = r600_set_surface_reg,
1478 .clear_reg = r600_clear_surface_reg,
1479 },
1480 .hpd = {
1481 .init = &evergreen_hpd_init,
1482 .fini = &evergreen_hpd_fini,
1483 .sense = &evergreen_hpd_sense,
1484 .set_polarity = &evergreen_hpd_set_polarity,
1485 },
1486 .pm = {
1487 .misc = &evergreen_pm_misc,
1488 .prepare = &evergreen_pm_prepare,
1489 .finish = &evergreen_pm_finish,
1490 .init_profile = &sumo_pm_init_profile,
1491 .get_dynpm_state = &r600_pm_get_dynpm_state,
1492 .get_engine_clock = &radeon_atom_get_engine_clock,
1493 .set_engine_clock = &radeon_atom_set_engine_clock,
1494 .get_memory_clock = NULL,
1495 .set_memory_clock = NULL,
1496 .get_pcie_lanes = NULL,
1497 .set_pcie_lanes = NULL,
1498 .set_clock_gating = NULL,
1499 },
1500 .pflip = {
1501 .pre_page_flip = &evergreen_pre_page_flip,
1502 .page_flip = &evergreen_page_flip,
1503 .post_page_flip = &evergreen_post_page_flip,
1504 },
1505 };
1506
1507 static const struct radeon_vm_funcs si_vm_funcs = {
1508 .init = &si_vm_init,
1509 .fini = &si_vm_fini,
1510 .bind = &si_vm_bind,
1511 .unbind = &si_vm_unbind,
1512 .tlb_flush = &si_vm_tlb_flush,
1513 .page_flags = &cayman_vm_page_flags,
1514 .set_page = &cayman_vm_set_page,
1515 };
1516
1517 static struct radeon_asic si_asic = {
1518 .init = &si_init,
1519 .fini = &si_fini,
1520 .suspend = &si_suspend,
1521 .resume = &si_resume,
1522 .asic_reset = &si_asic_reset,
1523 .vga_set_state = &r600_vga_set_state,
1524 .ioctl_wait_idle = r600_ioctl_wait_idle,
1525 .gui_idle = &r600_gui_idle,
1526 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1527 .gart = {
1528 .tlb_flush = &si_pcie_gart_tlb_flush,
1529 .set_page = &rs600_gart_set_page,
1530 },
1531 .ring = {
1532 [RADEON_RING_TYPE_GFX_INDEX] = {
1533 .ib_execute = &si_ring_ib_execute,
1534 .ib_parse = &si_ib_parse,
1535 .emit_fence = &si_fence_ring_emit,
1536 .emit_semaphore = &r600_semaphore_ring_emit,
1537 .cs_parse = NULL,
1538 .ring_test = &r600_ring_test,
1539 .ib_test = &r600_ib_test,
1540 .is_lockup = &si_gpu_is_lockup,
1541 },
1542 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1543 .ib_execute = &si_ring_ib_execute,
1544 .ib_parse = &si_ib_parse,
1545 .emit_fence = &si_fence_ring_emit,
1546 .emit_semaphore = &r600_semaphore_ring_emit,
1547 .cs_parse = NULL,
1548 .ring_test = &r600_ring_test,
1549 .ib_test = &r600_ib_test,
1550 .is_lockup = &si_gpu_is_lockup,
1551 },
1552 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1553 .ib_execute = &si_ring_ib_execute,
1554 .ib_parse = &si_ib_parse,
1555 .emit_fence = &si_fence_ring_emit,
1556 .emit_semaphore = &r600_semaphore_ring_emit,
1557 .cs_parse = NULL,
1558 .ring_test = &r600_ring_test,
1559 .ib_test = &r600_ib_test,
1560 .is_lockup = &si_gpu_is_lockup,
1561 }
1562 },
1563 .irq = {
1564 .set = &si_irq_set,
1565 .process = &si_irq_process,
1566 },
1567 .display = {
1568 .bandwidth_update = &dce6_bandwidth_update,
1569 .get_vblank_counter = &evergreen_get_vblank_counter,
1570 .wait_for_vblank = &dce4_wait_for_vblank,
1571 },
1572 .copy = {
1573 .blit = NULL,
1574 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1575 .dma = NULL,
1576 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1577 .copy = NULL,
1578 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1579 },
1580 .surface = {
1581 .set_reg = r600_set_surface_reg,
1582 .clear_reg = r600_clear_surface_reg,
1583 },
1584 .hpd = {
1585 .init = &evergreen_hpd_init,
1586 .fini = &evergreen_hpd_fini,
1587 .sense = &evergreen_hpd_sense,
1588 .set_polarity = &evergreen_hpd_set_polarity,
1589 },
1590 .pm = {
1591 .misc = &evergreen_pm_misc,
1592 .prepare = &evergreen_pm_prepare,
1593 .finish = &evergreen_pm_finish,
1594 .init_profile = &sumo_pm_init_profile,
1595 .get_dynpm_state = &r600_pm_get_dynpm_state,
1596 .get_engine_clock = &radeon_atom_get_engine_clock,
1597 .set_engine_clock = &radeon_atom_set_engine_clock,
1598 .get_memory_clock = &radeon_atom_get_memory_clock,
1599 .set_memory_clock = &radeon_atom_set_memory_clock,
1600 .get_pcie_lanes = NULL,
1601 .set_pcie_lanes = NULL,
1602 .set_clock_gating = NULL,
1603 },
1604 .pflip = {
1605 .pre_page_flip = &evergreen_pre_page_flip,
1606 .page_flip = &evergreen_page_flip,
1607 .post_page_flip = &evergreen_post_page_flip,
1608 },
1609 };
1610
1611 int radeon_asic_init(struct radeon_device *rdev)
1612 {
1613 radeon_register_accessor_init(rdev);
1614
1615 /* set the number of crtcs */
1616 if (rdev->flags & RADEON_SINGLE_CRTC)
1617 rdev->num_crtc = 1;
1618 else
1619 rdev->num_crtc = 2;
1620
1621 switch (rdev->family) {
1622 case CHIP_R100:
1623 case CHIP_RV100:
1624 case CHIP_RS100:
1625 case CHIP_RV200:
1626 case CHIP_RS200:
1627 rdev->asic = &r100_asic;
1628 break;
1629 case CHIP_R200:
1630 case CHIP_RV250:
1631 case CHIP_RS300:
1632 case CHIP_RV280:
1633 rdev->asic = &r200_asic;
1634 break;
1635 case CHIP_R300:
1636 case CHIP_R350:
1637 case CHIP_RV350:
1638 case CHIP_RV380:
1639 if (rdev->flags & RADEON_IS_PCIE)
1640 rdev->asic = &r300_asic_pcie;
1641 else
1642 rdev->asic = &r300_asic;
1643 break;
1644 case CHIP_R420:
1645 case CHIP_R423:
1646 case CHIP_RV410:
1647 rdev->asic = &r420_asic;
1648 /* handle macs */
1649 if (rdev->bios == NULL) {
1650 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1651 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1652 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1653 rdev->asic->pm.set_memory_clock = NULL;
1654 }
1655 break;
1656 case CHIP_RS400:
1657 case CHIP_RS480:
1658 rdev->asic = &rs400_asic;
1659 break;
1660 case CHIP_RS600:
1661 rdev->asic = &rs600_asic;
1662 break;
1663 case CHIP_RS690:
1664 case CHIP_RS740:
1665 rdev->asic = &rs690_asic;
1666 break;
1667 case CHIP_RV515:
1668 rdev->asic = &rv515_asic;
1669 break;
1670 case CHIP_R520:
1671 case CHIP_RV530:
1672 case CHIP_RV560:
1673 case CHIP_RV570:
1674 case CHIP_R580:
1675 rdev->asic = &r520_asic;
1676 break;
1677 case CHIP_R600:
1678 case CHIP_RV610:
1679 case CHIP_RV630:
1680 case CHIP_RV620:
1681 case CHIP_RV635:
1682 case CHIP_RV670:
1683 rdev->asic = &r600_asic;
1684 break;
1685 case CHIP_RS780:
1686 case CHIP_RS880:
1687 rdev->asic = &rs780_asic;
1688 break;
1689 case CHIP_RV770:
1690 case CHIP_RV730:
1691 case CHIP_RV710:
1692 case CHIP_RV740:
1693 rdev->asic = &rv770_asic;
1694 break;
1695 case CHIP_CEDAR:
1696 case CHIP_REDWOOD:
1697 case CHIP_JUNIPER:
1698 case CHIP_CYPRESS:
1699 case CHIP_HEMLOCK:
1700 /* set num crtcs */
1701 if (rdev->family == CHIP_CEDAR)
1702 rdev->num_crtc = 4;
1703 else
1704 rdev->num_crtc = 6;
1705 rdev->asic = &evergreen_asic;
1706 break;
1707 case CHIP_PALM:
1708 case CHIP_SUMO:
1709 case CHIP_SUMO2:
1710 rdev->asic = &sumo_asic;
1711 break;
1712 case CHIP_BARTS:
1713 case CHIP_TURKS:
1714 case CHIP_CAICOS:
1715 /* set num crtcs */
1716 if (rdev->family == CHIP_CAICOS)
1717 rdev->num_crtc = 4;
1718 else
1719 rdev->num_crtc = 6;
1720 rdev->asic = &btc_asic;
1721 break;
1722 case CHIP_CAYMAN:
1723 rdev->asic = &cayman_asic;
1724 /* set num crtcs */
1725 rdev->num_crtc = 6;
1726 rdev->vm_manager.funcs = &cayman_vm_funcs;
1727 break;
1728 case CHIP_ARUBA:
1729 rdev->asic = &trinity_asic;
1730 /* set num crtcs */
1731 rdev->num_crtc = 4;
1732 rdev->vm_manager.funcs = &cayman_vm_funcs;
1733 break;
1734 case CHIP_TAHITI:
1735 case CHIP_PITCAIRN:
1736 case CHIP_VERDE:
1737 rdev->asic = &si_asic;
1738 /* set num crtcs */
1739 rdev->num_crtc = 6;
1740 rdev->vm_manager.funcs = &si_vm_funcs;
1741 break;
1742 default:
1743 /* FIXME: not supported yet */
1744 return -EINVAL;
1745 }
1746
1747 if (rdev->flags & RADEON_IS_IGP) {
1748 rdev->asic->pm.get_memory_clock = NULL;
1749 rdev->asic->pm.set_memory_clock = NULL;
1750 }
1751
1752 return 0;
1753 }
1754
Linux with added FPC-III support