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hfs: get rid of hfs_sync_super
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_legacy_encoders.c
bloba0c82229e8f07203b2fd0bb41a928d637e521f65
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31 #include <linux/backlight.h>
32 #ifdef CONFIG_PMAC_BACKLIGHT
33 #include <asm/backlight.h>
34 #endif
35
36 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
37 {
38 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
39 struct drm_encoder_helper_funcs *encoder_funcs;
40
41 encoder_funcs = encoder->helper_private;
42 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
43 radeon_encoder->active_device = 0;
44 }
45
46 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
47 {
48 struct drm_device *dev = encoder->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
51 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
52 int panel_pwr_delay = 2000;
53 bool is_mac = false;
54 uint8_t backlight_level;
55 DRM_DEBUG_KMS("\n");
56
57 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
58 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
59
60 if (radeon_encoder->enc_priv) {
61 if (rdev->is_atom_bios) {
62 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
63 panel_pwr_delay = lvds->panel_pwr_delay;
64 if (lvds->bl_dev)
65 backlight_level = lvds->backlight_level;
66 } else {
67 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
68 panel_pwr_delay = lvds->panel_pwr_delay;
69 if (lvds->bl_dev)
70 backlight_level = lvds->backlight_level;
71 }
72 }
73
74 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
75 * Taken from radeonfb.
76 */
77 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
78 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
79 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
80 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
81 is_mac = true;
82
83 switch (mode) {
84 case DRM_MODE_DPMS_ON:
85 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
86 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
87 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
88 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
89 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
90 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
91 mdelay(1);
92
93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
94 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
95 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
96
97 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
98 RADEON_LVDS_BL_MOD_LEVEL_MASK);
99 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
100 RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
101 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
102 if (is_mac)
103 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
104 mdelay(panel_pwr_delay);
105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
106 break;
107 case DRM_MODE_DPMS_STANDBY:
108 case DRM_MODE_DPMS_SUSPEND:
109 case DRM_MODE_DPMS_OFF:
110 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
111 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
112 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
113 if (is_mac) {
114 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
115 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
116 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
117 } else {
118 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
119 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
120 }
121 mdelay(panel_pwr_delay);
122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
123 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
124 mdelay(panel_pwr_delay);
125 break;
126 }
127
128 if (rdev->is_atom_bios)
129 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
130 else
131 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
132
133 }
134
135 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
136 {
137 struct radeon_device *rdev = encoder->dev->dev_private;
138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
139 DRM_DEBUG("\n");
140
141 if (radeon_encoder->enc_priv) {
142 if (rdev->is_atom_bios) {
143 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
144 lvds->dpms_mode = mode;
145 } else {
146 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
147 lvds->dpms_mode = mode;
148 }
149 }
150
151 radeon_legacy_lvds_update(encoder, mode);
152 }
153
154 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
155 {
156 struct radeon_device *rdev = encoder->dev->dev_private;
157
158 if (rdev->is_atom_bios)
159 radeon_atom_output_lock(encoder, true);
160 else
161 radeon_combios_output_lock(encoder, true);
162 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
163 }
164
165 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
166 {
167 struct radeon_device *rdev = encoder->dev->dev_private;
168
169 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
170 if (rdev->is_atom_bios)
171 radeon_atom_output_lock(encoder, false);
172 else
173 radeon_combios_output_lock(encoder, false);
174 }
175
176 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
177 struct drm_display_mode *mode,
178 struct drm_display_mode *adjusted_mode)
179 {
180 struct drm_device *dev = encoder->dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
184 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
185
186 DRM_DEBUG_KMS("\n");
187
188 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
189 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
190
191 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
192 if (rdev->is_atom_bios) {
193 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
194 * need to call that on resume to set up the reg properly.
195 */
196 radeon_encoder->pixel_clock = adjusted_mode->clock;
197 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
198 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
199 } else {
200 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
201 if (lvds) {
202 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
203 lvds_gen_cntl = lvds->lvds_gen_cntl;
204 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
205 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
206 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
207 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
208 } else
209 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
210 }
211 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
212 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
213 RADEON_LVDS_BLON |
214 RADEON_LVDS_EN |
215 RADEON_LVDS_RST_FM);
216
217 if (ASIC_IS_R300(rdev))
218 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
219
220 if (radeon_crtc->crtc_id == 0) {
221 if (ASIC_IS_R300(rdev)) {
222 if (radeon_encoder->rmx_type != RMX_OFF)
223 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
224 } else
225 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
226 } else {
227 if (ASIC_IS_R300(rdev))
228 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
229 else
230 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
231 }
232
233 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
234 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
235 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
236
237 if (rdev->family == CHIP_RV410)
238 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
239
240 if (rdev->is_atom_bios)
241 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
242 else
243 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
244 }
245
246 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
247 struct drm_display_mode *mode,
248 struct drm_display_mode *adjusted_mode)
249 {
250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
251
252 /* set the active encoder to connector routing */
253 radeon_encoder_set_active_device(encoder);
254 drm_mode_set_crtcinfo(adjusted_mode, 0);
255
256 /* get the native mode for LVDS */
257 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
258 radeon_panel_mode_fixup(encoder, adjusted_mode);
259
260 return true;
261 }
262
263 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
264 .dpms = radeon_legacy_lvds_dpms,
265 .mode_fixup = radeon_legacy_mode_fixup,
266 .prepare = radeon_legacy_lvds_prepare,
267 .mode_set = radeon_legacy_lvds_mode_set,
268 .commit = radeon_legacy_lvds_commit,
269 .disable = radeon_legacy_encoder_disable,
270 };
271
272 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
273
274 #define MAX_RADEON_LEVEL 0xFF
275
276 struct radeon_backlight_privdata {
277 struct radeon_encoder *encoder;
278 uint8_t negative;
279 };
280
281 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
282 {
283 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
284 uint8_t level;
285
286 /* Convert brightness to hardware level */
287 if (bd->props.brightness < 0)
288 level = 0;
289 else if (bd->props.brightness > MAX_RADEON_LEVEL)
290 level = MAX_RADEON_LEVEL;
291 else
292 level = bd->props.brightness;
293
294 if (pdata->negative)
295 level = MAX_RADEON_LEVEL - level;
296
297 return level;
298 }
299
300 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
301 {
302 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
303 struct radeon_encoder *radeon_encoder = pdata->encoder;
304 struct drm_device *dev = radeon_encoder->base.dev;
305 struct radeon_device *rdev = dev->dev_private;
306 int dpms_mode = DRM_MODE_DPMS_ON;
307
308 if (radeon_encoder->enc_priv) {
309 if (rdev->is_atom_bios) {
310 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
311 dpms_mode = lvds->dpms_mode;
312 lvds->backlight_level = radeon_legacy_lvds_level(bd);
313 } else {
314 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
315 dpms_mode = lvds->dpms_mode;
316 lvds->backlight_level = radeon_legacy_lvds_level(bd);
317 }
318 }
319
320 if (bd->props.brightness > 0)
321 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
322 else
323 radeon_legacy_lvds_update(&radeon_encoder->base, DRM_MODE_DPMS_OFF);
324
325 return 0;
326 }
327
328 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
329 {
330 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
331 struct radeon_encoder *radeon_encoder = pdata->encoder;
332 struct drm_device *dev = radeon_encoder->base.dev;
333 struct radeon_device *rdev = dev->dev_private;
334 uint8_t backlight_level;
335
336 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
337 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
338
339 return pdata->negative ? MAX_RADEON_LEVEL - backlight_level : backlight_level;
340 }
341
342 static const struct backlight_ops radeon_backlight_ops = {
343 .get_brightness = radeon_legacy_backlight_get_brightness,
344 .update_status = radeon_legacy_backlight_update_status,
345 };
346
347 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
348 struct drm_connector *drm_connector)
349 {
350 struct drm_device *dev = radeon_encoder->base.dev;
351 struct radeon_device *rdev = dev->dev_private;
352 struct backlight_device *bd;
353 struct backlight_properties props;
354 struct radeon_backlight_privdata *pdata;
355 uint8_t backlight_level;
356
357 if (!radeon_encoder->enc_priv)
358 return;
359
360 #ifdef CONFIG_PMAC_BACKLIGHT
361 if (!pmac_has_backlight_type("ati") &&
362 !pmac_has_backlight_type("mnca"))
363 return;
364 #endif
365
366 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
367 if (!pdata) {
368 DRM_ERROR("Memory allocation failed\n");
369 goto error;
370 }
371
372 memset(&props, 0, sizeof(props));
373 props.max_brightness = MAX_RADEON_LEVEL;
374 props.type = BACKLIGHT_RAW;
375 bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
376 pdata, &radeon_backlight_ops, &props);
377 if (IS_ERR(bd)) {
378 DRM_ERROR("Backlight registration failed\n");
379 goto error;
380 }
381
382 pdata->encoder = radeon_encoder;
383
384 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
385 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
386
387 /* First, try to detect backlight level sense based on the assumption
388 * that firmware set it up at full brightness
389 */
390 if (backlight_level == 0)
391 pdata->negative = true;
392 else if (backlight_level == 0xff)
393 pdata->negative = false;
394 else {
395 /* XXX hack... maybe some day we can figure out in what direction
396 * backlight should work on a given panel?
397 */
398 pdata->negative = (rdev->family != CHIP_RV200 &&
399 rdev->family != CHIP_RV250 &&
400 rdev->family != CHIP_RV280 &&
401 rdev->family != CHIP_RV350);
402
403 #ifdef CONFIG_PMAC_BACKLIGHT
404 pdata->negative = (pdata->negative ||
405 of_machine_is_compatible("PowerBook4,3") ||
406 of_machine_is_compatible("PowerBook6,3") ||
407 of_machine_is_compatible("PowerBook6,5"));
408 #endif
409 }
410
411 if (rdev->is_atom_bios) {
412 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
413 lvds->bl_dev = bd;
414 } else {
415 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
416 lvds->bl_dev = bd;
417 }
418
419 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
420 bd->props.power = FB_BLANK_UNBLANK;
421 backlight_update_status(bd);
422
423 DRM_INFO("radeon legacy LVDS backlight initialized\n");
424
425 return;
426
427 error:
428 kfree(pdata);
429 return;
430 }
431
432 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
433 {
434 struct drm_device *dev = radeon_encoder->base.dev;
435 struct radeon_device *rdev = dev->dev_private;
436 struct backlight_device *bd = NULL;
437
438 if (!radeon_encoder->enc_priv)
439 return;
440
441 if (rdev->is_atom_bios) {
442 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
443 bd = lvds->bl_dev;
444 lvds->bl_dev = NULL;
445 } else {
446 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
447 bd = lvds->bl_dev;
448 lvds->bl_dev = NULL;
449 }
450
451 if (bd) {
452 struct radeon_legacy_backlight_privdata *pdata;
453
454 pdata = bl_get_data(bd);
455 backlight_device_unregister(bd);
456 kfree(pdata);
457
458 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
459 }
460 }
461
462 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
463
464 void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
465 {
466 }
467
468 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
469 {
470 }
471
472 #endif
473
474
475 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
476 {
477 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
478
479 if (radeon_encoder->enc_priv) {
480 radeon_legacy_backlight_exit(radeon_encoder);
481 kfree(radeon_encoder->enc_priv);
482 }
483 drm_encoder_cleanup(encoder);
484 kfree(radeon_encoder);
485 }
486
487 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
488 .destroy = radeon_lvds_enc_destroy,
489 };
490
491 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
492 {
493 struct drm_device *dev = encoder->dev;
494 struct radeon_device *rdev = dev->dev_private;
495 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
496 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
497 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
498
499 DRM_DEBUG_KMS("\n");
500
501 switch (mode) {
502 case DRM_MODE_DPMS_ON:
503 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
504 dac_cntl &= ~RADEON_DAC_PDWN;
505 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
506 RADEON_DAC_PDWN_G |
507 RADEON_DAC_PDWN_B);
508 break;
509 case DRM_MODE_DPMS_STANDBY:
510 case DRM_MODE_DPMS_SUSPEND:
511 case DRM_MODE_DPMS_OFF:
512 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
513 dac_cntl |= RADEON_DAC_PDWN;
514 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
515 RADEON_DAC_PDWN_G |
516 RADEON_DAC_PDWN_B);
517 break;
518 }
519
520 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
521 WREG32(RADEON_DAC_CNTL, dac_cntl);
522 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
523
524 if (rdev->is_atom_bios)
525 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
526 else
527 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
528
529 }
530
531 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
532 {
533 struct radeon_device *rdev = encoder->dev->dev_private;
534
535 if (rdev->is_atom_bios)
536 radeon_atom_output_lock(encoder, true);
537 else
538 radeon_combios_output_lock(encoder, true);
539 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
540 }
541
542 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
543 {
544 struct radeon_device *rdev = encoder->dev->dev_private;
545
546 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
547
548 if (rdev->is_atom_bios)
549 radeon_atom_output_lock(encoder, false);
550 else
551 radeon_combios_output_lock(encoder, false);
552 }
553
554 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
555 struct drm_display_mode *mode,
556 struct drm_display_mode *adjusted_mode)
557 {
558 struct drm_device *dev = encoder->dev;
559 struct radeon_device *rdev = dev->dev_private;
560 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
561 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
562 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
563
564 DRM_DEBUG_KMS("\n");
565
566 if (radeon_crtc->crtc_id == 0) {
567 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
568 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
569 ~(RADEON_DISP_DAC_SOURCE_MASK);
570 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
571 } else {
572 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
573 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
574 }
575 } else {
576 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
577 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
578 ~(RADEON_DISP_DAC_SOURCE_MASK);
579 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
580 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
581 } else {
582 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
583 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
584 }
585 }
586
587 dac_cntl = (RADEON_DAC_MASK_ALL |
588 RADEON_DAC_VGA_ADR_EN |
589 /* TODO 6-bits */
590 RADEON_DAC_8BIT_EN);
591
592 WREG32_P(RADEON_DAC_CNTL,
593 dac_cntl,
594 RADEON_DAC_RANGE_CNTL |
595 RADEON_DAC_BLANKING);
596
597 if (radeon_encoder->enc_priv) {
598 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
599 dac_macro_cntl = p_dac->ps2_pdac_adj;
600 } else
601 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
602 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
603 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
604
605 if (rdev->is_atom_bios)
606 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
607 else
608 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
609 }
610
611 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
612 struct drm_connector *connector)
613 {
614 struct drm_device *dev = encoder->dev;
615 struct radeon_device *rdev = dev->dev_private;
616 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
617 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
618 enum drm_connector_status found = connector_status_disconnected;
619 bool color = true;
620
621 /* save the regs we need */
622 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
623 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
624 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
625 dac_cntl = RREG32(RADEON_DAC_CNTL);
626 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
627
628 tmp = vclk_ecp_cntl &
629 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
630 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
631
632 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
633 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
634
635 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
636 RADEON_DAC_FORCE_DATA_EN;
637
638 if (color)
639 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
640 else
641 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
642
643 if (ASIC_IS_R300(rdev))
644 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
645 else
646 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
647
648 WREG32(RADEON_DAC_EXT_CNTL, tmp);
649
650 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
651 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
652 WREG32(RADEON_DAC_CNTL, tmp);
653
654 tmp &= ~(RADEON_DAC_PDWN_R |
655 RADEON_DAC_PDWN_G |
656 RADEON_DAC_PDWN_B);
657
658 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
659
660 mdelay(2);
661
662 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
663 found = connector_status_connected;
664
665 /* restore the regs we used */
666 WREG32(RADEON_DAC_CNTL, dac_cntl);
667 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
668 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
669 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
670 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
671
672 return found;
673 }
674
675 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
676 .dpms = radeon_legacy_primary_dac_dpms,
677 .mode_fixup = radeon_legacy_mode_fixup,
678 .prepare = radeon_legacy_primary_dac_prepare,
679 .mode_set = radeon_legacy_primary_dac_mode_set,
680 .commit = radeon_legacy_primary_dac_commit,
681 .detect = radeon_legacy_primary_dac_detect,
682 .disable = radeon_legacy_encoder_disable,
683 };
684
685
686 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
687 .destroy = radeon_enc_destroy,
688 };
689
690 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
691 {
692 struct drm_device *dev = encoder->dev;
693 struct radeon_device *rdev = dev->dev_private;
694 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
695 DRM_DEBUG_KMS("\n");
696
697 switch (mode) {
698 case DRM_MODE_DPMS_ON:
699 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
700 break;
701 case DRM_MODE_DPMS_STANDBY:
702 case DRM_MODE_DPMS_SUSPEND:
703 case DRM_MODE_DPMS_OFF:
704 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
705 break;
706 }
707
708 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
709
710 if (rdev->is_atom_bios)
711 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
712 else
713 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
714
715 }
716
717 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
718 {
719 struct radeon_device *rdev = encoder->dev->dev_private;
720
721 if (rdev->is_atom_bios)
722 radeon_atom_output_lock(encoder, true);
723 else
724 radeon_combios_output_lock(encoder, true);
725 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
726 }
727
728 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
729 {
730 struct radeon_device *rdev = encoder->dev->dev_private;
731
732 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
733
734 if (rdev->is_atom_bios)
735 radeon_atom_output_lock(encoder, true);
736 else
737 radeon_combios_output_lock(encoder, true);
738 }
739
740 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
741 struct drm_display_mode *mode,
742 struct drm_display_mode *adjusted_mode)
743 {
744 struct drm_device *dev = encoder->dev;
745 struct radeon_device *rdev = dev->dev_private;
746 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
747 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
748 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
749 int i;
750
751 DRM_DEBUG_KMS("\n");
752
753 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
754 tmp &= 0xfffff;
755 if (rdev->family == CHIP_RV280) {
756 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
757 tmp ^= (1 << 22);
758 tmds_pll_cntl ^= (1 << 22);
759 }
760
761 if (radeon_encoder->enc_priv) {
762 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
763
764 for (i = 0; i < 4; i++) {
765 if (tmds->tmds_pll[i].freq == 0)
766 break;
767 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
768 tmp = tmds->tmds_pll[i].value ;
769 break;
770 }
771 }
772 }
773
774 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
775 if (tmp & 0xfff00000)
776 tmds_pll_cntl = tmp;
777 else {
778 tmds_pll_cntl &= 0xfff00000;
779 tmds_pll_cntl |= tmp;
780 }
781 } else
782 tmds_pll_cntl = tmp;
783
784 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
785 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
786
787 if (rdev->family == CHIP_R200 ||
788 rdev->family == CHIP_R100 ||
789 ASIC_IS_R300(rdev))
790 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
791 else /* RV chips got this bit reversed */
792 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
793
794 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
795 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
796 RADEON_FP_CRTC_DONT_SHADOW_HEND));
797
798 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
799
800 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
801 RADEON_FP_DFP_SYNC_SEL |
802 RADEON_FP_CRT_SYNC_SEL |
803 RADEON_FP_CRTC_LOCK_8DOT |
804 RADEON_FP_USE_SHADOW_EN |
805 RADEON_FP_CRTC_USE_SHADOW_VEND |
806 RADEON_FP_CRT_SYNC_ALT);
807
808 if (1) /* FIXME rgbBits == 8 */
809 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
810 else
811 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
812
813 if (radeon_crtc->crtc_id == 0) {
814 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
815 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
816 if (radeon_encoder->rmx_type != RMX_OFF)
817 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
818 else
819 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
820 } else
821 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
822 } else {
823 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
824 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
825 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
826 } else
827 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
828 }
829
830 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
831 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
832 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
833
834 if (rdev->is_atom_bios)
835 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
836 else
837 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
838 }
839
840 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
841 .dpms = radeon_legacy_tmds_int_dpms,
842 .mode_fixup = radeon_legacy_mode_fixup,
843 .prepare = radeon_legacy_tmds_int_prepare,
844 .mode_set = radeon_legacy_tmds_int_mode_set,
845 .commit = radeon_legacy_tmds_int_commit,
846 .disable = radeon_legacy_encoder_disable,
847 };
848
849
850 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
851 .destroy = radeon_enc_destroy,
852 };
853
854 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
855 {
856 struct drm_device *dev = encoder->dev;
857 struct radeon_device *rdev = dev->dev_private;
858 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
859 DRM_DEBUG_KMS("\n");
860
861 switch (mode) {
862 case DRM_MODE_DPMS_ON:
863 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
864 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
865 break;
866 case DRM_MODE_DPMS_STANDBY:
867 case DRM_MODE_DPMS_SUSPEND:
868 case DRM_MODE_DPMS_OFF:
869 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
870 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
871 break;
872 }
873
874 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
875
876 if (rdev->is_atom_bios)
877 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
878 else
879 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
880
881 }
882
883 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
884 {
885 struct radeon_device *rdev = encoder->dev->dev_private;
886
887 if (rdev->is_atom_bios)
888 radeon_atom_output_lock(encoder, true);
889 else
890 radeon_combios_output_lock(encoder, true);
891 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
892 }
893
894 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
895 {
896 struct radeon_device *rdev = encoder->dev->dev_private;
897 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
898
899 if (rdev->is_atom_bios)
900 radeon_atom_output_lock(encoder, false);
901 else
902 radeon_combios_output_lock(encoder, false);
903 }
904
905 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
906 struct drm_display_mode *mode,
907 struct drm_display_mode *adjusted_mode)
908 {
909 struct drm_device *dev = encoder->dev;
910 struct radeon_device *rdev = dev->dev_private;
911 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
912 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
913 uint32_t fp2_gen_cntl;
914
915 DRM_DEBUG_KMS("\n");
916
917 if (rdev->is_atom_bios) {
918 radeon_encoder->pixel_clock = adjusted_mode->clock;
919 atombios_dvo_setup(encoder, ATOM_ENABLE);
920 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
921 } else {
922 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
923
924 if (1) /* FIXME rgbBits == 8 */
925 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
926 else
927 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
928
929 fp2_gen_cntl &= ~(RADEON_FP2_ON |
930 RADEON_FP2_DVO_EN |
931 RADEON_FP2_DVO_RATE_SEL_SDR);
932
933 /* XXX: these are oem specific */
934 if (ASIC_IS_R300(rdev)) {
935 if ((dev->pdev->device == 0x4850) &&
936 (dev->pdev->subsystem_vendor == 0x1028) &&
937 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
938 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
939 else
940 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
941
942 /*if (mode->clock > 165000)
943 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
944 }
945 if (!radeon_combios_external_tmds_setup(encoder))
946 radeon_external_tmds_setup(encoder);
947 }
948
949 if (radeon_crtc->crtc_id == 0) {
950 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
951 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
952 if (radeon_encoder->rmx_type != RMX_OFF)
953 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
954 else
955 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
956 } else
957 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
958 } else {
959 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
960 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
961 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
962 } else
963 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
964 }
965
966 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
967
968 if (rdev->is_atom_bios)
969 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
970 else
971 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
972 }
973
974 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
975 {
976 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
977 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
978 if (tmds) {
979 if (tmds->i2c_bus)
980 radeon_i2c_destroy(tmds->i2c_bus);
981 }
982 kfree(radeon_encoder->enc_priv);
983 drm_encoder_cleanup(encoder);
984 kfree(radeon_encoder);
985 }
986
987 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
988 .dpms = radeon_legacy_tmds_ext_dpms,
989 .mode_fixup = radeon_legacy_mode_fixup,
990 .prepare = radeon_legacy_tmds_ext_prepare,
991 .mode_set = radeon_legacy_tmds_ext_mode_set,
992 .commit = radeon_legacy_tmds_ext_commit,
993 .disable = radeon_legacy_encoder_disable,
994 };
995
996
997 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
998 .destroy = radeon_ext_tmds_enc_destroy,
999 };
1000
1001 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1002 {
1003 struct drm_device *dev = encoder->dev;
1004 struct radeon_device *rdev = dev->dev_private;
1005 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1006 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1007 uint32_t tv_master_cntl = 0;
1008 bool is_tv;
1009 DRM_DEBUG_KMS("\n");
1010
1011 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1012
1013 if (rdev->family == CHIP_R200)
1014 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1015 else {
1016 if (is_tv)
1017 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1018 else
1019 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1020 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1021 }
1022
1023 switch (mode) {
1024 case DRM_MODE_DPMS_ON:
1025 if (rdev->family == CHIP_R200) {
1026 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1027 } else {
1028 if (is_tv)
1029 tv_master_cntl |= RADEON_TV_ON;
1030 else
1031 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1032
1033 if (rdev->family == CHIP_R420 ||
1034 rdev->family == CHIP_R423 ||
1035 rdev->family == CHIP_RV410)
1036 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1037 R420_TV_DAC_GDACPD |
1038 R420_TV_DAC_BDACPD |
1039 RADEON_TV_DAC_BGSLEEP);
1040 else
1041 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1042 RADEON_TV_DAC_GDACPD |
1043 RADEON_TV_DAC_BDACPD |
1044 RADEON_TV_DAC_BGSLEEP);
1045 }
1046 break;
1047 case DRM_MODE_DPMS_STANDBY:
1048 case DRM_MODE_DPMS_SUSPEND:
1049 case DRM_MODE_DPMS_OFF:
1050 if (rdev->family == CHIP_R200)
1051 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1052 else {
1053 if (is_tv)
1054 tv_master_cntl &= ~RADEON_TV_ON;
1055 else
1056 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1057
1058 if (rdev->family == CHIP_R420 ||
1059 rdev->family == CHIP_R423 ||
1060 rdev->family == CHIP_RV410)
1061 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1062 R420_TV_DAC_GDACPD |
1063 R420_TV_DAC_BDACPD |
1064 RADEON_TV_DAC_BGSLEEP);
1065 else
1066 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1067 RADEON_TV_DAC_GDACPD |
1068 RADEON_TV_DAC_BDACPD |
1069 RADEON_TV_DAC_BGSLEEP);
1070 }
1071 break;
1072 }
1073
1074 if (rdev->family == CHIP_R200) {
1075 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1076 } else {
1077 if (is_tv)
1078 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1079 else
1080 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1081 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1082 }
1083
1084 if (rdev->is_atom_bios)
1085 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1086 else
1087 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1088
1089 }
1090
1091 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1092 {
1093 struct radeon_device *rdev = encoder->dev->dev_private;
1094
1095 if (rdev->is_atom_bios)
1096 radeon_atom_output_lock(encoder, true);
1097 else
1098 radeon_combios_output_lock(encoder, true);
1099 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1100 }
1101
1102 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1103 {
1104 struct radeon_device *rdev = encoder->dev->dev_private;
1105
1106 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1107
1108 if (rdev->is_atom_bios)
1109 radeon_atom_output_lock(encoder, true);
1110 else
1111 radeon_combios_output_lock(encoder, true);
1112 }
1113
1114 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1115 struct drm_display_mode *mode,
1116 struct drm_display_mode *adjusted_mode)
1117 {
1118 struct drm_device *dev = encoder->dev;
1119 struct radeon_device *rdev = dev->dev_private;
1120 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1121 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1122 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1123 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1124 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1125 bool is_tv = false;
1126
1127 DRM_DEBUG_KMS("\n");
1128
1129 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1130
1131 if (rdev->family != CHIP_R200) {
1132 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1133 if (rdev->family == CHIP_R420 ||
1134 rdev->family == CHIP_R423 ||
1135 rdev->family == CHIP_RV410) {
1136 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1137 RADEON_TV_DAC_BGADJ_MASK |
1138 R420_TV_DAC_DACADJ_MASK |
1139 R420_TV_DAC_RDACPD |
1140 R420_TV_DAC_GDACPD |
1141 R420_TV_DAC_BDACPD |
1142 R420_TV_DAC_TVENABLE);
1143 } else {
1144 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1145 RADEON_TV_DAC_BGADJ_MASK |
1146 RADEON_TV_DAC_DACADJ_MASK |
1147 RADEON_TV_DAC_RDACPD |
1148 RADEON_TV_DAC_GDACPD |
1149 RADEON_TV_DAC_BDACPD);
1150 }
1151
1152 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1153
1154 if (is_tv) {
1155 if (tv_dac->tv_std == TV_STD_NTSC ||
1156 tv_dac->tv_std == TV_STD_NTSC_J ||
1157 tv_dac->tv_std == TV_STD_PAL_M ||
1158 tv_dac->tv_std == TV_STD_PAL_60)
1159 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1160 else
1161 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1162
1163 if (tv_dac->tv_std == TV_STD_NTSC ||
1164 tv_dac->tv_std == TV_STD_NTSC_J)
1165 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1166 else
1167 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1168 } else
1169 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1170 tv_dac->ps2_tvdac_adj);
1171
1172 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1173 }
1174
1175 if (ASIC_IS_R300(rdev)) {
1176 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1177 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1178 } else if (rdev->family != CHIP_R200)
1179 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1180 else if (rdev->family == CHIP_R200)
1181 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1182
1183 if (rdev->family >= CHIP_R200)
1184 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1185
1186 if (is_tv) {
1187 uint32_t dac_cntl;
1188
1189 dac_cntl = RREG32(RADEON_DAC_CNTL);
1190 dac_cntl &= ~RADEON_DAC_TVO_EN;
1191 WREG32(RADEON_DAC_CNTL, dac_cntl);
1192
1193 if (ASIC_IS_R300(rdev))
1194 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1195
1196 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1197 if (radeon_crtc->crtc_id == 0) {
1198 if (ASIC_IS_R300(rdev)) {
1199 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1200 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1201 RADEON_DISP_TV_SOURCE_CRTC);
1202 }
1203 if (rdev->family >= CHIP_R200) {
1204 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1205 } else {
1206 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1207 }
1208 } else {
1209 if (ASIC_IS_R300(rdev)) {
1210 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1211 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1212 }
1213 if (rdev->family >= CHIP_R200) {
1214 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1215 } else {
1216 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1217 }
1218 }
1219 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1220 } else {
1221
1222 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1223
1224 if (radeon_crtc->crtc_id == 0) {
1225 if (ASIC_IS_R300(rdev)) {
1226 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1227 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1228 } else if (rdev->family == CHIP_R200) {
1229 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1230 RADEON_FP2_DVO_RATE_SEL_SDR);
1231 } else
1232 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1233 } else {
1234 if (ASIC_IS_R300(rdev)) {
1235 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1236 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1237 } else if (rdev->family == CHIP_R200) {
1238 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1239 RADEON_FP2_DVO_RATE_SEL_SDR);
1240 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1241 } else
1242 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1243 }
1244 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1245 }
1246
1247 if (ASIC_IS_R300(rdev)) {
1248 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1249 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1250 } else if (rdev->family != CHIP_R200)
1251 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1252 else if (rdev->family == CHIP_R200)
1253 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1254
1255 if (rdev->family >= CHIP_R200)
1256 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1257
1258 if (is_tv)
1259 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1260
1261 if (rdev->is_atom_bios)
1262 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1263 else
1264 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1265
1266 }
1267
1268 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1269 struct drm_connector *connector)
1270 {
1271 struct drm_device *dev = encoder->dev;
1272 struct radeon_device *rdev = dev->dev_private;
1273 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1274 uint32_t disp_output_cntl, gpiopad_a, tmp;
1275 bool found = false;
1276
1277 /* save regs needed */
1278 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1279 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1280 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1281 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1282 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1283 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1284
1285 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1286
1287 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1288
1289 WREG32(RADEON_CRTC2_GEN_CNTL,
1290 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1291
1292 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1293 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1294 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1295
1296 WREG32(RADEON_DAC_EXT_CNTL,
1297 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1298 RADEON_DAC2_FORCE_DATA_EN |
1299 RADEON_DAC_FORCE_DATA_SEL_RGB |
1300 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1301
1302 WREG32(RADEON_TV_DAC_CNTL,
1303 RADEON_TV_DAC_STD_NTSC |
1304 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1305 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1306
1307 RREG32(RADEON_TV_DAC_CNTL);
1308 mdelay(4);
1309
1310 WREG32(RADEON_TV_DAC_CNTL,
1311 RADEON_TV_DAC_NBLANK |
1312 RADEON_TV_DAC_NHOLD |
1313 RADEON_TV_MONITOR_DETECT_EN |
1314 RADEON_TV_DAC_STD_NTSC |
1315 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1316 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1317
1318 RREG32(RADEON_TV_DAC_CNTL);
1319 mdelay(6);
1320
1321 tmp = RREG32(RADEON_TV_DAC_CNTL);
1322 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1323 found = true;
1324 DRM_DEBUG_KMS("S-video TV connection detected\n");
1325 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1326 found = true;
1327 DRM_DEBUG_KMS("Composite TV connection detected\n");
1328 }
1329
1330 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1331 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1332 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1333 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1334 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1335 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1336 return found;
1337 }
1338
1339 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1340 struct drm_connector *connector)
1341 {
1342 struct drm_device *dev = encoder->dev;
1343 struct radeon_device *rdev = dev->dev_private;
1344 uint32_t tv_dac_cntl, dac_cntl2;
1345 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1346 bool found = false;
1347
1348 if (ASIC_IS_R300(rdev))
1349 return r300_legacy_tv_detect(encoder, connector);
1350
1351 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1352 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1353 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1354 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1355 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1356
1357 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1358 WREG32(RADEON_DAC_CNTL2, tmp);
1359
1360 tmp = tv_master_cntl | RADEON_TV_ON;
1361 tmp &= ~(RADEON_TV_ASYNC_RST |
1362 RADEON_RESTART_PHASE_FIX |
1363 RADEON_CRT_FIFO_CE_EN |
1364 RADEON_TV_FIFO_CE_EN |
1365 RADEON_RE_SYNC_NOW_SEL_MASK);
1366 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1367 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1368
1369 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1370 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1371 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1372
1373 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1374 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1375 else
1376 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1377 WREG32(RADEON_TV_DAC_CNTL, tmp);
1378
1379 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1380 RADEON_RED_MX_FORCE_DAC_DATA |
1381 RADEON_GRN_MX_FORCE_DAC_DATA |
1382 RADEON_BLU_MX_FORCE_DAC_DATA |
1383 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1384 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1385
1386 mdelay(3);
1387 tmp = RREG32(RADEON_TV_DAC_CNTL);
1388 if (tmp & RADEON_TV_DAC_GDACDET) {
1389 found = true;
1390 DRM_DEBUG_KMS("S-video TV connection detected\n");
1391 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1392 found = true;
1393 DRM_DEBUG_KMS("Composite TV connection detected\n");
1394 }
1395
1396 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1397 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1398 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1399 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1400 return found;
1401 }
1402
1403 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1404 struct drm_connector *connector)
1405 {
1406 struct drm_device *dev = encoder->dev;
1407 struct radeon_device *rdev = dev->dev_private;
1408 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1409 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1410 enum drm_connector_status found = connector_status_disconnected;
1411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1412 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1413 bool color = true;
1414 struct drm_crtc *crtc;
1415
1416 /* find out if crtc2 is in use or if this encoder is using it */
1417 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1418 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1419 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1420 if (encoder->crtc != crtc) {
1421 return connector_status_disconnected;
1422 }
1423 }
1424 }
1425
1426 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1427 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1428 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1429 bool tv_detect;
1430
1431 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1432 return connector_status_disconnected;
1433
1434 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1435 if (tv_detect && tv_dac)
1436 found = connector_status_connected;
1437 return found;
1438 }
1439
1440 /* don't probe if the encoder is being used for something else not CRT related */
1441 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1442 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1443 return connector_status_disconnected;
1444 }
1445
1446 /* save the regs we need */
1447 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1448 gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1449 disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1450 disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1451 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1452 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1453 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1454 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1455
1456 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1457 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1458 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1459
1460 if (ASIC_IS_R300(rdev))
1461 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1462
1463 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1464 tmp |= RADEON_CRTC2_CRT2_ON |
1465 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1466
1467 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1468
1469 if (ASIC_IS_R300(rdev)) {
1470 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1471 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1472 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1473 } else {
1474 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1475 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1476 }
1477
1478 tmp = RADEON_TV_DAC_NBLANK |
1479 RADEON_TV_DAC_NHOLD |
1480 RADEON_TV_MONITOR_DETECT_EN |
1481 RADEON_TV_DAC_STD_PS2;
1482
1483 WREG32(RADEON_TV_DAC_CNTL, tmp);
1484
1485 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1486 RADEON_DAC2_FORCE_DATA_EN;
1487
1488 if (color)
1489 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1490 else
1491 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1492
1493 if (ASIC_IS_R300(rdev))
1494 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1495 else
1496 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1497
1498 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1499
1500 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1501 WREG32(RADEON_DAC_CNTL2, tmp);
1502
1503 mdelay(10);
1504
1505 if (ASIC_IS_R300(rdev)) {
1506 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1507 found = connector_status_connected;
1508 } else {
1509 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1510 found = connector_status_connected;
1511 }
1512
1513 /* restore regs we used */
1514 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1515 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1516 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1517 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1518
1519 if (ASIC_IS_R300(rdev)) {
1520 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1521 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1522 } else {
1523 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1524 }
1525 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1526
1527 return found;
1528
1529 }
1530
1531 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1532 .dpms = radeon_legacy_tv_dac_dpms,
1533 .mode_fixup = radeon_legacy_mode_fixup,
1534 .prepare = radeon_legacy_tv_dac_prepare,
1535 .mode_set = radeon_legacy_tv_dac_mode_set,
1536 .commit = radeon_legacy_tv_dac_commit,
1537 .detect = radeon_legacy_tv_dac_detect,
1538 .disable = radeon_legacy_encoder_disable,
1539 };
1540
1541
1542 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1543 .destroy = radeon_enc_destroy,
1544 };
1545
1546
1547 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1548 {
1549 struct drm_device *dev = encoder->base.dev;
1550 struct radeon_device *rdev = dev->dev_private;
1551 struct radeon_encoder_int_tmds *tmds = NULL;
1552 bool ret;
1553
1554 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1555
1556 if (!tmds)
1557 return NULL;
1558
1559 if (rdev->is_atom_bios)
1560 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1561 else
1562 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1563
1564 if (ret == false)
1565 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1566
1567 return tmds;
1568 }
1569
1570 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1571 {
1572 struct drm_device *dev = encoder->base.dev;
1573 struct radeon_device *rdev = dev->dev_private;
1574 struct radeon_encoder_ext_tmds *tmds = NULL;
1575 bool ret;
1576
1577 if (rdev->is_atom_bios)
1578 return NULL;
1579
1580 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1581
1582 if (!tmds)
1583 return NULL;
1584
1585 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1586
1587 if (ret == false)
1588 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1589
1590 return tmds;
1591 }
1592
1593 void
1594 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1595 {
1596 struct radeon_device *rdev = dev->dev_private;
1597 struct drm_encoder *encoder;
1598 struct radeon_encoder *radeon_encoder;
1599
1600 /* see if we already added it */
1601 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1602 radeon_encoder = to_radeon_encoder(encoder);
1603 if (radeon_encoder->encoder_enum == encoder_enum) {
1604 radeon_encoder->devices |= supported_device;
1605 return;
1606 }
1607
1608 }
1609
1610 /* add a new one */
1611 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1612 if (!radeon_encoder)
1613 return;
1614
1615 encoder = &radeon_encoder->base;
1616 if (rdev->flags & RADEON_SINGLE_CRTC)
1617 encoder->possible_crtcs = 0x1;
1618 else
1619 encoder->possible_crtcs = 0x3;
1620
1621 radeon_encoder->enc_priv = NULL;
1622
1623 radeon_encoder->encoder_enum = encoder_enum;
1624 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1625 radeon_encoder->devices = supported_device;
1626 radeon_encoder->rmx_type = RMX_OFF;
1627
1628 switch (radeon_encoder->encoder_id) {
1629 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1630 encoder->possible_crtcs = 0x1;
1631 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1632 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1633 if (rdev->is_atom_bios)
1634 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1635 else
1636 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1637 radeon_encoder->rmx_type = RMX_FULL;
1638 break;
1639 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1640 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1641 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1642 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1643 break;
1644 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1645 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1646 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1647 if (rdev->is_atom_bios)
1648 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1649 else
1650 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1651 break;
1652 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1653 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1654 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1655 if (rdev->is_atom_bios)
1656 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1657 else
1658 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1659 break;
1660 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1661 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1662 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1663 if (!rdev->is_atom_bios)
1664 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1665 break;
1666 }
1667 }
Linux with added FPC-III support