arch/arc/boot/dts/nsim_hs.dts

   1 /*
   2  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 /include/ "skeleton_hs.dtsi"
  11
  12 / {
  13         model = "snps,nsim_hs";
  14         compatible = "snps,nsim_hs";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&core_intc>;
  18
  19         memory {
  20                 device_type = "memory";
  21                 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
  22                 reg = <0x0 0x80000000 0x0 0x20000000    /* 512 MB low mem */
  23                        0x1 0x00000000 0x0 0x40000000>;  /* 1 GB highmem */
  24         };
  25
  26         chosen {
  27                 bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
  28         };
  29
  30         aliases {
  31                 serial0 = &arcuart0;
  32         };
  33
  34         fpga {
  35                 compatible = "simple-bus";
  36                 #address-cells = <1>;
  37                 #size-cells = <1>;
  38
  39                 /* only perip space at end of low mem accessible
  40                          bus addr,   parent bus addr, size */
  41                 ranges = <0x80000000 0x0 0x80000000 0x80000000>;
  42
  43                 core_clk: core_clk {
  44                         #clock-cells = <0>;
  45                         compatible = "fixed-clock";
  46                         clock-frequency = <80000000>;
  47                 };
  48
  49                 core_intc: core-interrupt-controller {
  50                         compatible = "snps,archs-intc";
  51                         interrupt-controller;
  52                         #interrupt-cells = <1>;
  53                 };
  54
  55                 arcuart0: serial@c0fc1000 {
  56                         compatible = "snps,arc-uart";
  57                         reg = <0xc0fc1000 0x100>;
  58                         interrupts = <24>;
  59                         clock-frequency = <80000000>;
  60                         current-speed = <115200>;
  61                         status = "okay";
  62                 };
  63
  64                 arcpct0: pct {
  65                         compatible = "snps,archs-pct";
  66                         #interrupt-cells = <1>;
  67                         interrupts = <20>;
  68                 };
  69         };
  70 };