Linux 4.18.10
[linux/fpc-iii.git] / arch / arc / mm / cache.c
blob25c631942500ffe2802654f6690d9a223e2fbfaf
1 /*
2 * ARC Cache Management
4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/mm.h>
14 #include <linux/sched.h>
15 #include <linux/cache.h>
16 #include <linux/mmu_context.h>
17 #include <linux/syscalls.h>
18 #include <linux/uaccess.h>
19 #include <linux/pagemap.h>
20 #include <asm/cacheflush.h>
21 #include <asm/cachectl.h>
22 #include <asm/setup.h>
24 #ifdef CONFIG_ISA_ARCV2
25 #define USE_RGN_FLSH 1
26 #endif
28 static int l2_line_sz;
29 static int ioc_exists;
30 int slc_enable = 1, ioc_enable = 1;
31 unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
32 unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
34 void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
35 unsigned long sz, const int op, const int full_page);
37 void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz);
38 void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz);
39 void (*__dma_cache_wback)(phys_addr_t start, unsigned long sz);
41 char *arc_cache_mumbojumbo(int c, char *buf, int len)
43 int n = 0;
44 struct cpuinfo_arc_cache *p;
46 #define PR_CACHE(p, cfg, str) \
47 if (!(p)->line_len) \
48 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
49 else \
50 n += scnprintf(buf + n, len - n, \
51 str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \
52 (p)->sz_k, (p)->assoc, (p)->line_len, \
53 (p)->vipt ? "VIPT" : "PIPT", \
54 (p)->alias ? " aliasing" : "", \
55 IS_USED_CFG(cfg));
57 PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache");
58 PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache");
60 p = &cpuinfo_arc700[c].slc;
61 if (p->line_len)
62 n += scnprintf(buf + n, len - n,
63 "SLC\t\t: %uK, %uB Line%s\n",
64 p->sz_k, p->line_len, IS_USED_RUN(slc_enable));
66 n += scnprintf(buf + n, len - n, "Peripherals\t: %#lx%s%s\n",
67 perip_base,
68 IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency "));
70 return buf;
74 * Read the Cache Build Confuration Registers, Decode them and save into
75 * the cpuinfo structure for later use.
76 * No Validation done here, simply read/convert the BCRs
78 static void read_decode_cache_bcr_arcv2(int cpu)
80 struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc;
81 struct bcr_generic sbcr;
83 struct bcr_slc_cfg {
84 #ifdef CONFIG_CPU_BIG_ENDIAN
85 unsigned int pad:24, way:2, lsz:2, sz:4;
86 #else
87 unsigned int sz:4, lsz:2, way:2, pad:24;
88 #endif
89 } slc_cfg;
91 struct bcr_clust_cfg {
92 #ifdef CONFIG_CPU_BIG_ENDIAN
93 unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
94 #else
95 unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
96 #endif
97 } cbcr;
99 struct bcr_volatile {
100 #ifdef CONFIG_CPU_BIG_ENDIAN
101 unsigned int start:4, limit:4, pad:22, order:1, disable:1;
102 #else
103 unsigned int disable:1, order:1, pad:22, limit:4, start:4;
104 #endif
105 } vol;
108 READ_BCR(ARC_REG_SLC_BCR, sbcr);
109 if (sbcr.ver) {
110 READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
111 p_slc->sz_k = 128 << slc_cfg.sz;
112 l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64;
115 READ_BCR(ARC_REG_CLUSTER_BCR, cbcr);
116 if (cbcr.c)
117 ioc_exists = 1;
118 else
119 ioc_enable = 0;
121 /* HS 2.0 didn't have AUX_VOL */
122 if (cpuinfo_arc700[cpu].core.family > 0x51) {
123 READ_BCR(AUX_VOL, vol);
124 perip_base = vol.start << 28;
125 /* HS 3.0 has limit and strict-ordering fields */
126 if (cpuinfo_arc700[cpu].core.family > 0x52)
127 perip_end = (vol.limit << 28) - 1;
131 void read_decode_cache_bcr(void)
133 struct cpuinfo_arc_cache *p_ic, *p_dc;
134 unsigned int cpu = smp_processor_id();
135 struct bcr_cache {
136 #ifdef CONFIG_CPU_BIG_ENDIAN
137 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
138 #else
139 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
140 #endif
141 } ibcr, dbcr;
143 p_ic = &cpuinfo_arc700[cpu].icache;
144 READ_BCR(ARC_REG_IC_BCR, ibcr);
146 if (!ibcr.ver)
147 goto dc_chk;
149 if (ibcr.ver <= 3) {
150 BUG_ON(ibcr.config != 3);
151 p_ic->assoc = 2; /* Fixed to 2w set assoc */
152 } else if (ibcr.ver >= 4) {
153 p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */
156 p_ic->line_len = 8 << ibcr.line_len;
157 p_ic->sz_k = 1 << (ibcr.sz - 1);
158 p_ic->vipt = 1;
159 p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1;
161 dc_chk:
162 p_dc = &cpuinfo_arc700[cpu].dcache;
163 READ_BCR(ARC_REG_DC_BCR, dbcr);
165 if (!dbcr.ver)
166 goto slc_chk;
168 if (dbcr.ver <= 3) {
169 BUG_ON(dbcr.config != 2);
170 p_dc->assoc = 4; /* Fixed to 4w set assoc */
171 p_dc->vipt = 1;
172 p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1;
173 } else if (dbcr.ver >= 4) {
174 p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */
175 p_dc->vipt = 0;
176 p_dc->alias = 0; /* PIPT so can't VIPT alias */
179 p_dc->line_len = 16 << dbcr.line_len;
180 p_dc->sz_k = 1 << (dbcr.sz - 1);
182 slc_chk:
183 if (is_isa_arcv2())
184 read_decode_cache_bcr_arcv2(cpu);
188 * Line Operation on {I,D}-Cache
191 #define OP_INV 0x1
192 #define OP_FLUSH 0x2
193 #define OP_FLUSH_N_INV 0x3
194 #define OP_INV_IC 0x4
197 * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3)
199 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
200 * The orig Cache Management Module "CDU" only required paddr to invalidate a
201 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
202 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
203 * the exact same line.
205 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
206 * paddr alone could not be used to correctly index the cache.
208 * ------------------
209 * MMU v1/v2 (Fixed Page Size 8k)
210 * ------------------
211 * The solution was to provide CDU with these additonal vaddr bits. These
212 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
213 * standard page size of 8k.
214 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
215 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
216 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
217 * represent the offset within cache-line. The adv of using this "clumsy"
218 * interface for additional info was no new reg was needed in CDU programming
219 * model.
221 * 17:13 represented the max num of bits passable, actual bits needed were
222 * fewer, based on the num-of-aliases possible.
223 * -for 2 alias possibility, only bit 13 needed (32K cache)
224 * -for 4 alias possibility, bits 14:13 needed (64K cache)
226 * ------------------
227 * MMU v3
228 * ------------------
229 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
230 * only support 8k (default), 16k and 4k.
231 * However from hardware perspective, smaller page sizes aggravate aliasing
232 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
233 * the existing scheme of piggybacking won't work for certain configurations.
234 * Two new registers IC_PTAG and DC_PTAG inttoduced.
235 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
238 static inline
239 void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
240 unsigned long sz, const int op, const int full_page)
242 unsigned int aux_cmd;
243 int num_lines;
245 if (op == OP_INV_IC) {
246 aux_cmd = ARC_REG_IC_IVIL;
247 } else {
248 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
249 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
252 /* Ensure we properly floor/ceil the non-line aligned/sized requests
253 * and have @paddr - aligned to cache line and integral @num_lines.
254 * This however can be avoided for page sized since:
255 * -@paddr will be cache-line aligned already (being page aligned)
256 * -@sz will be integral multiple of line size (being page sized).
258 if (!full_page) {
259 sz += paddr & ~CACHE_LINE_MASK;
260 paddr &= CACHE_LINE_MASK;
261 vaddr &= CACHE_LINE_MASK;
264 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
266 /* MMUv2 and before: paddr contains stuffed vaddrs bits */
267 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
269 while (num_lines-- > 0) {
270 write_aux_reg(aux_cmd, paddr);
271 paddr += L1_CACHE_BYTES;
276 * For ARC700 MMUv3 I-cache and D-cache flushes
277 * - ARC700 programming model requires paddr and vaddr be passed in seperate
278 * AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the
279 * caches actually alias or not.
280 * - For HS38, only the aliasing I-cache configuration uses the PTAG reg
281 * (non aliasing I-cache version doesn't; while D-cache can't possibly alias)
283 static inline
284 void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
285 unsigned long sz, const int op, const int full_page)
287 unsigned int aux_cmd, aux_tag;
288 int num_lines;
290 if (op == OP_INV_IC) {
291 aux_cmd = ARC_REG_IC_IVIL;
292 aux_tag = ARC_REG_IC_PTAG;
293 } else {
294 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
295 aux_tag = ARC_REG_DC_PTAG;
298 /* Ensure we properly floor/ceil the non-line aligned/sized requests
299 * and have @paddr - aligned to cache line and integral @num_lines.
300 * This however can be avoided for page sized since:
301 * -@paddr will be cache-line aligned already (being page aligned)
302 * -@sz will be integral multiple of line size (being page sized).
304 if (!full_page) {
305 sz += paddr & ~CACHE_LINE_MASK;
306 paddr &= CACHE_LINE_MASK;
307 vaddr &= CACHE_LINE_MASK;
309 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
312 * MMUv3, cache ops require paddr in PTAG reg
313 * if V-P const for loop, PTAG can be written once outside loop
315 if (full_page)
316 write_aux_reg(aux_tag, paddr);
319 * This is technically for MMU v4, using the MMU v3 programming model
320 * Special work for HS38 aliasing I-cache configuration with PAE40
321 * - upper 8 bits of paddr need to be written into PTAG_HI
322 * - (and needs to be written before the lower 32 bits)
323 * Note that PTAG_HI is hoisted outside the line loop
325 if (is_pae40_enabled() && op == OP_INV_IC)
326 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
328 while (num_lines-- > 0) {
329 if (!full_page) {
330 write_aux_reg(aux_tag, paddr);
331 paddr += L1_CACHE_BYTES;
334 write_aux_reg(aux_cmd, vaddr);
335 vaddr += L1_CACHE_BYTES;
339 #ifndef USE_RGN_FLSH
342 * In HS38x (MMU v4), I-cache is VIPT (can alias), D-cache is PIPT
343 * Here's how cache ops are implemented
345 * - D-cache: only paddr needed (in DC_IVDL/DC_FLDL)
346 * - I-cache Non Aliasing: Despite VIPT, only paddr needed (in IC_IVIL)
347 * - I-cache Aliasing: Both vaddr and paddr needed (in IC_IVIL, IC_PTAG
348 * respectively, similar to MMU v3 programming model, hence
349 * __cache_line_loop_v3() is used)
351 * If PAE40 is enabled, independent of aliasing considerations, the higher bits
352 * needs to be written into PTAG_HI
354 static inline
355 void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
356 unsigned long sz, const int op, const int full_page)
358 unsigned int aux_cmd;
359 int num_lines;
361 if (op == OP_INV_IC) {
362 aux_cmd = ARC_REG_IC_IVIL;
363 } else {
364 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
365 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
368 /* Ensure we properly floor/ceil the non-line aligned/sized requests
369 * and have @paddr - aligned to cache line and integral @num_lines.
370 * This however can be avoided for page sized since:
371 * -@paddr will be cache-line aligned already (being page aligned)
372 * -@sz will be integral multiple of line size (being page sized).
374 if (!full_page) {
375 sz += paddr & ~CACHE_LINE_MASK;
376 paddr &= CACHE_LINE_MASK;
379 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
382 * For HS38 PAE40 configuration
383 * - upper 8 bits of paddr need to be written into PTAG_HI
384 * - (and needs to be written before the lower 32 bits)
386 if (is_pae40_enabled()) {
387 if (op == OP_INV_IC)
389 * Non aliasing I-cache in HS38,
390 * aliasing I-cache handled in __cache_line_loop_v3()
392 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
393 else
394 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
397 while (num_lines-- > 0) {
398 write_aux_reg(aux_cmd, paddr);
399 paddr += L1_CACHE_BYTES;
403 #else
406 * optimized flush operation which takes a region as opposed to iterating per line
408 static inline
409 void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
410 unsigned long sz, const int op, const int full_page)
412 unsigned int s, e;
414 /* Only for Non aliasing I-cache in HS38 */
415 if (op == OP_INV_IC) {
416 s = ARC_REG_IC_IVIR;
417 e = ARC_REG_IC_ENDR;
418 } else {
419 s = ARC_REG_DC_STARTR;
420 e = ARC_REG_DC_ENDR;
423 if (!full_page) {
424 /* for any leading gap between @paddr and start of cache line */
425 sz += paddr & ~CACHE_LINE_MASK;
426 paddr &= CACHE_LINE_MASK;
429 * account for any trailing gap to end of cache line
430 * this is equivalent to DIV_ROUND_UP() in line ops above
432 sz += L1_CACHE_BYTES - 1;
435 if (is_pae40_enabled()) {
436 /* TBD: check if crossing 4TB boundary */
437 if (op == OP_INV_IC)
438 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
439 else
440 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
443 /* ENDR needs to be set ahead of START */
444 write_aux_reg(e, paddr + sz); /* ENDR is exclusive */
445 write_aux_reg(s, paddr);
447 /* caller waits on DC_CTRL.FS */
450 #endif
452 #if (CONFIG_ARC_MMU_VER < 3)
453 #define __cache_line_loop __cache_line_loop_v2
454 #elif (CONFIG_ARC_MMU_VER == 3)
455 #define __cache_line_loop __cache_line_loop_v3
456 #elif (CONFIG_ARC_MMU_VER > 3)
457 #define __cache_line_loop __cache_line_loop_v4
458 #endif
460 #ifdef CONFIG_ARC_HAS_DCACHE
462 /***************************************************************
463 * Machine specific helpers for Entire D-Cache or Per Line ops
466 #ifndef USE_RGN_FLSH
468 * this version avoids extra read/write of DC_CTRL for flush or invalid ops
469 * in the non region flush regime (such as for ARCompact)
471 static inline void __before_dc_op(const int op)
473 if (op == OP_FLUSH_N_INV) {
474 /* Dcache provides 2 cmd: FLUSH or INV
475 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
476 * flush-n-inv is achieved by INV cmd but with IM=1
477 * So toggle INV sub-mode depending on op request and default
479 const unsigned int ctl = ARC_REG_DC_CTRL;
480 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);
484 #else
486 static inline void __before_dc_op(const int op)
488 const unsigned int ctl = ARC_REG_DC_CTRL;
489 unsigned int val = read_aux_reg(ctl);
491 if (op == OP_FLUSH_N_INV) {
492 val |= DC_CTRL_INV_MODE_FLUSH;
495 if (op != OP_INV_IC) {
497 * Flush / Invalidate is provided by DC_CTRL.RNG_OP 0 or 1
498 * combined Flush-n-invalidate uses DC_CTRL.IM = 1 set above
500 val &= ~DC_CTRL_RGN_OP_MSK;
501 if (op & OP_INV)
502 val |= DC_CTRL_RGN_OP_INV;
504 write_aux_reg(ctl, val);
507 #endif
510 static inline void __after_dc_op(const int op)
512 if (op & OP_FLUSH) {
513 const unsigned int ctl = ARC_REG_DC_CTRL;
514 unsigned int reg;
516 /* flush / flush-n-inv both wait */
517 while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS)
520 /* Switch back to default Invalidate mode */
521 if (op == OP_FLUSH_N_INV)
522 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);
527 * Operation on Entire D-Cache
528 * @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
529 * Note that constant propagation ensures all the checks are gone
530 * in generated code
532 static inline void __dc_entire_op(const int op)
534 int aux;
536 __before_dc_op(op);
538 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
539 aux = ARC_REG_DC_IVDC;
540 else
541 aux = ARC_REG_DC_FLSH;
543 write_aux_reg(aux, 0x1);
545 __after_dc_op(op);
548 static inline void __dc_disable(void)
550 const int r = ARC_REG_DC_CTRL;
552 __dc_entire_op(OP_FLUSH_N_INV);
553 write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);
556 static void __dc_enable(void)
558 const int r = ARC_REG_DC_CTRL;
560 write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);
563 /* For kernel mappings cache operation: index is same as paddr */
564 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
567 * D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback)
569 static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr,
570 unsigned long sz, const int op)
572 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
573 unsigned long flags;
575 local_irq_save(flags);
577 __before_dc_op(op);
579 __cache_line_loop(paddr, vaddr, sz, op, full_page);
581 __after_dc_op(op);
583 local_irq_restore(flags);
586 #else
588 #define __dc_entire_op(op)
589 #define __dc_disable()
590 #define __dc_enable()
591 #define __dc_line_op(paddr, vaddr, sz, op)
592 #define __dc_line_op_k(paddr, sz, op)
594 #endif /* CONFIG_ARC_HAS_DCACHE */
596 #ifdef CONFIG_ARC_HAS_ICACHE
598 static inline void __ic_entire_inv(void)
600 write_aux_reg(ARC_REG_IC_IVIC, 1);
601 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */
604 static inline void
605 __ic_line_inv_vaddr_local(phys_addr_t paddr, unsigned long vaddr,
606 unsigned long sz)
608 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
609 unsigned long flags;
611 local_irq_save(flags);
612 (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC, full_page);
613 local_irq_restore(flags);
616 #ifndef CONFIG_SMP
618 #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s)
620 #else
622 struct ic_inv_args {
623 phys_addr_t paddr, vaddr;
624 int sz;
627 static void __ic_line_inv_vaddr_helper(void *info)
629 struct ic_inv_args *ic_inv = info;
631 __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz);
634 static void __ic_line_inv_vaddr(phys_addr_t paddr, unsigned long vaddr,
635 unsigned long sz)
637 struct ic_inv_args ic_inv = {
638 .paddr = paddr,
639 .vaddr = vaddr,
640 .sz = sz
643 on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1);
646 #endif /* CONFIG_SMP */
648 #else /* !CONFIG_ARC_HAS_ICACHE */
650 #define __ic_entire_inv()
651 #define __ic_line_inv_vaddr(pstart, vstart, sz)
653 #endif /* CONFIG_ARC_HAS_ICACHE */
655 noinline void slc_op_rgn(phys_addr_t paddr, unsigned long sz, const int op)
657 #ifdef CONFIG_ISA_ARCV2
659 * SLC is shared between all cores and concurrent aux operations from
660 * multiple cores need to be serialized using a spinlock
661 * A concurrent operation can be silently ignored and/or the old/new
662 * operation can remain incomplete forever (lockup in SLC_CTRL_BUSY loop
663 * below)
665 static DEFINE_SPINLOCK(lock);
666 unsigned long flags;
667 unsigned int ctrl;
668 phys_addr_t end;
670 spin_lock_irqsave(&lock, flags);
673 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
674 * - b'000 (default) is Flush,
675 * - b'001 is Invalidate if CTRL.IM == 0
676 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
678 ctrl = read_aux_reg(ARC_REG_SLC_CTRL);
680 /* Don't rely on default value of IM bit */
681 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
682 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
683 else
684 ctrl |= SLC_CTRL_IM;
686 if (op & OP_INV)
687 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
688 else
689 ctrl &= ~SLC_CTRL_RGN_OP_INV;
691 write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
694 * Lower bits are ignored, no need to clip
695 * END needs to be setup before START (latter triggers the operation)
696 * END can't be same as START, so add (l2_line_sz - 1) to sz
698 end = paddr + sz + l2_line_sz - 1;
699 if (is_pae40_enabled())
700 write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
702 write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
704 if (is_pae40_enabled())
705 write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
707 write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
709 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
710 read_aux_reg(ARC_REG_SLC_CTRL);
712 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
714 spin_unlock_irqrestore(&lock, flags);
715 #endif
718 noinline void slc_op_line(phys_addr_t paddr, unsigned long sz, const int op)
720 #ifdef CONFIG_ISA_ARCV2
722 * SLC is shared between all cores and concurrent aux operations from
723 * multiple cores need to be serialized using a spinlock
724 * A concurrent operation can be silently ignored and/or the old/new
725 * operation can remain incomplete forever (lockup in SLC_CTRL_BUSY loop
726 * below)
728 static DEFINE_SPINLOCK(lock);
730 const unsigned long SLC_LINE_MASK = ~(l2_line_sz - 1);
731 unsigned int ctrl, cmd;
732 unsigned long flags;
733 int num_lines;
735 spin_lock_irqsave(&lock, flags);
737 ctrl = read_aux_reg(ARC_REG_SLC_CTRL);
739 /* Don't rely on default value of IM bit */
740 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
741 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
742 else
743 ctrl |= SLC_CTRL_IM;
745 write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
747 cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
749 sz += paddr & ~SLC_LINE_MASK;
750 paddr &= SLC_LINE_MASK;
752 num_lines = DIV_ROUND_UP(sz, l2_line_sz);
754 while (num_lines-- > 0) {
755 write_aux_reg(cmd, paddr);
756 paddr += l2_line_sz;
759 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
760 read_aux_reg(ARC_REG_SLC_CTRL);
762 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
764 spin_unlock_irqrestore(&lock, flags);
765 #endif
768 #define slc_op(paddr, sz, op) slc_op_rgn(paddr, sz, op)
770 noinline static void slc_entire_op(const int op)
772 unsigned int ctrl, r = ARC_REG_SLC_CTRL;
774 ctrl = read_aux_reg(r);
776 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
777 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
778 else
779 ctrl |= SLC_CTRL_IM;
781 write_aux_reg(r, ctrl);
783 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
784 write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);
785 else
786 write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);
788 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
789 read_aux_reg(r);
791 /* Important to wait for flush to complete */
792 while (read_aux_reg(r) & SLC_CTRL_BUSY);
795 static inline void arc_slc_disable(void)
797 const int r = ARC_REG_SLC_CTRL;
799 slc_entire_op(OP_FLUSH_N_INV);
800 write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);
803 static inline void arc_slc_enable(void)
805 const int r = ARC_REG_SLC_CTRL;
807 write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);
810 /***********************************************************
811 * Exported APIs
815 * Handle cache congruency of kernel and userspace mappings of page when kernel
816 * writes-to/reads-from
818 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
819 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
820 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
821 * -In SMP, if hardware caches are coherent
823 * There's a corollary case, where kernel READs from a userspace mapped page.
824 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
826 void flush_dcache_page(struct page *page)
828 struct address_space *mapping;
830 if (!cache_is_vipt_aliasing()) {
831 clear_bit(PG_dc_clean, &page->flags);
832 return;
835 /* don't handle anon pages here */
836 mapping = page_mapping_file(page);
837 if (!mapping)
838 return;
841 * pagecache page, file not yet mapped to userspace
842 * Make a note that K-mapping is dirty
844 if (!mapping_mapped(mapping)) {
845 clear_bit(PG_dc_clean, &page->flags);
846 } else if (page_mapcount(page)) {
848 /* kernel reading from page with U-mapping */
849 phys_addr_t paddr = (unsigned long)page_address(page);
850 unsigned long vaddr = page->index << PAGE_SHIFT;
852 if (addr_not_cache_congruent(paddr, vaddr))
853 __flush_dcache_page(paddr, vaddr);
856 EXPORT_SYMBOL(flush_dcache_page);
859 * DMA ops for systems with L1 cache only
860 * Make memory coherent with L1 cache by flushing/invalidating L1 lines
862 static void __dma_cache_wback_inv_l1(phys_addr_t start, unsigned long sz)
864 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
867 static void __dma_cache_inv_l1(phys_addr_t start, unsigned long sz)
869 __dc_line_op_k(start, sz, OP_INV);
872 static void __dma_cache_wback_l1(phys_addr_t start, unsigned long sz)
874 __dc_line_op_k(start, sz, OP_FLUSH);
878 * DMA ops for systems with both L1 and L2 caches, but without IOC
879 * Both L1 and L2 lines need to be explicitly flushed/invalidated
881 static void __dma_cache_wback_inv_slc(phys_addr_t start, unsigned long sz)
883 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
884 slc_op(start, sz, OP_FLUSH_N_INV);
887 static void __dma_cache_inv_slc(phys_addr_t start, unsigned long sz)
889 __dc_line_op_k(start, sz, OP_INV);
890 slc_op(start, sz, OP_INV);
893 static void __dma_cache_wback_slc(phys_addr_t start, unsigned long sz)
895 __dc_line_op_k(start, sz, OP_FLUSH);
896 slc_op(start, sz, OP_FLUSH);
900 * DMA ops for systems with IOC
901 * IOC hardware snoops all DMA traffic keeping the caches consistent with
902 * memory - eliding need for any explicit cache maintenance of DMA buffers
904 static void __dma_cache_wback_inv_ioc(phys_addr_t start, unsigned long sz) {}
905 static void __dma_cache_inv_ioc(phys_addr_t start, unsigned long sz) {}
906 static void __dma_cache_wback_ioc(phys_addr_t start, unsigned long sz) {}
909 * Exported DMA API
911 void dma_cache_wback_inv(phys_addr_t start, unsigned long sz)
913 __dma_cache_wback_inv(start, sz);
915 EXPORT_SYMBOL(dma_cache_wback_inv);
917 void dma_cache_inv(phys_addr_t start, unsigned long sz)
919 __dma_cache_inv(start, sz);
921 EXPORT_SYMBOL(dma_cache_inv);
923 void dma_cache_wback(phys_addr_t start, unsigned long sz)
925 __dma_cache_wback(start, sz);
927 EXPORT_SYMBOL(dma_cache_wback);
930 * This is API for making I/D Caches consistent when modifying
931 * kernel code (loadable modules, kprobes, kgdb...)
932 * This is called on insmod, with kernel virtual address for CODE of
933 * the module. ARC cache maintenance ops require PHY address thus we
934 * need to convert vmalloc addr to PHY addr
936 void flush_icache_range(unsigned long kstart, unsigned long kend)
938 unsigned int tot_sz;
940 WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__);
942 /* Shortcut for bigger flush ranges.
943 * Here we don't care if this was kernel virtual or phy addr
945 tot_sz = kend - kstart;
946 if (tot_sz > PAGE_SIZE) {
947 flush_cache_all();
948 return;
951 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
952 if (likely(kstart > PAGE_OFFSET)) {
954 * The 2nd arg despite being paddr will be used to index icache
955 * This is OK since no alternate virtual mappings will exist
956 * given the callers for this case: kprobe/kgdb in built-in
957 * kernel code only.
959 __sync_icache_dcache(kstart, kstart, kend - kstart);
960 return;
964 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
965 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
966 * handling of kernel vaddr.
968 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
969 * it still needs to handle a 2 page scenario, where the range
970 * straddles across 2 virtual pages and hence need for loop
972 while (tot_sz > 0) {
973 unsigned int off, sz;
974 unsigned long phy, pfn;
976 off = kstart % PAGE_SIZE;
977 pfn = vmalloc_to_pfn((void *)kstart);
978 phy = (pfn << PAGE_SHIFT) + off;
979 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
980 __sync_icache_dcache(phy, kstart, sz);
981 kstart += sz;
982 tot_sz -= sz;
985 EXPORT_SYMBOL(flush_icache_range);
988 * General purpose helper to make I and D cache lines consistent.
989 * @paddr is phy addr of region
990 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
991 * However in one instance, when called by kprobe (for a breakpt in
992 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
993 * use a paddr to index the cache (despite VIPT). This is fine since since a
994 * builtin kernel page will not have any virtual mappings.
995 * kprobe on loadable module will be kernel vaddr.
997 void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len)
999 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV);
1000 __ic_line_inv_vaddr(paddr, vaddr, len);
1003 /* wrapper to compile time eliminate alignment checks in flush loop */
1004 void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
1006 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
1010 * wrapper to clearout kernel or userspace mappings of a page
1011 * For kernel mappings @vaddr == @paddr
1013 void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr)
1015 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
1018 noinline void flush_cache_all(void)
1020 unsigned long flags;
1022 local_irq_save(flags);
1024 __ic_entire_inv();
1025 __dc_entire_op(OP_FLUSH_N_INV);
1027 local_irq_restore(flags);
1031 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
1033 void flush_cache_mm(struct mm_struct *mm)
1035 flush_cache_all();
1038 void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
1039 unsigned long pfn)
1041 phys_addr_t paddr = pfn << PAGE_SHIFT;
1043 u_vaddr &= PAGE_MASK;
1045 __flush_dcache_page(paddr, u_vaddr);
1047 if (vma->vm_flags & VM_EXEC)
1048 __inv_icache_page(paddr, u_vaddr);
1051 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1052 unsigned long end)
1054 flush_cache_all();
1057 void flush_anon_page(struct vm_area_struct *vma, struct page *page,
1058 unsigned long u_vaddr)
1060 /* TBD: do we really need to clear the kernel mapping */
1061 __flush_dcache_page((phys_addr_t)page_address(page), u_vaddr);
1062 __flush_dcache_page((phys_addr_t)page_address(page),
1063 (phys_addr_t)page_address(page));
1067 #endif
1069 void copy_user_highpage(struct page *to, struct page *from,
1070 unsigned long u_vaddr, struct vm_area_struct *vma)
1072 void *kfrom = kmap_atomic(from);
1073 void *kto = kmap_atomic(to);
1074 int clean_src_k_mappings = 0;
1077 * If SRC page was already mapped in userspace AND it's U-mapping is
1078 * not congruent with K-mapping, sync former to physical page so that
1079 * K-mapping in memcpy below, sees the right data
1081 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is
1082 * equally valid for SRC page as well
1084 * For !VIPT cache, all of this gets compiled out as
1085 * addr_not_cache_congruent() is 0
1087 if (page_mapcount(from) && addr_not_cache_congruent(kfrom, u_vaddr)) {
1088 __flush_dcache_page((unsigned long)kfrom, u_vaddr);
1089 clean_src_k_mappings = 1;
1092 copy_page(kto, kfrom);
1095 * Mark DST page K-mapping as dirty for a later finalization by
1096 * update_mmu_cache(). Although the finalization could have been done
1097 * here as well (given that both vaddr/paddr are available).
1098 * But update_mmu_cache() already has code to do that for other
1099 * non copied user pages (e.g. read faults which wire in pagecache page
1100 * directly).
1102 clear_bit(PG_dc_clean, &to->flags);
1105 * if SRC was already usermapped and non-congruent to kernel mapping
1106 * sync the kernel mapping back to physical page
1108 if (clean_src_k_mappings) {
1109 __flush_dcache_page((unsigned long)kfrom, (unsigned long)kfrom);
1110 set_bit(PG_dc_clean, &from->flags);
1111 } else {
1112 clear_bit(PG_dc_clean, &from->flags);
1115 kunmap_atomic(kto);
1116 kunmap_atomic(kfrom);
1119 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
1121 clear_page(to);
1122 clear_bit(PG_dc_clean, &page->flags);
1126 /**********************************************************************
1127 * Explicit Cache flush request from user space via syscall
1128 * Needed for JITs which generate code on the fly
1130 SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
1132 /* TBD: optimize this */
1133 flush_cache_all();
1134 return 0;
1138 * IO-Coherency (IOC) setup rules:
1140 * 1. Needs to be at system level, so only once by Master core
1141 * Non-Masters need not be accessing caches at that time
1142 * - They are either HALT_ON_RESET and kick started much later or
1143 * - if run on reset, need to ensure that arc_platform_smp_wait_to_boot()
1144 * doesn't perturb caches or coherency unit
1146 * 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
1147 * otherwise any straggler data might behave strangely post IOC enabling
1149 * 3. All Caches need to be disabled when setting up IOC to elide any in-flight
1150 * Coherency transactions
1152 noinline void __init arc_ioc_setup(void)
1154 unsigned int ioc_base, mem_sz;
1156 /* Flush + invalidate + disable L1 dcache */
1157 __dc_disable();
1159 /* Flush + invalidate SLC */
1160 if (read_aux_reg(ARC_REG_SLC_BCR))
1161 slc_entire_op(OP_FLUSH_N_INV);
1164 * currently IOC Aperture covers entire DDR
1165 * TBD: fix for PGU + 1GB of low mem
1166 * TBD: fix for PAE
1168 mem_sz = arc_get_mem_sz();
1170 if (!is_power_of_2(mem_sz) || mem_sz < 4096)
1171 panic("IOC Aperture size must be power of 2 larger than 4KB");
1174 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
1175 * so setting 0x11 implies 512MB, 0x12 implies 1GB...
1177 write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2);
1179 /* for now assume kernel base is start of IOC aperture */
1180 ioc_base = CONFIG_LINUX_RAM_BASE;
1182 if (ioc_base % mem_sz != 0)
1183 panic("IOC Aperture start must be aligned to the size of the aperture");
1185 write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);
1186 write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
1187 write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
1189 /* Re-enable L1 dcache */
1190 __dc_enable();
1194 * Cache related boot time checks/setups only needed on master CPU:
1195 * - Geometry checks (kernel build and hardware agree: e.g. L1_CACHE_BYTES)
1196 * Assume SMP only, so all cores will have same cache config. A check on
1197 * one core suffices for all
1198 * - IOC setup / dma callbacks only need to be done once
1200 void __init arc_cache_init_master(void)
1202 unsigned int __maybe_unused cpu = smp_processor_id();
1204 if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
1205 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
1207 if (!ic->line_len)
1208 panic("cache support enabled but non-existent cache\n");
1210 if (ic->line_len != L1_CACHE_BYTES)
1211 panic("ICache line [%d] != kernel Config [%d]",
1212 ic->line_len, L1_CACHE_BYTES);
1215 * In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG
1216 * pair to provide vaddr/paddr respectively, just as in MMU v3
1218 if (is_isa_arcv2() && ic->alias)
1219 _cache_line_loop_ic_fn = __cache_line_loop_v3;
1220 else
1221 _cache_line_loop_ic_fn = __cache_line_loop;
1224 if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {
1225 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
1227 if (!dc->line_len)
1228 panic("cache support enabled but non-existent cache\n");
1230 if (dc->line_len != L1_CACHE_BYTES)
1231 panic("DCache line [%d] != kernel Config [%d]",
1232 dc->line_len, L1_CACHE_BYTES);
1234 /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */
1235 if (is_isa_arcompact()) {
1236 int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
1237 int num_colors = dc->sz_k/dc->assoc/TO_KB(PAGE_SIZE);
1239 if (dc->alias) {
1240 if (!handled)
1241 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
1242 if (CACHE_COLORS_NUM != num_colors)
1243 panic("CACHE_COLORS_NUM not optimized for config\n");
1244 } else if (!dc->alias && handled) {
1245 panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
1251 * Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger
1252 * or equal to any cache line length.
1254 BUILD_BUG_ON_MSG(L1_CACHE_BYTES > SMP_CACHE_BYTES,
1255 "SMP_CACHE_BYTES must be >= any cache line length");
1256 if (is_isa_arcv2() && (l2_line_sz > SMP_CACHE_BYTES))
1257 panic("L2 Cache line [%d] > kernel Config [%d]\n",
1258 l2_line_sz, SMP_CACHE_BYTES);
1260 /* Note that SLC disable not formally supported till HS 3.0 */
1261 if (is_isa_arcv2() && l2_line_sz && !slc_enable)
1262 arc_slc_disable();
1264 if (is_isa_arcv2() && ioc_enable)
1265 arc_ioc_setup();
1267 if (is_isa_arcv2() && ioc_enable) {
1268 __dma_cache_wback_inv = __dma_cache_wback_inv_ioc;
1269 __dma_cache_inv = __dma_cache_inv_ioc;
1270 __dma_cache_wback = __dma_cache_wback_ioc;
1271 } else if (is_isa_arcv2() && l2_line_sz && slc_enable) {
1272 __dma_cache_wback_inv = __dma_cache_wback_inv_slc;
1273 __dma_cache_inv = __dma_cache_inv_slc;
1274 __dma_cache_wback = __dma_cache_wback_slc;
1275 } else {
1276 __dma_cache_wback_inv = __dma_cache_wback_inv_l1;
1277 __dma_cache_inv = __dma_cache_inv_l1;
1278 __dma_cache_wback = __dma_cache_wback_l1;
1282 void __ref arc_cache_init(void)
1284 unsigned int __maybe_unused cpu = smp_processor_id();
1285 char str[256];
1287 pr_info("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
1289 if (!cpu)
1290 arc_cache_init_master();
1293 * In PAE regime, TLB and cache maintenance ops take wider addresses
1294 * And even if PAE is not enabled in kernel, the upper 32-bits still need
1295 * to be zeroed to keep the ops sane.
1296 * As an optimization for more common !PAE enabled case, zero them out
1297 * once at init, rather than checking/setting to 0 for every runtime op
1299 if (is_isa_arcv2() && pae40_exist_but_not_enab()) {
1301 if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE))
1302 write_aux_reg(ARC_REG_IC_PTAG_HI, 0);
1304 if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE))
1305 write_aux_reg(ARC_REG_DC_PTAG_HI, 0);
1307 if (l2_line_sz) {
1308 write_aux_reg(ARC_REG_SLC_RGN_END1, 0);
1309 write_aux_reg(ARC_REG_SLC_RGN_START1, 0);