arch/arc/plat-axs10x/axs10x.c

   1 /*
   2  * AXS101/AXS103 Software Development Platform
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/of_fdt.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/libfdt.h>
  20
  21 #include <asm/asm-offsets.h>
  22 #include <asm/io.h>
  23 #include <asm/mach_desc.h>
  24 #include <soc/arc/mcip.h>
  25
  26 #define AXS_MB_CGU              0xE0010000
  27 #define AXS_MB_CREG             0xE0011000
  28
  29 #define CREG_MB_IRQ_MUX         (AXS_MB_CREG + 0x214)
  30 #define CREG_MB_SW_RESET        (AXS_MB_CREG + 0x220)
  31 #define CREG_MB_VER             (AXS_MB_CREG + 0x230)
  32 #define CREG_MB_CONFIG          (AXS_MB_CREG + 0x234)
  33
  34 #define AXC001_CREG             0xF0001000
  35 #define AXC001_GPIO_INTC        0xF0003000
  36
  37 static void __init axs10x_enable_gpio_intc_wire(void)
  38 {
  39         /*
  40          * Peripherals on CPU Card and Mother Board are wired to cpu intc via
  41          * intermediate DW APB GPIO blocks (mainly for debouncing)
  42          *
  43          *         ---------------------
  44          *        |  snps,arc700-intc |
  45          *        ---------------------
  46          *          | #7          | #15
  47          * -------------------   -------------------
  48          * | snps,dw-apb-gpio |  | snps,dw-apb-gpio |
  49          * -------------------   -------------------
  50          *        | #12                     |
  51          *        |                 [ Debug UART on cpu card ]
  52          *        |
  53          * ------------------------
  54          * | snps,dw-apb-intc (MB)|
  55          * ------------------------
  56          *  |      |       |      |
  57          * [eth] [uart]        [... other perip on Main Board]
  58          *
  59          * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
  60          * with stacked INTCs. In particular problem happens if its master INTC
  61          * not yet instantiated. See discussion here -
  62          * https://lkml.org/lkml/2015/3/4/755
  63          *
  64          * So setup the first gpio block as a passive pass thru and hide it from
  65          * DT hardware topology - connect MB intc directly to cpu intc
  66          * The GPIO "wire" needs to be init nevertheless (here)
  67          *
  68          * One side adv is that peripheral interrupt handling avoids one nested
  69          * intc ISR hop
  70          */
  71 #define GPIO_INTEN              (AXC001_GPIO_INTC + 0x30)
  72 #define GPIO_INTMASK            (AXC001_GPIO_INTC + 0x34)
  73 #define GPIO_INTTYPE_LEVEL      (AXC001_GPIO_INTC + 0x38)
  74 #define GPIO_INT_POLARITY       (AXC001_GPIO_INTC + 0x3c)
  75 #define MB_TO_GPIO_IRQ          12
  76
  77         iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
  78         iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
  79         iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
  80         iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
  81 }
  82
  83 static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
  84 {
  85         union ver {
  86                 struct {
  87 #ifdef CONFIG_CPU_BIG_ENDIAN
  88                         unsigned int pad:11, y:12, m:4, d:5;
  89 #else
  90                         unsigned int d:5, m:4, y:12, pad:11;
  91 #endif
  92                 };
  93                 unsigned int val;
  94         } board;
  95
  96         board.val = ioread32((void __iomem *)creg);
  97         pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
  98                 board.y);
  99 }
 100
 101 static void __init axs10x_early_init(void)
 102 {
 103         int mb_rev;
 104         char mb[32];
 105
 106         /* Determine motherboard version */
 107         if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
 108                 mb_rev = 3;     /* HT-3 (rev3.0) */
 109         else
 110                 mb_rev = 2;     /* HT-2 (rev2.0) */
 111
 112         axs10x_enable_gpio_intc_wire();
 113
 114         scnprintf(mb, 32, "MainBoard v%d", mb_rev);
 115         axs10x_print_board_ver(CREG_MB_VER, mb);
 116 }
 117
 118 #ifdef CONFIG_AXS101
 119
 120 #define CREG_CPU_ADDR_770       (AXC001_CREG + 0x20)
 121 #define CREG_CPU_ADDR_TUNN      (AXC001_CREG + 0x60)
 122 #define CREG_CPU_ADDR_770_UPD   (AXC001_CREG + 0x34)
 123 #define CREG_CPU_ADDR_TUNN_UPD  (AXC001_CREG + 0x74)
 124
 125 #define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
 126 #define CREG_CPU_GPIO_UART_MUX  (AXC001_CREG + 0x120)
 127
 128 /*
 129  * Set up System Memory Map for ARC cpu / peripherals controllers
 130  *
 131  * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
 132  * of which maps to a corresponding 256MB aperture in Target slave memory map.
 133  *
 134  * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
 135  * (0x0000_0000) of DDR Port 0 (slave #1)
 136  *
 137  * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
 138  * which has master/slaves on both ends.
 139  * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
 140  * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
 141  * MB AXI Tunnel Master, which also has a mem map setup
 142  *
 143  * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
 144  * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
 145  */
 146 struct aperture {
 147         unsigned int slave_sel:4, slave_off:4, pad:24;
 148 };
 149
 150 /* CPU Card target slaves */
 151 #define AXC001_SLV_NONE                 0
 152 #define AXC001_SLV_DDR_PORT0            1
 153 #define AXC001_SLV_SRAM                 2
 154 #define AXC001_SLV_AXI_TUNNEL           3
 155 #define AXC001_SLV_AXI2APB              6
 156 #define AXC001_SLV_DDR_PORT1            7
 157
 158 /* MB AXI Target slaves */
 159 #define AXS_MB_SLV_NONE                 0
 160 #define AXS_MB_SLV_AXI_TUNNEL_CPU       1
 161 #define AXS_MB_SLV_AXI_TUNNEL_HAPS      2
 162 #define AXS_MB_SLV_SRAM                 3
 163 #define AXS_MB_SLV_CONTROL              4
 164
 165 /* MB AXI masters */
 166 #define AXS_MB_MST_TUNNEL_CPU           0
 167 #define AXS_MB_MST_USB_OHCI             10
 168
 169 /*
 170  * memmap for ARC core on CPU Card
 171  */
 172 static const struct aperture axc001_memmap[16] = {
 173         {AXC001_SLV_AXI_TUNNEL,         0x0},
 174         {AXC001_SLV_AXI_TUNNEL,         0x1},
 175         {AXC001_SLV_SRAM,               0x0}, /* 0x2000_0000: Local SRAM */
 176         {AXC001_SLV_NONE,               0x0},
 177         {AXC001_SLV_NONE,               0x0},
 178         {AXC001_SLV_NONE,               0x0},
 179         {AXC001_SLV_NONE,               0x0},
 180         {AXC001_SLV_NONE,               0x0},
 181         {AXC001_SLV_DDR_PORT0,          0x0}, /* 0x8000_0000: DDR   0..256M */
 182         {AXC001_SLV_DDR_PORT0,          0x1}, /* 0x9000_0000: DDR 256..512M */
 183         {AXC001_SLV_DDR_PORT0,          0x2},
 184         {AXC001_SLV_DDR_PORT0,          0x3},
 185         {AXC001_SLV_NONE,               0x0},
 186         {AXC001_SLV_AXI_TUNNEL,         0xD},
 187         {AXC001_SLV_AXI_TUNNEL,         0xE}, /* MB: CREG, CGU... */
 188         {AXC001_SLV_AXI2APB,            0x0}, /* CPU Card local CREG, CGU... */
 189 };
 190
 191 /*
 192  * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
 193  * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
 194  */
 195 static const struct aperture axc001_axi_tunnel_memmap[16] = {
 196         {AXC001_SLV_AXI_TUNNEL,         0x0},
 197         {AXC001_SLV_AXI_TUNNEL,         0x1},
 198         {AXC001_SLV_SRAM,               0x0},
 199         {AXC001_SLV_NONE,               0x0},
 200         {AXC001_SLV_NONE,               0x0},
 201         {AXC001_SLV_NONE,               0x0},
 202         {AXC001_SLV_NONE,               0x0},
 203         {AXC001_SLV_NONE,               0x0},
 204         {AXC001_SLV_DDR_PORT1,          0x0},
 205         {AXC001_SLV_DDR_PORT1,          0x1},
 206         {AXC001_SLV_DDR_PORT1,          0x2},
 207         {AXC001_SLV_DDR_PORT1,          0x3},
 208         {AXC001_SLV_NONE,               0x0},
 209         {AXC001_SLV_AXI_TUNNEL,         0xD},
 210         {AXC001_SLV_AXI_TUNNEL,         0xE},
 211         {AXC001_SLV_AXI2APB,            0x0},
 212 };
 213
 214 /*
 215  * memmap for MB AXI Masters
 216  * Same mem map for all perip controllers as well as MB AXI Tunnel Master
 217  */
 218 static const struct aperture axs_mb_memmap[16] = {
 219         {AXS_MB_SLV_SRAM,               0x0},
 220         {AXS_MB_SLV_SRAM,               0x0},
 221         {AXS_MB_SLV_NONE,               0x0},
 222         {AXS_MB_SLV_NONE,               0x0},
 223         {AXS_MB_SLV_NONE,               0x0},
 224         {AXS_MB_SLV_NONE,               0x0},
 225         {AXS_MB_SLV_NONE,               0x0},
 226         {AXS_MB_SLV_NONE,               0x0},
 227         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0x8},   /* DDR on CPU Card */
 228         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0x9},   /* DDR on CPU Card */
 229         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0xA},
 230         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0xB},
 231         {AXS_MB_SLV_NONE,               0x0},
 232         {AXS_MB_SLV_AXI_TUNNEL_HAPS,    0xD},
 233         {AXS_MB_SLV_CONTROL,            0x0},   /* MB Local CREG, CGU... */
 234         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0xF},
 235 };
 236
 237 static noinline void __init
 238 axs101_set_memmap(void __iomem *base, const struct aperture map[16])
 239 {
 240         unsigned int slave_select, slave_offset;
 241         int i;
 242
 243         slave_select = slave_offset = 0;
 244         for (i = 0; i < 8; i++) {
 245                 slave_select |= map[i].slave_sel << (i << 2);
 246                 slave_offset |= map[i].slave_off << (i << 2);
 247         }
 248
 249         iowrite32(slave_select, base + 0x0);    /* SLV0 */
 250         iowrite32(slave_offset, base + 0x8);    /* OFFSET0 */
 251
 252         slave_select = slave_offset = 0;
 253         for (i = 0; i < 8; i++) {
 254                 slave_select |= map[i+8].slave_sel << (i << 2);
 255                 slave_offset |= map[i+8].slave_off << (i << 2);
 256         }
 257
 258         iowrite32(slave_select, base + 0x4);    /* SLV1 */
 259         iowrite32(slave_offset, base + 0xC);    /* OFFSET1 */
 260 }
 261
 262 static void __init axs101_early_init(void)
 263 {
 264         int i;
 265
 266         /* ARC 770D memory view */
 267         axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
 268         iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
 269
 270         /* AXI tunnel memory map (incoming traffic from MB into CPU Card */
 271         axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
 272                               axc001_axi_tunnel_memmap);
 273         iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
 274
 275         /* MB peripherals memory map */
 276         for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
 277                 axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
 278                                       axs_mb_memmap);
 279
 280         iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */
 281
 282         /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
 283         iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
 284
 285         /* Set up the MB interrupt system: mux interrupts to GPIO7) */
 286         iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
 287
 288         /* reset ethernet and ULPI interfaces */
 289         iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
 290
 291         /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
 292         iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
 293
 294         axs10x_early_init();
 295 }
 296
 297 #endif  /* CONFIG_AXS101 */
 298
 299 #ifdef CONFIG_AXS103
 300
 301 #define AXC003_CREG     0xF0001000
 302 #define AXC003_MST_AXI_TUNNEL   0
 303 #define AXC003_MST_HS38         1
 304
 305 #define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440)
 306 #define CREG_CPU_GPIO_UART_MUX  (AXC003_CREG + 0x480)
 307 #define CREG_CPU_TUN_IO_CTRL    (AXC003_CREG + 0x494)
 308
 309
 310 static void __init axs103_early_init(void)
 311 {
 312 #ifdef CONFIG_ARC_MCIP
 313         /*
 314          * AXS103 configurations for SMP/QUAD configurations share device tree
 315          * which defaults to 100 MHz. However recent failures of Quad config
 316          * revealed P&R timing violations so clamp it down to safe 50 MHz
 317          * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
 318          * of fudging the freq in DT
 319          */
 320 #define AXS103_QUAD_CORE_CPU_FREQ_HZ    50000000
 321
 322         unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
 323         if (num_cores > 2) {
 324                 u32 freq;
 325                 int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
 326                 const struct fdt_property *prop;
 327
 328                 prop = fdt_get_property(initial_boot_params, off,
 329                                         "assigned-clock-rates", NULL);
 330                 freq = be32_to_cpu(*(u32 *)(prop->data));
 331
 332                 /* Patching .dtb in-place with new core clock value */
 333                 if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) {
 334                         freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ);
 335                         fdt_setprop_inplace(initial_boot_params, off,
 336                                             "assigned-clock-rates", &freq, sizeof(freq));
 337                 }
 338         }
 339 #endif
 340
 341         /* Memory maps already config in pre-bootloader */
 342
 343         /* set GPIO mux to UART */
 344         iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
 345
 346         iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
 347                   (void __iomem *) CREG_CPU_TUN_IO_CTRL);
 348
 349         /* Set up the AXS_MB interrupt system.*/
 350         iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
 351                                          + (AXC003_MST_HS38 << 2)));
 352
 353         /* connect ICTL - Main Board with GPIO line */
 354         iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
 355
 356         axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
 357
 358         axs10x_early_init();
 359 }
 360 #endif
 361
 362 #ifdef CONFIG_AXS101
 363
 364 static const char *axs101_compat[] __initconst = {
 365         "snps,axs101",
 366         NULL,
 367 };
 368
 369 MACHINE_START(AXS101, "axs101")
 370         .dt_compat      = axs101_compat,
 371         .init_early     = axs101_early_init,
 372 MACHINE_END
 373
 374 #endif  /* CONFIG_AXS101 */
 375
 376 #ifdef CONFIG_AXS103
 377
 378 static const char *axs103_compat[] __initconst = {
 379         "snps,axs103",
 380         NULL,
 381 };
 382
 383 MACHINE_START(AXS103, "axs103")
 384         .dt_compat      = axs103_compat,
 385         .init_early     = axs103_early_init,
 386 MACHINE_END
 387
 388 /*
 389  * For the VDK OS-kit, to get the offset to pid and command fields
 390  */
 391 char coware_swa_pid_offset[TASK_PID];
 392 char coware_swa_comm_offset[TASK_COMM];
 393
 394 #endif  /* CONFIG_AXS103 */