| blob | 843edfd000be7210ebef62e529ba074df5ee242f |
1 # SPDX-License-Identifier: GPL-2.0
2 config ARM
3 bool
4 default y
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KCOV
12 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
13 select ARCH_HAS_PHYS_TO_DMA
14 select ARCH_HAS_SET_MEMORY
15 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
16 select ARCH_HAS_STRICT_MODULE_RWX if MMU
17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
18 select ARCH_HAVE_CUSTOM_GPIO_H
19 select ARCH_HAS_GCOV_PROFILE_ALL
20 select ARCH_MIGHT_HAVE_PC_PARPORT
21 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
23 select ARCH_SUPPORTS_ATOMIC_RMW
24 select ARCH_USE_BUILTIN_BSWAP
25 select ARCH_USE_CMPXCHG_LOCKREF
26 select ARCH_WANT_IPC_PARSE_VERSION
27 select BUILDTIME_EXTABLE_SORT if MMU
28 select CLONE_BACKWARDS
29 select CPU_PM if (SUSPEND || CPU_IDLE)
30 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
31 select DMA_DIRECT_OPS if !MMU
32 select EDAC_SUPPORT
33 select EDAC_ATOMIC_SCRUB
34 select GENERIC_ALLOCATOR
35 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
36 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
37 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
38 select GENERIC_CPU_AUTOPROBE
39 select GENERIC_EARLY_IOREMAP
40 select GENERIC_IDLE_POLL_SETUP
41 select GENERIC_IRQ_PROBE
42 select GENERIC_IRQ_SHOW
43 select GENERIC_IRQ_SHOW_LEVEL
44 select GENERIC_PCI_IOMAP
45 select GENERIC_SCHED_CLOCK
46 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_STRNCPY_FROM_USER
48 select GENERIC_STRNLEN_USER
49 select HANDLE_DOMAIN_IRQ
50 select HARDIRQS_SW_RESEND
51 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
52 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
53 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
54 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
55 select HAVE_ARCH_MMAP_RND_BITS if MMU
56 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
57 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
58 select HAVE_ARCH_TRACEHOOK
59 select HAVE_ARM_SMCCC if CPU_V7
60 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
61 select HAVE_CONTEXT_TRACKING
62 select HAVE_C_RECORDMCOUNT
63 select HAVE_DEBUG_KMEMLEAK
64 select HAVE_DMA_CONTIGUOUS if MMU
65 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
66 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
67 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
68 select HAVE_EXIT_THREAD
69 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
70 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
71 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
72 select HAVE_GCC_PLUGINS
73 select HAVE_GENERIC_DMA_COHERENT
74 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
75 select HAVE_IDE if PCI || ISA || PCMCIA
76 select HAVE_IRQ_TIME_ACCOUNTING
77 select HAVE_KERNEL_GZIP
78 select HAVE_KERNEL_LZ4
79 select HAVE_KERNEL_LZMA
80 select HAVE_KERNEL_LZO
81 select HAVE_KERNEL_XZ
82 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
83 select HAVE_KRETPROBES if (HAVE_KPROBES)
84 select HAVE_MEMBLOCK
85 select HAVE_MOD_ARCH_SPECIFIC
86 select HAVE_NMI
87 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
88 select HAVE_OPTPROBES if !THUMB2_KERNEL
89 select HAVE_PERF_EVENTS
90 select HAVE_PERF_REGS
91 select HAVE_PERF_USER_STACK_DUMP
92 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
93 select HAVE_REGS_AND_STACK_ACCESS_API
94 select HAVE_RSEQ
95 select HAVE_STACKPROTECTOR
96 select HAVE_SYSCALL_TRACEPOINTS
97 select HAVE_UID16
98 select HAVE_VIRT_CPU_ACCOUNTING_GEN
99 select IRQ_FORCED_THREADING
100 select MODULES_USE_ELF_REL
101 select NEED_DMA_MAP_STATE
102 select NO_BOOTMEM
103 select OF_EARLY_FLATTREE if OF
104 select OF_RESERVED_MEM if OF
105 select OLD_SIGACTION
106 select OLD_SIGSUSPEND3
107 select PERF_USE_VMALLOC
108 select REFCOUNT_FULL
109 select RTC_LIB
110 select SYS_SUPPORTS_APM_EMULATION
111 # Above selects are sorted alphabetically; please add new ones
112 # according to that. Thanks.
113 help
114 The ARM series is a line of low-power-consumption RISC chip designs
115 licensed by ARM Ltd and targeted at embedded applications and
116 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
117 manufactured, but legacy ARM-based PC hardware remains popular in
118 Europe. There is an ARM Linux project with a web page at
119 <http://www.arm.linux.org.uk/>.
121 config ARM_HAS_SG_CHAIN
122 select ARCH_HAS_SG_CHAIN
123 bool
125 config ARM_DMA_USE_IOMMU
126 bool
127 select ARM_HAS_SG_CHAIN
128 select NEED_SG_DMA_LENGTH
130 if ARM_DMA_USE_IOMMU
132 config ARM_DMA_IOMMU_ALIGNMENT
133 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
134 range 4 9
135 default 8
136 help
137 DMA mapping framework by default aligns all buffers to the smallest
138 PAGE_SIZE order which is greater than or equal to the requested buffer
139 size. This works well for buffers up to a few hundreds kilobytes, but
140 for larger buffers it just a waste of address space. Drivers which has
141 relatively small addressing window (like 64Mib) might run out of
142 virtual space with just a few allocations.
144 With this parameter you can specify the maximum PAGE_SIZE order for
145 DMA IOMMU buffers. Larger buffers will be aligned only to this
146 specified order. The order is expressed as a power of two multiplied
147 by the PAGE_SIZE.
149 endif
151 config MIGHT_HAVE_PCI
152 bool
154 config SYS_SUPPORTS_APM_EMULATION
155 bool
157 config HAVE_TCM
158 bool
159 select GENERIC_ALLOCATOR
161 config HAVE_PROC_CPU
162 bool
164 config NO_IOPORT_MAP
165 bool
167 config EISA
168 bool
169 ---help---
170 The Extended Industry Standard Architecture (EISA) bus was
171 developed as an open alternative to the IBM MicroChannel bus.
173 The EISA bus provided some of the features of the IBM MicroChannel
174 bus while maintaining backward compatibility with cards made for
175 the older ISA bus. The EISA bus saw limited use between 1988 and
176 1995 when it was made obsolete by the PCI bus.
178 Say Y here if you are building a kernel for an EISA-based machine.
180 Otherwise, say N.
182 config SBUS
183 bool
185 config STACKTRACE_SUPPORT
186 bool
187 default y
189 config LOCKDEP_SUPPORT
190 bool
191 default y
193 config TRACE_IRQFLAGS_SUPPORT
194 bool
195 default !CPU_V7M
197 config RWSEM_XCHGADD_ALGORITHM
198 bool
199 default y
201 config ARCH_HAS_ILOG2_U32
202 bool
204 config ARCH_HAS_ILOG2_U64
205 bool
207 config ARCH_HAS_BANDGAP
208 bool
210 config FIX_EARLYCON_MEM
211 def_bool y if MMU
213 config GENERIC_HWEIGHT
214 bool
215 default y
217 config GENERIC_CALIBRATE_DELAY
218 bool
219 default y
221 config ARCH_MAY_HAVE_PC_FDC
222 bool
224 config ZONE_DMA
225 bool
227 config ARCH_SUPPORTS_UPROBES
228 def_bool y
230 config ARCH_HAS_DMA_SET_COHERENT_MASK
231 bool
233 config GENERIC_ISA_DMA
234 bool
236 config FIQ
237 bool
239 config NEED_RET_TO_USER
240 bool
242 config ARCH_MTD_XIP
243 bool
245 config ARM_PATCH_PHYS_VIRT
246 bool "Patch physical to virtual translations at runtime" if EMBEDDED
247 default y
248 depends on !XIP_KERNEL && MMU
249 help
250 Patch phys-to-virt and virt-to-phys translation functions at
251 boot and module load time according to the position of the
252 kernel in system memory.
254 This can only be used with non-XIP MMU kernels where the base
255 of physical memory is at a 16MB boundary.
257 Only disable this option if you know that you do not require
258 this feature (eg, building a kernel for a single machine) and
259 you need to shrink the kernel to the minimal size.
261 config NEED_MACH_IO_H
262 bool
263 help
264 Select this when mach/io.h is required to provide special
265 definitions for this platform. The need for mach/io.h should
266 be avoided when possible.
268 config NEED_MACH_MEMORY_H
269 bool
270 help
271 Select this when mach/memory.h is required to provide special
272 definitions for this platform. The need for mach/memory.h should
273 be avoided when possible.
275 config PHYS_OFFSET
276 hex "Physical address of main memory" if MMU
277 depends on !ARM_PATCH_PHYS_VIRT
278 default DRAM_BASE if !MMU
279 default 0x00000000 if ARCH_EBSA110 || \
280 ARCH_FOOTBRIDGE || \
281 ARCH_INTEGRATOR || \
282 ARCH_IOP13XX || \
283 ARCH_KS8695 || \
284 ARCH_REALVIEW
285 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
286 default 0x20000000 if ARCH_S5PV210
287 default 0xc0000000 if ARCH_SA1100
288 help
289 Please provide the physical address corresponding to the
290 location of main memory in your system.
292 config GENERIC_BUG
293 def_bool y
294 depends on BUG
296 config PGTABLE_LEVELS
297 int
298 default 3 if ARM_LPAE
299 default 2
301 source "init/Kconfig"
303 source "kernel/Kconfig.freezer"
305 menu "System Type"
307 config MMU
308 bool "MMU-based Paged Memory Management Support"
309 default y
310 help
311 Select if you want MMU-based virtualised addressing space
312 support by paged memory management. If unsure, say 'Y'.
314 config ARCH_MMAP_RND_BITS_MIN
315 default 8
317 config ARCH_MMAP_RND_BITS_MAX
318 default 14 if PAGE_OFFSET=0x40000000
319 default 15 if PAGE_OFFSET=0x80000000
320 default 16
322 #
323 # The "ARM system type" choice list is ordered alphabetically by option
324 # text. Please add new entries in the option alphabetic order.
325 #
326 choice
327 prompt "ARM system type"
328 default ARM_SINGLE_ARMV7M if !MMU
329 default ARCH_MULTIPLATFORM if MMU
331 config ARCH_MULTIPLATFORM
332 bool "Allow multiple platforms to be selected"
333 depends on MMU
334 select ARM_HAS_SG_CHAIN
335 select ARM_PATCH_PHYS_VIRT
336 select AUTO_ZRELADDR
337 select TIMER_OF
338 select COMMON_CLK
339 select GENERIC_CLOCKEVENTS
340 select MIGHT_HAVE_PCI
341 select MULTI_IRQ_HANDLER
342 select PCI_DOMAINS if PCI
343 select SPARSE_IRQ
344 select USE_OF
346 config ARM_SINGLE_ARMV7M
347 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
348 depends on !MMU
349 select ARM_NVIC
350 select AUTO_ZRELADDR
351 select TIMER_OF
352 select COMMON_CLK
353 select CPU_V7M
354 select GENERIC_CLOCKEVENTS
355 select NO_IOPORT_MAP
356 select SPARSE_IRQ
357 select USE_OF
359 config ARCH_EBSA110
360 bool "EBSA-110"
361 select ARCH_USES_GETTIMEOFFSET
362 select CPU_SA110
363 select ISA
364 select NEED_MACH_IO_H
365 select NEED_MACH_MEMORY_H
366 select NO_IOPORT_MAP
367 help
368 This is an evaluation board for the StrongARM processor available
369 from Digital. It has limited hardware on-board, including an
370 Ethernet interface, two PCMCIA sockets, two serial ports and a
371 parallel port.
373 config ARCH_EP93XX
374 bool "EP93xx-based"
375 select ARCH_SPARSEMEM_ENABLE
376 select ARM_AMBA
377 imply ARM_PATCH_PHYS_VIRT
378 select ARM_VIC
379 select AUTO_ZRELADDR
380 select CLKDEV_LOOKUP
381 select CLKSRC_MMIO
382 select CPU_ARM920T
383 select GENERIC_CLOCKEVENTS
384 select GPIOLIB
385 help
386 This enables support for the Cirrus EP93xx series of CPUs.
388 config ARCH_FOOTBRIDGE
389 bool "FootBridge"
390 select CPU_SA110
391 select FOOTBRIDGE
392 select GENERIC_CLOCKEVENTS
393 select HAVE_IDE
394 select NEED_MACH_IO_H if !MMU
395 select NEED_MACH_MEMORY_H
396 help
397 Support for systems based on the DC21285 companion chip
398 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
400 config ARCH_NETX
401 bool "Hilscher NetX based"
402 select ARM_VIC
403 select CLKSRC_MMIO
404 select CPU_ARM926T
405 select GENERIC_CLOCKEVENTS
406 help
407 This enables support for systems based on the Hilscher NetX Soc
409 config ARCH_IOP13XX
410 bool "IOP13xx-based"
411 depends on MMU
412 select CPU_XSC3
413 select NEED_MACH_MEMORY_H
414 select NEED_RET_TO_USER
415 select PCI
416 select PLAT_IOP
417 select VMSPLIT_1G
418 select SPARSE_IRQ
419 help
420 Support for Intel's IOP13XX (XScale) family of processors.
422 config ARCH_IOP32X
423 bool "IOP32x-based"
424 depends on MMU
425 select CPU_XSCALE
426 select GPIO_IOP
427 select GPIOLIB
428 select NEED_RET_TO_USER
429 select PCI
430 select PLAT_IOP
431 help
432 Support for Intel's 80219 and IOP32X (XScale) family of
433 processors.
435 config ARCH_IOP33X
436 bool "IOP33x-based"
437 depends on MMU
438 select CPU_XSCALE
439 select GPIO_IOP
440 select GPIOLIB
441 select NEED_RET_TO_USER
442 select PCI
443 select PLAT_IOP
444 help
445 Support for Intel's IOP33X (XScale) family of processors.
447 config ARCH_IXP4XX
448 bool "IXP4xx-based"
449 depends on MMU
450 select ARCH_HAS_DMA_SET_COHERENT_MASK
451 select ARCH_SUPPORTS_BIG_ENDIAN
452 select CLKSRC_MMIO
453 select CPU_XSCALE
454 select DMABOUNCE if PCI
455 select GENERIC_CLOCKEVENTS
456 select GPIOLIB
457 select MIGHT_HAVE_PCI
458 select NEED_MACH_IO_H
459 select USB_EHCI_BIG_ENDIAN_DESC
460 select USB_EHCI_BIG_ENDIAN_MMIO
461 help
462 Support for Intel's IXP4XX (XScale) family of processors.
464 config ARCH_DOVE
465 bool "Marvell Dove"
466 select CPU_PJ4
467 select GENERIC_CLOCKEVENTS
468 select GPIOLIB
469 select MIGHT_HAVE_PCI
470 select MULTI_IRQ_HANDLER
471 select MVEBU_MBUS
472 select PINCTRL
473 select PINCTRL_DOVE
474 select PLAT_ORION_LEGACY
475 select SPARSE_IRQ
476 select PM_GENERIC_DOMAINS if PM
477 help
478 Support for the Marvell Dove SoC 88AP510
480 config ARCH_KS8695
481 bool "Micrel/Kendin KS8695"
482 select CLKSRC_MMIO
483 select CPU_ARM922T
484 select GENERIC_CLOCKEVENTS
485 select GPIOLIB
486 select NEED_MACH_MEMORY_H
487 help
488 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
489 System-on-Chip devices.
491 config ARCH_W90X900
492 bool "Nuvoton W90X900 CPU"
493 select CLKDEV_LOOKUP
494 select CLKSRC_MMIO
495 select CPU_ARM926T
496 select GENERIC_CLOCKEVENTS
497 select GPIOLIB
498 help
499 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
500 At present, the w90x900 has been renamed nuc900, regarding
501 the ARM series product line, you can login the following
502 link address to know more.
504 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
505 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
507 config ARCH_LPC32XX
508 bool "NXP LPC32XX"
509 select ARM_AMBA
510 select CLKDEV_LOOKUP
511 select CLKSRC_LPC32XX
512 select COMMON_CLK
513 select CPU_ARM926T
514 select GENERIC_CLOCKEVENTS
515 select GPIOLIB
516 select MULTI_IRQ_HANDLER
517 select SPARSE_IRQ
518 select USE_OF
519 help
520 Support for the NXP LPC32XX family of processors
522 config ARCH_PXA
523 bool "PXA2xx/PXA3xx-based"
524 depends on MMU
525 select ARCH_MTD_XIP
526 select ARM_CPU_SUSPEND if PM
527 select AUTO_ZRELADDR
528 select COMMON_CLK
529 select CLKDEV_LOOKUP
530 select CLKSRC_PXA
531 select CLKSRC_MMIO
532 select TIMER_OF
533 select CPU_XSCALE if !CPU_XSC3
534 select GENERIC_CLOCKEVENTS
535 select GPIO_PXA
536 select GPIOLIB
537 select HAVE_IDE
538 select IRQ_DOMAIN
539 select MULTI_IRQ_HANDLER
540 select PLAT_PXA
541 select SPARSE_IRQ
542 help
543 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
545 config ARCH_RPC
546 bool "RiscPC"
547 depends on MMU
548 select ARCH_ACORN
549 select ARCH_MAY_HAVE_PC_FDC
550 select ARCH_SPARSEMEM_ENABLE
551 select ARCH_USES_GETTIMEOFFSET
552 select CPU_SA110
553 select FIQ
554 select HAVE_IDE
555 select HAVE_PATA_PLATFORM
556 select ISA_DMA_API
557 select NEED_MACH_IO_H
558 select NEED_MACH_MEMORY_H
559 select NO_IOPORT_MAP
560 help
561 On the Acorn Risc-PC, Linux can support the internal IDE disk and
562 CD-ROM interface, serial and parallel port, and the floppy drive.
564 config ARCH_SA1100
565 bool "SA1100-based"
566 select ARCH_MTD_XIP
567 select ARCH_SPARSEMEM_ENABLE
568 select CLKDEV_LOOKUP
569 select CLKSRC_MMIO
570 select CLKSRC_PXA
571 select TIMER_OF if OF
572 select CPU_FREQ
573 select CPU_SA1100
574 select GENERIC_CLOCKEVENTS
575 select GPIOLIB
576 select HAVE_IDE
577 select IRQ_DOMAIN
578 select ISA
579 select MULTI_IRQ_HANDLER
580 select NEED_MACH_MEMORY_H
581 select SPARSE_IRQ
582 help
583 Support for StrongARM 11x0 based boards.
585 config ARCH_S3C24XX
586 bool "Samsung S3C24XX SoCs"
587 select ATAGS
588 select CLKDEV_LOOKUP
589 select CLKSRC_SAMSUNG_PWM
590 select GENERIC_CLOCKEVENTS
591 select GPIO_SAMSUNG
592 select GPIOLIB
593 select HAVE_S3C2410_I2C if I2C
594 select HAVE_S3C2410_WATCHDOG if WATCHDOG
595 select HAVE_S3C_RTC if RTC_CLASS
596 select MULTI_IRQ_HANDLER
597 select NEED_MACH_IO_H
598 select SAMSUNG_ATAGS
599 select USE_OF
600 help
601 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
602 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
603 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
604 Samsung SMDK2410 development board (and derivatives).
606 config ARCH_DAVINCI
607 bool "TI DaVinci"
608 select ARCH_HAS_HOLES_MEMORYMODEL
609 select CLKDEV_LOOKUP
610 select CPU_ARM926T
611 select GENERIC_ALLOCATOR
612 select GENERIC_CLOCKEVENTS
613 select GENERIC_IRQ_CHIP
614 select GPIOLIB
615 select HAVE_IDE
616 select USE_OF
617 select ZONE_DMA
618 help
619 Support for TI's DaVinci platform.
621 config ARCH_OMAP1
622 bool "TI OMAP1"
623 depends on MMU
624 select ARCH_HAS_HOLES_MEMORYMODEL
625 select ARCH_OMAP
626 select CLKDEV_LOOKUP
627 select CLKSRC_MMIO
628 select GENERIC_CLOCKEVENTS
629 select GENERIC_IRQ_CHIP
630 select GPIOLIB
631 select HAVE_IDE
632 select IRQ_DOMAIN
633 select MULTI_IRQ_HANDLER
634 select NEED_MACH_IO_H if PCCARD
635 select NEED_MACH_MEMORY_H
636 select SPARSE_IRQ
637 help
638 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
640 endchoice
642 menu "Multiple platform selection"
643 depends on ARCH_MULTIPLATFORM
645 comment "CPU Core family selection"
647 config ARCH_MULTI_V4
648 bool "ARMv4 based platforms (FA526)"
649 depends on !ARCH_MULTI_V6_V7
650 select ARCH_MULTI_V4_V5
651 select CPU_FA526
653 config ARCH_MULTI_V4T
654 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
655 depends on !ARCH_MULTI_V6_V7
656 select ARCH_MULTI_V4_V5
657 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
658 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
659 CPU_ARM925T || CPU_ARM940T)
661 config ARCH_MULTI_V5
662 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
663 depends on !ARCH_MULTI_V6_V7
664 select ARCH_MULTI_V4_V5
665 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
666 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
667 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
669 config ARCH_MULTI_V4_V5
670 bool
672 config ARCH_MULTI_V6
673 bool "ARMv6 based platforms (ARM11)"
674 select ARCH_MULTI_V6_V7
675 select CPU_V6K
677 config ARCH_MULTI_V7
678 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
679 default y
680 select ARCH_MULTI_V6_V7
681 select CPU_V7
682 select HAVE_SMP
684 config ARCH_MULTI_V6_V7
685 bool
686 select MIGHT_HAVE_CACHE_L2X0
688 config ARCH_MULTI_CPU_AUTO
689 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
690 select ARCH_MULTI_V5
692 endmenu
694 config ARCH_VIRT
695 bool "Dummy Virtual Machine"
696 depends on ARCH_MULTI_V7
697 select ARM_AMBA
698 select ARM_GIC
699 select ARM_GIC_V2M if PCI
700 select ARM_GIC_V3
701 select ARM_GIC_V3_ITS if PCI
702 select ARM_PSCI
703 select HAVE_ARM_ARCH_TIMER
705 #
706 # This is sorted alphabetically by mach-* pathname. However, plat-*
707 # Kconfigs may be included either alphabetically (according to the
708 # plat- suffix) or along side the corresponding mach-* source.
709 #
710 source "arch/arm/mach-actions/Kconfig"
712 source "arch/arm/mach-alpine/Kconfig"
714 source "arch/arm/mach-artpec/Kconfig"
716 source "arch/arm/mach-asm9260/Kconfig"
718 source "arch/arm/mach-aspeed/Kconfig"
720 source "arch/arm/mach-at91/Kconfig"
722 source "arch/arm/mach-axxia/Kconfig"
724 source "arch/arm/mach-bcm/Kconfig"
726 source "arch/arm/mach-berlin/Kconfig"
728 source "arch/arm/mach-clps711x/Kconfig"
730 source "arch/arm/mach-cns3xxx/Kconfig"
732 source "arch/arm/mach-davinci/Kconfig"
734 source "arch/arm/mach-digicolor/Kconfig"
736 source "arch/arm/mach-dove/Kconfig"
738 source "arch/arm/mach-ep93xx/Kconfig"
740 source "arch/arm/mach-exynos/Kconfig"
741 source "arch/arm/plat-samsung/Kconfig"
743 source "arch/arm/mach-footbridge/Kconfig"
745 source "arch/arm/mach-gemini/Kconfig"
747 source "arch/arm/mach-highbank/Kconfig"
749 source "arch/arm/mach-hisi/Kconfig"
751 source "arch/arm/mach-imx/Kconfig"
753 source "arch/arm/mach-integrator/Kconfig"
755 source "arch/arm/mach-iop13xx/Kconfig"
757 source "arch/arm/mach-iop32x/Kconfig"
759 source "arch/arm/mach-iop33x/Kconfig"
761 source "arch/arm/mach-ixp4xx/Kconfig"
763 source "arch/arm/mach-keystone/Kconfig"
765 source "arch/arm/mach-ks8695/Kconfig"
767 source "arch/arm/mach-mediatek/Kconfig"
769 source "arch/arm/mach-meson/Kconfig"
771 source "arch/arm/mach-mmp/Kconfig"
773 source "arch/arm/mach-moxart/Kconfig"
775 source "arch/arm/mach-mv78xx0/Kconfig"
777 source "arch/arm/mach-mvebu/Kconfig"
779 source "arch/arm/mach-mxs/Kconfig"
781 source "arch/arm/mach-netx/Kconfig"
783 source "arch/arm/mach-nomadik/Kconfig"
785 source "arch/arm/mach-npcm/Kconfig"
787 source "arch/arm/mach-nspire/Kconfig"
789 source "arch/arm/plat-omap/Kconfig"
791 source "arch/arm/mach-omap1/Kconfig"
793 source "arch/arm/mach-omap2/Kconfig"
795 source "arch/arm/mach-orion5x/Kconfig"
797 source "arch/arm/mach-oxnas/Kconfig"
799 source "arch/arm/mach-picoxcell/Kconfig"
801 source "arch/arm/mach-prima2/Kconfig"
803 source "arch/arm/mach-pxa/Kconfig"
804 source "arch/arm/plat-pxa/Kconfig"
806 source "arch/arm/mach-qcom/Kconfig"
808 source "arch/arm/mach-realview/Kconfig"
810 source "arch/arm/mach-rockchip/Kconfig"
812 source "arch/arm/mach-s3c24xx/Kconfig"
814 source "arch/arm/mach-s3c64xx/Kconfig"
816 source "arch/arm/mach-s5pv210/Kconfig"
818 source "arch/arm/mach-sa1100/Kconfig"
820 source "arch/arm/mach-shmobile/Kconfig"
822 source "arch/arm/mach-socfpga/Kconfig"
824 source "arch/arm/mach-spear/Kconfig"
826 source "arch/arm/mach-sti/Kconfig"
828 source "arch/arm/mach-stm32/Kconfig"
830 source "arch/arm/mach-sunxi/Kconfig"
832 source "arch/arm/mach-tango/Kconfig"
834 source "arch/arm/mach-tegra/Kconfig"
836 source "arch/arm/mach-u300/Kconfig"
838 source "arch/arm/mach-uniphier/Kconfig"
840 source "arch/arm/mach-ux500/Kconfig"
842 source "arch/arm/mach-versatile/Kconfig"
844 source "arch/arm/mach-vexpress/Kconfig"
845 source "arch/arm/plat-versatile/Kconfig"
847 source "arch/arm/mach-vt8500/Kconfig"
849 source "arch/arm/mach-w90x900/Kconfig"
851 source "arch/arm/mach-zx/Kconfig"
853 source "arch/arm/mach-zynq/Kconfig"
855 # ARMv7-M architecture
856 config ARCH_EFM32
857 bool "Energy Micro efm32"
858 depends on ARM_SINGLE_ARMV7M
859 select GPIOLIB
860 help
861 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
862 processors.
864 config ARCH_LPC18XX
865 bool "NXP LPC18xx/LPC43xx"
866 depends on ARM_SINGLE_ARMV7M
867 select ARCH_HAS_RESET_CONTROLLER
868 select ARM_AMBA
869 select CLKSRC_LPC32XX
870 select PINCTRL
871 help
872 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
873 high performance microcontrollers.
875 config ARCH_MPS2
876 bool "ARM MPS2 platform"
877 depends on ARM_SINGLE_ARMV7M
878 select ARM_AMBA
879 select CLKSRC_MPS2
880 help
881 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
882 with a range of available cores like Cortex-M3/M4/M7.
884 Please, note that depends which Application Note is used memory map
885 for the platform may vary, so adjustment of RAM base might be needed.
887 # Definitions to make life easier
888 config ARCH_ACORN
889 bool
891 config PLAT_IOP
892 bool
893 select GENERIC_CLOCKEVENTS
895 config PLAT_ORION
896 bool
897 select CLKSRC_MMIO
898 select COMMON_CLK
899 select GENERIC_IRQ_CHIP
900 select IRQ_DOMAIN
902 config PLAT_ORION_LEGACY
903 bool
904 select PLAT_ORION
906 config PLAT_PXA
907 bool
909 config PLAT_VERSATILE
910 bool
912 source "arch/arm/firmware/Kconfig"
914 source arch/arm/mm/Kconfig
916 config IWMMXT
917 bool "Enable iWMMXt support"
918 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
919 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
920 help
921 Enable support for iWMMXt context switching at run time if
922 running on a CPU that supports it.
924 config MULTI_IRQ_HANDLER
925 bool
926 help
927 Allow each machine to specify it's own IRQ handler at run time.
929 if !MMU
930 source "arch/arm/Kconfig-nommu"
931 endif
933 config PJ4B_ERRATA_4742
934 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
935 depends on CPU_PJ4B && MACH_ARMADA_370
936 default y
937 help
938 When coming out of either a Wait for Interrupt (WFI) or a Wait for
939 Event (WFE) IDLE states, a specific timing sensitivity exists between
940 the retiring WFI/WFE instructions and the newly issued subsequent
941 instructions. This sensitivity can result in a CPU hang scenario.
942 Workaround:
943 The software must insert either a Data Synchronization Barrier (DSB)
944 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
945 instruction
947 config ARM_ERRATA_326103
948 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
949 depends on CPU_V6
950 help
951 Executing a SWP instruction to read-only memory does not set bit 11
952 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
953 treat the access as a read, preventing a COW from occurring and
954 causing the faulting task to livelock.
956 config ARM_ERRATA_411920
957 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
958 depends on CPU_V6 || CPU_V6K
959 help
960 Invalidation of the Instruction Cache operation can
961 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
962 It does not affect the MPCore. This option enables the ARM Ltd.
963 recommended workaround.
965 config ARM_ERRATA_430973
966 bool "ARM errata: Stale prediction on replaced interworking branch"
967 depends on CPU_V7
968 help
969 This option enables the workaround for the 430973 Cortex-A8
970 r1p* erratum. If a code sequence containing an ARM/Thumb
971 interworking branch is replaced with another code sequence at the
972 same virtual address, whether due to self-modifying code or virtual
973 to physical address re-mapping, Cortex-A8 does not recover from the
974 stale interworking branch prediction. This results in Cortex-A8
975 executing the new code sequence in the incorrect ARM or Thumb state.
976 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
977 and also flushes the branch target cache at every context switch.
978 Note that setting specific bits in the ACTLR register may not be
979 available in non-secure mode.
981 config ARM_ERRATA_458693
982 bool "ARM errata: Processor deadlock when a false hazard is created"
983 depends on CPU_V7
984 depends on !ARCH_MULTIPLATFORM
985 help
986 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
987 erratum. For very specific sequences of memory operations, it is
988 possible for a hazard condition intended for a cache line to instead
989 be incorrectly associated with a different cache line. This false
990 hazard might then cause a processor deadlock. The workaround enables
991 the L1 caching of the NEON accesses and disables the PLD instruction
992 in the ACTLR register. Note that setting specific bits in the ACTLR
993 register may not be available in non-secure mode.
995 config ARM_ERRATA_460075
996 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
997 depends on CPU_V7
998 depends on !ARCH_MULTIPLATFORM
999 help
1000 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1001 erratum. Any asynchronous access to the L2 cache may encounter a
1002 situation in which recent store transactions to the L2 cache are lost
1003 and overwritten with stale memory contents from external memory. The
1004 workaround disables the write-allocate mode for the L2 cache via the
1005 ACTLR register. Note that setting specific bits in the ACTLR register
1006 may not be available in non-secure mode.
1008 config ARM_ERRATA_742230
1009 bool "ARM errata: DMB operation may be faulty"
1010 depends on CPU_V7 && SMP
1011 depends on !ARCH_MULTIPLATFORM
1012 help
1013 This option enables the workaround for the 742230 Cortex-A9
1014 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1015 between two write operations may not ensure the correct visibility
1016 ordering of the two writes. This workaround sets a specific bit in
1017 the diagnostic register of the Cortex-A9 which causes the DMB
1018 instruction to behave as a DSB, ensuring the correct behaviour of
1019 the two writes.
1021 config ARM_ERRATA_742231
1022 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1023 depends on CPU_V7 && SMP
1024 depends on !ARCH_MULTIPLATFORM
1025 help
1026 This option enables the workaround for the 742231 Cortex-A9
1027 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1028 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1029 accessing some data located in the same cache line, may get corrupted
1030 data due to bad handling of the address hazard when the line gets
1031 replaced from one of the CPUs at the same time as another CPU is
1032 accessing it. This workaround sets specific bits in the diagnostic
1033 register of the Cortex-A9 which reduces the linefill issuing
1034 capabilities of the processor.
1036 config ARM_ERRATA_643719
1037 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1038 depends on CPU_V7 && SMP
1039 default y
1040 help
1041 This option enables the workaround for the 643719 Cortex-A9 (prior to
1042 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1043 register returns zero when it should return one. The workaround
1044 corrects this value, ensuring cache maintenance operations which use
1045 it behave as intended and avoiding data corruption.
1047 config ARM_ERRATA_720789
1048 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1049 depends on CPU_V7
1050 help
1051 This option enables the workaround for the 720789 Cortex-A9 (prior to
1052 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1053 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1054 As a consequence of this erratum, some TLB entries which should be
1055 invalidated are not, resulting in an incoherency in the system page
1056 tables. The workaround changes the TLB flushing routines to invalidate
1057 entries regardless of the ASID.
1059 config ARM_ERRATA_743622
1060 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1061 depends on CPU_V7
1062 depends on !ARCH_MULTIPLATFORM
1063 help
1064 This option enables the workaround for the 743622 Cortex-A9
1065 (r2p*) erratum. Under very rare conditions, a faulty
1066 optimisation in the Cortex-A9 Store Buffer may lead to data
1067 corruption. This workaround sets a specific bit in the diagnostic
1068 register of the Cortex-A9 which disables the Store Buffer
1069 optimisation, preventing the defect from occurring. This has no
1070 visible impact on the overall performance or power consumption of the
1071 processor.
1073 config ARM_ERRATA_751472
1074 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1075 depends on CPU_V7
1076 depends on !ARCH_MULTIPLATFORM
1077 help
1078 This option enables the workaround for the 751472 Cortex-A9 (prior
1079 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1080 completion of a following broadcasted operation if the second
1081 operation is received by a CPU before the ICIALLUIS has completed,
1082 potentially leading to corrupted entries in the cache or TLB.
1084 config ARM_ERRATA_754322
1085 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1086 depends on CPU_V7
1087 help
1088 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1089 r3p*) erratum. A speculative memory access may cause a page table walk
1090 which starts prior to an ASID switch but completes afterwards. This
1091 can populate the micro-TLB with a stale entry which may be hit with
1092 the new ASID. This workaround places two dsb instructions in the mm
1093 switching code so that no page table walks can cross the ASID switch.
1095 config ARM_ERRATA_754327
1096 bool "ARM errata: no automatic Store Buffer drain"
1097 depends on CPU_V7 && SMP
1098 help
1099 This option enables the workaround for the 754327 Cortex-A9 (prior to
1100 r2p0) erratum. The Store Buffer does not have any automatic draining
1101 mechanism and therefore a livelock may occur if an external agent
1102 continuously polls a memory location waiting to observe an update.
1103 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1104 written polling loops from denying visibility of updates to memory.
1106 config ARM_ERRATA_364296
1107 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1108 depends on CPU_V6
1109 help
1110 This options enables the workaround for the 364296 ARM1136
1111 r0p2 erratum (possible cache data corruption with
1112 hit-under-miss enabled). It sets the undocumented bit 31 in
1113 the auxiliary control register and the FI bit in the control
1114 register, thus disabling hit-under-miss without putting the
1115 processor into full low interrupt latency mode. ARM11MPCore
1116 is not affected.
1118 config ARM_ERRATA_764369
1119 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1120 depends on CPU_V7 && SMP
1121 help
1122 This option enables the workaround for erratum 764369
1123 affecting Cortex-A9 MPCore with two or more processors (all
1124 current revisions). Under certain timing circumstances, a data
1125 cache line maintenance operation by MVA targeting an Inner
1126 Shareable memory region may fail to proceed up to either the
1127 Point of Coherency or to the Point of Unification of the
1128 system. This workaround adds a DSB instruction before the
1129 relevant cache maintenance functions and sets a specific bit
1130 in the diagnostic control register of the SCU.
1132 config ARM_ERRATA_775420
1133 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1134 depends on CPU_V7
1135 help
1136 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1137 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1138 operation aborts with MMU exception, it might cause the processor
1139 to deadlock. This workaround puts DSB before executing ISB if
1140 an abort may occur on cache maintenance.
1142 config ARM_ERRATA_798181
1143 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1144 depends on CPU_V7 && SMP
1145 help
1146 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1147 adequately shooting down all use of the old entries. This
1148 option enables the Linux kernel workaround for this erratum
1149 which sends an IPI to the CPUs that are running the same ASID
1150 as the one being invalidated.
1152 config ARM_ERRATA_773022
1153 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1154 depends on CPU_V7
1155 help
1156 This option enables the workaround for the 773022 Cortex-A15
1157 (up to r0p4) erratum. In certain rare sequences of code, the
1158 loop buffer may deliver incorrect instructions. This
1159 workaround disables the loop buffer to avoid the erratum.
1161 config ARM_ERRATA_818325_852422
1162 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1163 depends on CPU_V7
1164 help
1165 This option enables the workaround for:
1166 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1167 instruction might deadlock. Fixed in r0p1.
1168 - Cortex-A12 852422: Execution of a sequence of instructions might
1169 lead to either a data corruption or a CPU deadlock. Not fixed in
1170 any Cortex-A12 cores yet.
1171 This workaround for all both errata involves setting bit[12] of the
1172 Feature Register. This bit disables an optimisation applied to a
1173 sequence of 2 instructions that use opposing condition codes.
1175 config ARM_ERRATA_821420
1176 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1177 depends on CPU_V7
1178 help
1179 This option enables the workaround for the 821420 Cortex-A12
1180 (all revs) erratum. In very rare timing conditions, a sequence
1181 of VMOV to Core registers instructions, for which the second
1182 one is in the shadow of a branch or abort, can lead to a
1183 deadlock when the VMOV instructions are issued out-of-order.
1185 config ARM_ERRATA_825619
1186 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1187 depends on CPU_V7
1188 help
1189 This option enables the workaround for the 825619 Cortex-A12
1190 (all revs) erratum. Within rare timing constraints, executing a
1191 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1192 and Device/Strongly-Ordered loads and stores might cause deadlock
1194 config ARM_ERRATA_852421
1195 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1196 depends on CPU_V7
1197 help
1198 This option enables the workaround for the 852421 Cortex-A17
1199 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1200 execution of a DMB ST instruction might fail to properly order
1201 stores from GroupA and stores from GroupB.
1203 config ARM_ERRATA_852423
1204 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1205 depends on CPU_V7
1206 help
1207 This option enables the workaround for:
1208 - Cortex-A17 852423: Execution of a sequence of instructions might
1209 lead to either a data corruption or a CPU deadlock. Not fixed in
1210 any Cortex-A17 cores yet.
1211 This is identical to Cortex-A12 erratum 852422. It is a separate
1212 config option from the A12 erratum due to the way errata are checked
1213 for and handled.
1215 endmenu
1217 source "arch/arm/common/Kconfig"
1219 menu "Bus support"
1221 config ISA
1222 bool
1223 help
1224 Find out whether you have ISA slots on your motherboard. ISA is the
1225 name of a bus system, i.e. the way the CPU talks to the other stuff
1226 inside your box. Other bus systems are PCI, EISA, MicroChannel
1227 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1228 newer boards don't support it. If you have ISA, say Y, otherwise N.
1230 # Select ISA DMA controller support
1231 config ISA_DMA
1232 bool
1233 select ISA_DMA_API
1235 # Select ISA DMA interface
1236 config ISA_DMA_API
1237 bool
1239 config PCI
1240 bool "PCI support" if MIGHT_HAVE_PCI
1241 help
1242 Find out whether you have a PCI motherboard. PCI is the name of a
1243 bus system, i.e. the way the CPU talks to the other stuff inside
1244 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1245 VESA. If you have PCI, say Y, otherwise N.
1247 config PCI_DOMAINS
1248 bool "Support for multiple PCI domains"
1249 depends on PCI
1250 help
1251 Enable PCI domains kernel management. Say Y if your machine
1252 has a PCI bus hierarchy that requires more than one PCI
1253 domain (aka segment) to be correctly managed. Say N otherwise.
1255 If you don't know what to do here, say N.
1257 config PCI_DOMAINS_GENERIC
1258 def_bool PCI_DOMAINS
1260 config PCI_NANOENGINE
1261 bool "BSE nanoEngine PCI support"
1262 depends on SA1100_NANOENGINE
1263 help
1264 Enable PCI on the BSE nanoEngine board.
1266 config PCI_SYSCALL
1267 def_bool PCI
1269 config PCI_HOST_ITE8152
1270 bool
1271 depends on PCI && MACH_ARMCORE
1272 default y
1273 select DMABOUNCE
1275 source "drivers/pci/Kconfig"
1277 source "drivers/pcmcia/Kconfig"
1279 endmenu
1281 menu "Kernel Features"
1283 config HAVE_SMP
1284 bool
1285 help
1286 This option should be selected by machines which have an SMP-
1287 capable CPU.
1289 The only effect of this option is to make the SMP-related
1290 options available to the user for configuration.
1292 config SMP
1293 bool "Symmetric Multi-Processing"
1294 depends on CPU_V6K || CPU_V7
1295 depends on GENERIC_CLOCKEVENTS
1296 depends on HAVE_SMP
1297 depends on MMU || ARM_MPU
1298 select IRQ_WORK
1299 help
1300 This enables support for systems with more than one CPU. If you have
1301 a system with only one CPU, say N. If you have a system with more
1302 than one CPU, say Y.
1304 If you say N here, the kernel will run on uni- and multiprocessor
1305 machines, but will use only one CPU of a multiprocessor machine. If
1306 you say Y here, the kernel will run on many, but not all,
1307 uniprocessor machines. On a uniprocessor machine, the kernel
1308 will run faster if you say N here.
1310 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1311 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1312 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1314 If you don't know what to do here, say N.
1316 config SMP_ON_UP
1317 bool "Allow booting SMP kernel on uniprocessor systems"
1318 depends on SMP && !XIP_KERNEL && MMU
1319 default y
1320 help
1321 SMP kernels contain instructions which fail on non-SMP processors.
1322 Enabling this option allows the kernel to modify itself to make
1323 these instructions safe. Disabling it allows about 1K of space
1324 savings.
1326 If you don't know what to do here, say Y.
1328 config ARM_CPU_TOPOLOGY
1329 bool "Support cpu topology definition"
1330 depends on SMP && CPU_V7
1331 default y
1332 help
1333 Support ARM cpu topology definition. The MPIDR register defines
1334 affinity between processors which is then used to describe the cpu
1335 topology of an ARM System.
1337 config SCHED_MC
1338 bool "Multi-core scheduler support"
1339 depends on ARM_CPU_TOPOLOGY
1340 help
1341 Multi-core scheduler support improves the CPU scheduler's decision
1342 making when dealing with multi-core CPU chips at a cost of slightly
1343 increased overhead in some places. If unsure say N here.
1345 config SCHED_SMT
1346 bool "SMT scheduler support"
1347 depends on ARM_CPU_TOPOLOGY
1348 help
1349 Improves the CPU scheduler's decision making when dealing with
1350 MultiThreading at a cost of slightly increased overhead in some
1351 places. If unsure say N here.
1353 config HAVE_ARM_SCU
1354 bool
1355 help
1356 This option enables support for the ARM system coherency unit
1358 config HAVE_ARM_ARCH_TIMER
1359 bool "Architected timer support"
1360 depends on CPU_V7
1361 select ARM_ARCH_TIMER
1362 select GENERIC_CLOCKEVENTS
1363 help
1364 This option enables support for the ARM architected timer
1366 config HAVE_ARM_TWD
1367 bool
1368 select TIMER_OF if OF
1369 help
1370 This options enables support for the ARM timer and watchdog unit
1372 config MCPM
1373 bool "Multi-Cluster Power Management"
1374 depends on CPU_V7 && SMP
1375 help
1376 This option provides the common power management infrastructure
1377 for (multi-)cluster based systems, such as big.LITTLE based
1378 systems.
1380 config MCPM_QUAD_CLUSTER
1381 bool
1382 depends on MCPM
1383 help
1384 To avoid wasting resources unnecessarily, MCPM only supports up
1385 to 2 clusters by default.
1386 Platforms with 3 or 4 clusters that use MCPM must select this
1387 option to allow the additional clusters to be managed.
1389 config BIG_LITTLE
1390 bool "big.LITTLE support (Experimental)"
1391 depends on CPU_V7 && SMP
1392 select MCPM
1393 help
1394 This option enables support selections for the big.LITTLE
1395 system architecture.
1397 config BL_SWITCHER
1398 bool "big.LITTLE switcher support"
1399 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1400 select CPU_PM
1401 help
1402 The big.LITTLE "switcher" provides the core functionality to
1403 transparently handle transition between a cluster of A15's
1404 and a cluster of A7's in a big.LITTLE system.
1406 config BL_SWITCHER_DUMMY_IF
1407 tristate "Simple big.LITTLE switcher user interface"
1408 depends on BL_SWITCHER && DEBUG_KERNEL
1409 help
1410 This is a simple and dummy char dev interface to control
1411 the big.LITTLE switcher core code. It is meant for
1412 debugging purposes only.
1414 choice
1415 prompt "Memory split"
1416 depends on MMU
1417 default VMSPLIT_3G
1418 help
1419 Select the desired split between kernel and user memory.
1421 If you are not absolutely sure what you are doing, leave this
1422 option alone!
1424 config VMSPLIT_3G
1425 bool "3G/1G user/kernel split"
1426 config VMSPLIT_3G_OPT
1427 depends on !ARM_LPAE
1428 bool "3G/1G user/kernel split (for full 1G low memory)"
1429 config VMSPLIT_2G
1430 bool "2G/2G user/kernel split"
1431 config VMSPLIT_1G
1432 bool "1G/3G user/kernel split"
1433 endchoice
1435 config PAGE_OFFSET
1436 hex
1437 default PHYS_OFFSET if !MMU
1438 default 0x40000000 if VMSPLIT_1G
1439 default 0x80000000 if VMSPLIT_2G
1440 default 0xB0000000 if VMSPLIT_3G_OPT
1441 default 0xC0000000
1443 config NR_CPUS
1444 int "Maximum number of CPUs (2-32)"
1445 range 2 32
1446 depends on SMP
1447 default "4"
1449 config HOTPLUG_CPU
1450 bool "Support for hot-pluggable CPUs"
1451 depends on SMP
1452 help
1453 Say Y here to experiment with turning CPUs off and on. CPUs
1454 can be controlled through /sys/devices/system/cpu.
1456 config ARM_PSCI
1457 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1458 depends on HAVE_ARM_SMCCC
1459 select ARM_PSCI_FW
1460 help
1461 Say Y here if you want Linux to communicate with system firmware
1462 implementing the PSCI specification for CPU-centric power
1463 management operations described in ARM document number ARM DEN
1464 0022A ("Power State Coordination Interface System Software on
1465 ARM processors").
1467 # The GPIO number here must be sorted by descending number. In case of
1468 # a multiplatform kernel, we just want the highest value required by the
1469 # selected platforms.
1470 config ARCH_NR_GPIO
1471 int
1472 default 2048 if ARCH_SOCFPGA
1473 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1474 ARCH_ZYNQ
1475 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1476 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1477 default 416 if ARCH_SUNXI
1478 default 392 if ARCH_U8500
1479 default 352 if ARCH_VT8500
1480 default 288 if ARCH_ROCKCHIP
1481 default 264 if MACH_H4700
1482 default 0
1483 help
1484 Maximum number of GPIOs in the system.
1486 If unsure, leave the default value.
1488 source kernel/Kconfig.preempt
1490 config HZ_FIXED
1491 int
1492 default 200 if ARCH_EBSA110
1493 default 128 if SOC_AT91RM9200
1494 default 0
1496 choice
1497 depends on HZ_FIXED = 0
1498 prompt "Timer frequency"
1500 config HZ_100
1501 bool "100 Hz"
1503 config HZ_200
1504 bool "200 Hz"
1506 config HZ_250
1507 bool "250 Hz"
1509 config HZ_300
1510 bool "300 Hz"
1512 config HZ_500
1513 bool "500 Hz"
1515 config HZ_1000
1516 bool "1000 Hz"
1518 endchoice
1520 config HZ
1521 int
1522 default HZ_FIXED if HZ_FIXED != 0
1523 default 100 if HZ_100
1524 default 200 if HZ_200
1525 default 250 if HZ_250
1526 default 300 if HZ_300
1527 default 500 if HZ_500
1528 default 1000
1530 config SCHED_HRTICK
1531 def_bool HIGH_RES_TIMERS
1533 config THUMB2_KERNEL
1534 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1535 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1536 default y if CPU_THUMBONLY
1537 select ARM_UNWIND
1538 help
1539 By enabling this option, the kernel will be compiled in
1540 Thumb-2 mode.
1542 If unsure, say N.
1544 config THUMB2_AVOID_R_ARM_THM_JUMP11
1545 bool "Work around buggy Thumb-2 short branch relocations in gas"
1546 depends on THUMB2_KERNEL && MODULES
1547 default y
1548 help
1549 Various binutils versions can resolve Thumb-2 branches to
1550 locally-defined, preemptible global symbols as short-range "b.n"
1551 branch instructions.
1553 This is a problem, because there's no guarantee the final
1554 destination of the symbol, or any candidate locations for a
1555 trampoline, are within range of the branch. For this reason, the
1556 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1557 relocation in modules at all, and it makes little sense to add
1558 support.
1560 The symptom is that the kernel fails with an "unsupported
1561 relocation" error when loading some modules.
1563 Until fixed tools are available, passing
1564 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1565 code which hits this problem, at the cost of a bit of extra runtime
1566 stack usage in some cases.
1568 The problem is described in more detail at:
1569 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1571 Only Thumb-2 kernels are affected.
1573 Unless you are sure your tools don't have this problem, say Y.
1575 config ARM_PATCH_IDIV
1576 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1577 depends on CPU_32v7 && !XIP_KERNEL
1578 default y
1579 help
1580 The ARM compiler inserts calls to __aeabi_idiv() and
1581 __aeabi_uidiv() when it needs to perform division on signed
1582 and unsigned integers. Some v7 CPUs have support for the sdiv
1583 and udiv instructions that can be used to implement those
1584 functions.
1586 Enabling this option allows the kernel to modify itself to
1587 replace the first two instructions of these library functions
1588 with the sdiv or udiv plus "bx lr" instructions when the CPU
1589 it is running on supports them. Typically this will be faster
1590 and less power intensive than running the original library
1591 code to do integer division.
1593 config AEABI
1594 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1595 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1596 help
1597 This option allows for the kernel to be compiled using the latest
1598 ARM ABI (aka EABI). This is only useful if you are using a user
1599 space environment that is also compiled with EABI.
1601 Since there are major incompatibilities between the legacy ABI and
1602 EABI, especially with regard to structure member alignment, this
1603 option also changes the kernel syscall calling convention to
1604 disambiguate both ABIs and allow for backward compatibility support
1605 (selected with CONFIG_OABI_COMPAT).
1607 To use this you need GCC version 4.0.0 or later.
1609 config OABI_COMPAT
1610 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1611 depends on AEABI && !THUMB2_KERNEL
1612 help
1613 This option preserves the old syscall interface along with the
1614 new (ARM EABI) one. It also provides a compatibility layer to
1615 intercept syscalls that have structure arguments which layout
1616 in memory differs between the legacy ABI and the new ARM EABI
1617 (only for non "thumb" binaries). This option adds a tiny
1618 overhead to all syscalls and produces a slightly larger kernel.
1620 The seccomp filter system will not be available when this is
1621 selected, since there is no way yet to sensibly distinguish
1622 between calling conventions during filtering.
1624 If you know you'll be using only pure EABI user space then you
1625 can say N here. If this option is not selected and you attempt
1626 to execute a legacy ABI binary then the result will be
1627 UNPREDICTABLE (in fact it can be predicted that it won't work
1628 at all). If in doubt say N.
1630 config ARCH_HAS_HOLES_MEMORYMODEL
1631 bool
1633 config ARCH_SPARSEMEM_ENABLE
1634 bool
1636 config ARCH_SPARSEMEM_DEFAULT
1637 def_bool ARCH_SPARSEMEM_ENABLE
1639 config ARCH_SELECT_MEMORY_MODEL
1640 def_bool ARCH_SPARSEMEM_ENABLE
1642 config HAVE_ARCH_PFN_VALID
1643 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1645 config HAVE_GENERIC_GUP
1646 def_bool y
1647 depends on ARM_LPAE
1649 config HIGHMEM
1650 bool "High Memory Support"
1651 depends on MMU
1652 help
1653 The address space of ARM processors is only 4 Gigabytes large
1654 and it has to accommodate user address space, kernel address
1655 space as well as some memory mapped IO. That means that, if you
1656 have a large amount of physical memory and/or IO, not all of the
1657 memory can be "permanently mapped" by the kernel. The physical
1658 memory that is not permanently mapped is called "high memory".
1660 Depending on the selected kernel/user memory split, minimum
1661 vmalloc space and actual amount of RAM, you may not need this
1662 option which should result in a slightly faster kernel.
1664 If unsure, say n.
1666 config HIGHPTE
1667 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1668 depends on HIGHMEM
1669 default y
1670 help
1671 The VM uses one page of physical memory for each page table.
1672 For systems with a lot of processes, this can use a lot of
1673 precious low memory, eventually leading to low memory being
1674 consumed by page tables. Setting this option will allow
1675 user-space 2nd level page tables to reside in high memory.
1677 config CPU_SW_DOMAIN_PAN
1678 bool "Enable use of CPU domains to implement privileged no-access"
1679 depends on MMU && !ARM_LPAE
1680 default y
1681 help
1682 Increase kernel security by ensuring that normal kernel accesses
1683 are unable to access userspace addresses. This can help prevent
1684 use-after-free bugs becoming an exploitable privilege escalation
1685 by ensuring that magic values (such as LIST_POISON) will always
1686 fault when dereferenced.
1688 CPUs with low-vector mappings use a best-efforts implementation.
1689 Their lower 1MB needs to remain accessible for the vectors, but
1690 the remainder of userspace will become appropriately inaccessible.
1692 config HW_PERF_EVENTS
1693 def_bool y
1694 depends on ARM_PMU
1696 config SYS_SUPPORTS_HUGETLBFS
1697 def_bool y
1698 depends on ARM_LPAE
1700 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1701 def_bool y
1702 depends on ARM_LPAE
1704 config ARCH_WANT_GENERAL_HUGETLB
1705 def_bool y
1707 config ARM_MODULE_PLTS
1708 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1709 depends on MODULES
1710 default y
1711 help
1712 Allocate PLTs when loading modules so that jumps and calls whose
1713 targets are too far away for their relative offsets to be encoded
1714 in the instructions themselves can be bounced via veneers in the
1715 module's PLT. This allows modules to be allocated in the generic
1716 vmalloc area after the dedicated module memory area has been
1717 exhausted. The modules will use slightly more memory, but after
1718 rounding up to page size, the actual memory footprint is usually
1719 the same.
1721 Disabling this is usually safe for small single-platform
1722 configurations. If unsure, say y.
1724 source "mm/Kconfig"
1726 config FORCE_MAX_ZONEORDER
1727 int "Maximum zone order"
1728 default "12" if SOC_AM33XX
1729 default "9" if SA1111 || ARCH_EFM32
1730 default "11"
1731 help
1732 The kernel memory allocator divides physically contiguous memory
1733 blocks into "zones", where each zone is a power of two number of
1734 pages. This option selects the largest power of two that the kernel
1735 keeps in the memory allocator. If you need to allocate very large
1736 blocks of physically contiguous memory, then you may need to
1737 increase this value.
1739 This config option is actually maximum order plus one. For example,
1740 a value of 11 means that the largest free memory block is 2^10 pages.
1742 config ALIGNMENT_TRAP
1743 bool
1744 depends on CPU_CP15_MMU
1745 default y if !ARCH_EBSA110
1746 select HAVE_PROC_CPU if PROC_FS
1747 help
1748 ARM processors cannot fetch/store information which is not
1749 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1750 address divisible by 4. On 32-bit ARM processors, these non-aligned
1751 fetch/store instructions will be emulated in software if you say
1752 here, which has a severe performance impact. This is necessary for
1753 correct operation of some network protocols. With an IP-only
1754 configuration it is safe to say N, otherwise say Y.
1756 config UACCESS_WITH_MEMCPY
1757 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1758 depends on MMU
1759 default y if CPU_FEROCEON
1760 help
1761 Implement faster copy_to_user and clear_user methods for CPU
1762 cores where a 8-word STM instruction give significantly higher
1763 memory write throughput than a sequence of individual 32bit stores.
1765 A possible side effect is a slight increase in scheduling latency
1766 between threads sharing the same address space if they invoke
1767 such copy operations with large buffers.
1769 However, if the CPU data cache is using a write-allocate mode,
1770 this option is unlikely to provide any performance gain.
1772 config SECCOMP
1773 bool
1774 prompt "Enable seccomp to safely compute untrusted bytecode"
1775 ---help---
1776 This kernel feature is useful for number crunching applications
1777 that may need to compute untrusted bytecode during their
1778 execution. By using pipes or other transports made available to
1779 the process as file descriptors supporting the read/write
1780 syscalls, it's possible to isolate those applications in
1781 their own address space using seccomp. Once seccomp is
1782 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1783 and the task is only allowed to execute a few safe syscalls
1784 defined by each seccomp mode.
1786 config PARAVIRT
1787 bool "Enable paravirtualization code"
1788 help
1789 This changes the kernel so it can modify itself when it is run
1790 under a hypervisor, potentially improving performance significantly
1791 over full virtualization.
1793 config PARAVIRT_TIME_ACCOUNTING
1794 bool "Paravirtual steal time accounting"
1795 select PARAVIRT
1796 default n
1797 help
1798 Select this option to enable fine granularity task steal time
1799 accounting. Time spent executing other tasks in parallel with
1800 the current vCPU is discounted from the vCPU power. To account for
1801 that, there can be a small performance impact.
1803 If in doubt, say N here.
1805 config XEN_DOM0
1806 def_bool y
1807 depends on XEN
1809 config XEN
1810 bool "Xen guest support on ARM"
1811 depends on ARM && AEABI && OF
1812 depends on CPU_V7 && !CPU_V6
1813 depends on !GENERIC_ATOMIC64
1814 depends on MMU
1815 select ARCH_DMA_ADDR_T_64BIT
1816 select ARM_PSCI
1817 select SWIOTLB
1818 select SWIOTLB_XEN
1819 select PARAVIRT
1820 help
1821 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1823 endmenu
1825 menu "Boot options"
1827 config USE_OF
1828 bool "Flattened Device Tree support"
1829 select IRQ_DOMAIN
1830 select OF
1831 help
1832 Include support for flattened device tree machine descriptions.
1834 config ATAGS
1835 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1836 default y
1837 help
1838 This is the traditional way of passing data to the kernel at boot
1839 time. If you are solely relying on the flattened device tree (or
1840 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1841 to remove ATAGS support from your kernel binary. If unsure,
1842 leave this to y.
1844 config DEPRECATED_PARAM_STRUCT
1845 bool "Provide old way to pass kernel parameters"
1846 depends on ATAGS
1847 help
1848 This was deprecated in 2001 and announced to live on for 5 years.
1849 Some old boot loaders still use this way.
1851 # Compressed boot loader in ROM. Yes, we really want to ask about
1852 # TEXT and BSS so we preserve their values in the config files.
1853 config ZBOOT_ROM_TEXT
1854 hex "Compressed ROM boot loader base address"
1855 default "0"
1856 help
1857 The physical address at which the ROM-able zImage is to be
1858 placed in the target. Platforms which normally make use of
1859 ROM-able zImage formats normally set this to a suitable
1860 value in their defconfig file.
1862 If ZBOOT_ROM is not enabled, this has no effect.
1864 config ZBOOT_ROM_BSS
1865 hex "Compressed ROM boot loader BSS address"
1866 default "0"
1867 help
1868 The base address of an area of read/write memory in the target
1869 for the ROM-able zImage which must be available while the
1870 decompressor is running. It must be large enough to hold the
1871 entire decompressed kernel plus an additional 128 KiB.
1872 Platforms which normally make use of ROM-able zImage formats
1873 normally set this to a suitable value in their defconfig file.
1875 If ZBOOT_ROM is not enabled, this has no effect.
1877 config ZBOOT_ROM
1878 bool "Compressed boot loader in ROM/flash"
1879 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1880 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1881 help
1882 Say Y here if you intend to execute your compressed kernel image
1883 (zImage) directly from ROM or flash. If unsure, say N.
1885 config ARM_APPENDED_DTB
1886 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1887 depends on OF
1888 help
1889 With this option, the boot code will look for a device tree binary
1890 (DTB) appended to zImage
1891 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1893 This is meant as a backward compatibility convenience for those
1894 systems with a bootloader that can't be upgraded to accommodate
1895 the documented boot protocol using a device tree.
1897 Beware that there is very little in terms of protection against
1898 this option being confused by leftover garbage in memory that might
1899 look like a DTB header after a reboot if no actual DTB is appended
1900 to zImage. Do not leave this option active in a production kernel
1901 if you don't intend to always append a DTB. Proper passing of the
1902 location into r2 of a bootloader provided DTB is always preferable
1903 to this option.
1905 config ARM_ATAG_DTB_COMPAT
1906 bool "Supplement the appended DTB with traditional ATAG information"
1907 depends on ARM_APPENDED_DTB
1908 help
1909 Some old bootloaders can't be updated to a DTB capable one, yet
1910 they provide ATAGs with memory configuration, the ramdisk address,
1911 the kernel cmdline string, etc. Such information is dynamically
1912 provided by the bootloader and can't always be stored in a static
1913 DTB. To allow a device tree enabled kernel to be used with such
1914 bootloaders, this option allows zImage to extract the information
1915 from the ATAG list and store it at run time into the appended DTB.
1917 choice
1918 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1919 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1921 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1922 bool "Use bootloader kernel arguments if available"
1923 help
1924 Uses the command-line options passed by the boot loader instead of
1925 the device tree bootargs property. If the boot loader doesn't provide
1926 any, the device tree bootargs property will be used.
1928 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1929 bool "Extend with bootloader kernel arguments"
1930 help
1931 The command-line arguments provided by the boot loader will be
1932 appended to the the device tree bootargs property.
1934 endchoice
1936 config CMDLINE
1937 string "Default kernel command string"
1938 default ""
1939 help
1940 On some architectures (EBSA110 and CATS), there is currently no way
1941 for the boot loader to pass arguments to the kernel. For these
1942 architectures, you should supply some command-line options at build
1943 time by entering them here. As a minimum, you should specify the
1944 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1946 choice
1947 prompt "Kernel command line type" if CMDLINE != ""
1948 default CMDLINE_FROM_BOOTLOADER
1949 depends on ATAGS
1951 config CMDLINE_FROM_BOOTLOADER
1952 bool "Use bootloader kernel arguments if available"
1953 help
1954 Uses the command-line options passed by the boot loader. If
1955 the boot loader doesn't provide any, the default kernel command
1956 string provided in CMDLINE will be used.
1958 config CMDLINE_EXTEND
1959 bool "Extend bootloader kernel arguments"
1960 help
1961 The command-line arguments provided by the boot loader will be
1962 appended to the default kernel command string.
1964 config CMDLINE_FORCE
1965 bool "Always use the default kernel command string"
1966 help
1967 Always use the default kernel command string, even if the boot
1968 loader passes other arguments to the kernel.
1969 This is useful if you cannot or don't want to change the
1970 command-line options your boot loader passes to the kernel.
1971 endchoice
1973 config XIP_KERNEL
1974 bool "Kernel Execute-In-Place from ROM"
1975 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1976 help
1977 Execute-In-Place allows the kernel to run from non-volatile storage
1978 directly addressable by the CPU, such as NOR flash. This saves RAM
1979 space since the text section of the kernel is not loaded from flash
1980 to RAM. Read-write sections, such as the data section and stack,
1981 are still copied to RAM. The XIP kernel is not compressed since
1982 it has to run directly from flash, so it will take more space to
1983 store it. The flash address used to link the kernel object files,
1984 and for storing it, is configuration dependent. Therefore, if you
1985 say Y here, you must know the proper physical address where to
1986 store the kernel image depending on your own flash memory usage.
1988 Also note that the make target becomes "make xipImage" rather than
1989 "make zImage" or "make Image". The final kernel binary to put in
1990 ROM memory will be arch/arm/boot/xipImage.
1992 If unsure, say N.
1994 config XIP_PHYS_ADDR
1995 hex "XIP Kernel Physical Location"
1996 depends on XIP_KERNEL
1997 default "0x00080000"
1998 help
1999 This is the physical address in your flash memory the kernel will
2000 be linked for and stored to. This address is dependent on your
2001 own flash usage.
2003 config XIP_DEFLATED_DATA
2004 bool "Store kernel .data section compressed in ROM"
2005 depends on XIP_KERNEL
2006 select ZLIB_INFLATE
2007 help
2008 Before the kernel is actually executed, its .data section has to be
2009 copied to RAM from ROM. This option allows for storing that data
2010 in compressed form and decompressed to RAM rather than merely being
2011 copied, saving some precious ROM space. A possible drawback is a
2012 slightly longer boot delay.
2014 config KEXEC
2015 bool "Kexec system call (EXPERIMENTAL)"
2016 depends on (!SMP || PM_SLEEP_SMP)
2017 depends on !CPU_V7M
2018 select KEXEC_CORE
2019 help
2020 kexec is a system call that implements the ability to shutdown your
2021 current kernel, and to start another kernel. It is like a reboot
2022 but it is independent of the system firmware. And like a reboot
2023 you can start any kernel with it, not just Linux.
2025 It is an ongoing process to be certain the hardware in a machine
2026 is properly shutdown, so do not be surprised if this code does not
2027 initially work for you.
2029 config ATAGS_PROC
2030 bool "Export atags in procfs"
2031 depends on ATAGS && KEXEC
2032 default y
2033 help
2034 Should the atags used to boot the kernel be exported in an "atags"
2035 file in procfs. Useful with kexec.
2037 config CRASH_DUMP
2038 bool "Build kdump crash kernel (EXPERIMENTAL)"
2039 help
2040 Generate crash dump after being started by kexec. This should
2041 be normally only set in special crash dump kernels which are
2042 loaded in the main kernel with kexec-tools into a specially
2043 reserved region and then later executed after a crash by
2044 kdump/kexec. The crash dump kernel must be compiled to a
2045 memory address not used by the main kernel
2047 For more details see Documentation/kdump/kdump.txt
2049 config AUTO_ZRELADDR
2050 bool "Auto calculation of the decompressed kernel image address"
2051 help
2052 ZRELADDR is the physical address where the decompressed kernel
2053 image will be placed. If AUTO_ZRELADDR is selected, the address
2054 will be determined at run-time by masking the current IP with
2055 0xf8000000. This assumes the zImage being placed in the first 128MB
2056 from start of memory.
2058 config EFI_STUB
2059 bool
2061 config EFI
2062 bool "UEFI runtime support"
2063 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2064 select UCS2_STRING
2065 select EFI_PARAMS_FROM_FDT
2066 select EFI_STUB
2067 select EFI_ARMSTUB
2068 select EFI_RUNTIME_WRAPPERS
2069 ---help---
2070 This option provides support for runtime services provided
2071 by UEFI firmware (such as non-volatile variables, realtime
2072 clock, and platform reset). A UEFI stub is also provided to
2073 allow the kernel to be booted as an EFI application. This
2074 is only useful for kernels that may run on systems that have
2075 UEFI firmware.
2077 config DMI
2078 bool "Enable support for SMBIOS (DMI) tables"
2079 depends on EFI
2080 default y
2081 help
2082 This enables SMBIOS/DMI feature for systems.
2084 This option is only useful on systems that have UEFI firmware.
2085 However, even with this option, the resultant kernel should
2086 continue to boot on existing non-UEFI platforms.
2088 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2089 i.e., the the practice of identifying the platform via DMI to
2090 decide whether certain workarounds for buggy hardware and/or
2091 firmware need to be enabled. This would require the DMI subsystem
2092 to be enabled much earlier than we do on ARM, which is non-trivial.
2094 endmenu
2096 menu "CPU Power Management"
2098 source "drivers/cpufreq/Kconfig"
2100 source "drivers/cpuidle/Kconfig"
2102 endmenu
2104 menu "Floating point emulation"
2106 comment "At least one emulation must be selected"
2108 config FPE_NWFPE
2109 bool "NWFPE math emulation"
2110 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2111 ---help---
2112 Say Y to include the NWFPE floating point emulator in the kernel.
2113 This is necessary to run most binaries. Linux does not currently
2114 support floating point hardware so you need to say Y here even if
2115 your machine has an FPA or floating point co-processor podule.
2117 You may say N here if you are going to load the Acorn FPEmulator
2118 early in the bootup.
2120 config FPE_NWFPE_XP
2121 bool "Support extended precision"
2122 depends on FPE_NWFPE
2123 help
2124 Say Y to include 80-bit support in the kernel floating-point
2125 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2126 Note that gcc does not generate 80-bit operations by default,
2127 so in most cases this option only enlarges the size of the
2128 floating point emulator without any good reason.
2130 You almost surely want to say N here.
2132 config FPE_FASTFPE
2133 bool "FastFPE math emulation (EXPERIMENTAL)"
2134 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2135 ---help---
2136 Say Y here to include the FAST floating point emulator in the kernel.
2137 This is an experimental much faster emulator which now also has full
2138 precision for the mantissa. It does not support any exceptions.
2139 It is very simple, and approximately 3-6 times faster than NWFPE.
2141 It should be sufficient for most programs. It may be not suitable
2142 for scientific calculations, but you have to check this for yourself.
2143 If you do not feel you need a faster FP emulation you should better
2144 choose NWFPE.
2146 config VFP
2147 bool "VFP-format floating point maths"
2148 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2149 help
2150 Say Y to include VFP support code in the kernel. This is needed
2151 if your hardware includes a VFP unit.
2153 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2154 release notes and additional status information.
2156 Say N if your target does not have VFP hardware.
2158 config VFPv3
2159 bool
2160 depends on VFP
2161 default y if CPU_V7
2163 config NEON
2164 bool "Advanced SIMD (NEON) Extension support"
2165 depends on VFPv3 && CPU_V7
2166 help
2167 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2168 Extension.
2170 config KERNEL_MODE_NEON
2171 bool "Support for NEON in kernel mode"
2172 depends on NEON && AEABI
2173 help
2174 Say Y to include support for NEON in kernel mode.
2176 endmenu
2178 menu "Userspace binary formats"
2180 source "fs/Kconfig.binfmt"
2182 endmenu
2184 menu "Power management options"
2186 source "kernel/power/Kconfig"
2188 config ARCH_SUSPEND_POSSIBLE
2189 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2190 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2191 def_bool y
2193 config ARM_CPU_SUSPEND
2194 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2195 depends on ARCH_SUSPEND_POSSIBLE
2197 config ARCH_HIBERNATION_POSSIBLE
2198 bool
2199 depends on MMU
2200 default y if ARCH_SUSPEND_POSSIBLE
2202 endmenu
2204 source "net/Kconfig"
2206 source "drivers/Kconfig"
2208 source "drivers/firmware/Kconfig"
2210 source "fs/Kconfig"
2212 source "arch/arm/Kconfig.debug"
2214 source "security/Kconfig"
2216 source "crypto/Kconfig"
2217 if CRYPTO
2218 source "arch/arm/crypto/Kconfig"
2219 endif
2221 source "lib/Kconfig"
2223 source "arch/arm/kvm/Kconfig"