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Linux 4.18.10
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
blobe6c7061a8e73679695f7816c0461ccccf66151c6
1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/io.h>
21 #include <linux/platform_data/hsmmc-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/platform_data/i2c-omap.h>
24
25 #include <linux/omap-dma.h>
26
27 #include "omap_hwmod.h"
28 #include "omap_hwmod_common_data.h"
29 #include "cm1_7xx.h"
30 #include "cm2_7xx.h"
31 #include "prm7xx.h"
32 #include "i2c.h"
33 #include "wd_timer.h"
34 #include "soc.h"
35
36 /* Base offset for all DRA7XX interrupts external to MPUSS */
37 #define DRA7XX_IRQ_GIC_START 32
38
39 /* Base offset for all DRA7XX dma requests */
40 #define DRA7XX_DMA_REQ_START 1
41
42
43 /*
44 * IP blocks
45 */
46
47 /*
48 * 'dmm' class
49 * instance(s): dmm
50 */
51 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
52 .name = "dmm",
53 };
54
55 /* dmm */
56 static struct omap_hwmod dra7xx_dmm_hwmod = {
57 .name = "dmm",
58 .class = &dra7xx_dmm_hwmod_class,
59 .clkdm_name = "emif_clkdm",
60 .prcm = {
61 .omap4 = {
62 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
63 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
64 },
65 },
66 };
67
68 /*
69 * 'l3' class
70 * instance(s): l3_instr, l3_main_1, l3_main_2
71 */
72 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
73 .name = "l3",
74 };
75
76 /* l3_instr */
77 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
78 .name = "l3_instr",
79 .class = &dra7xx_l3_hwmod_class,
80 .clkdm_name = "l3instr_clkdm",
81 .prcm = {
82 .omap4 = {
83 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
84 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
85 .modulemode = MODULEMODE_HWCTRL,
86 },
87 },
88 };
89
90 /* l3_main_1 */
91 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
92 .name = "l3_main_1",
93 .class = &dra7xx_l3_hwmod_class,
94 .clkdm_name = "l3main1_clkdm",
95 .prcm = {
96 .omap4 = {
97 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
98 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
99 },
100 },
101 };
102
103 /* l3_main_2 */
104 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
105 .name = "l3_main_2",
106 .class = &dra7xx_l3_hwmod_class,
107 .clkdm_name = "l3instr_clkdm",
108 .prcm = {
109 .omap4 = {
110 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
111 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
112 .modulemode = MODULEMODE_HWCTRL,
113 },
114 },
115 };
116
117 /*
118 * 'l4' class
119 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
120 */
121 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
122 .name = "l4",
123 };
124
125 /* l4_cfg */
126 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
127 .name = "l4_cfg",
128 .class = &dra7xx_l4_hwmod_class,
129 .clkdm_name = "l4cfg_clkdm",
130 .prcm = {
131 .omap4 = {
132 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
133 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
134 },
135 },
136 };
137
138 /* l4_per1 */
139 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
140 .name = "l4_per1",
141 .class = &dra7xx_l4_hwmod_class,
142 .clkdm_name = "l4per_clkdm",
143 .prcm = {
144 .omap4 = {
145 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
146 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
147 },
148 },
149 };
150
151 /* l4_per2 */
152 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
153 .name = "l4_per2",
154 .class = &dra7xx_l4_hwmod_class,
155 .clkdm_name = "l4per2_clkdm",
156 .prcm = {
157 .omap4 = {
158 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
159 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
160 },
161 },
162 };
163
164 /* l4_per3 */
165 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
166 .name = "l4_per3",
167 .class = &dra7xx_l4_hwmod_class,
168 .clkdm_name = "l4per3_clkdm",
169 .prcm = {
170 .omap4 = {
171 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
172 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
173 },
174 },
175 };
176
177 /* l4_wkup */
178 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
179 .name = "l4_wkup",
180 .class = &dra7xx_l4_hwmod_class,
181 .clkdm_name = "wkupaon_clkdm",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
185 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
186 },
187 },
188 };
189
190 /*
191 * 'atl' class
192 *
193 */
194
195 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
196 .name = "atl",
197 };
198
199 /* atl */
200 static struct omap_hwmod dra7xx_atl_hwmod = {
201 .name = "atl",
202 .class = &dra7xx_atl_hwmod_class,
203 .clkdm_name = "atl_clkdm",
204 .main_clk = "atl_gfclk_mux",
205 .prcm = {
206 .omap4 = {
207 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
208 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
209 .modulemode = MODULEMODE_SWCTRL,
210 },
211 },
212 };
213
214 /*
215 * 'bb2d' class
216 *
217 */
218
219 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
220 .name = "bb2d",
221 };
222
223 /* bb2d */
224 static struct omap_hwmod dra7xx_bb2d_hwmod = {
225 .name = "bb2d",
226 .class = &dra7xx_bb2d_hwmod_class,
227 .clkdm_name = "dss_clkdm",
228 .main_clk = "dpll_core_h24x2_ck",
229 .prcm = {
230 .omap4 = {
231 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
232 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
233 .modulemode = MODULEMODE_SWCTRL,
234 },
235 },
236 };
237
238 /*
239 * 'counter' class
240 *
241 */
242
243 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
244 .rev_offs = 0x0000,
245 .sysc_offs = 0x0010,
246 .sysc_flags = SYSC_HAS_SIDLEMODE,
247 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
248 SIDLE_SMART_WKUP),
249 .sysc_fields = &omap_hwmod_sysc_type1,
250 };
251
252 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
253 .name = "counter",
254 .sysc = &dra7xx_counter_sysc,
255 };
256
257 /* counter_32k */
258 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
259 .name = "counter_32k",
260 .class = &dra7xx_counter_hwmod_class,
261 .clkdm_name = "wkupaon_clkdm",
262 .flags = HWMOD_SWSUP_SIDLE,
263 .main_clk = "wkupaon_iclk_mux",
264 .prcm = {
265 .omap4 = {
266 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
267 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
268 },
269 },
270 };
271
272 /*
273 * 'ctrl_module' class
274 *
275 */
276
277 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
278 .name = "ctrl_module",
279 };
280
281 /* ctrl_module_wkup */
282 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
283 .name = "ctrl_module_wkup",
284 .class = &dra7xx_ctrl_module_hwmod_class,
285 .clkdm_name = "wkupaon_clkdm",
286 .prcm = {
287 .omap4 = {
288 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
289 },
290 },
291 };
292
293 /*
294 * 'gmac' class
295 * cpsw/gmac sub system
296 */
297 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
298 .rev_offs = 0x0,
299 .sysc_offs = 0x8,
300 .syss_offs = 0x4,
301 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
302 SYSS_HAS_RESET_STATUS),
303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
304 MSTANDBY_NO),
305 .sysc_fields = &omap_hwmod_sysc_type3,
306 };
307
308 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
309 .name = "gmac",
310 .sysc = &dra7xx_gmac_sysc,
311 };
312
313 static struct omap_hwmod dra7xx_gmac_hwmod = {
314 .name = "gmac",
315 .class = &dra7xx_gmac_hwmod_class,
316 .clkdm_name = "gmac_clkdm",
317 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
318 .main_clk = "dpll_gmac_ck",
319 .mpu_rt_idx = 1,
320 .prcm = {
321 .omap4 = {
322 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
323 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
324 .modulemode = MODULEMODE_SWCTRL,
325 },
326 },
327 };
328
329 /*
330 * 'mdio' class
331 */
332 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
333 .name = "davinci_mdio",
334 };
335
336 static struct omap_hwmod dra7xx_mdio_hwmod = {
337 .name = "davinci_mdio",
338 .class = &dra7xx_mdio_hwmod_class,
339 .clkdm_name = "gmac_clkdm",
340 .main_clk = "dpll_gmac_ck",
341 };
342
343 /*
344 * 'dcan' class
345 *
346 */
347
348 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
349 .name = "dcan",
350 };
351
352 /* dcan1 */
353 static struct omap_hwmod dra7xx_dcan1_hwmod = {
354 .name = "dcan1",
355 .class = &dra7xx_dcan_hwmod_class,
356 .clkdm_name = "wkupaon_clkdm",
357 .main_clk = "dcan1_sys_clk_mux",
358 .flags = HWMOD_CLKDM_NOAUTO,
359 .prcm = {
360 .omap4 = {
361 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
362 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
363 .modulemode = MODULEMODE_SWCTRL,
364 },
365 },
366 };
367
368 /* dcan2 */
369 static struct omap_hwmod dra7xx_dcan2_hwmod = {
370 .name = "dcan2",
371 .class = &dra7xx_dcan_hwmod_class,
372 .clkdm_name = "l4per2_clkdm",
373 .main_clk = "sys_clkin1",
374 .flags = HWMOD_CLKDM_NOAUTO,
375 .prcm = {
376 .omap4 = {
377 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
378 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
379 .modulemode = MODULEMODE_SWCTRL,
380 },
381 },
382 };
383
384 /* pwmss */
385 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
386 .rev_offs = 0x0,
387 .sysc_offs = 0x4,
388 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
389 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
390 .sysc_fields = &omap_hwmod_sysc_type2,
391 };
392
393 /*
394 * epwmss class
395 */
396 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
397 .name = "epwmss",
398 .sysc = &dra7xx_epwmss_sysc,
399 };
400
401 /* epwmss0 */
402 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
403 .name = "epwmss0",
404 .class = &dra7xx_epwmss_hwmod_class,
405 .clkdm_name = "l4per2_clkdm",
406 .main_clk = "l4_root_clk_div",
407 .prcm = {
408 .omap4 = {
409 .modulemode = MODULEMODE_SWCTRL,
410 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
412 },
413 },
414 };
415
416 /* epwmss1 */
417 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
418 .name = "epwmss1",
419 .class = &dra7xx_epwmss_hwmod_class,
420 .clkdm_name = "l4per2_clkdm",
421 .main_clk = "l4_root_clk_div",
422 .prcm = {
423 .omap4 = {
424 .modulemode = MODULEMODE_SWCTRL,
425 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
427 },
428 },
429 };
430
431 /* epwmss2 */
432 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
433 .name = "epwmss2",
434 .class = &dra7xx_epwmss_hwmod_class,
435 .clkdm_name = "l4per2_clkdm",
436 .main_clk = "l4_root_clk_div",
437 .prcm = {
438 .omap4 = {
439 .modulemode = MODULEMODE_SWCTRL,
440 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
441 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
442 },
443 },
444 };
445
446 /*
447 * 'dma' class
448 *
449 */
450
451 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
452 .rev_offs = 0x0000,
453 .sysc_offs = 0x002c,
454 .syss_offs = 0x0028,
455 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
456 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
457 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
458 SYSS_HAS_RESET_STATUS),
459 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
460 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
461 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
462 .sysc_fields = &omap_hwmod_sysc_type1,
463 };
464
465 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
466 .name = "dma",
467 .sysc = &dra7xx_dma_sysc,
468 };
469
470 /* dma dev_attr */
471 static struct omap_dma_dev_attr dma_dev_attr = {
472 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
473 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
474 .lch_count = 32,
475 };
476
477 /* dma_system */
478 static struct omap_hwmod dra7xx_dma_system_hwmod = {
479 .name = "dma_system",
480 .class = &dra7xx_dma_hwmod_class,
481 .clkdm_name = "dma_clkdm",
482 .main_clk = "l3_iclk_div",
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
486 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
487 },
488 },
489 .dev_attr = &dma_dev_attr,
490 };
491
492 /*
493 * 'tpcc' class
494 *
495 */
496 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
497 .name = "tpcc",
498 };
499
500 static struct omap_hwmod dra7xx_tpcc_hwmod = {
501 .name = "tpcc",
502 .class = &dra7xx_tpcc_hwmod_class,
503 .clkdm_name = "l3main1_clkdm",
504 .main_clk = "l3_iclk_div",
505 .prcm = {
506 .omap4 = {
507 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
508 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
509 },
510 },
511 };
512
513 /*
514 * 'tptc' class
515 *
516 */
517 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
518 .name = "tptc",
519 };
520
521 /* tptc0 */
522 static struct omap_hwmod dra7xx_tptc0_hwmod = {
523 .name = "tptc0",
524 .class = &dra7xx_tptc_hwmod_class,
525 .clkdm_name = "l3main1_clkdm",
526 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
527 .main_clk = "l3_iclk_div",
528 .prcm = {
529 .omap4 = {
530 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
531 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
532 .modulemode = MODULEMODE_HWCTRL,
533 },
534 },
535 };
536
537 /* tptc1 */
538 static struct omap_hwmod dra7xx_tptc1_hwmod = {
539 .name = "tptc1",
540 .class = &dra7xx_tptc_hwmod_class,
541 .clkdm_name = "l3main1_clkdm",
542 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
543 .main_clk = "l3_iclk_div",
544 .prcm = {
545 .omap4 = {
546 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
547 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
548 .modulemode = MODULEMODE_HWCTRL,
549 },
550 },
551 };
552
553 /*
554 * 'dss' class
555 *
556 */
557
558 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
559 .rev_offs = 0x0000,
560 .syss_offs = 0x0014,
561 .sysc_flags = SYSS_HAS_RESET_STATUS,
562 };
563
564 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
565 .name = "dss",
566 .sysc = &dra7xx_dss_sysc,
567 .reset = omap_dss_reset,
568 };
569
570 /* dss */
571 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
572 { .role = "dss_clk", .clk = "dss_dss_clk" },
573 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
574 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
575 { .role = "video2_clk", .clk = "dss_video2_clk" },
576 { .role = "video1_clk", .clk = "dss_video1_clk" },
577 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
578 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
579 };
580
581 static struct omap_hwmod dra7xx_dss_hwmod = {
582 .name = "dss_core",
583 .class = &dra7xx_dss_hwmod_class,
584 .clkdm_name = "dss_clkdm",
585 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
586 .main_clk = "dss_dss_clk",
587 .prcm = {
588 .omap4 = {
589 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
590 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
591 .modulemode = MODULEMODE_SWCTRL,
592 },
593 },
594 .opt_clks = dss_opt_clks,
595 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
596 };
597
598 /*
599 * 'dispc' class
600 * display controller
601 */
602
603 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
604 .rev_offs = 0x0000,
605 .sysc_offs = 0x0010,
606 .syss_offs = 0x0014,
607 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
608 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
609 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
610 SYSS_HAS_RESET_STATUS),
611 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
612 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
613 .sysc_fields = &omap_hwmod_sysc_type1,
614 };
615
616 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
617 .name = "dispc",
618 .sysc = &dra7xx_dispc_sysc,
619 };
620
621 /* dss_dispc */
622 /* dss_dispc dev_attr */
623 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
624 .has_framedonetv_irq = 1,
625 .manager_count = 4,
626 };
627
628 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
629 .name = "dss_dispc",
630 .class = &dra7xx_dispc_hwmod_class,
631 .clkdm_name = "dss_clkdm",
632 .main_clk = "dss_dss_clk",
633 .prcm = {
634 .omap4 = {
635 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
636 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
637 },
638 },
639 .dev_attr = &dss_dispc_dev_attr,
640 .parent_hwmod = &dra7xx_dss_hwmod,
641 };
642
643 /*
644 * 'hdmi' class
645 * hdmi controller
646 */
647
648 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
649 .rev_offs = 0x0000,
650 .sysc_offs = 0x0010,
651 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
652 SYSC_HAS_SOFTRESET),
653 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
654 SIDLE_SMART_WKUP),
655 .sysc_fields = &omap_hwmod_sysc_type2,
656 };
657
658 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
659 .name = "hdmi",
660 .sysc = &dra7xx_hdmi_sysc,
661 };
662
663 /* dss_hdmi */
664
665 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
666 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
667 };
668
669 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
670 .name = "dss_hdmi",
671 .class = &dra7xx_hdmi_hwmod_class,
672 .clkdm_name = "dss_clkdm",
673 .main_clk = "dss_48mhz_clk",
674 .prcm = {
675 .omap4 = {
676 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
677 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
678 },
679 },
680 .opt_clks = dss_hdmi_opt_clks,
681 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
682 .parent_hwmod = &dra7xx_dss_hwmod,
683 };
684
685 /* AES (the 'P' (public) device) */
686 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
687 .rev_offs = 0x0080,
688 .sysc_offs = 0x0084,
689 .syss_offs = 0x0088,
690 .sysc_flags = SYSS_HAS_RESET_STATUS,
691 };
692
693 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
694 .name = "aes",
695 .sysc = &dra7xx_aes_sysc,
696 .rev = 2,
697 };
698
699 /* AES1 */
700 static struct omap_hwmod dra7xx_aes1_hwmod = {
701 .name = "aes1",
702 .class = &dra7xx_aes_hwmod_class,
703 .clkdm_name = "l4sec_clkdm",
704 .main_clk = "l3_iclk_div",
705 .prcm = {
706 .omap4 = {
707 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
708 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
709 .modulemode = MODULEMODE_HWCTRL,
710 },
711 },
712 };
713
714 /* AES2 */
715 static struct omap_hwmod dra7xx_aes2_hwmod = {
716 .name = "aes2",
717 .class = &dra7xx_aes_hwmod_class,
718 .clkdm_name = "l4sec_clkdm",
719 .main_clk = "l3_iclk_div",
720 .prcm = {
721 .omap4 = {
722 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
723 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
724 .modulemode = MODULEMODE_HWCTRL,
725 },
726 },
727 };
728
729 /* sha0 HIB2 (the 'P' (public) device) */
730 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
731 .rev_offs = 0x100,
732 .sysc_offs = 0x110,
733 .syss_offs = 0x114,
734 .sysc_flags = SYSS_HAS_RESET_STATUS,
735 };
736
737 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
738 .name = "sham",
739 .sysc = &dra7xx_sha0_sysc,
740 .rev = 2,
741 };
742
743 struct omap_hwmod dra7xx_sha0_hwmod = {
744 .name = "sham",
745 .class = &dra7xx_sha0_hwmod_class,
746 .clkdm_name = "l4sec_clkdm",
747 .main_clk = "l3_iclk_div",
748 .prcm = {
749 .omap4 = {
750 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
751 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
752 .modulemode = MODULEMODE_HWCTRL,
753 },
754 },
755 };
756
757 /*
758 * 'elm' class
759 *
760 */
761
762 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
763 .rev_offs = 0x0000,
764 .sysc_offs = 0x0010,
765 .syss_offs = 0x0014,
766 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
767 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
768 SYSS_HAS_RESET_STATUS),
769 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
770 SIDLE_SMART_WKUP),
771 .sysc_fields = &omap_hwmod_sysc_type1,
772 };
773
774 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
775 .name = "elm",
776 .sysc = &dra7xx_elm_sysc,
777 };
778
779 /* elm */
780
781 static struct omap_hwmod dra7xx_elm_hwmod = {
782 .name = "elm",
783 .class = &dra7xx_elm_hwmod_class,
784 .clkdm_name = "l4per_clkdm",
785 .main_clk = "l3_iclk_div",
786 .prcm = {
787 .omap4 = {
788 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
789 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
790 },
791 },
792 };
793
794 /*
795 * 'gpio' class
796 *
797 */
798
799 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
800 .rev_offs = 0x0000,
801 .sysc_offs = 0x0010,
802 .syss_offs = 0x0114,
803 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
804 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
805 SYSS_HAS_RESET_STATUS),
806 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
807 SIDLE_SMART_WKUP),
808 .sysc_fields = &omap_hwmod_sysc_type1,
809 };
810
811 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
812 .name = "gpio",
813 .sysc = &dra7xx_gpio_sysc,
814 .rev = 2,
815 };
816
817 /* gpio1 */
818 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
819 { .role = "dbclk", .clk = "gpio1_dbclk" },
820 };
821
822 static struct omap_hwmod dra7xx_gpio1_hwmod = {
823 .name = "gpio1",
824 .class = &dra7xx_gpio_hwmod_class,
825 .clkdm_name = "wkupaon_clkdm",
826 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
827 .main_clk = "wkupaon_iclk_mux",
828 .prcm = {
829 .omap4 = {
830 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
831 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
832 .modulemode = MODULEMODE_HWCTRL,
833 },
834 },
835 .opt_clks = gpio1_opt_clks,
836 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
837 };
838
839 /* gpio2 */
840 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
841 { .role = "dbclk", .clk = "gpio2_dbclk" },
842 };
843
844 static struct omap_hwmod dra7xx_gpio2_hwmod = {
845 .name = "gpio2",
846 .class = &dra7xx_gpio_hwmod_class,
847 .clkdm_name = "l4per_clkdm",
848 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
849 .main_clk = "l3_iclk_div",
850 .prcm = {
851 .omap4 = {
852 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
853 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
854 .modulemode = MODULEMODE_HWCTRL,
855 },
856 },
857 .opt_clks = gpio2_opt_clks,
858 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
859 };
860
861 /* gpio3 */
862 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
863 { .role = "dbclk", .clk = "gpio3_dbclk" },
864 };
865
866 static struct omap_hwmod dra7xx_gpio3_hwmod = {
867 .name = "gpio3",
868 .class = &dra7xx_gpio_hwmod_class,
869 .clkdm_name = "l4per_clkdm",
870 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
871 .main_clk = "l3_iclk_div",
872 .prcm = {
873 .omap4 = {
874 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
875 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
876 .modulemode = MODULEMODE_HWCTRL,
877 },
878 },
879 .opt_clks = gpio3_opt_clks,
880 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
881 };
882
883 /* gpio4 */
884 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
885 { .role = "dbclk", .clk = "gpio4_dbclk" },
886 };
887
888 static struct omap_hwmod dra7xx_gpio4_hwmod = {
889 .name = "gpio4",
890 .class = &dra7xx_gpio_hwmod_class,
891 .clkdm_name = "l4per_clkdm",
892 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
893 .main_clk = "l3_iclk_div",
894 .prcm = {
895 .omap4 = {
896 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
897 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
898 .modulemode = MODULEMODE_HWCTRL,
899 },
900 },
901 .opt_clks = gpio4_opt_clks,
902 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
903 };
904
905 /* gpio5 */
906 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
907 { .role = "dbclk", .clk = "gpio5_dbclk" },
908 };
909
910 static struct omap_hwmod dra7xx_gpio5_hwmod = {
911 .name = "gpio5",
912 .class = &dra7xx_gpio_hwmod_class,
913 .clkdm_name = "l4per_clkdm",
914 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
915 .main_clk = "l3_iclk_div",
916 .prcm = {
917 .omap4 = {
918 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
919 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
920 .modulemode = MODULEMODE_HWCTRL,
921 },
922 },
923 .opt_clks = gpio5_opt_clks,
924 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
925 };
926
927 /* gpio6 */
928 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
929 { .role = "dbclk", .clk = "gpio6_dbclk" },
930 };
931
932 static struct omap_hwmod dra7xx_gpio6_hwmod = {
933 .name = "gpio6",
934 .class = &dra7xx_gpio_hwmod_class,
935 .clkdm_name = "l4per_clkdm",
936 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
937 .main_clk = "l3_iclk_div",
938 .prcm = {
939 .omap4 = {
940 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
941 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
942 .modulemode = MODULEMODE_HWCTRL,
943 },
944 },
945 .opt_clks = gpio6_opt_clks,
946 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
947 };
948
949 /* gpio7 */
950 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
951 { .role = "dbclk", .clk = "gpio7_dbclk" },
952 };
953
954 static struct omap_hwmod dra7xx_gpio7_hwmod = {
955 .name = "gpio7",
956 .class = &dra7xx_gpio_hwmod_class,
957 .clkdm_name = "l4per_clkdm",
958 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
959 .main_clk = "l3_iclk_div",
960 .prcm = {
961 .omap4 = {
962 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
963 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
964 .modulemode = MODULEMODE_HWCTRL,
965 },
966 },
967 .opt_clks = gpio7_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
969 };
970
971 /* gpio8 */
972 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
973 { .role = "dbclk", .clk = "gpio8_dbclk" },
974 };
975
976 static struct omap_hwmod dra7xx_gpio8_hwmod = {
977 .name = "gpio8",
978 .class = &dra7xx_gpio_hwmod_class,
979 .clkdm_name = "l4per_clkdm",
980 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
981 .main_clk = "l3_iclk_div",
982 .prcm = {
983 .omap4 = {
984 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
985 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
986 .modulemode = MODULEMODE_HWCTRL,
987 },
988 },
989 .opt_clks = gpio8_opt_clks,
990 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
991 };
992
993 /*
994 * 'gpmc' class
995 *
996 */
997
998 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
999 .rev_offs = 0x0000,
1000 .sysc_offs = 0x0010,
1001 .syss_offs = 0x0014,
1002 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1003 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1005 .sysc_fields = &omap_hwmod_sysc_type1,
1006 };
1007
1008 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1009 .name = "gpmc",
1010 .sysc = &dra7xx_gpmc_sysc,
1011 };
1012
1013 /* gpmc */
1014
1015 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1016 .name = "gpmc",
1017 .class = &dra7xx_gpmc_hwmod_class,
1018 .clkdm_name = "l3main1_clkdm",
1019 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1020 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1021 .main_clk = "l3_iclk_div",
1022 .prcm = {
1023 .omap4 = {
1024 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1025 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1026 .modulemode = MODULEMODE_HWCTRL,
1027 },
1028 },
1029 };
1030
1031 /*
1032 * 'hdq1w' class
1033 *
1034 */
1035
1036 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1037 .rev_offs = 0x0000,
1038 .sysc_offs = 0x0014,
1039 .syss_offs = 0x0018,
1040 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1041 SYSS_HAS_RESET_STATUS),
1042 .sysc_fields = &omap_hwmod_sysc_type1,
1043 };
1044
1045 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1046 .name = "hdq1w",
1047 .sysc = &dra7xx_hdq1w_sysc,
1048 };
1049
1050 /* hdq1w */
1051
1052 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1053 .name = "hdq1w",
1054 .class = &dra7xx_hdq1w_hwmod_class,
1055 .clkdm_name = "l4per_clkdm",
1056 .flags = HWMOD_INIT_NO_RESET,
1057 .main_clk = "func_12m_fclk",
1058 .prcm = {
1059 .omap4 = {
1060 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1061 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1062 .modulemode = MODULEMODE_SWCTRL,
1063 },
1064 },
1065 };
1066
1067 /*
1068 * 'i2c' class
1069 *
1070 */
1071
1072 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1073 .rev_offs = 0,
1074 .sysc_offs = 0x0010,
1075 .syss_offs = 0x0090,
1076 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1077 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1078 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1079 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1080 SIDLE_SMART_WKUP),
1081 .sysc_fields = &omap_hwmod_sysc_type1,
1082 };
1083
1084 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1085 .name = "i2c",
1086 .sysc = &dra7xx_i2c_sysc,
1087 .reset = &omap_i2c_reset,
1088 .rev = OMAP_I2C_IP_VERSION_2,
1089 };
1090
1091 /* i2c1 */
1092 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1093 .name = "i2c1",
1094 .class = &dra7xx_i2c_hwmod_class,
1095 .clkdm_name = "l4per_clkdm",
1096 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1097 .main_clk = "func_96m_fclk",
1098 .prcm = {
1099 .omap4 = {
1100 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1101 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1102 .modulemode = MODULEMODE_SWCTRL,
1103 },
1104 },
1105 };
1106
1107 /* i2c2 */
1108 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1109 .name = "i2c2",
1110 .class = &dra7xx_i2c_hwmod_class,
1111 .clkdm_name = "l4per_clkdm",
1112 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1113 .main_clk = "func_96m_fclk",
1114 .prcm = {
1115 .omap4 = {
1116 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1117 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1118 .modulemode = MODULEMODE_SWCTRL,
1119 },
1120 },
1121 };
1122
1123 /* i2c3 */
1124 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1125 .name = "i2c3",
1126 .class = &dra7xx_i2c_hwmod_class,
1127 .clkdm_name = "l4per_clkdm",
1128 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1129 .main_clk = "func_96m_fclk",
1130 .prcm = {
1131 .omap4 = {
1132 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1133 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1134 .modulemode = MODULEMODE_SWCTRL,
1135 },
1136 },
1137 };
1138
1139 /* i2c4 */
1140 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1141 .name = "i2c4",
1142 .class = &dra7xx_i2c_hwmod_class,
1143 .clkdm_name = "l4per_clkdm",
1144 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1145 .main_clk = "func_96m_fclk",
1146 .prcm = {
1147 .omap4 = {
1148 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1149 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1150 .modulemode = MODULEMODE_SWCTRL,
1151 },
1152 },
1153 };
1154
1155 /* i2c5 */
1156 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1157 .name = "i2c5",
1158 .class = &dra7xx_i2c_hwmod_class,
1159 .clkdm_name = "ipu_clkdm",
1160 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1161 .main_clk = "func_96m_fclk",
1162 .prcm = {
1163 .omap4 = {
1164 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1165 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1166 .modulemode = MODULEMODE_SWCTRL,
1167 },
1168 },
1169 };
1170
1171 /*
1172 * 'mailbox' class
1173 *
1174 */
1175
1176 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1177 .rev_offs = 0x0000,
1178 .sysc_offs = 0x0010,
1179 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1180 SYSC_HAS_SOFTRESET),
1181 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1182 .sysc_fields = &omap_hwmod_sysc_type2,
1183 };
1184
1185 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1186 .name = "mailbox",
1187 .sysc = &dra7xx_mailbox_sysc,
1188 };
1189
1190 /* mailbox1 */
1191 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1192 .name = "mailbox1",
1193 .class = &dra7xx_mailbox_hwmod_class,
1194 .clkdm_name = "l4cfg_clkdm",
1195 .prcm = {
1196 .omap4 = {
1197 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1198 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1199 },
1200 },
1201 };
1202
1203 /* mailbox2 */
1204 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1205 .name = "mailbox2",
1206 .class = &dra7xx_mailbox_hwmod_class,
1207 .clkdm_name = "l4cfg_clkdm",
1208 .prcm = {
1209 .omap4 = {
1210 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1211 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1212 },
1213 },
1214 };
1215
1216 /* mailbox3 */
1217 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1218 .name = "mailbox3",
1219 .class = &dra7xx_mailbox_hwmod_class,
1220 .clkdm_name = "l4cfg_clkdm",
1221 .prcm = {
1222 .omap4 = {
1223 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1224 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1225 },
1226 },
1227 };
1228
1229 /* mailbox4 */
1230 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1231 .name = "mailbox4",
1232 .class = &dra7xx_mailbox_hwmod_class,
1233 .clkdm_name = "l4cfg_clkdm",
1234 .prcm = {
1235 .omap4 = {
1236 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1237 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1238 },
1239 },
1240 };
1241
1242 /* mailbox5 */
1243 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1244 .name = "mailbox5",
1245 .class = &dra7xx_mailbox_hwmod_class,
1246 .clkdm_name = "l4cfg_clkdm",
1247 .prcm = {
1248 .omap4 = {
1249 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1250 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1251 },
1252 },
1253 };
1254
1255 /* mailbox6 */
1256 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1257 .name = "mailbox6",
1258 .class = &dra7xx_mailbox_hwmod_class,
1259 .clkdm_name = "l4cfg_clkdm",
1260 .prcm = {
1261 .omap4 = {
1262 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1263 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1264 },
1265 },
1266 };
1267
1268 /* mailbox7 */
1269 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1270 .name = "mailbox7",
1271 .class = &dra7xx_mailbox_hwmod_class,
1272 .clkdm_name = "l4cfg_clkdm",
1273 .prcm = {
1274 .omap4 = {
1275 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1276 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1277 },
1278 },
1279 };
1280
1281 /* mailbox8 */
1282 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1283 .name = "mailbox8",
1284 .class = &dra7xx_mailbox_hwmod_class,
1285 .clkdm_name = "l4cfg_clkdm",
1286 .prcm = {
1287 .omap4 = {
1288 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1289 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1290 },
1291 },
1292 };
1293
1294 /* mailbox9 */
1295 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1296 .name = "mailbox9",
1297 .class = &dra7xx_mailbox_hwmod_class,
1298 .clkdm_name = "l4cfg_clkdm",
1299 .prcm = {
1300 .omap4 = {
1301 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1302 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1303 },
1304 },
1305 };
1306
1307 /* mailbox10 */
1308 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1309 .name = "mailbox10",
1310 .class = &dra7xx_mailbox_hwmod_class,
1311 .clkdm_name = "l4cfg_clkdm",
1312 .prcm = {
1313 .omap4 = {
1314 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1315 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1316 },
1317 },
1318 };
1319
1320 /* mailbox11 */
1321 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1322 .name = "mailbox11",
1323 .class = &dra7xx_mailbox_hwmod_class,
1324 .clkdm_name = "l4cfg_clkdm",
1325 .prcm = {
1326 .omap4 = {
1327 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1328 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1329 },
1330 },
1331 };
1332
1333 /* mailbox12 */
1334 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1335 .name = "mailbox12",
1336 .class = &dra7xx_mailbox_hwmod_class,
1337 .clkdm_name = "l4cfg_clkdm",
1338 .prcm = {
1339 .omap4 = {
1340 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1341 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1342 },
1343 },
1344 };
1345
1346 /* mailbox13 */
1347 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1348 .name = "mailbox13",
1349 .class = &dra7xx_mailbox_hwmod_class,
1350 .clkdm_name = "l4cfg_clkdm",
1351 .prcm = {
1352 .omap4 = {
1353 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1354 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1355 },
1356 },
1357 };
1358
1359 /*
1360 * 'mcspi' class
1361 *
1362 */
1363
1364 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1365 .rev_offs = 0x0000,
1366 .sysc_offs = 0x0010,
1367 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1368 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1369 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1370 SIDLE_SMART_WKUP),
1371 .sysc_fields = &omap_hwmod_sysc_type2,
1372 };
1373
1374 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1375 .name = "mcspi",
1376 .sysc = &dra7xx_mcspi_sysc,
1377 };
1378
1379 /* mcspi1 */
1380 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1381 .name = "mcspi1",
1382 .class = &dra7xx_mcspi_hwmod_class,
1383 .clkdm_name = "l4per_clkdm",
1384 .main_clk = "func_48m_fclk",
1385 .prcm = {
1386 .omap4 = {
1387 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1388 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1389 .modulemode = MODULEMODE_SWCTRL,
1390 },
1391 },
1392 };
1393
1394 /* mcspi2 */
1395 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1396 .name = "mcspi2",
1397 .class = &dra7xx_mcspi_hwmod_class,
1398 .clkdm_name = "l4per_clkdm",
1399 .main_clk = "func_48m_fclk",
1400 .prcm = {
1401 .omap4 = {
1402 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1403 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1404 .modulemode = MODULEMODE_SWCTRL,
1405 },
1406 },
1407 };
1408
1409 /* mcspi3 */
1410 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1411 .name = "mcspi3",
1412 .class = &dra7xx_mcspi_hwmod_class,
1413 .clkdm_name = "l4per_clkdm",
1414 .main_clk = "func_48m_fclk",
1415 .prcm = {
1416 .omap4 = {
1417 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1418 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1419 .modulemode = MODULEMODE_SWCTRL,
1420 },
1421 },
1422 };
1423
1424 /* mcspi4 */
1425 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1426 .name = "mcspi4",
1427 .class = &dra7xx_mcspi_hwmod_class,
1428 .clkdm_name = "l4per_clkdm",
1429 .main_clk = "func_48m_fclk",
1430 .prcm = {
1431 .omap4 = {
1432 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1433 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1434 .modulemode = MODULEMODE_SWCTRL,
1435 },
1436 },
1437 };
1438
1439 /*
1440 * 'mcasp' class
1441 *
1442 */
1443 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1444 .rev_offs = 0,
1445 .sysc_offs = 0x0004,
1446 .sysc_flags = SYSC_HAS_SIDLEMODE,
1447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1448 .sysc_fields = &omap_hwmod_sysc_type3,
1449 };
1450
1451 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1452 .name = "mcasp",
1453 .sysc = &dra7xx_mcasp_sysc,
1454 };
1455
1456 /* mcasp1 */
1457 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1458 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1459 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1460 };
1461
1462 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1463 .name = "mcasp1",
1464 .class = &dra7xx_mcasp_hwmod_class,
1465 .clkdm_name = "ipu_clkdm",
1466 .main_clk = "mcasp1_aux_gfclk_mux",
1467 .flags = HWMOD_OPT_CLKS_NEEDED,
1468 .prcm = {
1469 .omap4 = {
1470 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1471 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1472 .modulemode = MODULEMODE_SWCTRL,
1473 },
1474 },
1475 .opt_clks = mcasp1_opt_clks,
1476 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1477 };
1478
1479 /* mcasp2 */
1480 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1481 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1482 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1483 };
1484
1485 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1486 .name = "mcasp2",
1487 .class = &dra7xx_mcasp_hwmod_class,
1488 .clkdm_name = "l4per2_clkdm",
1489 .main_clk = "mcasp2_aux_gfclk_mux",
1490 .flags = HWMOD_OPT_CLKS_NEEDED,
1491 .prcm = {
1492 .omap4 = {
1493 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1494 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1495 .modulemode = MODULEMODE_SWCTRL,
1496 },
1497 },
1498 .opt_clks = mcasp2_opt_clks,
1499 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1500 };
1501
1502 /* mcasp3 */
1503 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1504 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1505 };
1506
1507 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1508 .name = "mcasp3",
1509 .class = &dra7xx_mcasp_hwmod_class,
1510 .clkdm_name = "l4per2_clkdm",
1511 .main_clk = "mcasp3_aux_gfclk_mux",
1512 .flags = HWMOD_OPT_CLKS_NEEDED,
1513 .prcm = {
1514 .omap4 = {
1515 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1516 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1517 .modulemode = MODULEMODE_SWCTRL,
1518 },
1519 },
1520 .opt_clks = mcasp3_opt_clks,
1521 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1522 };
1523
1524 /* mcasp4 */
1525 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1526 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1527 };
1528
1529 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1530 .name = "mcasp4",
1531 .class = &dra7xx_mcasp_hwmod_class,
1532 .clkdm_name = "l4per2_clkdm",
1533 .main_clk = "mcasp4_aux_gfclk_mux",
1534 .flags = HWMOD_OPT_CLKS_NEEDED,
1535 .prcm = {
1536 .omap4 = {
1537 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1538 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1539 .modulemode = MODULEMODE_SWCTRL,
1540 },
1541 },
1542 .opt_clks = mcasp4_opt_clks,
1543 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1544 };
1545
1546 /* mcasp5 */
1547 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1548 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1549 };
1550
1551 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1552 .name = "mcasp5",
1553 .class = &dra7xx_mcasp_hwmod_class,
1554 .clkdm_name = "l4per2_clkdm",
1555 .main_clk = "mcasp5_aux_gfclk_mux",
1556 .flags = HWMOD_OPT_CLKS_NEEDED,
1557 .prcm = {
1558 .omap4 = {
1559 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1560 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1561 .modulemode = MODULEMODE_SWCTRL,
1562 },
1563 },
1564 .opt_clks = mcasp5_opt_clks,
1565 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1566 };
1567
1568 /* mcasp6 */
1569 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1570 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1571 };
1572
1573 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1574 .name = "mcasp6",
1575 .class = &dra7xx_mcasp_hwmod_class,
1576 .clkdm_name = "l4per2_clkdm",
1577 .main_clk = "mcasp6_aux_gfclk_mux",
1578 .flags = HWMOD_OPT_CLKS_NEEDED,
1579 .prcm = {
1580 .omap4 = {
1581 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1582 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1583 .modulemode = MODULEMODE_SWCTRL,
1584 },
1585 },
1586 .opt_clks = mcasp6_opt_clks,
1587 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1588 };
1589
1590 /* mcasp7 */
1591 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1592 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1593 };
1594
1595 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1596 .name = "mcasp7",
1597 .class = &dra7xx_mcasp_hwmod_class,
1598 .clkdm_name = "l4per2_clkdm",
1599 .main_clk = "mcasp7_aux_gfclk_mux",
1600 .flags = HWMOD_OPT_CLKS_NEEDED,
1601 .prcm = {
1602 .omap4 = {
1603 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1604 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1605 .modulemode = MODULEMODE_SWCTRL,
1606 },
1607 },
1608 .opt_clks = mcasp7_opt_clks,
1609 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1610 };
1611
1612 /* mcasp8 */
1613 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1614 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1615 };
1616
1617 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1618 .name = "mcasp8",
1619 .class = &dra7xx_mcasp_hwmod_class,
1620 .clkdm_name = "l4per2_clkdm",
1621 .main_clk = "mcasp8_aux_gfclk_mux",
1622 .flags = HWMOD_OPT_CLKS_NEEDED,
1623 .prcm = {
1624 .omap4 = {
1625 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1626 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1627 .modulemode = MODULEMODE_SWCTRL,
1628 },
1629 },
1630 .opt_clks = mcasp8_opt_clks,
1631 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1632 };
1633
1634 /*
1635 * 'mmc' class
1636 *
1637 */
1638
1639 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1640 .rev_offs = 0x0000,
1641 .sysc_offs = 0x0010,
1642 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1643 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1644 SYSC_HAS_SOFTRESET),
1645 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1646 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1647 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1648 .sysc_fields = &omap_hwmod_sysc_type2,
1649 };
1650
1651 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1652 .name = "mmc",
1653 .sysc = &dra7xx_mmc_sysc,
1654 };
1655
1656 /* mmc1 */
1657 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1658 { .role = "clk32k", .clk = "mmc1_clk32k" },
1659 };
1660
1661 /* mmc1 dev_attr */
1662 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1663 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1664 };
1665
1666 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1667 .name = "mmc1",
1668 .class = &dra7xx_mmc_hwmod_class,
1669 .clkdm_name = "l3init_clkdm",
1670 .main_clk = "mmc1_fclk_div",
1671 .prcm = {
1672 .omap4 = {
1673 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1674 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1675 .modulemode = MODULEMODE_SWCTRL,
1676 },
1677 },
1678 .opt_clks = mmc1_opt_clks,
1679 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1680 .dev_attr = &mmc1_dev_attr,
1681 };
1682
1683 /* mmc2 */
1684 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1685 { .role = "clk32k", .clk = "mmc2_clk32k" },
1686 };
1687
1688 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1689 .name = "mmc2",
1690 .class = &dra7xx_mmc_hwmod_class,
1691 .clkdm_name = "l3init_clkdm",
1692 .main_clk = "mmc2_fclk_div",
1693 .prcm = {
1694 .omap4 = {
1695 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1696 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1697 .modulemode = MODULEMODE_SWCTRL,
1698 },
1699 },
1700 .opt_clks = mmc2_opt_clks,
1701 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1702 };
1703
1704 /* mmc3 */
1705 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1706 { .role = "clk32k", .clk = "mmc3_clk32k" },
1707 };
1708
1709 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1710 .name = "mmc3",
1711 .class = &dra7xx_mmc_hwmod_class,
1712 .clkdm_name = "l4per_clkdm",
1713 .main_clk = "mmc3_gfclk_div",
1714 .prcm = {
1715 .omap4 = {
1716 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1717 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1718 .modulemode = MODULEMODE_SWCTRL,
1719 },
1720 },
1721 .opt_clks = mmc3_opt_clks,
1722 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1723 };
1724
1725 /* mmc4 */
1726 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1727 { .role = "clk32k", .clk = "mmc4_clk32k" },
1728 };
1729
1730 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1731 .name = "mmc4",
1732 .class = &dra7xx_mmc_hwmod_class,
1733 .clkdm_name = "l4per_clkdm",
1734 .main_clk = "mmc4_gfclk_div",
1735 .prcm = {
1736 .omap4 = {
1737 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1738 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1739 .modulemode = MODULEMODE_SWCTRL,
1740 },
1741 },
1742 .opt_clks = mmc4_opt_clks,
1743 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1744 };
1745
1746 /*
1747 * 'mpu' class
1748 *
1749 */
1750
1751 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1752 .name = "mpu",
1753 };
1754
1755 /* mpu */
1756 static struct omap_hwmod dra7xx_mpu_hwmod = {
1757 .name = "mpu",
1758 .class = &dra7xx_mpu_hwmod_class,
1759 .clkdm_name = "mpu_clkdm",
1760 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1761 .main_clk = "dpll_mpu_m2_ck",
1762 .prcm = {
1763 .omap4 = {
1764 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1765 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1766 },
1767 },
1768 };
1769
1770 /*
1771 * 'ocp2scp' class
1772 *
1773 */
1774
1775 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1776 .rev_offs = 0x0000,
1777 .sysc_offs = 0x0010,
1778 .syss_offs = 0x0014,
1779 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1780 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1781 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1782 .sysc_fields = &omap_hwmod_sysc_type1,
1783 };
1784
1785 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1786 .name = "ocp2scp",
1787 .sysc = &dra7xx_ocp2scp_sysc,
1788 };
1789
1790 /* ocp2scp1 */
1791 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1792 .name = "ocp2scp1",
1793 .class = &dra7xx_ocp2scp_hwmod_class,
1794 .clkdm_name = "l3init_clkdm",
1795 .main_clk = "l4_root_clk_div",
1796 .prcm = {
1797 .omap4 = {
1798 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1799 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1800 .modulemode = MODULEMODE_HWCTRL,
1801 },
1802 },
1803 };
1804
1805 /* ocp2scp3 */
1806 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1807 .name = "ocp2scp3",
1808 .class = &dra7xx_ocp2scp_hwmod_class,
1809 .clkdm_name = "l3init_clkdm",
1810 .main_clk = "l4_root_clk_div",
1811 .prcm = {
1812 .omap4 = {
1813 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1814 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1815 .modulemode = MODULEMODE_HWCTRL,
1816 },
1817 },
1818 };
1819
1820 /*
1821 * 'PCIE' class
1822 *
1823 */
1824
1825 /*
1826 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1827 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1828 * associated with an IP automatically leaving the driver to handle that
1829 * by itself. This does not work for PCIeSS which needs the reset lines
1830 * deasserted for the driver to start accessing registers.
1831 *
1832 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1833 * lines after asserting them.
1834 */
1835 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1836 {
1837 int i;
1838
1839 for (i = 0; i < oh->rst_lines_cnt; i++) {
1840 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1841 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1842 }
1843
1844 return 0;
1845 }
1846
1847 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1848 .name = "pcie",
1849 .reset = dra7xx_pciess_reset,
1850 };
1851
1852 /* pcie1 */
1853 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1854 { .name = "pcie", .rst_shift = 0 },
1855 };
1856
1857 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1858 .name = "pcie1",
1859 .class = &dra7xx_pciess_hwmod_class,
1860 .clkdm_name = "pcie_clkdm",
1861 .rst_lines = dra7xx_pciess1_resets,
1862 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
1863 .main_clk = "l4_root_clk_div",
1864 .prcm = {
1865 .omap4 = {
1866 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1867 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1868 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1869 .modulemode = MODULEMODE_SWCTRL,
1870 },
1871 },
1872 };
1873
1874 /* pcie2 */
1875 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1876 { .name = "pcie", .rst_shift = 1 },
1877 };
1878
1879 /* pcie2 */
1880 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1881 .name = "pcie2",
1882 .class = &dra7xx_pciess_hwmod_class,
1883 .clkdm_name = "pcie_clkdm",
1884 .rst_lines = dra7xx_pciess2_resets,
1885 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
1886 .main_clk = "l4_root_clk_div",
1887 .prcm = {
1888 .omap4 = {
1889 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1890 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1891 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1892 .modulemode = MODULEMODE_SWCTRL,
1893 },
1894 },
1895 };
1896
1897 /*
1898 * 'qspi' class
1899 *
1900 */
1901
1902 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1903 .rev_offs = 0,
1904 .sysc_offs = 0x0010,
1905 .sysc_flags = SYSC_HAS_SIDLEMODE,
1906 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1907 SIDLE_SMART_WKUP),
1908 .sysc_fields = &omap_hwmod_sysc_type2,
1909 };
1910
1911 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1912 .name = "qspi",
1913 .sysc = &dra7xx_qspi_sysc,
1914 };
1915
1916 /* qspi */
1917 static struct omap_hwmod dra7xx_qspi_hwmod = {
1918 .name = "qspi",
1919 .class = &dra7xx_qspi_hwmod_class,
1920 .clkdm_name = "l4per2_clkdm",
1921 .main_clk = "qspi_gfclk_div",
1922 .prcm = {
1923 .omap4 = {
1924 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1925 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1926 .modulemode = MODULEMODE_SWCTRL,
1927 },
1928 },
1929 };
1930
1931 /*
1932 * 'rtcss' class
1933 *
1934 */
1935 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1936 .rev_offs = 0x0074,
1937 .sysc_offs = 0x0078,
1938 .sysc_flags = SYSC_HAS_SIDLEMODE,
1939 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1940 SIDLE_SMART_WKUP),
1941 .sysc_fields = &omap_hwmod_sysc_type3,
1942 };
1943
1944 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1945 .name = "rtcss",
1946 .sysc = &dra7xx_rtcss_sysc,
1947 .unlock = &omap_hwmod_rtc_unlock,
1948 .lock = &omap_hwmod_rtc_lock,
1949 };
1950
1951 /* rtcss */
1952 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1953 .name = "rtcss",
1954 .class = &dra7xx_rtcss_hwmod_class,
1955 .clkdm_name = "rtc_clkdm",
1956 .main_clk = "sys_32k_ck",
1957 .prcm = {
1958 .omap4 = {
1959 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1960 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1961 .modulemode = MODULEMODE_SWCTRL,
1962 },
1963 },
1964 };
1965
1966 /*
1967 * 'sata' class
1968 *
1969 */
1970
1971 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1972 .rev_offs = 0x00fc,
1973 .sysc_offs = 0x0000,
1974 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1975 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1976 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1977 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1978 .sysc_fields = &omap_hwmod_sysc_type2,
1979 };
1980
1981 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1982 .name = "sata",
1983 .sysc = &dra7xx_sata_sysc,
1984 };
1985
1986 /* sata */
1987
1988 static struct omap_hwmod dra7xx_sata_hwmod = {
1989 .name = "sata",
1990 .class = &dra7xx_sata_hwmod_class,
1991 .clkdm_name = "l3init_clkdm",
1992 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1993 .main_clk = "func_48m_fclk",
1994 .mpu_rt_idx = 1,
1995 .prcm = {
1996 .omap4 = {
1997 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1998 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1999 .modulemode = MODULEMODE_SWCTRL,
2000 },
2001 },
2002 };
2003
2004 /*
2005 * 'smartreflex' class
2006 *
2007 */
2008
2009 /* The IP is not compliant to type1 / type2 scheme */
2010 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2011 .rev_offs = -ENODEV,
2012 .sysc_offs = 0x0038,
2013 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2014 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2015 SIDLE_SMART_WKUP),
2016 .sysc_fields = &omap36xx_sr_sysc_fields,
2017 };
2018
2019 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2020 .name = "smartreflex",
2021 .sysc = &dra7xx_smartreflex_sysc,
2022 .rev = 2,
2023 };
2024
2025 /* smartreflex_core */
2026 /* smartreflex_core dev_attr */
2027 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2028 .sensor_voltdm_name = "core",
2029 };
2030
2031 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2032 .name = "smartreflex_core",
2033 .class = &dra7xx_smartreflex_hwmod_class,
2034 .clkdm_name = "coreaon_clkdm",
2035 .main_clk = "wkupaon_iclk_mux",
2036 .prcm = {
2037 .omap4 = {
2038 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2039 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2040 .modulemode = MODULEMODE_SWCTRL,
2041 },
2042 },
2043 .dev_attr = &smartreflex_core_dev_attr,
2044 };
2045
2046 /* smartreflex_mpu */
2047 /* smartreflex_mpu dev_attr */
2048 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2049 .sensor_voltdm_name = "mpu",
2050 };
2051
2052 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2053 .name = "smartreflex_mpu",
2054 .class = &dra7xx_smartreflex_hwmod_class,
2055 .clkdm_name = "coreaon_clkdm",
2056 .main_clk = "wkupaon_iclk_mux",
2057 .prcm = {
2058 .omap4 = {
2059 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2060 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2061 .modulemode = MODULEMODE_SWCTRL,
2062 },
2063 },
2064 .dev_attr = &smartreflex_mpu_dev_attr,
2065 };
2066
2067 /*
2068 * 'spinlock' class
2069 *
2070 */
2071
2072 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2073 .rev_offs = 0x0000,
2074 .sysc_offs = 0x0010,
2075 .syss_offs = 0x0014,
2076 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2077 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2078 SYSS_HAS_RESET_STATUS),
2079 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2080 .sysc_fields = &omap_hwmod_sysc_type1,
2081 };
2082
2083 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2084 .name = "spinlock",
2085 .sysc = &dra7xx_spinlock_sysc,
2086 };
2087
2088 /* spinlock */
2089 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2090 .name = "spinlock",
2091 .class = &dra7xx_spinlock_hwmod_class,
2092 .clkdm_name = "l4cfg_clkdm",
2093 .main_clk = "l3_iclk_div",
2094 .prcm = {
2095 .omap4 = {
2096 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2097 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2098 },
2099 },
2100 };
2101
2102 /*
2103 * 'timer' class
2104 *
2105 * This class contains several variants: ['timer_1ms', 'timer_secure',
2106 * 'timer']
2107 */
2108
2109 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2110 .rev_offs = 0x0000,
2111 .sysc_offs = 0x0010,
2112 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2113 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2114 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2115 SIDLE_SMART_WKUP),
2116 .sysc_fields = &omap_hwmod_sysc_type2,
2117 };
2118
2119 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2120 .name = "timer",
2121 .sysc = &dra7xx_timer_1ms_sysc,
2122 };
2123
2124 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2125 .rev_offs = 0x0000,
2126 .sysc_offs = 0x0010,
2127 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2128 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2129 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2130 SIDLE_SMART_WKUP),
2131 .sysc_fields = &omap_hwmod_sysc_type2,
2132 };
2133
2134 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2135 .name = "timer",
2136 .sysc = &dra7xx_timer_sysc,
2137 };
2138
2139 /* timer1 */
2140 static struct omap_hwmod dra7xx_timer1_hwmod = {
2141 .name = "timer1",
2142 .class = &dra7xx_timer_1ms_hwmod_class,
2143 .clkdm_name = "wkupaon_clkdm",
2144 .main_clk = "timer1_gfclk_mux",
2145 .prcm = {
2146 .omap4 = {
2147 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2148 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2149 .modulemode = MODULEMODE_SWCTRL,
2150 },
2151 },
2152 };
2153
2154 /* timer2 */
2155 static struct omap_hwmod dra7xx_timer2_hwmod = {
2156 .name = "timer2",
2157 .class = &dra7xx_timer_1ms_hwmod_class,
2158 .clkdm_name = "l4per_clkdm",
2159 .main_clk = "timer2_gfclk_mux",
2160 .prcm = {
2161 .omap4 = {
2162 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2163 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2164 .modulemode = MODULEMODE_SWCTRL,
2165 },
2166 },
2167 };
2168
2169 /* timer3 */
2170 static struct omap_hwmod dra7xx_timer3_hwmod = {
2171 .name = "timer3",
2172 .class = &dra7xx_timer_hwmod_class,
2173 .clkdm_name = "l4per_clkdm",
2174 .main_clk = "timer3_gfclk_mux",
2175 .prcm = {
2176 .omap4 = {
2177 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2178 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2179 .modulemode = MODULEMODE_SWCTRL,
2180 },
2181 },
2182 };
2183
2184 /* timer4 */
2185 static struct omap_hwmod dra7xx_timer4_hwmod = {
2186 .name = "timer4",
2187 .class = &dra7xx_timer_hwmod_class,
2188 .clkdm_name = "l4per_clkdm",
2189 .main_clk = "timer4_gfclk_mux",
2190 .prcm = {
2191 .omap4 = {
2192 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2193 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2194 .modulemode = MODULEMODE_SWCTRL,
2195 },
2196 },
2197 };
2198
2199 /* timer5 */
2200 static struct omap_hwmod dra7xx_timer5_hwmod = {
2201 .name = "timer5",
2202 .class = &dra7xx_timer_hwmod_class,
2203 .clkdm_name = "ipu_clkdm",
2204 .main_clk = "timer5_gfclk_mux",
2205 .prcm = {
2206 .omap4 = {
2207 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2208 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2209 .modulemode = MODULEMODE_SWCTRL,
2210 },
2211 },
2212 };
2213
2214 /* timer6 */
2215 static struct omap_hwmod dra7xx_timer6_hwmod = {
2216 .name = "timer6",
2217 .class = &dra7xx_timer_hwmod_class,
2218 .clkdm_name = "ipu_clkdm",
2219 .main_clk = "timer6_gfclk_mux",
2220 .prcm = {
2221 .omap4 = {
2222 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2223 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2224 .modulemode = MODULEMODE_SWCTRL,
2225 },
2226 },
2227 };
2228
2229 /* timer7 */
2230 static struct omap_hwmod dra7xx_timer7_hwmod = {
2231 .name = "timer7",
2232 .class = &dra7xx_timer_hwmod_class,
2233 .clkdm_name = "ipu_clkdm",
2234 .main_clk = "timer7_gfclk_mux",
2235 .prcm = {
2236 .omap4 = {
2237 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2238 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2239 .modulemode = MODULEMODE_SWCTRL,
2240 },
2241 },
2242 };
2243
2244 /* timer8 */
2245 static struct omap_hwmod dra7xx_timer8_hwmod = {
2246 .name = "timer8",
2247 .class = &dra7xx_timer_hwmod_class,
2248 .clkdm_name = "ipu_clkdm",
2249 .main_clk = "timer8_gfclk_mux",
2250 .prcm = {
2251 .omap4 = {
2252 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2253 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2254 .modulemode = MODULEMODE_SWCTRL,
2255 },
2256 },
2257 };
2258
2259 /* timer9 */
2260 static struct omap_hwmod dra7xx_timer9_hwmod = {
2261 .name = "timer9",
2262 .class = &dra7xx_timer_hwmod_class,
2263 .clkdm_name = "l4per_clkdm",
2264 .main_clk = "timer9_gfclk_mux",
2265 .prcm = {
2266 .omap4 = {
2267 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2268 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2269 .modulemode = MODULEMODE_SWCTRL,
2270 },
2271 },
2272 };
2273
2274 /* timer10 */
2275 static struct omap_hwmod dra7xx_timer10_hwmod = {
2276 .name = "timer10",
2277 .class = &dra7xx_timer_1ms_hwmod_class,
2278 .clkdm_name = "l4per_clkdm",
2279 .main_clk = "timer10_gfclk_mux",
2280 .prcm = {
2281 .omap4 = {
2282 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2283 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2284 .modulemode = MODULEMODE_SWCTRL,
2285 },
2286 },
2287 };
2288
2289 /* timer11 */
2290 static struct omap_hwmod dra7xx_timer11_hwmod = {
2291 .name = "timer11",
2292 .class = &dra7xx_timer_hwmod_class,
2293 .clkdm_name = "l4per_clkdm",
2294 .main_clk = "timer11_gfclk_mux",
2295 .prcm = {
2296 .omap4 = {
2297 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2298 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2299 .modulemode = MODULEMODE_SWCTRL,
2300 },
2301 },
2302 };
2303
2304 /* timer12 */
2305 static struct omap_hwmod dra7xx_timer12_hwmod = {
2306 .name = "timer12",
2307 .class = &dra7xx_timer_hwmod_class,
2308 .clkdm_name = "wkupaon_clkdm",
2309 .main_clk = "secure_32k_clk_src_ck",
2310 .prcm = {
2311 .omap4 = {
2312 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2313 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2314 },
2315 },
2316 };
2317
2318 /* timer13 */
2319 static struct omap_hwmod dra7xx_timer13_hwmod = {
2320 .name = "timer13",
2321 .class = &dra7xx_timer_hwmod_class,
2322 .clkdm_name = "l4per3_clkdm",
2323 .main_clk = "timer13_gfclk_mux",
2324 .prcm = {
2325 .omap4 = {
2326 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2327 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2328 .modulemode = MODULEMODE_SWCTRL,
2329 },
2330 },
2331 };
2332
2333 /* timer14 */
2334 static struct omap_hwmod dra7xx_timer14_hwmod = {
2335 .name = "timer14",
2336 .class = &dra7xx_timer_hwmod_class,
2337 .clkdm_name = "l4per3_clkdm",
2338 .main_clk = "timer14_gfclk_mux",
2339 .prcm = {
2340 .omap4 = {
2341 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2342 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2343 .modulemode = MODULEMODE_SWCTRL,
2344 },
2345 },
2346 };
2347
2348 /* timer15 */
2349 static struct omap_hwmod dra7xx_timer15_hwmod = {
2350 .name = "timer15",
2351 .class = &dra7xx_timer_hwmod_class,
2352 .clkdm_name = "l4per3_clkdm",
2353 .main_clk = "timer15_gfclk_mux",
2354 .prcm = {
2355 .omap4 = {
2356 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2357 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2358 .modulemode = MODULEMODE_SWCTRL,
2359 },
2360 },
2361 };
2362
2363 /* timer16 */
2364 static struct omap_hwmod dra7xx_timer16_hwmod = {
2365 .name = "timer16",
2366 .class = &dra7xx_timer_hwmod_class,
2367 .clkdm_name = "l4per3_clkdm",
2368 .main_clk = "timer16_gfclk_mux",
2369 .prcm = {
2370 .omap4 = {
2371 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2372 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2373 .modulemode = MODULEMODE_SWCTRL,
2374 },
2375 },
2376 };
2377
2378 /*
2379 * 'uart' class
2380 *
2381 */
2382
2383 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2384 .rev_offs = 0x0050,
2385 .sysc_offs = 0x0054,
2386 .syss_offs = 0x0058,
2387 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2388 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2389 SYSS_HAS_RESET_STATUS),
2390 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2391 SIDLE_SMART_WKUP),
2392 .sysc_fields = &omap_hwmod_sysc_type1,
2393 };
2394
2395 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2396 .name = "uart",
2397 .sysc = &dra7xx_uart_sysc,
2398 };
2399
2400 /* uart1 */
2401 static struct omap_hwmod dra7xx_uart1_hwmod = {
2402 .name = "uart1",
2403 .class = &dra7xx_uart_hwmod_class,
2404 .clkdm_name = "l4per_clkdm",
2405 .main_clk = "uart1_gfclk_mux",
2406 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2407 .prcm = {
2408 .omap4 = {
2409 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2410 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2411 .modulemode = MODULEMODE_SWCTRL,
2412 },
2413 },
2414 };
2415
2416 /* uart2 */
2417 static struct omap_hwmod dra7xx_uart2_hwmod = {
2418 .name = "uart2",
2419 .class = &dra7xx_uart_hwmod_class,
2420 .clkdm_name = "l4per_clkdm",
2421 .main_clk = "uart2_gfclk_mux",
2422 .flags = HWMOD_SWSUP_SIDLE_ACT,
2423 .prcm = {
2424 .omap4 = {
2425 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2426 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2427 .modulemode = MODULEMODE_SWCTRL,
2428 },
2429 },
2430 };
2431
2432 /* uart3 */
2433 static struct omap_hwmod dra7xx_uart3_hwmod = {
2434 .name = "uart3",
2435 .class = &dra7xx_uart_hwmod_class,
2436 .clkdm_name = "l4per_clkdm",
2437 .main_clk = "uart3_gfclk_mux",
2438 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2439 .prcm = {
2440 .omap4 = {
2441 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2442 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2443 .modulemode = MODULEMODE_SWCTRL,
2444 },
2445 },
2446 };
2447
2448 /* uart4 */
2449 static struct omap_hwmod dra7xx_uart4_hwmod = {
2450 .name = "uart4",
2451 .class = &dra7xx_uart_hwmod_class,
2452 .clkdm_name = "l4per_clkdm",
2453 .main_clk = "uart4_gfclk_mux",
2454 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2455 .prcm = {
2456 .omap4 = {
2457 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2458 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2459 .modulemode = MODULEMODE_SWCTRL,
2460 },
2461 },
2462 };
2463
2464 /* uart5 */
2465 static struct omap_hwmod dra7xx_uart5_hwmod = {
2466 .name = "uart5",
2467 .class = &dra7xx_uart_hwmod_class,
2468 .clkdm_name = "l4per_clkdm",
2469 .main_clk = "uart5_gfclk_mux",
2470 .flags = HWMOD_SWSUP_SIDLE_ACT,
2471 .prcm = {
2472 .omap4 = {
2473 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2474 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2475 .modulemode = MODULEMODE_SWCTRL,
2476 },
2477 },
2478 };
2479
2480 /* uart6 */
2481 static struct omap_hwmod dra7xx_uart6_hwmod = {
2482 .name = "uart6",
2483 .class = &dra7xx_uart_hwmod_class,
2484 .clkdm_name = "ipu_clkdm",
2485 .main_clk = "uart6_gfclk_mux",
2486 .flags = HWMOD_SWSUP_SIDLE_ACT,
2487 .prcm = {
2488 .omap4 = {
2489 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2490 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2491 .modulemode = MODULEMODE_SWCTRL,
2492 },
2493 },
2494 };
2495
2496 /* uart7 */
2497 static struct omap_hwmod dra7xx_uart7_hwmod = {
2498 .name = "uart7",
2499 .class = &dra7xx_uart_hwmod_class,
2500 .clkdm_name = "l4per2_clkdm",
2501 .main_clk = "uart7_gfclk_mux",
2502 .flags = HWMOD_SWSUP_SIDLE_ACT,
2503 .prcm = {
2504 .omap4 = {
2505 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2506 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2507 .modulemode = MODULEMODE_SWCTRL,
2508 },
2509 },
2510 };
2511
2512 /* uart8 */
2513 static struct omap_hwmod dra7xx_uart8_hwmod = {
2514 .name = "uart8",
2515 .class = &dra7xx_uart_hwmod_class,
2516 .clkdm_name = "l4per2_clkdm",
2517 .main_clk = "uart8_gfclk_mux",
2518 .flags = HWMOD_SWSUP_SIDLE_ACT,
2519 .prcm = {
2520 .omap4 = {
2521 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2522 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2523 .modulemode = MODULEMODE_SWCTRL,
2524 },
2525 },
2526 };
2527
2528 /* uart9 */
2529 static struct omap_hwmod dra7xx_uart9_hwmod = {
2530 .name = "uart9",
2531 .class = &dra7xx_uart_hwmod_class,
2532 .clkdm_name = "l4per2_clkdm",
2533 .main_clk = "uart9_gfclk_mux",
2534 .flags = HWMOD_SWSUP_SIDLE_ACT,
2535 .prcm = {
2536 .omap4 = {
2537 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2538 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2539 .modulemode = MODULEMODE_SWCTRL,
2540 },
2541 },
2542 };
2543
2544 /* uart10 */
2545 static struct omap_hwmod dra7xx_uart10_hwmod = {
2546 .name = "uart10",
2547 .class = &dra7xx_uart_hwmod_class,
2548 .clkdm_name = "wkupaon_clkdm",
2549 .main_clk = "uart10_gfclk_mux",
2550 .flags = HWMOD_SWSUP_SIDLE_ACT,
2551 .prcm = {
2552 .omap4 = {
2553 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2554 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2555 .modulemode = MODULEMODE_SWCTRL,
2556 },
2557 },
2558 };
2559
2560 /* DES (the 'P' (public) device) */
2561 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2562 .rev_offs = 0x0030,
2563 .sysc_offs = 0x0034,
2564 .syss_offs = 0x0038,
2565 .sysc_flags = SYSS_HAS_RESET_STATUS,
2566 };
2567
2568 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2569 .name = "des",
2570 .sysc = &dra7xx_des_sysc,
2571 };
2572
2573 /* DES */
2574 static struct omap_hwmod dra7xx_des_hwmod = {
2575 .name = "des",
2576 .class = &dra7xx_des_hwmod_class,
2577 .clkdm_name = "l4sec_clkdm",
2578 .main_clk = "l3_iclk_div",
2579 .prcm = {
2580 .omap4 = {
2581 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2582 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2583 .modulemode = MODULEMODE_HWCTRL,
2584 },
2585 },
2586 };
2587
2588 /* rng */
2589 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2590 .rev_offs = 0x1fe0,
2591 .sysc_offs = 0x1fe4,
2592 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2593 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2594 .sysc_fields = &omap_hwmod_sysc_type1,
2595 };
2596
2597 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2598 .name = "rng",
2599 .sysc = &dra7xx_rng_sysc,
2600 };
2601
2602 static struct omap_hwmod dra7xx_rng_hwmod = {
2603 .name = "rng",
2604 .class = &dra7xx_rng_hwmod_class,
2605 .flags = HWMOD_SWSUP_SIDLE,
2606 .clkdm_name = "l4sec_clkdm",
2607 .prcm = {
2608 .omap4 = {
2609 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2610 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2611 .modulemode = MODULEMODE_HWCTRL,
2612 },
2613 },
2614 };
2615
2616 /*
2617 * 'usb_otg_ss' class
2618 *
2619 */
2620
2621 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2622 .rev_offs = 0x0000,
2623 .sysc_offs = 0x0010,
2624 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2625 SYSC_HAS_SIDLEMODE),
2626 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2627 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2628 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2629 .sysc_fields = &omap_hwmod_sysc_type2,
2630 };
2631
2632 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2633 .name = "usb_otg_ss",
2634 .sysc = &dra7xx_usb_otg_ss_sysc,
2635 };
2636
2637 /* usb_otg_ss1 */
2638 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2639 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2640 };
2641
2642 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2643 .name = "usb_otg_ss1",
2644 .class = &dra7xx_usb_otg_ss_hwmod_class,
2645 .clkdm_name = "l3init_clkdm",
2646 .main_clk = "dpll_core_h13x2_ck",
2647 .flags = HWMOD_CLKDM_NOAUTO,
2648 .prcm = {
2649 .omap4 = {
2650 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2651 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2652 .modulemode = MODULEMODE_HWCTRL,
2653 },
2654 },
2655 .opt_clks = usb_otg_ss1_opt_clks,
2656 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2657 };
2658
2659 /* usb_otg_ss2 */
2660 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2661 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2662 };
2663
2664 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2665 .name = "usb_otg_ss2",
2666 .class = &dra7xx_usb_otg_ss_hwmod_class,
2667 .clkdm_name = "l3init_clkdm",
2668 .main_clk = "dpll_core_h13x2_ck",
2669 .flags = HWMOD_CLKDM_NOAUTO,
2670 .prcm = {
2671 .omap4 = {
2672 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2673 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2674 .modulemode = MODULEMODE_HWCTRL,
2675 },
2676 },
2677 .opt_clks = usb_otg_ss2_opt_clks,
2678 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2679 };
2680
2681 /* usb_otg_ss3 */
2682 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2683 .name = "usb_otg_ss3",
2684 .class = &dra7xx_usb_otg_ss_hwmod_class,
2685 .clkdm_name = "l3init_clkdm",
2686 .main_clk = "dpll_core_h13x2_ck",
2687 .prcm = {
2688 .omap4 = {
2689 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2690 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2691 .modulemode = MODULEMODE_HWCTRL,
2692 },
2693 },
2694 };
2695
2696 /* usb_otg_ss4 */
2697 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2698 .name = "usb_otg_ss4",
2699 .class = &dra7xx_usb_otg_ss_hwmod_class,
2700 .clkdm_name = "l3init_clkdm",
2701 .main_clk = "dpll_core_h13x2_ck",
2702 .prcm = {
2703 .omap4 = {
2704 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2705 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2706 .modulemode = MODULEMODE_HWCTRL,
2707 },
2708 },
2709 };
2710
2711 /*
2712 * 'vcp' class
2713 *
2714 */
2715
2716 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2717 .name = "vcp",
2718 };
2719
2720 /* vcp1 */
2721 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2722 .name = "vcp1",
2723 .class = &dra7xx_vcp_hwmod_class,
2724 .clkdm_name = "l3main1_clkdm",
2725 .main_clk = "l3_iclk_div",
2726 .prcm = {
2727 .omap4 = {
2728 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2729 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2730 },
2731 },
2732 };
2733
2734 /* vcp2 */
2735 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2736 .name = "vcp2",
2737 .class = &dra7xx_vcp_hwmod_class,
2738 .clkdm_name = "l3main1_clkdm",
2739 .main_clk = "l3_iclk_div",
2740 .prcm = {
2741 .omap4 = {
2742 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2743 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2744 },
2745 },
2746 };
2747
2748 /*
2749 * 'wd_timer' class
2750 *
2751 */
2752
2753 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2754 .rev_offs = 0x0000,
2755 .sysc_offs = 0x0010,
2756 .syss_offs = 0x0014,
2757 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2758 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2759 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2760 SIDLE_SMART_WKUP),
2761 .sysc_fields = &omap_hwmod_sysc_type1,
2762 };
2763
2764 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2765 .name = "wd_timer",
2766 .sysc = &dra7xx_wd_timer_sysc,
2767 .pre_shutdown = &omap2_wd_timer_disable,
2768 .reset = &omap2_wd_timer_reset,
2769 };
2770
2771 /* wd_timer2 */
2772 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2773 .name = "wd_timer2",
2774 .class = &dra7xx_wd_timer_hwmod_class,
2775 .clkdm_name = "wkupaon_clkdm",
2776 .main_clk = "sys_32k_ck",
2777 .prcm = {
2778 .omap4 = {
2779 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2780 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2781 .modulemode = MODULEMODE_SWCTRL,
2782 },
2783 },
2784 };
2785
2786
2787 /*
2788 * Interfaces
2789 */
2790
2791 /* l3_main_1 -> dmm */
2792 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2793 .master = &dra7xx_l3_main_1_hwmod,
2794 .slave = &dra7xx_dmm_hwmod,
2795 .clk = "l3_iclk_div",
2796 .user = OCP_USER_SDMA,
2797 };
2798
2799 /* l3_main_2 -> l3_instr */
2800 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2801 .master = &dra7xx_l3_main_2_hwmod,
2802 .slave = &dra7xx_l3_instr_hwmod,
2803 .clk = "l3_iclk_div",
2804 .user = OCP_USER_MPU | OCP_USER_SDMA,
2805 };
2806
2807 /* l4_cfg -> l3_main_1 */
2808 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2809 .master = &dra7xx_l4_cfg_hwmod,
2810 .slave = &dra7xx_l3_main_1_hwmod,
2811 .clk = "l3_iclk_div",
2812 .user = OCP_USER_MPU | OCP_USER_SDMA,
2813 };
2814
2815 /* mpu -> l3_main_1 */
2816 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2817 .master = &dra7xx_mpu_hwmod,
2818 .slave = &dra7xx_l3_main_1_hwmod,
2819 .clk = "l3_iclk_div",
2820 .user = OCP_USER_MPU,
2821 };
2822
2823 /* l3_main_1 -> l3_main_2 */
2824 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2825 .master = &dra7xx_l3_main_1_hwmod,
2826 .slave = &dra7xx_l3_main_2_hwmod,
2827 .clk = "l3_iclk_div",
2828 .user = OCP_USER_MPU,
2829 };
2830
2831 /* l4_cfg -> l3_main_2 */
2832 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2833 .master = &dra7xx_l4_cfg_hwmod,
2834 .slave = &dra7xx_l3_main_2_hwmod,
2835 .clk = "l3_iclk_div",
2836 .user = OCP_USER_MPU | OCP_USER_SDMA,
2837 };
2838
2839 /* l3_main_1 -> l4_cfg */
2840 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2841 .master = &dra7xx_l3_main_1_hwmod,
2842 .slave = &dra7xx_l4_cfg_hwmod,
2843 .clk = "l3_iclk_div",
2844 .user = OCP_USER_MPU | OCP_USER_SDMA,
2845 };
2846
2847 /* l3_main_1 -> l4_per1 */
2848 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2849 .master = &dra7xx_l3_main_1_hwmod,
2850 .slave = &dra7xx_l4_per1_hwmod,
2851 .clk = "l3_iclk_div",
2852 .user = OCP_USER_MPU | OCP_USER_SDMA,
2853 };
2854
2855 /* l3_main_1 -> l4_per2 */
2856 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2857 .master = &dra7xx_l3_main_1_hwmod,
2858 .slave = &dra7xx_l4_per2_hwmod,
2859 .clk = "l3_iclk_div",
2860 .user = OCP_USER_MPU | OCP_USER_SDMA,
2861 };
2862
2863 /* l3_main_1 -> l4_per3 */
2864 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2865 .master = &dra7xx_l3_main_1_hwmod,
2866 .slave = &dra7xx_l4_per3_hwmod,
2867 .clk = "l3_iclk_div",
2868 .user = OCP_USER_MPU | OCP_USER_SDMA,
2869 };
2870
2871 /* l3_main_1 -> l4_wkup */
2872 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2873 .master = &dra7xx_l3_main_1_hwmod,
2874 .slave = &dra7xx_l4_wkup_hwmod,
2875 .clk = "wkupaon_iclk_mux",
2876 .user = OCP_USER_MPU | OCP_USER_SDMA,
2877 };
2878
2879 /* l4_per2 -> atl */
2880 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2881 .master = &dra7xx_l4_per2_hwmod,
2882 .slave = &dra7xx_atl_hwmod,
2883 .clk = "l3_iclk_div",
2884 .user = OCP_USER_MPU | OCP_USER_SDMA,
2885 };
2886
2887 /* l3_main_1 -> bb2d */
2888 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2889 .master = &dra7xx_l3_main_1_hwmod,
2890 .slave = &dra7xx_bb2d_hwmod,
2891 .clk = "l3_iclk_div",
2892 .user = OCP_USER_MPU | OCP_USER_SDMA,
2893 };
2894
2895 /* l4_wkup -> counter_32k */
2896 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2897 .master = &dra7xx_l4_wkup_hwmod,
2898 .slave = &dra7xx_counter_32k_hwmod,
2899 .clk = "wkupaon_iclk_mux",
2900 .user = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2902
2903 /* l4_wkup -> ctrl_module_wkup */
2904 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2905 .master = &dra7xx_l4_wkup_hwmod,
2906 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2907 .clk = "wkupaon_iclk_mux",
2908 .user = OCP_USER_MPU | OCP_USER_SDMA,
2909 };
2910
2911 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2912 .master = &dra7xx_l4_per2_hwmod,
2913 .slave = &dra7xx_gmac_hwmod,
2914 .clk = "dpll_gmac_ck",
2915 .user = OCP_USER_MPU,
2916 };
2917
2918 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2919 .master = &dra7xx_gmac_hwmod,
2920 .slave = &dra7xx_mdio_hwmod,
2921 .user = OCP_USER_MPU,
2922 };
2923
2924 /* l4_wkup -> dcan1 */
2925 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2926 .master = &dra7xx_l4_wkup_hwmod,
2927 .slave = &dra7xx_dcan1_hwmod,
2928 .clk = "wkupaon_iclk_mux",
2929 .user = OCP_USER_MPU | OCP_USER_SDMA,
2930 };
2931
2932 /* l4_per2 -> dcan2 */
2933 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2934 .master = &dra7xx_l4_per2_hwmod,
2935 .slave = &dra7xx_dcan2_hwmod,
2936 .clk = "l3_iclk_div",
2937 .user = OCP_USER_MPU | OCP_USER_SDMA,
2938 };
2939
2940 /* l4_cfg -> dma_system */
2941 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2942 .master = &dra7xx_l4_cfg_hwmod,
2943 .slave = &dra7xx_dma_system_hwmod,
2944 .clk = "l3_iclk_div",
2945 .user = OCP_USER_MPU | OCP_USER_SDMA,
2946 };
2947
2948 /* l3_main_1 -> tpcc */
2949 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2950 .master = &dra7xx_l3_main_1_hwmod,
2951 .slave = &dra7xx_tpcc_hwmod,
2952 .clk = "l3_iclk_div",
2953 .user = OCP_USER_MPU,
2954 };
2955
2956 /* l3_main_1 -> tptc0 */
2957 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2958 .master = &dra7xx_l3_main_1_hwmod,
2959 .slave = &dra7xx_tptc0_hwmod,
2960 .clk = "l3_iclk_div",
2961 .user = OCP_USER_MPU,
2962 };
2963
2964 /* l3_main_1 -> tptc1 */
2965 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2966 .master = &dra7xx_l3_main_1_hwmod,
2967 .slave = &dra7xx_tptc1_hwmod,
2968 .clk = "l3_iclk_div",
2969 .user = OCP_USER_MPU,
2970 };
2971
2972 /* l3_main_1 -> dss */
2973 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2974 .master = &dra7xx_l3_main_1_hwmod,
2975 .slave = &dra7xx_dss_hwmod,
2976 .clk = "l3_iclk_div",
2977 .user = OCP_USER_MPU | OCP_USER_SDMA,
2978 };
2979
2980 /* l3_main_1 -> dispc */
2981 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2982 .master = &dra7xx_l3_main_1_hwmod,
2983 .slave = &dra7xx_dss_dispc_hwmod,
2984 .clk = "l3_iclk_div",
2985 .user = OCP_USER_MPU | OCP_USER_SDMA,
2986 };
2987
2988 /* l3_main_1 -> dispc */
2989 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2990 .master = &dra7xx_l3_main_1_hwmod,
2991 .slave = &dra7xx_dss_hdmi_hwmod,
2992 .clk = "l3_iclk_div",
2993 .user = OCP_USER_MPU | OCP_USER_SDMA,
2994 };
2995
2996 /* l3_main_1 -> aes1 */
2997 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
2998 .master = &dra7xx_l3_main_1_hwmod,
2999 .slave = &dra7xx_aes1_hwmod,
3000 .clk = "l3_iclk_div",
3001 .user = OCP_USER_MPU | OCP_USER_SDMA,
3002 };
3003
3004 /* l3_main_1 -> aes2 */
3005 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3006 .master = &dra7xx_l3_main_1_hwmod,
3007 .slave = &dra7xx_aes2_hwmod,
3008 .clk = "l3_iclk_div",
3009 .user = OCP_USER_MPU | OCP_USER_SDMA,
3010 };
3011
3012 /* l3_main_1 -> sha0 */
3013 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3014 .master = &dra7xx_l3_main_1_hwmod,
3015 .slave = &dra7xx_sha0_hwmod,
3016 .clk = "l3_iclk_div",
3017 .user = OCP_USER_MPU | OCP_USER_SDMA,
3018 };
3019
3020 /* l4_per2 -> mcasp1 */
3021 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3022 .master = &dra7xx_l4_per2_hwmod,
3023 .slave = &dra7xx_mcasp1_hwmod,
3024 .clk = "l4_root_clk_div",
3025 .user = OCP_USER_MPU | OCP_USER_SDMA,
3026 };
3027
3028 /* l3_main_1 -> mcasp1 */
3029 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3030 .master = &dra7xx_l3_main_1_hwmod,
3031 .slave = &dra7xx_mcasp1_hwmod,
3032 .clk = "l3_iclk_div",
3033 .user = OCP_USER_MPU | OCP_USER_SDMA,
3034 };
3035
3036 /* l4_per2 -> mcasp2 */
3037 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3038 .master = &dra7xx_l4_per2_hwmod,
3039 .slave = &dra7xx_mcasp2_hwmod,
3040 .clk = "l4_root_clk_div",
3041 .user = OCP_USER_MPU | OCP_USER_SDMA,
3042 };
3043
3044 /* l3_main_1 -> mcasp2 */
3045 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3046 .master = &dra7xx_l3_main_1_hwmod,
3047 .slave = &dra7xx_mcasp2_hwmod,
3048 .clk = "l3_iclk_div",
3049 .user = OCP_USER_MPU | OCP_USER_SDMA,
3050 };
3051
3052 /* l4_per2 -> mcasp3 */
3053 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3054 .master = &dra7xx_l4_per2_hwmod,
3055 .slave = &dra7xx_mcasp3_hwmod,
3056 .clk = "l4_root_clk_div",
3057 .user = OCP_USER_MPU | OCP_USER_SDMA,
3058 };
3059
3060 /* l3_main_1 -> mcasp3 */
3061 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3062 .master = &dra7xx_l3_main_1_hwmod,
3063 .slave = &dra7xx_mcasp3_hwmod,
3064 .clk = "l3_iclk_div",
3065 .user = OCP_USER_MPU | OCP_USER_SDMA,
3066 };
3067
3068 /* l4_per2 -> mcasp4 */
3069 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3070 .master = &dra7xx_l4_per2_hwmod,
3071 .slave = &dra7xx_mcasp4_hwmod,
3072 .clk = "l4_root_clk_div",
3073 .user = OCP_USER_MPU | OCP_USER_SDMA,
3074 };
3075
3076 /* l4_per2 -> mcasp5 */
3077 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3078 .master = &dra7xx_l4_per2_hwmod,
3079 .slave = &dra7xx_mcasp5_hwmod,
3080 .clk = "l4_root_clk_div",
3081 .user = OCP_USER_MPU | OCP_USER_SDMA,
3082 };
3083
3084 /* l4_per2 -> mcasp6 */
3085 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3086 .master = &dra7xx_l4_per2_hwmod,
3087 .slave = &dra7xx_mcasp6_hwmod,
3088 .clk = "l4_root_clk_div",
3089 .user = OCP_USER_MPU | OCP_USER_SDMA,
3090 };
3091
3092 /* l4_per2 -> mcasp7 */
3093 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3094 .master = &dra7xx_l4_per2_hwmod,
3095 .slave = &dra7xx_mcasp7_hwmod,
3096 .clk = "l4_root_clk_div",
3097 .user = OCP_USER_MPU | OCP_USER_SDMA,
3098 };
3099
3100 /* l4_per2 -> mcasp8 */
3101 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3102 .master = &dra7xx_l4_per2_hwmod,
3103 .slave = &dra7xx_mcasp8_hwmod,
3104 .clk = "l4_root_clk_div",
3105 .user = OCP_USER_MPU | OCP_USER_SDMA,
3106 };
3107
3108 /* l4_per1 -> elm */
3109 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3110 .master = &dra7xx_l4_per1_hwmod,
3111 .slave = &dra7xx_elm_hwmod,
3112 .clk = "l3_iclk_div",
3113 .user = OCP_USER_MPU | OCP_USER_SDMA,
3114 };
3115
3116 /* l4_wkup -> gpio1 */
3117 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3118 .master = &dra7xx_l4_wkup_hwmod,
3119 .slave = &dra7xx_gpio1_hwmod,
3120 .clk = "wkupaon_iclk_mux",
3121 .user = OCP_USER_MPU | OCP_USER_SDMA,
3122 };
3123
3124 /* l4_per1 -> gpio2 */
3125 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3126 .master = &dra7xx_l4_per1_hwmod,
3127 .slave = &dra7xx_gpio2_hwmod,
3128 .clk = "l3_iclk_div",
3129 .user = OCP_USER_MPU | OCP_USER_SDMA,
3130 };
3131
3132 /* l4_per1 -> gpio3 */
3133 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3134 .master = &dra7xx_l4_per1_hwmod,
3135 .slave = &dra7xx_gpio3_hwmod,
3136 .clk = "l3_iclk_div",
3137 .user = OCP_USER_MPU | OCP_USER_SDMA,
3138 };
3139
3140 /* l4_per1 -> gpio4 */
3141 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3142 .master = &dra7xx_l4_per1_hwmod,
3143 .slave = &dra7xx_gpio4_hwmod,
3144 .clk = "l3_iclk_div",
3145 .user = OCP_USER_MPU | OCP_USER_SDMA,
3146 };
3147
3148 /* l4_per1 -> gpio5 */
3149 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3150 .master = &dra7xx_l4_per1_hwmod,
3151 .slave = &dra7xx_gpio5_hwmod,
3152 .clk = "l3_iclk_div",
3153 .user = OCP_USER_MPU | OCP_USER_SDMA,
3154 };
3155
3156 /* l4_per1 -> gpio6 */
3157 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3158 .master = &dra7xx_l4_per1_hwmod,
3159 .slave = &dra7xx_gpio6_hwmod,
3160 .clk = "l3_iclk_div",
3161 .user = OCP_USER_MPU | OCP_USER_SDMA,
3162 };
3163
3164 /* l4_per1 -> gpio7 */
3165 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3166 .master = &dra7xx_l4_per1_hwmod,
3167 .slave = &dra7xx_gpio7_hwmod,
3168 .clk = "l3_iclk_div",
3169 .user = OCP_USER_MPU | OCP_USER_SDMA,
3170 };
3171
3172 /* l4_per1 -> gpio8 */
3173 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3174 .master = &dra7xx_l4_per1_hwmod,
3175 .slave = &dra7xx_gpio8_hwmod,
3176 .clk = "l3_iclk_div",
3177 .user = OCP_USER_MPU | OCP_USER_SDMA,
3178 };
3179
3180 /* l3_main_1 -> gpmc */
3181 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3182 .master = &dra7xx_l3_main_1_hwmod,
3183 .slave = &dra7xx_gpmc_hwmod,
3184 .clk = "l3_iclk_div",
3185 .user = OCP_USER_MPU | OCP_USER_SDMA,
3186 };
3187
3188 /* l4_per1 -> hdq1w */
3189 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3190 .master = &dra7xx_l4_per1_hwmod,
3191 .slave = &dra7xx_hdq1w_hwmod,
3192 .clk = "l3_iclk_div",
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3194 };
3195
3196 /* l4_per1 -> i2c1 */
3197 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3198 .master = &dra7xx_l4_per1_hwmod,
3199 .slave = &dra7xx_i2c1_hwmod,
3200 .clk = "l3_iclk_div",
3201 .user = OCP_USER_MPU | OCP_USER_SDMA,
3202 };
3203
3204 /* l4_per1 -> i2c2 */
3205 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3206 .master = &dra7xx_l4_per1_hwmod,
3207 .slave = &dra7xx_i2c2_hwmod,
3208 .clk = "l3_iclk_div",
3209 .user = OCP_USER_MPU | OCP_USER_SDMA,
3210 };
3211
3212 /* l4_per1 -> i2c3 */
3213 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3214 .master = &dra7xx_l4_per1_hwmod,
3215 .slave = &dra7xx_i2c3_hwmod,
3216 .clk = "l3_iclk_div",
3217 .user = OCP_USER_MPU | OCP_USER_SDMA,
3218 };
3219
3220 /* l4_per1 -> i2c4 */
3221 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3222 .master = &dra7xx_l4_per1_hwmod,
3223 .slave = &dra7xx_i2c4_hwmod,
3224 .clk = "l3_iclk_div",
3225 .user = OCP_USER_MPU | OCP_USER_SDMA,
3226 };
3227
3228 /* l4_per1 -> i2c5 */
3229 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3230 .master = &dra7xx_l4_per1_hwmod,
3231 .slave = &dra7xx_i2c5_hwmod,
3232 .clk = "l3_iclk_div",
3233 .user = OCP_USER_MPU | OCP_USER_SDMA,
3234 };
3235
3236 /* l4_cfg -> mailbox1 */
3237 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3238 .master = &dra7xx_l4_cfg_hwmod,
3239 .slave = &dra7xx_mailbox1_hwmod,
3240 .clk = "l3_iclk_div",
3241 .user = OCP_USER_MPU | OCP_USER_SDMA,
3242 };
3243
3244 /* l4_per3 -> mailbox2 */
3245 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3246 .master = &dra7xx_l4_per3_hwmod,
3247 .slave = &dra7xx_mailbox2_hwmod,
3248 .clk = "l3_iclk_div",
3249 .user = OCP_USER_MPU | OCP_USER_SDMA,
3250 };
3251
3252 /* l4_per3 -> mailbox3 */
3253 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3254 .master = &dra7xx_l4_per3_hwmod,
3255 .slave = &dra7xx_mailbox3_hwmod,
3256 .clk = "l3_iclk_div",
3257 .user = OCP_USER_MPU | OCP_USER_SDMA,
3258 };
3259
3260 /* l4_per3 -> mailbox4 */
3261 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3262 .master = &dra7xx_l4_per3_hwmod,
3263 .slave = &dra7xx_mailbox4_hwmod,
3264 .clk = "l3_iclk_div",
3265 .user = OCP_USER_MPU | OCP_USER_SDMA,
3266 };
3267
3268 /* l4_per3 -> mailbox5 */
3269 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3270 .master = &dra7xx_l4_per3_hwmod,
3271 .slave = &dra7xx_mailbox5_hwmod,
3272 .clk = "l3_iclk_div",
3273 .user = OCP_USER_MPU | OCP_USER_SDMA,
3274 };
3275
3276 /* l4_per3 -> mailbox6 */
3277 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3278 .master = &dra7xx_l4_per3_hwmod,
3279 .slave = &dra7xx_mailbox6_hwmod,
3280 .clk = "l3_iclk_div",
3281 .user = OCP_USER_MPU | OCP_USER_SDMA,
3282 };
3283
3284 /* l4_per3 -> mailbox7 */
3285 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3286 .master = &dra7xx_l4_per3_hwmod,
3287 .slave = &dra7xx_mailbox7_hwmod,
3288 .clk = "l3_iclk_div",
3289 .user = OCP_USER_MPU | OCP_USER_SDMA,
3290 };
3291
3292 /* l4_per3 -> mailbox8 */
3293 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3294 .master = &dra7xx_l4_per3_hwmod,
3295 .slave = &dra7xx_mailbox8_hwmod,
3296 .clk = "l3_iclk_div",
3297 .user = OCP_USER_MPU | OCP_USER_SDMA,
3298 };
3299
3300 /* l4_per3 -> mailbox9 */
3301 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3302 .master = &dra7xx_l4_per3_hwmod,
3303 .slave = &dra7xx_mailbox9_hwmod,
3304 .clk = "l3_iclk_div",
3305 .user = OCP_USER_MPU | OCP_USER_SDMA,
3306 };
3307
3308 /* l4_per3 -> mailbox10 */
3309 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3310 .master = &dra7xx_l4_per3_hwmod,
3311 .slave = &dra7xx_mailbox10_hwmod,
3312 .clk = "l3_iclk_div",
3313 .user = OCP_USER_MPU | OCP_USER_SDMA,
3314 };
3315
3316 /* l4_per3 -> mailbox11 */
3317 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3318 .master = &dra7xx_l4_per3_hwmod,
3319 .slave = &dra7xx_mailbox11_hwmod,
3320 .clk = "l3_iclk_div",
3321 .user = OCP_USER_MPU | OCP_USER_SDMA,
3322 };
3323
3324 /* l4_per3 -> mailbox12 */
3325 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3326 .master = &dra7xx_l4_per3_hwmod,
3327 .slave = &dra7xx_mailbox12_hwmod,
3328 .clk = "l3_iclk_div",
3329 .user = OCP_USER_MPU | OCP_USER_SDMA,
3330 };
3331
3332 /* l4_per3 -> mailbox13 */
3333 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3334 .master = &dra7xx_l4_per3_hwmod,
3335 .slave = &dra7xx_mailbox13_hwmod,
3336 .clk = "l3_iclk_div",
3337 .user = OCP_USER_MPU | OCP_USER_SDMA,
3338 };
3339
3340 /* l4_per1 -> mcspi1 */
3341 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3342 .master = &dra7xx_l4_per1_hwmod,
3343 .slave = &dra7xx_mcspi1_hwmod,
3344 .clk = "l3_iclk_div",
3345 .user = OCP_USER_MPU | OCP_USER_SDMA,
3346 };
3347
3348 /* l4_per1 -> mcspi2 */
3349 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3350 .master = &dra7xx_l4_per1_hwmod,
3351 .slave = &dra7xx_mcspi2_hwmod,
3352 .clk = "l3_iclk_div",
3353 .user = OCP_USER_MPU | OCP_USER_SDMA,
3354 };
3355
3356 /* l4_per1 -> mcspi3 */
3357 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3358 .master = &dra7xx_l4_per1_hwmod,
3359 .slave = &dra7xx_mcspi3_hwmod,
3360 .clk = "l3_iclk_div",
3361 .user = OCP_USER_MPU | OCP_USER_SDMA,
3362 };
3363
3364 /* l4_per1 -> mcspi4 */
3365 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3366 .master = &dra7xx_l4_per1_hwmod,
3367 .slave = &dra7xx_mcspi4_hwmod,
3368 .clk = "l3_iclk_div",
3369 .user = OCP_USER_MPU | OCP_USER_SDMA,
3370 };
3371
3372 /* l4_per1 -> mmc1 */
3373 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3374 .master = &dra7xx_l4_per1_hwmod,
3375 .slave = &dra7xx_mmc1_hwmod,
3376 .clk = "l3_iclk_div",
3377 .user = OCP_USER_MPU | OCP_USER_SDMA,
3378 };
3379
3380 /* l4_per1 -> mmc2 */
3381 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3382 .master = &dra7xx_l4_per1_hwmod,
3383 .slave = &dra7xx_mmc2_hwmod,
3384 .clk = "l3_iclk_div",
3385 .user = OCP_USER_MPU | OCP_USER_SDMA,
3386 };
3387
3388 /* l4_per1 -> mmc3 */
3389 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3390 .master = &dra7xx_l4_per1_hwmod,
3391 .slave = &dra7xx_mmc3_hwmod,
3392 .clk = "l3_iclk_div",
3393 .user = OCP_USER_MPU | OCP_USER_SDMA,
3394 };
3395
3396 /* l4_per1 -> mmc4 */
3397 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3398 .master = &dra7xx_l4_per1_hwmod,
3399 .slave = &dra7xx_mmc4_hwmod,
3400 .clk = "l3_iclk_div",
3401 .user = OCP_USER_MPU | OCP_USER_SDMA,
3402 };
3403
3404 /* l4_cfg -> mpu */
3405 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3406 .master = &dra7xx_l4_cfg_hwmod,
3407 .slave = &dra7xx_mpu_hwmod,
3408 .clk = "l3_iclk_div",
3409 .user = OCP_USER_MPU | OCP_USER_SDMA,
3410 };
3411
3412 /* l4_cfg -> ocp2scp1 */
3413 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3414 .master = &dra7xx_l4_cfg_hwmod,
3415 .slave = &dra7xx_ocp2scp1_hwmod,
3416 .clk = "l4_root_clk_div",
3417 .user = OCP_USER_MPU | OCP_USER_SDMA,
3418 };
3419
3420 /* l4_cfg -> ocp2scp3 */
3421 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3422 .master = &dra7xx_l4_cfg_hwmod,
3423 .slave = &dra7xx_ocp2scp3_hwmod,
3424 .clk = "l4_root_clk_div",
3425 .user = OCP_USER_MPU | OCP_USER_SDMA,
3426 };
3427
3428 /* l3_main_1 -> pciess1 */
3429 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3430 .master = &dra7xx_l3_main_1_hwmod,
3431 .slave = &dra7xx_pciess1_hwmod,
3432 .clk = "l3_iclk_div",
3433 .user = OCP_USER_MPU | OCP_USER_SDMA,
3434 };
3435
3436 /* l4_cfg -> pciess1 */
3437 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3438 .master = &dra7xx_l4_cfg_hwmod,
3439 .slave = &dra7xx_pciess1_hwmod,
3440 .clk = "l4_root_clk_div",
3441 .user = OCP_USER_MPU | OCP_USER_SDMA,
3442 };
3443
3444 /* l3_main_1 -> pciess2 */
3445 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3446 .master = &dra7xx_l3_main_1_hwmod,
3447 .slave = &dra7xx_pciess2_hwmod,
3448 .clk = "l3_iclk_div",
3449 .user = OCP_USER_MPU | OCP_USER_SDMA,
3450 };
3451
3452 /* l4_cfg -> pciess2 */
3453 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3454 .master = &dra7xx_l4_cfg_hwmod,
3455 .slave = &dra7xx_pciess2_hwmod,
3456 .clk = "l4_root_clk_div",
3457 .user = OCP_USER_MPU | OCP_USER_SDMA,
3458 };
3459
3460 /* l3_main_1 -> qspi */
3461 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3462 .master = &dra7xx_l3_main_1_hwmod,
3463 .slave = &dra7xx_qspi_hwmod,
3464 .clk = "l3_iclk_div",
3465 .user = OCP_USER_MPU | OCP_USER_SDMA,
3466 };
3467
3468 /* l4_per3 -> rtcss */
3469 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3470 .master = &dra7xx_l4_per3_hwmod,
3471 .slave = &dra7xx_rtcss_hwmod,
3472 .clk = "l4_root_clk_div",
3473 .user = OCP_USER_MPU | OCP_USER_SDMA,
3474 };
3475
3476 /* l4_cfg -> sata */
3477 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3478 .master = &dra7xx_l4_cfg_hwmod,
3479 .slave = &dra7xx_sata_hwmod,
3480 .clk = "l3_iclk_div",
3481 .user = OCP_USER_MPU | OCP_USER_SDMA,
3482 };
3483
3484 /* l4_cfg -> smartreflex_core */
3485 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3486 .master = &dra7xx_l4_cfg_hwmod,
3487 .slave = &dra7xx_smartreflex_core_hwmod,
3488 .clk = "l4_root_clk_div",
3489 .user = OCP_USER_MPU | OCP_USER_SDMA,
3490 };
3491
3492 /* l4_cfg -> smartreflex_mpu */
3493 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3494 .master = &dra7xx_l4_cfg_hwmod,
3495 .slave = &dra7xx_smartreflex_mpu_hwmod,
3496 .clk = "l4_root_clk_div",
3497 .user = OCP_USER_MPU | OCP_USER_SDMA,
3498 };
3499
3500 /* l4_cfg -> spinlock */
3501 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3502 .master = &dra7xx_l4_cfg_hwmod,
3503 .slave = &dra7xx_spinlock_hwmod,
3504 .clk = "l3_iclk_div",
3505 .user = OCP_USER_MPU | OCP_USER_SDMA,
3506 };
3507
3508 /* l4_wkup -> timer1 */
3509 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3510 .master = &dra7xx_l4_wkup_hwmod,
3511 .slave = &dra7xx_timer1_hwmod,
3512 .clk = "wkupaon_iclk_mux",
3513 .user = OCP_USER_MPU | OCP_USER_SDMA,
3514 };
3515
3516 /* l4_per1 -> timer2 */
3517 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3518 .master = &dra7xx_l4_per1_hwmod,
3519 .slave = &dra7xx_timer2_hwmod,
3520 .clk = "l3_iclk_div",
3521 .user = OCP_USER_MPU | OCP_USER_SDMA,
3522 };
3523
3524 /* l4_per1 -> timer3 */
3525 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3526 .master = &dra7xx_l4_per1_hwmod,
3527 .slave = &dra7xx_timer3_hwmod,
3528 .clk = "l3_iclk_div",
3529 .user = OCP_USER_MPU | OCP_USER_SDMA,
3530 };
3531
3532 /* l4_per1 -> timer4 */
3533 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3534 .master = &dra7xx_l4_per1_hwmod,
3535 .slave = &dra7xx_timer4_hwmod,
3536 .clk = "l3_iclk_div",
3537 .user = OCP_USER_MPU | OCP_USER_SDMA,
3538 };
3539
3540 /* l4_per3 -> timer5 */
3541 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3542 .master = &dra7xx_l4_per3_hwmod,
3543 .slave = &dra7xx_timer5_hwmod,
3544 .clk = "l3_iclk_div",
3545 .user = OCP_USER_MPU | OCP_USER_SDMA,
3546 };
3547
3548 /* l4_per3 -> timer6 */
3549 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3550 .master = &dra7xx_l4_per3_hwmod,
3551 .slave = &dra7xx_timer6_hwmod,
3552 .clk = "l3_iclk_div",
3553 .user = OCP_USER_MPU | OCP_USER_SDMA,
3554 };
3555
3556 /* l4_per3 -> timer7 */
3557 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3558 .master = &dra7xx_l4_per3_hwmod,
3559 .slave = &dra7xx_timer7_hwmod,
3560 .clk = "l3_iclk_div",
3561 .user = OCP_USER_MPU | OCP_USER_SDMA,
3562 };
3563
3564 /* l4_per3 -> timer8 */
3565 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3566 .master = &dra7xx_l4_per3_hwmod,
3567 .slave = &dra7xx_timer8_hwmod,
3568 .clk = "l3_iclk_div",
3569 .user = OCP_USER_MPU | OCP_USER_SDMA,
3570 };
3571
3572 /* l4_per1 -> timer9 */
3573 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3574 .master = &dra7xx_l4_per1_hwmod,
3575 .slave = &dra7xx_timer9_hwmod,
3576 .clk = "l3_iclk_div",
3577 .user = OCP_USER_MPU | OCP_USER_SDMA,
3578 };
3579
3580 /* l4_per1 -> timer10 */
3581 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3582 .master = &dra7xx_l4_per1_hwmod,
3583 .slave = &dra7xx_timer10_hwmod,
3584 .clk = "l3_iclk_div",
3585 .user = OCP_USER_MPU | OCP_USER_SDMA,
3586 };
3587
3588 /* l4_per1 -> timer11 */
3589 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3590 .master = &dra7xx_l4_per1_hwmod,
3591 .slave = &dra7xx_timer11_hwmod,
3592 .clk = "l3_iclk_div",
3593 .user = OCP_USER_MPU | OCP_USER_SDMA,
3594 };
3595
3596 /* l4_wkup -> timer12 */
3597 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3598 .master = &dra7xx_l4_wkup_hwmod,
3599 .slave = &dra7xx_timer12_hwmod,
3600 .clk = "wkupaon_iclk_mux",
3601 .user = OCP_USER_MPU | OCP_USER_SDMA,
3602 };
3603
3604 /* l4_per3 -> timer13 */
3605 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3606 .master = &dra7xx_l4_per3_hwmod,
3607 .slave = &dra7xx_timer13_hwmod,
3608 .clk = "l3_iclk_div",
3609 .user = OCP_USER_MPU | OCP_USER_SDMA,
3610 };
3611
3612 /* l4_per3 -> timer14 */
3613 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3614 .master = &dra7xx_l4_per3_hwmod,
3615 .slave = &dra7xx_timer14_hwmod,
3616 .clk = "l3_iclk_div",
3617 .user = OCP_USER_MPU | OCP_USER_SDMA,
3618 };
3619
3620 /* l4_per3 -> timer15 */
3621 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3622 .master = &dra7xx_l4_per3_hwmod,
3623 .slave = &dra7xx_timer15_hwmod,
3624 .clk = "l3_iclk_div",
3625 .user = OCP_USER_MPU | OCP_USER_SDMA,
3626 };
3627
3628 /* l4_per3 -> timer16 */
3629 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3630 .master = &dra7xx_l4_per3_hwmod,
3631 .slave = &dra7xx_timer16_hwmod,
3632 .clk = "l3_iclk_div",
3633 .user = OCP_USER_MPU | OCP_USER_SDMA,
3634 };
3635
3636 /* l4_per1 -> uart1 */
3637 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3638 .master = &dra7xx_l4_per1_hwmod,
3639 .slave = &dra7xx_uart1_hwmod,
3640 .clk = "l3_iclk_div",
3641 .user = OCP_USER_MPU | OCP_USER_SDMA,
3642 };
3643
3644 /* l4_per1 -> uart2 */
3645 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3646 .master = &dra7xx_l4_per1_hwmod,
3647 .slave = &dra7xx_uart2_hwmod,
3648 .clk = "l3_iclk_div",
3649 .user = OCP_USER_MPU | OCP_USER_SDMA,
3650 };
3651
3652 /* l4_per1 -> uart3 */
3653 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3654 .master = &dra7xx_l4_per1_hwmod,
3655 .slave = &dra7xx_uart3_hwmod,
3656 .clk = "l3_iclk_div",
3657 .user = OCP_USER_MPU | OCP_USER_SDMA,
3658 };
3659
3660 /* l4_per1 -> uart4 */
3661 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3662 .master = &dra7xx_l4_per1_hwmod,
3663 .slave = &dra7xx_uart4_hwmod,
3664 .clk = "l3_iclk_div",
3665 .user = OCP_USER_MPU | OCP_USER_SDMA,
3666 };
3667
3668 /* l4_per1 -> uart5 */
3669 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3670 .master = &dra7xx_l4_per1_hwmod,
3671 .slave = &dra7xx_uart5_hwmod,
3672 .clk = "l3_iclk_div",
3673 .user = OCP_USER_MPU | OCP_USER_SDMA,
3674 };
3675
3676 /* l4_per1 -> uart6 */
3677 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3678 .master = &dra7xx_l4_per1_hwmod,
3679 .slave = &dra7xx_uart6_hwmod,
3680 .clk = "l3_iclk_div",
3681 .user = OCP_USER_MPU | OCP_USER_SDMA,
3682 };
3683
3684 /* l4_per2 -> uart7 */
3685 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3686 .master = &dra7xx_l4_per2_hwmod,
3687 .slave = &dra7xx_uart7_hwmod,
3688 .clk = "l3_iclk_div",
3689 .user = OCP_USER_MPU | OCP_USER_SDMA,
3690 };
3691
3692 /* l4_per1 -> des */
3693 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3694 .master = &dra7xx_l4_per1_hwmod,
3695 .slave = &dra7xx_des_hwmod,
3696 .clk = "l3_iclk_div",
3697 .user = OCP_USER_MPU | OCP_USER_SDMA,
3698 };
3699
3700 /* l4_per2 -> uart8 */
3701 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3702 .master = &dra7xx_l4_per2_hwmod,
3703 .slave = &dra7xx_uart8_hwmod,
3704 .clk = "l3_iclk_div",
3705 .user = OCP_USER_MPU | OCP_USER_SDMA,
3706 };
3707
3708 /* l4_per2 -> uart9 */
3709 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3710 .master = &dra7xx_l4_per2_hwmod,
3711 .slave = &dra7xx_uart9_hwmod,
3712 .clk = "l3_iclk_div",
3713 .user = OCP_USER_MPU | OCP_USER_SDMA,
3714 };
3715
3716 /* l4_wkup -> uart10 */
3717 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3718 .master = &dra7xx_l4_wkup_hwmod,
3719 .slave = &dra7xx_uart10_hwmod,
3720 .clk = "wkupaon_iclk_mux",
3721 .user = OCP_USER_MPU | OCP_USER_SDMA,
3722 };
3723
3724 /* l4_per1 -> rng */
3725 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3726 .master = &dra7xx_l4_per1_hwmod,
3727 .slave = &dra7xx_rng_hwmod,
3728 .user = OCP_USER_MPU,
3729 };
3730
3731 /* l4_per3 -> usb_otg_ss1 */
3732 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3733 .master = &dra7xx_l4_per3_hwmod,
3734 .slave = &dra7xx_usb_otg_ss1_hwmod,
3735 .clk = "dpll_core_h13x2_ck",
3736 .user = OCP_USER_MPU | OCP_USER_SDMA,
3737 };
3738
3739 /* l4_per3 -> usb_otg_ss2 */
3740 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3741 .master = &dra7xx_l4_per3_hwmod,
3742 .slave = &dra7xx_usb_otg_ss2_hwmod,
3743 .clk = "dpll_core_h13x2_ck",
3744 .user = OCP_USER_MPU | OCP_USER_SDMA,
3745 };
3746
3747 /* l4_per3 -> usb_otg_ss3 */
3748 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3749 .master = &dra7xx_l4_per3_hwmod,
3750 .slave = &dra7xx_usb_otg_ss3_hwmod,
3751 .clk = "dpll_core_h13x2_ck",
3752 .user = OCP_USER_MPU | OCP_USER_SDMA,
3753 };
3754
3755 /* l4_per3 -> usb_otg_ss4 */
3756 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3757 .master = &dra7xx_l4_per3_hwmod,
3758 .slave = &dra7xx_usb_otg_ss4_hwmod,
3759 .clk = "dpll_core_h13x2_ck",
3760 .user = OCP_USER_MPU | OCP_USER_SDMA,
3761 };
3762
3763 /* l3_main_1 -> vcp1 */
3764 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3765 .master = &dra7xx_l3_main_1_hwmod,
3766 .slave = &dra7xx_vcp1_hwmod,
3767 .clk = "l3_iclk_div",
3768 .user = OCP_USER_MPU | OCP_USER_SDMA,
3769 };
3770
3771 /* l4_per2 -> vcp1 */
3772 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3773 .master = &dra7xx_l4_per2_hwmod,
3774 .slave = &dra7xx_vcp1_hwmod,
3775 .clk = "l3_iclk_div",
3776 .user = OCP_USER_MPU | OCP_USER_SDMA,
3777 };
3778
3779 /* l3_main_1 -> vcp2 */
3780 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3781 .master = &dra7xx_l3_main_1_hwmod,
3782 .slave = &dra7xx_vcp2_hwmod,
3783 .clk = "l3_iclk_div",
3784 .user = OCP_USER_MPU | OCP_USER_SDMA,
3785 };
3786
3787 /* l4_per2 -> vcp2 */
3788 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3789 .master = &dra7xx_l4_per2_hwmod,
3790 .slave = &dra7xx_vcp2_hwmod,
3791 .clk = "l3_iclk_div",
3792 .user = OCP_USER_MPU | OCP_USER_SDMA,
3793 };
3794
3795 /* l4_wkup -> wd_timer2 */
3796 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3797 .master = &dra7xx_l4_wkup_hwmod,
3798 .slave = &dra7xx_wd_timer2_hwmod,
3799 .clk = "wkupaon_iclk_mux",
3800 .user = OCP_USER_MPU | OCP_USER_SDMA,
3801 };
3802
3803 /* l4_per2 -> epwmss0 */
3804 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3805 .master = &dra7xx_l4_per2_hwmod,
3806 .slave = &dra7xx_epwmss0_hwmod,
3807 .clk = "l4_root_clk_div",
3808 .user = OCP_USER_MPU,
3809 };
3810
3811 /* l4_per2 -> epwmss1 */
3812 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3813 .master = &dra7xx_l4_per2_hwmod,
3814 .slave = &dra7xx_epwmss1_hwmod,
3815 .clk = "l4_root_clk_div",
3816 .user = OCP_USER_MPU,
3817 };
3818
3819 /* l4_per2 -> epwmss2 */
3820 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3821 .master = &dra7xx_l4_per2_hwmod,
3822 .slave = &dra7xx_epwmss2_hwmod,
3823 .clk = "l4_root_clk_div",
3824 .user = OCP_USER_MPU,
3825 };
3826
3827 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3828 &dra7xx_l3_main_1__dmm,
3829 &dra7xx_l3_main_2__l3_instr,
3830 &dra7xx_l4_cfg__l3_main_1,
3831 &dra7xx_mpu__l3_main_1,
3832 &dra7xx_l3_main_1__l3_main_2,
3833 &dra7xx_l4_cfg__l3_main_2,
3834 &dra7xx_l3_main_1__l4_cfg,
3835 &dra7xx_l3_main_1__l4_per1,
3836 &dra7xx_l3_main_1__l4_per2,
3837 &dra7xx_l3_main_1__l4_per3,
3838 &dra7xx_l3_main_1__l4_wkup,
3839 &dra7xx_l4_per2__atl,
3840 &dra7xx_l3_main_1__bb2d,
3841 &dra7xx_l4_wkup__counter_32k,
3842 &dra7xx_l4_wkup__ctrl_module_wkup,
3843 &dra7xx_l4_wkup__dcan1,
3844 &dra7xx_l4_per2__dcan2,
3845 &dra7xx_l4_per2__cpgmac0,
3846 &dra7xx_l4_per2__mcasp1,
3847 &dra7xx_l3_main_1__mcasp1,
3848 &dra7xx_l4_per2__mcasp2,
3849 &dra7xx_l3_main_1__mcasp2,
3850 &dra7xx_l4_per2__mcasp3,
3851 &dra7xx_l3_main_1__mcasp3,
3852 &dra7xx_l4_per2__mcasp4,
3853 &dra7xx_l4_per2__mcasp5,
3854 &dra7xx_l4_per2__mcasp6,
3855 &dra7xx_l4_per2__mcasp7,
3856 &dra7xx_l4_per2__mcasp8,
3857 &dra7xx_gmac__mdio,
3858 &dra7xx_l4_cfg__dma_system,
3859 &dra7xx_l3_main_1__tpcc,
3860 &dra7xx_l3_main_1__tptc0,
3861 &dra7xx_l3_main_1__tptc1,
3862 &dra7xx_l3_main_1__dss,
3863 &dra7xx_l3_main_1__dispc,
3864 &dra7xx_l3_main_1__hdmi,
3865 &dra7xx_l3_main_1__aes1,
3866 &dra7xx_l3_main_1__aes2,
3867 &dra7xx_l3_main_1__sha0,
3868 &dra7xx_l4_per1__elm,
3869 &dra7xx_l4_wkup__gpio1,
3870 &dra7xx_l4_per1__gpio2,
3871 &dra7xx_l4_per1__gpio3,
3872 &dra7xx_l4_per1__gpio4,
3873 &dra7xx_l4_per1__gpio5,
3874 &dra7xx_l4_per1__gpio6,
3875 &dra7xx_l4_per1__gpio7,
3876 &dra7xx_l4_per1__gpio8,
3877 &dra7xx_l3_main_1__gpmc,
3878 &dra7xx_l4_per1__hdq1w,
3879 &dra7xx_l4_per1__i2c1,
3880 &dra7xx_l4_per1__i2c2,
3881 &dra7xx_l4_per1__i2c3,
3882 &dra7xx_l4_per1__i2c4,
3883 &dra7xx_l4_per1__i2c5,
3884 &dra7xx_l4_cfg__mailbox1,
3885 &dra7xx_l4_per3__mailbox2,
3886 &dra7xx_l4_per3__mailbox3,
3887 &dra7xx_l4_per3__mailbox4,
3888 &dra7xx_l4_per3__mailbox5,
3889 &dra7xx_l4_per3__mailbox6,
3890 &dra7xx_l4_per3__mailbox7,
3891 &dra7xx_l4_per3__mailbox8,
3892 &dra7xx_l4_per3__mailbox9,
3893 &dra7xx_l4_per3__mailbox10,
3894 &dra7xx_l4_per3__mailbox11,
3895 &dra7xx_l4_per3__mailbox12,
3896 &dra7xx_l4_per3__mailbox13,
3897 &dra7xx_l4_per1__mcspi1,
3898 &dra7xx_l4_per1__mcspi2,
3899 &dra7xx_l4_per1__mcspi3,
3900 &dra7xx_l4_per1__mcspi4,
3901 &dra7xx_l4_per1__mmc1,
3902 &dra7xx_l4_per1__mmc2,
3903 &dra7xx_l4_per1__mmc3,
3904 &dra7xx_l4_per1__mmc4,
3905 &dra7xx_l4_cfg__mpu,
3906 &dra7xx_l4_cfg__ocp2scp1,
3907 &dra7xx_l4_cfg__ocp2scp3,
3908 &dra7xx_l3_main_1__pciess1,
3909 &dra7xx_l4_cfg__pciess1,
3910 &dra7xx_l3_main_1__pciess2,
3911 &dra7xx_l4_cfg__pciess2,
3912 &dra7xx_l3_main_1__qspi,
3913 &dra7xx_l4_cfg__sata,
3914 &dra7xx_l4_cfg__smartreflex_core,
3915 &dra7xx_l4_cfg__smartreflex_mpu,
3916 &dra7xx_l4_cfg__spinlock,
3917 &dra7xx_l4_wkup__timer1,
3918 &dra7xx_l4_per1__timer2,
3919 &dra7xx_l4_per1__timer3,
3920 &dra7xx_l4_per1__timer4,
3921 &dra7xx_l4_per3__timer5,
3922 &dra7xx_l4_per3__timer6,
3923 &dra7xx_l4_per3__timer7,
3924 &dra7xx_l4_per3__timer8,
3925 &dra7xx_l4_per1__timer9,
3926 &dra7xx_l4_per1__timer10,
3927 &dra7xx_l4_per1__timer11,
3928 &dra7xx_l4_per3__timer13,
3929 &dra7xx_l4_per3__timer14,
3930 &dra7xx_l4_per3__timer15,
3931 &dra7xx_l4_per3__timer16,
3932 &dra7xx_l4_per1__uart1,
3933 &dra7xx_l4_per1__uart2,
3934 &dra7xx_l4_per1__uart3,
3935 &dra7xx_l4_per1__uart4,
3936 &dra7xx_l4_per1__uart5,
3937 &dra7xx_l4_per1__uart6,
3938 &dra7xx_l4_per2__uart7,
3939 &dra7xx_l4_per2__uart8,
3940 &dra7xx_l4_per2__uart9,
3941 &dra7xx_l4_wkup__uart10,
3942 &dra7xx_l4_per1__des,
3943 &dra7xx_l4_per3__usb_otg_ss1,
3944 &dra7xx_l4_per3__usb_otg_ss2,
3945 &dra7xx_l4_per3__usb_otg_ss3,
3946 &dra7xx_l3_main_1__vcp1,
3947 &dra7xx_l4_per2__vcp1,
3948 &dra7xx_l3_main_1__vcp2,
3949 &dra7xx_l4_per2__vcp2,
3950 &dra7xx_l4_wkup__wd_timer2,
3951 &dra7xx_l4_per2__epwmss0,
3952 &dra7xx_l4_per2__epwmss1,
3953 &dra7xx_l4_per2__epwmss2,
3954 NULL,
3955 };
3956
3957 /* GP-only hwmod links */
3958 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
3959 &dra7xx_l4_wkup__timer12,
3960 &dra7xx_l4_per1__rng,
3961 NULL,
3962 };
3963
3964 /* SoC variant specific hwmod links */
3965 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
3966 &dra7xx_l4_per3__usb_otg_ss4,
3967 NULL,
3968 };
3969
3970 static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
3971 NULL,
3972 };
3973
3974 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3975 &dra7xx_l4_per3__usb_otg_ss4,
3976 NULL,
3977 };
3978
3979 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3980 NULL,
3981 };
3982
3983 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
3984 &dra7xx_l4_per3__rtcss,
3985 NULL,
3986 };
3987
3988 int __init dra7xx_hwmod_init(void)
3989 {
3990 int ret;
3991
3992 omap_hwmod_init();
3993 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3994
3995 if (!ret && soc_is_dra74x()) {
3996 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3997 if (!ret)
3998 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
3999 } else if (!ret && soc_is_dra72x()) {
4000 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4001 if (!ret && !of_machine_is_compatible("ti,dra718"))
4002 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4003 } else if (!ret && soc_is_dra76x()) {
4004 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
4005
4006 if (!ret && soc_is_dra76x_acd()) {
4007 ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
4008 } else if (!ret && soc_is_dra76x_abz()) {
4009 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4010 }
4011 }
4012
4013 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4014 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4015
4016 return ret;
4017 }
Linux with added FPC-III support