arch/arm64/include/asm/kvm_arm.h

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __ARM64_KVM_ARM_H__
  19 #define __ARM64_KVM_ARM_H__
  20
  21 #include <asm/esr.h>
  22 #include <asm/memory.h>
  23 #include <asm/types.h>
  24
  25 /* Hyp Configuration Register (HCR) bits */
  26 #define HCR_TEA         (UL(1) << 37)
  27 #define HCR_TERR        (UL(1) << 36)
  28 #define HCR_TLOR        (UL(1) << 35)
  29 #define HCR_E2H         (UL(1) << 34)
  30 #define HCR_ID          (UL(1) << 33)
  31 #define HCR_CD          (UL(1) << 32)
  32 #define HCR_RW_SHIFT    31
  33 #define HCR_RW          (UL(1) << HCR_RW_SHIFT)
  34 #define HCR_TRVM        (UL(1) << 30)
  35 #define HCR_HCD         (UL(1) << 29)
  36 #define HCR_TDZ         (UL(1) << 28)
  37 #define HCR_TGE         (UL(1) << 27)
  38 #define HCR_TVM         (UL(1) << 26)
  39 #define HCR_TTLB        (UL(1) << 25)
  40 #define HCR_TPU         (UL(1) << 24)
  41 #define HCR_TPC         (UL(1) << 23)
  42 #define HCR_TSW         (UL(1) << 22)
  43 #define HCR_TAC         (UL(1) << 21)
  44 #define HCR_TIDCP       (UL(1) << 20)
  45 #define HCR_TSC         (UL(1) << 19)
  46 #define HCR_TID3        (UL(1) << 18)
  47 #define HCR_TID2        (UL(1) << 17)
  48 #define HCR_TID1        (UL(1) << 16)
  49 #define HCR_TID0        (UL(1) << 15)
  50 #define HCR_TWE         (UL(1) << 14)
  51 #define HCR_TWI         (UL(1) << 13)
  52 #define HCR_DC          (UL(1) << 12)
  53 #define HCR_BSU         (3 << 10)
  54 #define HCR_BSU_IS      (UL(1) << 10)
  55 #define HCR_FB          (UL(1) << 9)
  56 #define HCR_VSE         (UL(1) << 8)
  57 #define HCR_VI          (UL(1) << 7)
  58 #define HCR_VF          (UL(1) << 6)
  59 #define HCR_AMO         (UL(1) << 5)
  60 #define HCR_IMO         (UL(1) << 4)
  61 #define HCR_FMO         (UL(1) << 3)
  62 #define HCR_PTW         (UL(1) << 2)
  63 #define HCR_SWIO        (UL(1) << 1)
  64 #define HCR_VM          (UL(1) << 0)
  65
  66 /*
  67  * The bits we set in HCR:
  68  * TLOR:        Trap LORegion register accesses
  69  * RW:          64bit by default, can be overridden for 32bit VMs
  70  * TAC:         Trap ACTLR
  71  * TSC:         Trap SMC
  72  * TVM:         Trap VM ops (until M+C set in SCTLR_EL1)
  73  * TSW:         Trap cache operations by set/way
  74  * TWE:         Trap WFE
  75  * TWI:         Trap WFI
  76  * TIDCP:       Trap L2CTLR/L2ECTLR
  77  * BSU_IS:      Upgrade barriers to the inner shareable domain
  78  * FB:          Force broadcast of all maintainance operations
  79  * AMO:         Override CPSR.A and enable signaling with VA
  80  * IMO:         Override CPSR.I and enable signaling with VI
  81  * FMO:         Override CPSR.F and enable signaling with VF
  82  * SWIO:        Turn set/way invalidates into set/way clean+invalidate
  83  */
  84 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
  85                          HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
  86                          HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
  87                          HCR_FMO | HCR_IMO)
  88 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
  89 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
  90
  91 /* TCR_EL2 Registers bits */
  92 #define TCR_EL2_RES1            ((1 << 31) | (1 << 23))
  93 #define TCR_EL2_TBI             (1 << 20)
  94 #define TCR_EL2_PS_SHIFT        16
  95 #define TCR_EL2_PS_MASK         (7 << TCR_EL2_PS_SHIFT)
  96 #define TCR_EL2_PS_40B          (2 << TCR_EL2_PS_SHIFT)
  97 #define TCR_EL2_TG0_MASK        TCR_TG0_MASK
  98 #define TCR_EL2_SH0_MASK        TCR_SH0_MASK
  99 #define TCR_EL2_ORGN0_MASK      TCR_ORGN0_MASK
 100 #define TCR_EL2_IRGN0_MASK      TCR_IRGN0_MASK
 101 #define TCR_EL2_T0SZ_MASK       0x3f
 102 #define TCR_EL2_MASK    (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
 103                          TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
 104
 105 /* VTCR_EL2 Registers bits */
 106 #define VTCR_EL2_RES1           (1 << 31)
 107 #define VTCR_EL2_HD             (1 << 22)
 108 #define VTCR_EL2_HA             (1 << 21)
 109 #define VTCR_EL2_PS_MASK        TCR_EL2_PS_MASK
 110 #define VTCR_EL2_TG0_MASK       TCR_TG0_MASK
 111 #define VTCR_EL2_TG0_4K         TCR_TG0_4K
 112 #define VTCR_EL2_TG0_16K        TCR_TG0_16K
 113 #define VTCR_EL2_TG0_64K        TCR_TG0_64K
 114 #define VTCR_EL2_SH0_MASK       TCR_SH0_MASK
 115 #define VTCR_EL2_SH0_INNER      TCR_SH0_INNER
 116 #define VTCR_EL2_ORGN0_MASK     TCR_ORGN0_MASK
 117 #define VTCR_EL2_ORGN0_WBWA     TCR_ORGN0_WBWA
 118 #define VTCR_EL2_IRGN0_MASK     TCR_IRGN0_MASK
 119 #define VTCR_EL2_IRGN0_WBWA     TCR_IRGN0_WBWA
 120 #define VTCR_EL2_SL0_SHIFT      6
 121 #define VTCR_EL2_SL0_MASK       (3 << VTCR_EL2_SL0_SHIFT)
 122 #define VTCR_EL2_SL0_LVL1       (1 << VTCR_EL2_SL0_SHIFT)
 123 #define VTCR_EL2_T0SZ_MASK      0x3f
 124 #define VTCR_EL2_T0SZ_40B       24
 125 #define VTCR_EL2_VS_SHIFT       19
 126 #define VTCR_EL2_VS_8BIT        (0 << VTCR_EL2_VS_SHIFT)
 127 #define VTCR_EL2_VS_16BIT       (1 << VTCR_EL2_VS_SHIFT)
 128
 129 /*
 130  * We configure the Stage-2 page tables to always restrict the IPA space to be
 131  * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
 132  * not known to exist and will break with this configuration.
 133  *
 134  * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time
 135  * (see hyp-init.S).
 136  *
 137  * Note that when using 4K pages, we concatenate two first level page tables
 138  * together. With 16K pages, we concatenate 16 first level page tables.
 139  *
 140  * The magic numbers used for VTTBR_X in this patch can be found in Tables
 141  * D4-23 and D4-25 in ARM DDI 0487A.b.
 142  */
 143
 144 #define VTCR_EL2_T0SZ_IPA       VTCR_EL2_T0SZ_40B
 145 #define VTCR_EL2_COMMON_BITS    (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
 146                                  VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
 147
 148 #ifdef CONFIG_ARM64_64K_PAGES
 149 /*
 150  * Stage2 translation configuration:
 151  * 64kB pages (TG0 = 1)
 152  * 2 level page tables (SL = 1)
 153  */
 154 #define VTCR_EL2_TGRAN_FLAGS            (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1)
 155 #define VTTBR_X_TGRAN_MAGIC             38
 156 #elif defined(CONFIG_ARM64_16K_PAGES)
 157 /*
 158  * Stage2 translation configuration:
 159  * 16kB pages (TG0 = 2)
 160  * 2 level page tables (SL = 1)
 161  */
 162 #define VTCR_EL2_TGRAN_FLAGS            (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1)
 163 #define VTTBR_X_TGRAN_MAGIC             42
 164 #else   /* 4K */
 165 /*
 166  * Stage2 translation configuration:
 167  * 4kB pages (TG0 = 0)
 168  * 3 level page tables (SL = 1)
 169  */
 170 #define VTCR_EL2_TGRAN_FLAGS            (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1)
 171 #define VTTBR_X_TGRAN_MAGIC             37
 172 #endif
 173
 174 #define VTCR_EL2_FLAGS                  (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS)
 175 #define VTTBR_X                         (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA)
 176
 177 #define VTTBR_BADDR_MASK  (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X)
 178 #define VTTBR_VMID_SHIFT  (UL(48))
 179 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
 180
 181 /* Hyp System Trap Register */
 182 #define HSTR_EL2_T(x)   (1 << x)
 183
 184 /* Hyp Coprocessor Trap Register Shifts */
 185 #define CPTR_EL2_TFP_SHIFT 10
 186
 187 /* Hyp Coprocessor Trap Register */
 188 #define CPTR_EL2_TCPAC  (1 << 31)
 189 #define CPTR_EL2_TTA    (1 << 20)
 190 #define CPTR_EL2_TFP    (1 << CPTR_EL2_TFP_SHIFT)
 191 #define CPTR_EL2_TZ     (1 << 8)
 192 #define CPTR_EL2_RES1   0x000032ff /* known RES1 bits in CPTR_EL2 */
 193 #define CPTR_EL2_DEFAULT        CPTR_EL2_RES1
 194
 195 /* Hyp Debug Configuration Register bits */
 196 #define MDCR_EL2_TPMS           (1 << 14)
 197 #define MDCR_EL2_E2PB_MASK      (UL(0x3))
 198 #define MDCR_EL2_E2PB_SHIFT     (UL(12))
 199 #define MDCR_EL2_TDRA           (1 << 11)
 200 #define MDCR_EL2_TDOSA          (1 << 10)
 201 #define MDCR_EL2_TDA            (1 << 9)
 202 #define MDCR_EL2_TDE            (1 << 8)
 203 #define MDCR_EL2_HPME           (1 << 7)
 204 #define MDCR_EL2_TPM            (1 << 6)
 205 #define MDCR_EL2_TPMCR          (1 << 5)
 206 #define MDCR_EL2_HPMN_MASK      (0x1F)
 207
 208 /* For compatibility with fault code shared with 32-bit */
 209 #define FSC_FAULT       ESR_ELx_FSC_FAULT
 210 #define FSC_ACCESS      ESR_ELx_FSC_ACCESS
 211 #define FSC_PERM        ESR_ELx_FSC_PERM
 212 #define FSC_SEA         ESR_ELx_FSC_EXTABT
 213 #define FSC_SEA_TTW0    (0x14)
 214 #define FSC_SEA_TTW1    (0x15)
 215 #define FSC_SEA_TTW2    (0x16)
 216 #define FSC_SEA_TTW3    (0x17)
 217 #define FSC_SECC        (0x18)
 218 #define FSC_SECC_TTW0   (0x1c)
 219 #define FSC_SECC_TTW1   (0x1d)
 220 #define FSC_SECC_TTW2   (0x1e)
 221 #define FSC_SECC_TTW3   (0x1f)
 222
 223 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
 224 #define HPFAR_MASK      (~UL(0xf))
 225
 226 #define kvm_arm_exception_type  \
 227         {0, "IRQ" },            \
 228         {1, "TRAP" }
 229
 230 #define ECN(x) { ESR_ELx_EC_##x, #x }
 231
 232 #define kvm_arm_exception_class \
 233         ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
 234         ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
 235         ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
 236         ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
 237         ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
 238         ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
 239         ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
 240         ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
 241
 242 #define CPACR_EL1_FPEN          (3 << 20)
 243 #define CPACR_EL1_TTA           (1 << 28)
 244 #define CPACR_EL1_DEFAULT       (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN)
 245
 246 #endif /* __ARM64_KVM_ARM_H__ */