Linux 4.18.10
[linux/fpc-iii.git] / arch / arm64 / include / asm / module.h
blob97d0ef12e2ff561938acdf96196a1a213664c522
1 /*
2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_MODULE_H
17 #define __ASM_MODULE_H
19 #include <asm-generic/module.h>
21 #define MODULE_ARCH_VERMAGIC "aarch64"
23 #ifdef CONFIG_ARM64_MODULE_PLTS
24 struct mod_plt_sec {
25 struct elf64_shdr *plt;
26 int plt_num_entries;
27 int plt_max_entries;
30 struct mod_arch_specific {
31 struct mod_plt_sec core;
32 struct mod_plt_sec init;
34 /* for CONFIG_DYNAMIC_FTRACE */
35 struct plt_entry *ftrace_trampoline;
37 #endif
39 u64 module_emit_plt_entry(struct module *mod, void *loc, const Elf64_Rela *rela,
40 Elf64_Sym *sym);
42 u64 module_emit_veneer_for_adrp(struct module *mod, void *loc, u64 val);
44 #ifdef CONFIG_RANDOMIZE_BASE
45 extern u64 module_alloc_base;
46 #else
47 #define module_alloc_base ((u64)_etext - MODULES_VSIZE)
48 #endif
50 struct plt_entry {
52 * A program that conforms to the AArch64 Procedure Call Standard
53 * (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or
54 * IP1 (x17) may be inserted at any branch instruction that is
55 * exposed to a relocation that supports long branches. Since that
56 * is exactly what we are dealing with here, we are free to use x16
57 * as a scratch register in the PLT veneers.
59 __le32 mov0; /* movn x16, #0x.... */
60 __le32 mov1; /* movk x16, #0x...., lsl #16 */
61 __le32 mov2; /* movk x16, #0x...., lsl #32 */
62 __le32 br; /* br x16 */
65 static inline struct plt_entry get_plt_entry(u64 val)
68 * MOVK/MOVN/MOVZ opcode:
69 * +--------+------------+--------+-----------+-------------+---------+
70 * | sf[31] | opc[30:29] | 100101 | hw[22:21] | imm16[20:5] | Rd[4:0] |
71 * +--------+------------+--------+-----------+-------------+---------+
73 * Rd := 0x10 (x16)
74 * hw := 0b00 (no shift), 0b01 (lsl #16), 0b10 (lsl #32)
75 * opc := 0b11 (MOVK), 0b00 (MOVN), 0b10 (MOVZ)
76 * sf := 1 (64-bit variant)
78 return (struct plt_entry){
79 cpu_to_le32(0x92800010 | (((~val ) & 0xffff)) << 5),
80 cpu_to_le32(0xf2a00010 | ((( val >> 16) & 0xffff)) << 5),
81 cpu_to_le32(0xf2c00010 | ((( val >> 32) & 0xffff)) << 5),
82 cpu_to_le32(0xd61f0200)
86 static inline bool plt_entries_equal(const struct plt_entry *a,
87 const struct plt_entry *b)
89 return a->mov0 == b->mov0 &&
90 a->mov1 == b->mov1 &&
91 a->mov2 == b->mov2;
94 #endif /* __ASM_MODULE_H */