arch/arm64/kernel/cpu_errata.c

   1 /*
   2  * Contains CPU specific errata definitions
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/arm-smccc.h>
  20 #include <linux/psci.h>
  21 #include <linux/types.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cputype.h>
  24 #include <asm/cpufeature.h>
  25
  26 static bool __maybe_unused
  27 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
  28 {
  29         const struct arm64_midr_revidr *fix;
  30         u32 midr = read_cpuid_id(), revidr;
  31
  32         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  33         if (!is_midr_in_range(midr, &entry->midr_range))
  34                 return false;
  35
  36         midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
  37         revidr = read_cpuid(REVIDR_EL1);
  38         for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
  39                 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
  40                         return false;
  41
  42         return true;
  43 }
  44
  45 static bool __maybe_unused
  46 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
  47                             int scope)
  48 {
  49         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  50         return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
  51 }
  52
  53 static bool __maybe_unused
  54 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
  55 {
  56         u32 model;
  57
  58         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  59
  60         model = read_cpuid_id();
  61         model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
  62                  MIDR_ARCHITECTURE_MASK;
  63
  64         return model == entry->midr_range.model;
  65 }
  66
  67 static bool
  68 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
  69                           int scope)
  70 {
  71         u64 mask = CTR_CACHE_MINLINE_MASK;
  72
  73         /* Skip matching the min line sizes for cache type check */
  74         if (entry->capability == ARM64_MISMATCHED_CACHE_TYPE)
  75                 mask ^= arm64_ftr_reg_ctrel0.strict_mask;
  76
  77         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  78         return (read_cpuid_cachetype() & mask) !=
  79                (arm64_ftr_reg_ctrel0.sys_val & mask);
  80 }
  81
  82 static void
  83 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
  84 {
  85         /* Clear SCTLR_EL1.UCT */
  86         config_sctlr_el1(SCTLR_EL1_UCT, 0);
  87 }
  88
  89 atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
  90
  91 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
  92 #include <asm/mmu_context.h>
  93 #include <asm/cacheflush.h>
  94
  95 DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
  96
  97 #ifdef CONFIG_KVM_INDIRECT_VECTORS
  98 extern char __smccc_workaround_1_smc_start[];
  99 extern char __smccc_workaround_1_smc_end[];
 100
 101 static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
 102                                 const char *hyp_vecs_end)
 103 {
 104         void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
 105         int i;
 106
 107         for (i = 0; i < SZ_2K; i += 0x80)
 108                 memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
 109
 110         flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
 111 }
 112
 113 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
 114                                       const char *hyp_vecs_start,
 115                                       const char *hyp_vecs_end)
 116 {
 117         static DEFINE_SPINLOCK(bp_lock);
 118         int cpu, slot = -1;
 119
 120         spin_lock(&bp_lock);
 121         for_each_possible_cpu(cpu) {
 122                 if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
 123                         slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
 124                         break;
 125                 }
 126         }
 127
 128         if (slot == -1) {
 129                 slot = atomic_inc_return(&arm64_el2_vector_last_slot);
 130                 BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
 131                 __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
 132         }
 133
 134         __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
 135         __this_cpu_write(bp_hardening_data.fn, fn);
 136         spin_unlock(&bp_lock);
 137 }
 138 #else
 139 #define __smccc_workaround_1_smc_start          NULL
 140 #define __smccc_workaround_1_smc_end            NULL
 141
 142 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
 143                                       const char *hyp_vecs_start,
 144                                       const char *hyp_vecs_end)
 145 {
 146         __this_cpu_write(bp_hardening_data.fn, fn);
 147 }
 148 #endif  /* CONFIG_KVM_INDIRECT_VECTORS */
 149
 150 static void  install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
 151                                      bp_hardening_cb_t fn,
 152                                      const char *hyp_vecs_start,
 153                                      const char *hyp_vecs_end)
 154 {
 155         u64 pfr0;
 156
 157         if (!entry->matches(entry, SCOPE_LOCAL_CPU))
 158                 return;
 159
 160         pfr0 = read_cpuid(ID_AA64PFR0_EL1);
 161         if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
 162                 return;
 163
 164         __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
 165 }
 166
 167 #include <uapi/linux/psci.h>
 168 #include <linux/arm-smccc.h>
 169 #include <linux/psci.h>
 170
 171 static void call_smc_arch_workaround_1(void)
 172 {
 173         arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
 174 }
 175
 176 static void call_hvc_arch_workaround_1(void)
 177 {
 178         arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
 179 }
 180
 181 static void qcom_link_stack_sanitization(void)
 182 {
 183         u64 tmp;
 184
 185         asm volatile("mov       %0, x30         \n"
 186                      ".rept     16              \n"
 187                      "bl        . + 4           \n"
 188                      ".endr                     \n"
 189                      "mov       x30, %0         \n"
 190                      : "=&r" (tmp));
 191 }
 192
 193 static void
 194 enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
 195 {
 196         bp_hardening_cb_t cb;
 197         void *smccc_start, *smccc_end;
 198         struct arm_smccc_res res;
 199         u32 midr = read_cpuid_id();
 200
 201         if (!entry->matches(entry, SCOPE_LOCAL_CPU))
 202                 return;
 203
 204         if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
 205                 return;
 206
 207         switch (psci_ops.conduit) {
 208         case PSCI_CONDUIT_HVC:
 209                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 210                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 211                 if ((int)res.a0 < 0)
 212                         return;
 213                 cb = call_hvc_arch_workaround_1;
 214                 /* This is a guest, no need to patch KVM vectors */
 215                 smccc_start = NULL;
 216                 smccc_end = NULL;
 217                 break;
 218
 219         case PSCI_CONDUIT_SMC:
 220                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 221                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 222                 if ((int)res.a0 < 0)
 223                         return;
 224                 cb = call_smc_arch_workaround_1;
 225                 smccc_start = __smccc_workaround_1_smc_start;
 226                 smccc_end = __smccc_workaround_1_smc_end;
 227                 break;
 228
 229         default:
 230                 return;
 231         }
 232
 233         if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
 234             ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
 235                 cb = qcom_link_stack_sanitization;
 236
 237         install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
 238
 239         return;
 240 }
 241 #endif  /* CONFIG_HARDEN_BRANCH_PREDICTOR */
 242
 243 #ifdef CONFIG_ARM64_SSBD
 244 DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
 245
 246 int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
 247
 248 static const struct ssbd_options {
 249         const char      *str;
 250         int             state;
 251 } ssbd_options[] = {
 252         { "force-on",   ARM64_SSBD_FORCE_ENABLE, },
 253         { "force-off",  ARM64_SSBD_FORCE_DISABLE, },
 254         { "kernel",     ARM64_SSBD_KERNEL, },
 255 };
 256
 257 static int __init ssbd_cfg(char *buf)
 258 {
 259         int i;
 260
 261         if (!buf || !buf[0])
 262                 return -EINVAL;
 263
 264         for (i = 0; i < ARRAY_SIZE(ssbd_options); i++) {
 265                 int len = strlen(ssbd_options[i].str);
 266
 267                 if (strncmp(buf, ssbd_options[i].str, len))
 268                         continue;
 269
 270                 ssbd_state = ssbd_options[i].state;
 271                 return 0;
 272         }
 273
 274         return -EINVAL;
 275 }
 276 early_param("ssbd", ssbd_cfg);
 277
 278 void __init arm64_update_smccc_conduit(struct alt_instr *alt,
 279                                        __le32 *origptr, __le32 *updptr,
 280                                        int nr_inst)
 281 {
 282         u32 insn;
 283
 284         BUG_ON(nr_inst != 1);
 285
 286         switch (psci_ops.conduit) {
 287         case PSCI_CONDUIT_HVC:
 288                 insn = aarch64_insn_get_hvc_value();
 289                 break;
 290         case PSCI_CONDUIT_SMC:
 291                 insn = aarch64_insn_get_smc_value();
 292                 break;
 293         default:
 294                 return;
 295         }
 296
 297         *updptr = cpu_to_le32(insn);
 298 }
 299
 300 void __init arm64_enable_wa2_handling(struct alt_instr *alt,
 301                                       __le32 *origptr, __le32 *updptr,
 302                                       int nr_inst)
 303 {
 304         BUG_ON(nr_inst != 1);
 305         /*
 306          * Only allow mitigation on EL1 entry/exit and guest
 307          * ARCH_WORKAROUND_2 handling if the SSBD state allows it to
 308          * be flipped.
 309          */
 310         if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
 311                 *updptr = cpu_to_le32(aarch64_insn_gen_nop());
 312 }
 313
 314 void arm64_set_ssbd_mitigation(bool state)
 315 {
 316         switch (psci_ops.conduit) {
 317         case PSCI_CONDUIT_HVC:
 318                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
 319                 break;
 320
 321         case PSCI_CONDUIT_SMC:
 322                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
 323                 break;
 324
 325         default:
 326                 WARN_ON_ONCE(1);
 327                 break;
 328         }
 329 }
 330
 331 static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
 332                                     int scope)
 333 {
 334         struct arm_smccc_res res;
 335         bool required = true;
 336         s32 val;
 337
 338         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
 339
 340         if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
 341                 ssbd_state = ARM64_SSBD_UNKNOWN;
 342                 return false;
 343         }
 344
 345         switch (psci_ops.conduit) {
 346         case PSCI_CONDUIT_HVC:
 347                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 348                                   ARM_SMCCC_ARCH_WORKAROUND_2, &res);
 349                 break;
 350
 351         case PSCI_CONDUIT_SMC:
 352                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 353                                   ARM_SMCCC_ARCH_WORKAROUND_2, &res);
 354                 break;
 355
 356         default:
 357                 ssbd_state = ARM64_SSBD_UNKNOWN;
 358                 return false;
 359         }
 360
 361         val = (s32)res.a0;
 362
 363         switch (val) {
 364         case SMCCC_RET_NOT_SUPPORTED:
 365                 ssbd_state = ARM64_SSBD_UNKNOWN;
 366                 return false;
 367
 368         case SMCCC_RET_NOT_REQUIRED:
 369                 pr_info_once("%s mitigation not required\n", entry->desc);
 370                 ssbd_state = ARM64_SSBD_MITIGATED;
 371                 return false;
 372
 373         case SMCCC_RET_SUCCESS:
 374                 required = true;
 375                 break;
 376
 377         case 1: /* Mitigation not required on this CPU */
 378                 required = false;
 379                 break;
 380
 381         default:
 382                 WARN_ON(1);
 383                 return false;
 384         }
 385
 386         switch (ssbd_state) {
 387         case ARM64_SSBD_FORCE_DISABLE:
 388                 pr_info_once("%s disabled from command-line\n", entry->desc);
 389                 arm64_set_ssbd_mitigation(false);
 390                 required = false;
 391                 break;
 392
 393         case ARM64_SSBD_KERNEL:
 394                 if (required) {
 395                         __this_cpu_write(arm64_ssbd_callback_required, 1);
 396                         arm64_set_ssbd_mitigation(true);
 397                 }
 398                 break;
 399
 400         case ARM64_SSBD_FORCE_ENABLE:
 401                 pr_info_once("%s forced from command-line\n", entry->desc);
 402                 arm64_set_ssbd_mitigation(true);
 403                 required = true;
 404                 break;
 405
 406         default:
 407                 WARN_ON(1);
 408                 break;
 409         }
 410
 411         return required;
 412 }
 413 #endif  /* CONFIG_ARM64_SSBD */
 414
 415 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)       \
 416         .matches = is_affected_midr_range,                      \
 417         .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
 418
 419 #define CAP_MIDR_ALL_VERSIONS(model)                                    \
 420         .matches = is_affected_midr_range,                              \
 421         .midr_range = MIDR_ALL_VERSIONS(model)
 422
 423 #define MIDR_FIXED(rev, revidr_mask) \
 424         .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
 425
 426 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)            \
 427         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                         \
 428         CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
 429
 430 #define CAP_MIDR_RANGE_LIST(list)                               \
 431         .matches = is_affected_midr_range_list,                 \
 432         .midr_range_list = list
 433
 434 /* Errata affecting a range of revisions of  given model variant */
 435 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)      \
 436         ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
 437
 438 /* Errata affecting a single variant/revision of a model */
 439 #define ERRATA_MIDR_REV(model, var, rev)        \
 440         ERRATA_MIDR_RANGE(model, var, rev, var, rev)
 441
 442 /* Errata affecting all variants/revisions of a given a model */
 443 #define ERRATA_MIDR_ALL_VERSIONS(model)                         \
 444         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
 445         CAP_MIDR_ALL_VERSIONS(model)
 446
 447 /* Errata affecting a list of midr ranges, with same work around */
 448 #define ERRATA_MIDR_RANGE_LIST(midr_list)                       \
 449         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
 450         CAP_MIDR_RANGE_LIST(midr_list)
 451
 452 /*
 453  * Generic helper for handling capabilties with multiple (match,enable) pairs
 454  * of call backs, sharing the same capability bit.
 455  * Iterate over each entry to see if at least one matches.
 456  */
 457 static bool __maybe_unused
 458 multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
 459 {
 460         const struct arm64_cpu_capabilities *caps;
 461
 462         for (caps = entry->match_list; caps->matches; caps++)
 463                 if (caps->matches(caps, scope))
 464                         return true;
 465
 466         return false;
 467 }
 468
 469 /*
 470  * Take appropriate action for all matching entries in the shared capability
 471  * entry.
 472  */
 473 static void __maybe_unused
 474 multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
 475 {
 476         const struct arm64_cpu_capabilities *caps;
 477
 478         for (caps = entry->match_list; caps->matches; caps++)
 479                 if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
 480                     caps->cpu_enable)
 481                         caps->cpu_enable(caps);
 482 }
 483
 484 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 485
 486 /*
 487  * List of CPUs where we need to issue a psci call to
 488  * harden the branch predictor.
 489  */
 490 static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
 491         MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 492         MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 493         MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 494         MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
 495         MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 496         MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 497         MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
 498         MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
 499         MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
 500         {},
 501 };
 502
 503 #endif
 504
 505 #ifdef CONFIG_HARDEN_EL2_VECTORS
 506
 507 static const struct midr_range arm64_harden_el2_vectors[] = {
 508         MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 509         MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 510         {},
 511 };
 512
 513 #endif
 514
 515 const struct arm64_cpu_capabilities arm64_errata[] = {
 516 #if     defined(CONFIG_ARM64_ERRATUM_826319) || \
 517         defined(CONFIG_ARM64_ERRATUM_827319) || \
 518         defined(CONFIG_ARM64_ERRATUM_824069)
 519         {
 520         /* Cortex-A53 r0p[012] */
 521                 .desc = "ARM errata 826319, 827319, 824069",
 522                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
 523                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
 524                 .cpu_enable = cpu_enable_cache_maint_trap,
 525         },
 526 #endif
 527 #ifdef CONFIG_ARM64_ERRATUM_819472
 528         {
 529         /* Cortex-A53 r0p[01] */
 530                 .desc = "ARM errata 819472",
 531                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
 532                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
 533                 .cpu_enable = cpu_enable_cache_maint_trap,
 534         },
 535 #endif
 536 #ifdef CONFIG_ARM64_ERRATUM_832075
 537         {
 538         /* Cortex-A57 r0p0 - r1p2 */
 539                 .desc = "ARM erratum 832075",
 540                 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
 541                 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
 542                                   0, 0,
 543                                   1, 2),
 544         },
 545 #endif
 546 #ifdef CONFIG_ARM64_ERRATUM_834220
 547         {
 548         /* Cortex-A57 r0p0 - r1p2 */
 549                 .desc = "ARM erratum 834220",
 550                 .capability = ARM64_WORKAROUND_834220,
 551                 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
 552                                   0, 0,
 553                                   1, 2),
 554         },
 555 #endif
 556 #ifdef CONFIG_ARM64_ERRATUM_843419
 557         {
 558         /* Cortex-A53 r0p[01234] */
 559                 .desc = "ARM erratum 843419",
 560                 .capability = ARM64_WORKAROUND_843419,
 561                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
 562                 MIDR_FIXED(0x4, BIT(8)),
 563         },
 564 #endif
 565 #ifdef CONFIG_ARM64_ERRATUM_845719
 566         {
 567         /* Cortex-A53 r0p[01234] */
 568                 .desc = "ARM erratum 845719",
 569                 .capability = ARM64_WORKAROUND_845719,
 570                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
 571         },
 572 #endif
 573 #ifdef CONFIG_CAVIUM_ERRATUM_23154
 574         {
 575         /* Cavium ThunderX, pass 1.x */
 576                 .desc = "Cavium erratum 23154",
 577                 .capability = ARM64_WORKAROUND_CAVIUM_23154,
 578                 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
 579         },
 580 #endif
 581 #ifdef CONFIG_CAVIUM_ERRATUM_27456
 582         {
 583         /* Cavium ThunderX, T88 pass 1.x - 2.1 */
 584                 .desc = "Cavium erratum 27456",
 585                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 586                 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
 587                                   0, 0,
 588                                   1, 1),
 589         },
 590         {
 591         /* Cavium ThunderX, T81 pass 1.0 */
 592                 .desc = "Cavium erratum 27456",
 593                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 594                 ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
 595         },
 596 #endif
 597 #ifdef CONFIG_CAVIUM_ERRATUM_30115
 598         {
 599         /* Cavium ThunderX, T88 pass 1.x - 2.2 */
 600                 .desc = "Cavium erratum 30115",
 601                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 602                 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
 603                                       0, 0,
 604                                       1, 2),
 605         },
 606         {
 607         /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
 608                 .desc = "Cavium erratum 30115",
 609                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 610                 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
 611         },
 612         {
 613         /* Cavium ThunderX, T83 pass 1.0 */
 614                 .desc = "Cavium erratum 30115",
 615                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 616                 ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
 617         },
 618 #endif
 619         {
 620                 .desc = "Mismatched cache line size",
 621                 .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
 622                 .matches = has_mismatched_cache_type,
 623                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 624                 .cpu_enable = cpu_enable_trap_ctr_access,
 625         },
 626         {
 627                 .desc = "Mismatched cache type",
 628                 .capability = ARM64_MISMATCHED_CACHE_TYPE,
 629                 .matches = has_mismatched_cache_type,
 630                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 631                 .cpu_enable = cpu_enable_trap_ctr_access,
 632         },
 633 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 634         {
 635                 .desc = "Qualcomm Technologies Falkor erratum 1003",
 636                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
 637                 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
 638         },
 639         {
 640                 .desc = "Qualcomm Technologies Kryo erratum 1003",
 641                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
 642                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 643                 .midr_range.model = MIDR_QCOM_KRYO,
 644                 .matches = is_kryo_midr,
 645         },
 646 #endif
 647 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
 648         {
 649                 .desc = "Qualcomm Technologies Falkor erratum 1009",
 650                 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
 651                 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
 652         },
 653 #endif
 654 #ifdef CONFIG_ARM64_ERRATUM_858921
 655         {
 656         /* Cortex-A73 all versions */
 657                 .desc = "ARM erratum 858921",
 658                 .capability = ARM64_WORKAROUND_858921,
 659                 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 660         },
 661 #endif
 662 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 663         {
 664                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 665                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 666                 .cpu_enable = enable_smccc_arch_workaround_1,
 667                 ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
 668         },
 669 #endif
 670 #ifdef CONFIG_HARDEN_EL2_VECTORS
 671         {
 672                 .desc = "EL2 vector hardening",
 673                 .capability = ARM64_HARDEN_EL2_VECTORS,
 674                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 675                 ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
 676         },
 677 #endif
 678 #ifdef CONFIG_ARM64_SSBD
 679         {
 680                 .desc = "Speculative Store Bypass Disable",
 681                 .capability = ARM64_SSBD,
 682                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 683                 .matches = has_ssbd_mitigation,
 684         },
 685 #endif
 686         {
 687         }
 688 };