arch/mips/loongson64/loongson-3/irq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <loongson.h>
   3 #include <irq.h>
   4 #include <linux/interrupt.h>
   5 #include <linux/init.h>
   6
   7 #include <asm/irq_cpu.h>
   8 #include <asm/i8259.h>
   9 #include <asm/mipsregs.h>
  10
  11 #include "smp.h"
  12
  13 extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
  14
  15 unsigned int irq_cpu[16] = {[0 ... 15] = -1};
  16 unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
  17 unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
  18
  19 int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
  20                           bool force)
  21 {
  22         unsigned int cpu;
  23         struct cpumask new_affinity;
  24
  25         /* I/O devices are connected on package-0 */
  26         cpumask_copy(&new_affinity, affinity);
  27         for_each_cpu(cpu, affinity)
  28                 if (cpu_data[cpu].package > 0)
  29                         cpumask_clear_cpu(cpu, &new_affinity);
  30
  31         if (cpumask_empty(&new_affinity))
  32                 return -EINVAL;
  33
  34         cpumask_copy(d->common->affinity, &new_affinity);
  35
  36         return IRQ_SET_MASK_OK_NOCOPY;
  37 }
  38
  39 static void ht_irqdispatch(void)
  40 {
  41         unsigned int i, irq;
  42         struct irq_data *irqd;
  43         struct cpumask affinity;
  44
  45         irq = LOONGSON_HT1_INT_VECTOR(0);
  46         LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
  47
  48         for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
  49                 if (!(irq & (0x1 << ht_irq[i])))
  50                         continue;
  51
  52                 /* handled by local core */
  53                 if (local_irq & (0x1 << ht_irq[i])) {
  54                         do_IRQ(ht_irq[i]);
  55                         continue;
  56                 }
  57
  58                 irqd = irq_get_irq_data(ht_irq[i]);
  59                 cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
  60                 if (cpumask_empty(&affinity)) {
  61                         do_IRQ(ht_irq[i]);
  62                         continue;
  63                 }
  64
  65                 irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
  66                 if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
  67                         irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
  68
  69                 if (irq_cpu[ht_irq[i]] == 0) {
  70                         do_IRQ(ht_irq[i]);
  71                         continue;
  72                 }
  73
  74                 /* balanced by other cores */
  75                 loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
  76         }
  77 }
  78
  79 #define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
  80
  81 void mach_irq_dispatch(unsigned int pending)
  82 {
  83         if (pending & CAUSEF_IP7)
  84                 do_IRQ(LOONGSON_TIMER_IRQ);
  85 #if defined(CONFIG_SMP)
  86         if (pending & CAUSEF_IP6)
  87                 loongson3_ipi_interrupt(NULL);
  88 #endif
  89         if (pending & CAUSEF_IP3)
  90                 ht_irqdispatch();
  91         if (pending & CAUSEF_IP2)
  92                 do_IRQ(LOONGSON_UART_IRQ);
  93         if (pending & UNUSED_IPS) {
  94                 pr_err("%s : spurious interrupt\n", __func__);
  95                 spurious_interrupt();
  96         }
  97 }
  98
  99 static struct irqaction cascade_irqaction = {
 100         .handler = no_action,
 101         .flags = IRQF_NO_SUSPEND,
 102         .name = "cascade",
 103 };
 104
 105 static inline void mask_loongson_irq(struct irq_data *d)
 106 {
 107         clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
 108         irq_disable_hazard();
 109
 110         /* Workaround: UART IRQ may deliver to any core */
 111         if (d->irq == LOONGSON_UART_IRQ) {
 112                 int cpu = smp_processor_id();
 113                 int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
 114                 int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
 115                 u64 intenclr_addr = smp_group[node_id] |
 116                         (u64)(&LOONGSON_INT_ROUTER_INTENCLR);
 117                 u64 introuter_lpc_addr = smp_group[node_id] |
 118                         (u64)(&LOONGSON_INT_ROUTER_LPC);
 119
 120                 *(volatile u32 *)intenclr_addr = 1 << 10;
 121                 *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
 122         }
 123 }
 124
 125 static inline void unmask_loongson_irq(struct irq_data *d)
 126 {
 127         /* Workaround: UART IRQ may deliver to any core */
 128         if (d->irq == LOONGSON_UART_IRQ) {
 129                 int cpu = smp_processor_id();
 130                 int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
 131                 int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
 132                 u64 intenset_addr = smp_group[node_id] |
 133                         (u64)(&LOONGSON_INT_ROUTER_INTENSET);
 134                 u64 introuter_lpc_addr = smp_group[node_id] |
 135                         (u64)(&LOONGSON_INT_ROUTER_LPC);
 136
 137                 *(volatile u32 *)intenset_addr = 1 << 10;
 138                 *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
 139         }
 140
 141         set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
 142         irq_enable_hazard();
 143 }
 144
 145  /* For MIPS IRQs which shared by all cores */
 146 static struct irq_chip loongson_irq_chip = {
 147         .name           = "Loongson",
 148         .irq_ack        = mask_loongson_irq,
 149         .irq_mask       = mask_loongson_irq,
 150         .irq_mask_ack   = mask_loongson_irq,
 151         .irq_unmask     = unmask_loongson_irq,
 152         .irq_eoi        = unmask_loongson_irq,
 153 };
 154
 155 void irq_router_init(void)
 156 {
 157         int i;
 158
 159         /* route LPC int to cpu core0 int 0 */
 160         LOONGSON_INT_ROUTER_LPC =
 161                 LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
 162         /* route HT1 int0 ~ int7 to cpu core0 INT1*/
 163         for (i = 0; i < 8; i++)
 164                 LOONGSON_INT_ROUTER_HT1(i) =
 165                         LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
 166         /* enable HT1 interrupt */
 167         LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
 168         /* enable router interrupt intenset */
 169         LOONGSON_INT_ROUTER_INTENSET =
 170                 LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
 171 }
 172
 173 void __init mach_init_irq(void)
 174 {
 175         struct irq_chip *chip;
 176
 177         clear_c0_status(ST0_IM | ST0_BEV);
 178
 179         irq_router_init();
 180         mips_cpu_irq_init();
 181         init_i8259_irqs();
 182         chip = irq_get_chip(I8259A_IRQ_BASE);
 183         chip->irq_set_affinity = plat_set_irq_affinity;
 184
 185         irq_set_chip_and_handler(LOONGSON_UART_IRQ,
 186                         &loongson_irq_chip, handle_level_irq);
 187
 188         /* setup HT1 irq */
 189         setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
 190
 191         set_c0_status(STATUSF_IP2 | STATUSF_IP6);
 192 }
 193
 194 #ifdef CONFIG_HOTPLUG_CPU
 195
 196 void fixup_irqs(void)
 197 {
 198         irq_cpu_offline();
 199         clear_c0_status(ST0_IM);
 200 }
 201
 202 #endif