arch/riscv/kernel/perf_event.c

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   4  * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   5  * Copyright (C) 2009 Jaswinder Singh Rajput
   6  * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   7  * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
   8  * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
   9  * Copyright (C) 2009 Google, Inc., Stephane Eranian
  10  * Copyright 2014 Tilera Corporation. All Rights Reserved.
  11  * Copyright (C) 2018 Andes Technology Corporation
  12  *
  13  * Perf_events support for RISC-V platforms.
  14  *
  15  * Since the spec. (as of now, Priv-Spec 1.10) does not provide enough
  16  * functionality for perf event to fully work, this file provides
  17  * the very basic framework only.
  18  *
  19  * For platform portings, please check Documentations/riscv/pmu.txt.
  20  *
  21  * The Copyright line includes x86 and tile ones.
  22  */
  23
  24 #include <linux/kprobes.h>
  25 #include <linux/kernel.h>
  26 #include <linux/kdebug.h>
  27 #include <linux/mutex.h>
  28 #include <linux/bitmap.h>
  29 #include <linux/irq.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/perf_event.h>
  32 #include <linux/atomic.h>
  33 #include <linux/of.h>
  34 #include <asm/perf_event.h>
  35
  36 static const struct riscv_pmu *riscv_pmu __read_mostly;
  37 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
  38
  39 /*
  40  * Hardware & cache maps and their methods
  41  */
  42
  43 static const int riscv_hw_event_map[] = {
  44         [PERF_COUNT_HW_CPU_CYCLES]              = RISCV_PMU_CYCLE,
  45         [PERF_COUNT_HW_INSTRUCTIONS]            = RISCV_PMU_INSTRET,
  46         [PERF_COUNT_HW_CACHE_REFERENCES]        = RISCV_OP_UNSUPP,
  47         [PERF_COUNT_HW_CACHE_MISSES]            = RISCV_OP_UNSUPP,
  48         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = RISCV_OP_UNSUPP,
  49         [PERF_COUNT_HW_BRANCH_MISSES]           = RISCV_OP_UNSUPP,
  50         [PERF_COUNT_HW_BUS_CYCLES]              = RISCV_OP_UNSUPP,
  51 };
  52
  53 #define C(x) PERF_COUNT_HW_CACHE_##x
  54 static const int riscv_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
  55 [PERF_COUNT_HW_CACHE_OP_MAX]
  56 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  57         [C(L1D)] = {
  58                 [C(OP_READ)] = {
  59                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
  60                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
  61                 },
  62                 [C(OP_WRITE)] = {
  63                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
  64                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
  65                 },
  66                 [C(OP_PREFETCH)] = {
  67                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
  68                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
  69                 },
  70         },
  71         [C(L1I)] = {
  72                 [C(OP_READ)] = {
  73                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
  74                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
  75                 },
  76                 [C(OP_WRITE)] = {
  77                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
  78                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
  79                 },
  80                 [C(OP_PREFETCH)] = {
  81                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
  82                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
  83                 },
  84         },
  85         [C(LL)] = {
  86                 [C(OP_READ)] = {
  87                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
  88                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
  89                 },
  90                 [C(OP_WRITE)] = {
  91                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
  92                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
  93                 },
  94                 [C(OP_PREFETCH)] = {
  95                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
  96                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
  97                 },
  98         },
  99         [C(DTLB)] = {
 100                 [C(OP_READ)] = {
 101                         [C(RESULT_ACCESS)] =  RISCV_OP_UNSUPP,
 102                         [C(RESULT_MISS)] =  RISCV_OP_UNSUPP,
 103                 },
 104                 [C(OP_WRITE)] = {
 105                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
 106                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
 107                 },
 108                 [C(OP_PREFETCH)] = {
 109                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
 110                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
 111                 },
 112         },
 113         [C(ITLB)] = {
 114                 [C(OP_READ)] = {
 115                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
 116                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
 117                 },
 118                 [C(OP_WRITE)] = {
 119                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
 120                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
 121                 },
 122                 [C(OP_PREFETCH)] = {
 123                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
 124                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
 125                 },
 126         },
 127         [C(BPU)] = {
 128                 [C(OP_READ)] = {
 129                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
 130                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
 131                 },
 132                 [C(OP_WRITE)] = {
 133                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
 134                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
 135                 },
 136                 [C(OP_PREFETCH)] = {
 137                         [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
 138                         [C(RESULT_MISS)] = RISCV_OP_UNSUPP,
 139                 },
 140         },
 141 };
 142
 143 static int riscv_map_hw_event(u64 config)
 144 {
 145         if (config >= riscv_pmu->max_events)
 146                 return -EINVAL;
 147
 148         return riscv_pmu->hw_events[config];
 149 }
 150
 151 int riscv_map_cache_decode(u64 config, unsigned int *type,
 152                            unsigned int *op, unsigned int *result)
 153 {
 154         return -ENOENT;
 155 }
 156
 157 static int riscv_map_cache_event(u64 config)
 158 {
 159         unsigned int type, op, result;
 160         int err = -ENOENT;
 161                 int code;
 162
 163         err = riscv_map_cache_decode(config, &type, &op, &result);
 164         if (!riscv_pmu->cache_events || err)
 165                 return err;
 166
 167         if (type >= PERF_COUNT_HW_CACHE_MAX ||
 168             op >= PERF_COUNT_HW_CACHE_OP_MAX ||
 169             result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 170                 return -EINVAL;
 171
 172         code = (*riscv_pmu->cache_events)[type][op][result];
 173         if (code == RISCV_OP_UNSUPP)
 174                 return -EINVAL;
 175
 176         return code;
 177 }
 178
 179 /*
 180  * Low-level functions: reading/writing counters
 181  */
 182
 183 static inline u64 read_counter(int idx)
 184 {
 185         u64 val = 0;
 186
 187         switch (idx) {
 188         case RISCV_PMU_CYCLE:
 189                 val = csr_read(cycle);
 190                 break;
 191         case RISCV_PMU_INSTRET:
 192                 val = csr_read(instret);
 193                 break;
 194         default:
 195                 WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS);
 196                 return -EINVAL;
 197         }
 198
 199         return val;
 200 }
 201
 202 static inline void write_counter(int idx, u64 value)
 203 {
 204         /* currently not supported */
 205         WARN_ON_ONCE(1);
 206 }
 207
 208 /*
 209  * pmu->read: read and update the counter
 210  *
 211  * Other architectures' implementation often have a xxx_perf_event_update
 212  * routine, which can return counter values when called in the IRQ, but
 213  * return void when being called by the pmu->read method.
 214  */
 215 static void riscv_pmu_read(struct perf_event *event)
 216 {
 217         struct hw_perf_event *hwc = &event->hw;
 218         u64 prev_raw_count, new_raw_count;
 219         u64 oldval;
 220         int idx = hwc->idx;
 221         u64 delta;
 222
 223         do {
 224                 prev_raw_count = local64_read(&hwc->prev_count);
 225                 new_raw_count = read_counter(idx);
 226
 227                 oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 228                                          new_raw_count);
 229         } while (oldval != prev_raw_count);
 230
 231         /*
 232          * delta is the value to update the counter we maintain in the kernel.
 233          */
 234         delta = (new_raw_count - prev_raw_count) &
 235                 ((1ULL << riscv_pmu->counter_width) - 1);
 236         local64_add(delta, &event->count);
 237         /*
 238          * Something like local64_sub(delta, &hwc->period_left) here is
 239          * needed if there is an interrupt for perf.
 240          */
 241 }
 242
 243 /*
 244  * State transition functions:
 245  *
 246  * stop()/start() & add()/del()
 247  */
 248
 249 /*
 250  * pmu->stop: stop the counter
 251  */
 252 static void riscv_pmu_stop(struct perf_event *event, int flags)
 253 {
 254         struct hw_perf_event *hwc = &event->hw;
 255
 256         WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
 257         hwc->state |= PERF_HES_STOPPED;
 258
 259         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
 260                 riscv_pmu->pmu->read(event);
 261                 hwc->state |= PERF_HES_UPTODATE;
 262         }
 263 }
 264
 265 /*
 266  * pmu->start: start the event.
 267  */
 268 static void riscv_pmu_start(struct perf_event *event, int flags)
 269 {
 270         struct hw_perf_event *hwc = &event->hw;
 271
 272         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
 273                 return;
 274
 275         if (flags & PERF_EF_RELOAD) {
 276                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
 277
 278                 /*
 279                  * Set the counter to the period to the next interrupt here,
 280                  * if you have any.
 281                  */
 282         }
 283
 284         hwc->state = 0;
 285         perf_event_update_userpage(event);
 286
 287         /*
 288          * Since we cannot write to counters, this serves as an initialization
 289          * to the delta-mechanism in pmu->read(); otherwise, the delta would be
 290          * wrong when pmu->read is called for the first time.
 291          */
 292         local64_set(&hwc->prev_count, read_counter(hwc->idx));
 293 }
 294
 295 /*
 296  * pmu->add: add the event to PMU.
 297  */
 298 static int riscv_pmu_add(struct perf_event *event, int flags)
 299 {
 300         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 301         struct hw_perf_event *hwc = &event->hw;
 302
 303         if (cpuc->n_events == riscv_pmu->num_counters)
 304                 return -ENOSPC;
 305
 306         /*
 307          * We don't have general conunters, so no binding-event-to-counter
 308          * process here.
 309          *
 310          * Indexing using hwc->config generally not works, since config may
 311          * contain extra information, but here the only info we have in
 312          * hwc->config is the event index.
 313          */
 314         hwc->idx = hwc->config;
 315         cpuc->events[hwc->idx] = event;
 316         cpuc->n_events++;
 317
 318         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 319
 320         if (flags & PERF_EF_START)
 321                 riscv_pmu->pmu->start(event, PERF_EF_RELOAD);
 322
 323         return 0;
 324 }
 325
 326 /*
 327  * pmu->del: delete the event from PMU.
 328  */
 329 static void riscv_pmu_del(struct perf_event *event, int flags)
 330 {
 331         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 332         struct hw_perf_event *hwc = &event->hw;
 333
 334         cpuc->events[hwc->idx] = NULL;
 335         cpuc->n_events--;
 336         riscv_pmu->pmu->stop(event, PERF_EF_UPDATE);
 337         perf_event_update_userpage(event);
 338 }
 339
 340 /*
 341  * Interrupt: a skeletion for reference.
 342  */
 343
 344 static DEFINE_MUTEX(pmc_reserve_mutex);
 345
 346 irqreturn_t riscv_base_pmu_handle_irq(int irq_num, void *dev)
 347 {
 348         return IRQ_NONE;
 349 }
 350
 351 static int reserve_pmc_hardware(void)
 352 {
 353         int err = 0;
 354
 355         mutex_lock(&pmc_reserve_mutex);
 356         if (riscv_pmu->irq >= 0 && riscv_pmu->handle_irq) {
 357                 err = request_irq(riscv_pmu->irq, riscv_pmu->handle_irq,
 358                                   IRQF_PERCPU, "riscv-base-perf", NULL);
 359         }
 360         mutex_unlock(&pmc_reserve_mutex);
 361
 362         return err;
 363 }
 364
 365 void release_pmc_hardware(void)
 366 {
 367         mutex_lock(&pmc_reserve_mutex);
 368         if (riscv_pmu->irq >= 0)
 369                 free_irq(riscv_pmu->irq, NULL);
 370         mutex_unlock(&pmc_reserve_mutex);
 371 }
 372
 373 /*
 374  * Event Initialization/Finalization
 375  */
 376
 377 static atomic_t riscv_active_events = ATOMIC_INIT(0);
 378
 379 static void riscv_event_destroy(struct perf_event *event)
 380 {
 381         if (atomic_dec_return(&riscv_active_events) == 0)
 382                 release_pmc_hardware();
 383 }
 384
 385 static int riscv_event_init(struct perf_event *event)
 386 {
 387         struct perf_event_attr *attr = &event->attr;
 388         struct hw_perf_event *hwc = &event->hw;
 389         int err;
 390         int code;
 391
 392         if (atomic_inc_return(&riscv_active_events) == 1) {
 393                 err = reserve_pmc_hardware();
 394
 395                 if (err) {
 396                         pr_warn("PMC hardware not available\n");
 397                         atomic_dec(&riscv_active_events);
 398                         return -EBUSY;
 399                 }
 400         }
 401
 402         switch (event->attr.type) {
 403         case PERF_TYPE_HARDWARE:
 404                 code = riscv_pmu->map_hw_event(attr->config);
 405                 break;
 406         case PERF_TYPE_HW_CACHE:
 407                 code = riscv_pmu->map_cache_event(attr->config);
 408                 break;
 409         case PERF_TYPE_RAW:
 410                 return -EOPNOTSUPP;
 411         default:
 412                 return -ENOENT;
 413         }
 414
 415         event->destroy = riscv_event_destroy;
 416         if (code < 0) {
 417                 event->destroy(event);
 418                 return code;
 419         }
 420
 421         /*
 422          * idx is set to -1 because the index of a general event should not be
 423          * decided until binding to some counter in pmu->add().
 424          *
 425          * But since we don't have such support, later in pmu->add(), we just
 426          * use hwc->config as the index instead.
 427          */
 428         hwc->config = code;
 429         hwc->idx = -1;
 430
 431         return 0;
 432 }
 433
 434 /*
 435  * Initialization
 436  */
 437
 438 static struct pmu min_pmu = {
 439         .name           = "riscv-base",
 440         .event_init     = riscv_event_init,
 441         .add            = riscv_pmu_add,
 442         .del            = riscv_pmu_del,
 443         .start          = riscv_pmu_start,
 444         .stop           = riscv_pmu_stop,
 445         .read           = riscv_pmu_read,
 446 };
 447
 448 static const struct riscv_pmu riscv_base_pmu = {
 449         .pmu = &min_pmu,
 450         .max_events = ARRAY_SIZE(riscv_hw_event_map),
 451         .map_hw_event = riscv_map_hw_event,
 452         .hw_events = riscv_hw_event_map,
 453         .map_cache_event = riscv_map_cache_event,
 454         .cache_events = &riscv_cache_event_map,
 455         .counter_width = 63,
 456         .num_counters = RISCV_BASE_COUNTERS + 0,
 457         .handle_irq = &riscv_base_pmu_handle_irq,
 458
 459         /* This means this PMU has no IRQ. */
 460         .irq = -1,
 461 };
 462
 463 static const struct of_device_id riscv_pmu_of_ids[] = {
 464         {.compatible = "riscv,base-pmu",        .data = &riscv_base_pmu},
 465         { /* sentinel value */ }
 466 };
 467
 468 int __init init_hw_perf_events(void)
 469 {
 470         struct device_node *node = of_find_node_by_type(NULL, "pmu");
 471         const struct of_device_id *of_id;
 472
 473         riscv_pmu = &riscv_base_pmu;
 474
 475         if (node) {
 476                 of_id = of_match_node(riscv_pmu_of_ids, node);
 477
 478                 if (of_id)
 479                         riscv_pmu = of_id->data;
 480         }
 481
 482         perf_pmu_register(riscv_pmu->pmu, "cpu", PERF_TYPE_RAW);
 483         return 0;
 484 }
 485 arch_initcall(init_hw_perf_events);