Linux 4.18.10
[linux/fpc-iii.git] / arch / unicore32 / include / mach / regs-nand.h
blob7f29939251effe777f15134704a5004de9f1a5a2
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * PKUnity NAND Controller Registers
4 */
5 /*
6 * ID Reg. 0 NAND_IDR0
7 */
8 #define NAND_IDR0 (PKUNITY_NAND_BASE + 0x0000)
9 /*
10 * ID Reg. 1 NAND_IDR1
12 #define NAND_IDR1 (PKUNITY_NAND_BASE + 0x0004)
14 * ID Reg. 2 NAND_IDR2
16 #define NAND_IDR2 (PKUNITY_NAND_BASE + 0x0008)
18 * ID Reg. 3 NAND_IDR3
20 #define NAND_IDR3 (PKUNITY_NAND_BASE + 0x000C)
22 * Page Address Reg 0 NAND_PAR0
24 #define NAND_PAR0 (PKUNITY_NAND_BASE + 0x0010)
26 * Page Address Reg 1 NAND_PAR1
28 #define NAND_PAR1 (PKUNITY_NAND_BASE + 0x0014)
30 * Page Address Reg 2 NAND_PAR2
32 #define NAND_PAR2 (PKUNITY_NAND_BASE + 0x0018)
34 * ECC Enable Reg NAND_ECCEN
36 #define NAND_ECCEN (PKUNITY_NAND_BASE + 0x001C)
38 * Buffer Reg NAND_BUF
40 #define NAND_BUF (PKUNITY_NAND_BASE + 0x0020)
42 * ECC Status Reg NAND_ECCSR
44 #define NAND_ECCSR (PKUNITY_NAND_BASE + 0x0024)
46 * Command Reg NAND_CMD
48 #define NAND_CMD (PKUNITY_NAND_BASE + 0x0028)
50 * DMA Configure Reg NAND_DMACR
52 #define NAND_DMACR (PKUNITY_NAND_BASE + 0x002C)
54 * Interrupt Reg NAND_IR
56 #define NAND_IR (PKUNITY_NAND_BASE + 0x0030)
58 * Interrupt Mask Reg NAND_IMR
60 #define NAND_IMR (PKUNITY_NAND_BASE + 0x0034)
62 * Chip Enable Reg NAND_CHIPEN
64 #define NAND_CHIPEN (PKUNITY_NAND_BASE + 0x0038)
66 * Address Reg NAND_ADDR
68 #define NAND_ADDR (PKUNITY_NAND_BASE + 0x003C)
71 * Command bits NAND_CMD_CMD_MASK
73 #define NAND_CMD_CMD_MASK FMASK(4, 4)
74 #define NAND_CMD_CMD_READPAGE FIELD(0x0, 4, 4)
75 #define NAND_CMD_CMD_ERASEBLOCK FIELD(0x6, 4, 4)
76 #define NAND_CMD_CMD_READSTATUS FIELD(0x7, 4, 4)
77 #define NAND_CMD_CMD_WRITEPAGE FIELD(0x8, 4, 4)
78 #define NAND_CMD_CMD_READID FIELD(0x9, 4, 4)
79 #define NAND_CMD_CMD_RESET FIELD(0xf, 4, 4)