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Linux 4.18.10
[linux/fpc-iii.git] / drivers / ata / sata_rcar.c
blob6456e07db72a7ea4e5cf2bcb1110dec9db42e946
1 /*
2 * Renesas R-Car SATA driver
3 *
4 * Author: Vladimir Barinov <source@cogentembedded.com>
5 * Copyright (C) 2013-2015 Cogent Embedded, Inc.
6 * Copyright (C) 2013-2015 Renesas Solutions Corp.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/ata.h>
17 #include <linux/libata.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
21 #include <linux/err.h>
22
23 #define DRV_NAME "sata_rcar"
24
25 /* SH-Navi2G/ATAPI-ATA compatible task registers */
26 #define DATA_REG 0x100
27 #define SDEVCON_REG 0x138
28
29 /* SH-Navi2G/ATAPI module compatible control registers */
30 #define ATAPI_CONTROL1_REG 0x180
31 #define ATAPI_STATUS_REG 0x184
32 #define ATAPI_INT_ENABLE_REG 0x188
33 #define ATAPI_DTB_ADR_REG 0x198
34 #define ATAPI_DMA_START_ADR_REG 0x19C
35 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0
36 #define ATAPI_CONTROL2_REG 0x1A4
37 #define ATAPI_SIG_ST_REG 0x1B0
38 #define ATAPI_BYTE_SWAP_REG 0x1BC
39
40 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */
41 #define ATAPI_CONTROL1_ISM BIT(16)
42 #define ATAPI_CONTROL1_DTA32M BIT(11)
43 #define ATAPI_CONTROL1_RESET BIT(7)
44 #define ATAPI_CONTROL1_DESE BIT(3)
45 #define ATAPI_CONTROL1_RW BIT(2)
46 #define ATAPI_CONTROL1_STOP BIT(1)
47 #define ATAPI_CONTROL1_START BIT(0)
48
49 /* ATAPI status register (ATAPI_STATUS) bits */
50 #define ATAPI_STATUS_SATAINT BIT(11)
51 #define ATAPI_STATUS_DNEND BIT(6)
52 #define ATAPI_STATUS_DEVTRM BIT(5)
53 #define ATAPI_STATUS_DEVINT BIT(4)
54 #define ATAPI_STATUS_ERR BIT(2)
55 #define ATAPI_STATUS_NEND BIT(1)
56 #define ATAPI_STATUS_ACT BIT(0)
57
58 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */
59 #define ATAPI_INT_ENABLE_SATAINT BIT(11)
60 #define ATAPI_INT_ENABLE_DNEND BIT(6)
61 #define ATAPI_INT_ENABLE_DEVTRM BIT(5)
62 #define ATAPI_INT_ENABLE_DEVINT BIT(4)
63 #define ATAPI_INT_ENABLE_ERR BIT(2)
64 #define ATAPI_INT_ENABLE_NEND BIT(1)
65 #define ATAPI_INT_ENABLE_ACT BIT(0)
66
67 /* Access control registers for physical layer control register */
68 #define SATAPHYADDR_REG 0x200
69 #define SATAPHYWDATA_REG 0x204
70 #define SATAPHYACCEN_REG 0x208
71 #define SATAPHYRESET_REG 0x20C
72 #define SATAPHYRDATA_REG 0x210
73 #define SATAPHYACK_REG 0x214
74
75 /* Physical layer control address command register (SATAPHYADDR) bits */
76 #define SATAPHYADDR_PHYRATEMODE BIT(10)
77 #define SATAPHYADDR_PHYCMD_READ BIT(9)
78 #define SATAPHYADDR_PHYCMD_WRITE BIT(8)
79
80 /* Physical layer control enable register (SATAPHYACCEN) bits */
81 #define SATAPHYACCEN_PHYLANE BIT(0)
82
83 /* Physical layer control reset register (SATAPHYRESET) bits */
84 #define SATAPHYRESET_PHYRST BIT(1)
85 #define SATAPHYRESET_PHYSRES BIT(0)
86
87 /* Physical layer control acknowledge register (SATAPHYACK) bits */
88 #define SATAPHYACK_PHYACK BIT(0)
89
90 /* Serial-ATA HOST control registers */
91 #define BISTCONF_REG 0x102C
92 #define SDATA_REG 0x1100
93 #define SSDEVCON_REG 0x1204
94
95 #define SCRSSTS_REG 0x1400
96 #define SCRSERR_REG 0x1404
97 #define SCRSCON_REG 0x1408
98 #define SCRSACT_REG 0x140C
99
100 #define SATAINTSTAT_REG 0x1508
101 #define SATAINTMASK_REG 0x150C
102
103 /* SATA INT status register (SATAINTSTAT) bits */
104 #define SATAINTSTAT_SERR BIT(3)
105 #define SATAINTSTAT_ATA BIT(0)
106
107 /* SATA INT mask register (SATAINTSTAT) bits */
108 #define SATAINTMASK_SERRMSK BIT(3)
109 #define SATAINTMASK_ERRMSK BIT(2)
110 #define SATAINTMASK_ERRCRTMSK BIT(1)
111 #define SATAINTMASK_ATAMSK BIT(0)
112
113 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \
114 SATAINTMASK_ATAMSK)
115
116 /* Physical Layer Control Registers */
117 #define SATAPCTLR1_REG 0x43
118 #define SATAPCTLR2_REG 0x52
119 #define SATAPCTLR3_REG 0x5A
120 #define SATAPCTLR4_REG 0x60
121
122 /* Descriptor table word 0 bit (when DTA32M = 1) */
123 #define SATA_RCAR_DTEND BIT(0)
124
125 #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
126
127 /* Gen2 Physical Layer Control Registers */
128 #define RCAR_GEN2_PHY_CTL1_REG 0x1704
129 #define RCAR_GEN2_PHY_CTL1 0x34180002
130 #define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */
131
132 #define RCAR_GEN2_PHY_CTL2_REG 0x170C
133 #define RCAR_GEN2_PHY_CTL2 0x00002303
134
135 #define RCAR_GEN2_PHY_CTL3_REG 0x171C
136 #define RCAR_GEN2_PHY_CTL3 0x000B0194
137
138 #define RCAR_GEN2_PHY_CTL4_REG 0x1724
139 #define RCAR_GEN2_PHY_CTL4 0x00030994
140
141 #define RCAR_GEN2_PHY_CTL5_REG 0x1740
142 #define RCAR_GEN2_PHY_CTL5 0x03004001
143 #define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */
144 #define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */
145
146 enum sata_rcar_type {
147 RCAR_GEN1_SATA,
148 RCAR_GEN2_SATA,
149 RCAR_GEN3_SATA,
150 RCAR_R8A7790_ES1_SATA,
151 };
152
153 struct sata_rcar_priv {
154 void __iomem *base;
155 struct clk *clk;
156 enum sata_rcar_type type;
157 };
158
159 static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv)
160 {
161 void __iomem *base = priv->base;
162
163 /* idle state */
164 iowrite32(0, base + SATAPHYADDR_REG);
165 /* reset */
166 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
167 udelay(10);
168 /* deassert reset */
169 iowrite32(0, base + SATAPHYRESET_REG);
170 }
171
172 static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg,
173 u32 val, int group)
174 {
175 void __iomem *base = priv->base;
176 int timeout;
177
178 /* deassert reset */
179 iowrite32(0, base + SATAPHYRESET_REG);
180 /* lane 1 */
181 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
182 /* write phy register value */
183 iowrite32(val, base + SATAPHYWDATA_REG);
184 /* set register group */
185 if (group)
186 reg |= SATAPHYADDR_PHYRATEMODE;
187 /* write command */
188 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
189 /* wait for ack */
190 for (timeout = 0; timeout < 100; timeout++) {
191 val = ioread32(base + SATAPHYACK_REG);
192 if (val & SATAPHYACK_PHYACK)
193 break;
194 }
195 if (timeout >= 100)
196 pr_err("%s timeout\n", __func__);
197 /* idle state */
198 iowrite32(0, base + SATAPHYADDR_REG);
199 }
200
201 static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv)
202 {
203 sata_rcar_gen1_phy_preinit(priv);
204 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
205 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
206 sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
207 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
208 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
209 sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
210 }
211
212 static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv)
213 {
214 void __iomem *base = priv->base;
215
216 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
217 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
218 iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
219 iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
220 iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC |
221 RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG);
222 }
223
224 static void sata_rcar_freeze(struct ata_port *ap)
225 {
226 struct sata_rcar_priv *priv = ap->host->private_data;
227
228 /* mask */
229 iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
230
231 ata_sff_freeze(ap);
232 }
233
234 static void sata_rcar_thaw(struct ata_port *ap)
235 {
236 struct sata_rcar_priv *priv = ap->host->private_data;
237 void __iomem *base = priv->base;
238
239 /* ack */
240 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
241
242 ata_sff_thaw(ap);
243
244 /* unmask */
245 iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
246 }
247
248 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
249 {
250 u16 *ptr = buffer;
251
252 while (count--) {
253 u16 data = ioread32(reg);
254
255 *ptr++ = data;
256 }
257 }
258
259 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
260 {
261 const u16 *ptr = buffer;
262
263 while (count--)
264 iowrite32(*ptr++, reg);
265 }
266
267 static u8 sata_rcar_check_status(struct ata_port *ap)
268 {
269 return ioread32(ap->ioaddr.status_addr);
270 }
271
272 static u8 sata_rcar_check_altstatus(struct ata_port *ap)
273 {
274 return ioread32(ap->ioaddr.altstatus_addr);
275 }
276
277 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
278 {
279 iowrite32(ctl, ap->ioaddr.ctl_addr);
280 }
281
282 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
283 {
284 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
285 ata_sff_pause(ap); /* needed; also flushes, for mmio */
286 }
287
288 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
289 unsigned int device)
290 {
291 struct ata_ioports *ioaddr = &ap->ioaddr;
292 u8 nsect, lbal;
293
294 sata_rcar_dev_select(ap, device);
295
296 iowrite32(0x55, ioaddr->nsect_addr);
297 iowrite32(0xaa, ioaddr->lbal_addr);
298
299 iowrite32(0xaa, ioaddr->nsect_addr);
300 iowrite32(0x55, ioaddr->lbal_addr);
301
302 iowrite32(0x55, ioaddr->nsect_addr);
303 iowrite32(0xaa, ioaddr->lbal_addr);
304
305 nsect = ioread32(ioaddr->nsect_addr);
306 lbal = ioread32(ioaddr->lbal_addr);
307
308 if (nsect == 0x55 && lbal == 0xaa)
309 return 1; /* found a device */
310
311 return 0; /* nothing found */
312 }
313
314 static int sata_rcar_wait_after_reset(struct ata_link *link,
315 unsigned long deadline)
316 {
317 struct ata_port *ap = link->ap;
318
319 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
320
321 return ata_sff_wait_ready(link, deadline);
322 }
323
324 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
325 {
326 struct ata_ioports *ioaddr = &ap->ioaddr;
327
328 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
329
330 /* software reset. causes dev0 to be selected */
331 iowrite32(ap->ctl, ioaddr->ctl_addr);
332 udelay(20);
333 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
334 udelay(20);
335 iowrite32(ap->ctl, ioaddr->ctl_addr);
336 ap->last_ctl = ap->ctl;
337
338 /* wait the port to become ready */
339 return sata_rcar_wait_after_reset(&ap->link, deadline);
340 }
341
342 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
343 unsigned long deadline)
344 {
345 struct ata_port *ap = link->ap;
346 unsigned int devmask = 0;
347 int rc;
348 u8 err;
349
350 /* determine if device 0 is present */
351 if (sata_rcar_ata_devchk(ap, 0))
352 devmask |= 1 << 0;
353
354 /* issue bus reset */
355 DPRINTK("about to softreset, devmask=%x\n", devmask);
356 rc = sata_rcar_bus_softreset(ap, deadline);
357 /* if link is occupied, -ENODEV too is an error */
358 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
359 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
360 return rc;
361 }
362
363 /* determine by signature whether we have ATA or ATAPI devices */
364 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
365
366 DPRINTK("classes[0]=%u\n", classes[0]);
367 return 0;
368 }
369
370 static void sata_rcar_tf_load(struct ata_port *ap,
371 const struct ata_taskfile *tf)
372 {
373 struct ata_ioports *ioaddr = &ap->ioaddr;
374 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
375
376 if (tf->ctl != ap->last_ctl) {
377 iowrite32(tf->ctl, ioaddr->ctl_addr);
378 ap->last_ctl = tf->ctl;
379 ata_wait_idle(ap);
380 }
381
382 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
383 iowrite32(tf->hob_feature, ioaddr->feature_addr);
384 iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
385 iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
386 iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
387 iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
388 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
389 tf->hob_feature,
390 tf->hob_nsect,
391 tf->hob_lbal,
392 tf->hob_lbam,
393 tf->hob_lbah);
394 }
395
396 if (is_addr) {
397 iowrite32(tf->feature, ioaddr->feature_addr);
398 iowrite32(tf->nsect, ioaddr->nsect_addr);
399 iowrite32(tf->lbal, ioaddr->lbal_addr);
400 iowrite32(tf->lbam, ioaddr->lbam_addr);
401 iowrite32(tf->lbah, ioaddr->lbah_addr);
402 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
403 tf->feature,
404 tf->nsect,
405 tf->lbal,
406 tf->lbam,
407 tf->lbah);
408 }
409
410 if (tf->flags & ATA_TFLAG_DEVICE) {
411 iowrite32(tf->device, ioaddr->device_addr);
412 VPRINTK("device 0x%X\n", tf->device);
413 }
414
415 ata_wait_idle(ap);
416 }
417
418 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
419 {
420 struct ata_ioports *ioaddr = &ap->ioaddr;
421
422 tf->command = sata_rcar_check_status(ap);
423 tf->feature = ioread32(ioaddr->error_addr);
424 tf->nsect = ioread32(ioaddr->nsect_addr);
425 tf->lbal = ioread32(ioaddr->lbal_addr);
426 tf->lbam = ioread32(ioaddr->lbam_addr);
427 tf->lbah = ioread32(ioaddr->lbah_addr);
428 tf->device = ioread32(ioaddr->device_addr);
429
430 if (tf->flags & ATA_TFLAG_LBA48) {
431 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
432 tf->hob_feature = ioread32(ioaddr->error_addr);
433 tf->hob_nsect = ioread32(ioaddr->nsect_addr);
434 tf->hob_lbal = ioread32(ioaddr->lbal_addr);
435 tf->hob_lbam = ioread32(ioaddr->lbam_addr);
436 tf->hob_lbah = ioread32(ioaddr->lbah_addr);
437 iowrite32(tf->ctl, ioaddr->ctl_addr);
438 ap->last_ctl = tf->ctl;
439 }
440 }
441
442 static void sata_rcar_exec_command(struct ata_port *ap,
443 const struct ata_taskfile *tf)
444 {
445 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
446
447 iowrite32(tf->command, ap->ioaddr.command_addr);
448 ata_sff_pause(ap);
449 }
450
451 static unsigned int sata_rcar_data_xfer(struct ata_queued_cmd *qc,
452 unsigned char *buf,
453 unsigned int buflen, int rw)
454 {
455 struct ata_port *ap = qc->dev->link->ap;
456 void __iomem *data_addr = ap->ioaddr.data_addr;
457 unsigned int words = buflen >> 1;
458
459 /* Transfer multiple of 2 bytes */
460 if (rw == READ)
461 sata_rcar_ioread16_rep(data_addr, buf, words);
462 else
463 sata_rcar_iowrite16_rep(data_addr, buf, words);
464
465 /* Transfer trailing byte, if any. */
466 if (unlikely(buflen & 0x01)) {
467 unsigned char pad[2] = { };
468
469 /* Point buf to the tail of buffer */
470 buf += buflen - 1;
471
472 /*
473 * Use io*16_rep() accessors here as well to avoid pointlessly
474 * swapping bytes to and from on the big endian machines...
475 */
476 if (rw == READ) {
477 sata_rcar_ioread16_rep(data_addr, pad, 1);
478 *buf = pad[0];
479 } else {
480 pad[0] = *buf;
481 sata_rcar_iowrite16_rep(data_addr, pad, 1);
482 }
483 words++;
484 }
485
486 return words << 1;
487 }
488
489 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
490 {
491 int count;
492 struct ata_port *ap;
493
494 /* We only need to flush incoming data when a command was running */
495 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
496 return;
497
498 ap = qc->ap;
499 /* Drain up to 64K of data before we give up this recovery method */
500 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
501 count < 65536; count += 2)
502 ioread32(ap->ioaddr.data_addr);
503
504 /* Can become DEBUG later */
505 if (count)
506 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
507 }
508
509 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
510 u32 *val)
511 {
512 if (sc_reg > SCR_ACTIVE)
513 return -EINVAL;
514
515 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
516 return 0;
517 }
518
519 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
520 u32 val)
521 {
522 if (sc_reg > SCR_ACTIVE)
523 return -EINVAL;
524
525 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
526 return 0;
527 }
528
529 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
530 {
531 struct ata_port *ap = qc->ap;
532 struct ata_bmdma_prd *prd = ap->bmdma_prd;
533 struct scatterlist *sg;
534 unsigned int si;
535
536 for_each_sg(qc->sg, sg, qc->n_elem, si) {
537 u32 addr, sg_len;
538
539 /*
540 * Note: h/w doesn't support 64-bit, so we unconditionally
541 * truncate dma_addr_t to u32.
542 */
543 addr = (u32)sg_dma_address(sg);
544 sg_len = sg_dma_len(sg);
545
546 prd[si].addr = cpu_to_le32(addr);
547 prd[si].flags_len = cpu_to_le32(sg_len);
548 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
549 }
550
551 /* end-of-table flag */
552 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
553 }
554
555 static void sata_rcar_qc_prep(struct ata_queued_cmd *qc)
556 {
557 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
558 return;
559
560 sata_rcar_bmdma_fill_sg(qc);
561 }
562
563 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
564 {
565 struct ata_port *ap = qc->ap;
566 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
567 struct sata_rcar_priv *priv = ap->host->private_data;
568 void __iomem *base = priv->base;
569 u32 dmactl;
570
571 /* load PRD table addr. */
572 mb(); /* make sure PRD table writes are visible to controller */
573 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
574
575 /* specify data direction, triple-check start bit is clear */
576 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
577 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
578 if (dmactl & ATAPI_CONTROL1_START) {
579 dmactl &= ~ATAPI_CONTROL1_START;
580 dmactl |= ATAPI_CONTROL1_STOP;
581 }
582 if (!rw)
583 dmactl |= ATAPI_CONTROL1_RW;
584 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
585
586 /* issue r/w command */
587 ap->ops->sff_exec_command(ap, &qc->tf);
588 }
589
590 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
591 {
592 struct ata_port *ap = qc->ap;
593 struct sata_rcar_priv *priv = ap->host->private_data;
594 void __iomem *base = priv->base;
595 u32 dmactl;
596
597 /* start host DMA transaction */
598 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
599 dmactl &= ~ATAPI_CONTROL1_STOP;
600 dmactl |= ATAPI_CONTROL1_START;
601 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
602 }
603
604 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
605 {
606 struct ata_port *ap = qc->ap;
607 struct sata_rcar_priv *priv = ap->host->private_data;
608 void __iomem *base = priv->base;
609 u32 dmactl;
610
611 /* force termination of DMA transfer if active */
612 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
613 if (dmactl & ATAPI_CONTROL1_START) {
614 dmactl &= ~ATAPI_CONTROL1_START;
615 dmactl |= ATAPI_CONTROL1_STOP;
616 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
617 }
618
619 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
620 ata_sff_dma_pause(ap);
621 }
622
623 static u8 sata_rcar_bmdma_status(struct ata_port *ap)
624 {
625 struct sata_rcar_priv *priv = ap->host->private_data;
626 u8 host_stat = 0;
627 u32 status;
628
629 status = ioread32(priv->base + ATAPI_STATUS_REG);
630 if (status & ATAPI_STATUS_DEVINT)
631 host_stat |= ATA_DMA_INTR;
632 if (status & ATAPI_STATUS_ACT)
633 host_stat |= ATA_DMA_ACTIVE;
634
635 return host_stat;
636 }
637
638 static struct scsi_host_template sata_rcar_sht = {
639 ATA_BASE_SHT(DRV_NAME),
640 /*
641 * This controller allows transfer chunks up to 512MB which cross 64KB
642 * boundaries, therefore the DMA limits are more relaxed than standard
643 * ATA SFF.
644 */
645 .sg_tablesize = ATA_MAX_PRD,
646 .dma_boundary = SATA_RCAR_DMA_BOUNDARY,
647 };
648
649 static struct ata_port_operations sata_rcar_port_ops = {
650 .inherits = &ata_bmdma_port_ops,
651
652 .freeze = sata_rcar_freeze,
653 .thaw = sata_rcar_thaw,
654 .softreset = sata_rcar_softreset,
655
656 .scr_read = sata_rcar_scr_read,
657 .scr_write = sata_rcar_scr_write,
658
659 .sff_dev_select = sata_rcar_dev_select,
660 .sff_set_devctl = sata_rcar_set_devctl,
661 .sff_check_status = sata_rcar_check_status,
662 .sff_check_altstatus = sata_rcar_check_altstatus,
663 .sff_tf_load = sata_rcar_tf_load,
664 .sff_tf_read = sata_rcar_tf_read,
665 .sff_exec_command = sata_rcar_exec_command,
666 .sff_data_xfer = sata_rcar_data_xfer,
667 .sff_drain_fifo = sata_rcar_drain_fifo,
668
669 .qc_prep = sata_rcar_qc_prep,
670
671 .bmdma_setup = sata_rcar_bmdma_setup,
672 .bmdma_start = sata_rcar_bmdma_start,
673 .bmdma_stop = sata_rcar_bmdma_stop,
674 .bmdma_status = sata_rcar_bmdma_status,
675 };
676
677 static void sata_rcar_serr_interrupt(struct ata_port *ap)
678 {
679 struct sata_rcar_priv *priv = ap->host->private_data;
680 struct ata_eh_info *ehi = &ap->link.eh_info;
681 int freeze = 0;
682 u32 serror;
683
684 serror = ioread32(priv->base + SCRSERR_REG);
685 if (!serror)
686 return;
687
688 DPRINTK("SError @host_intr: 0x%x\n", serror);
689
690 /* first, analyze and record host port events */
691 ata_ehi_clear_desc(ehi);
692
693 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
694 /* Setup a soft-reset EH action */
695 ata_ehi_hotplugged(ehi);
696 ata_ehi_push_desc(ehi, "%s", "hotplug");
697
698 freeze = serror & SERR_COMM_WAKE ? 0 : 1;
699 }
700
701 /* freeze or abort */
702 if (freeze)
703 ata_port_freeze(ap);
704 else
705 ata_port_abort(ap);
706 }
707
708 static void sata_rcar_ata_interrupt(struct ata_port *ap)
709 {
710 struct ata_queued_cmd *qc;
711 int handled = 0;
712
713 qc = ata_qc_from_tag(ap, ap->link.active_tag);
714 if (qc)
715 handled |= ata_bmdma_port_intr(ap, qc);
716
717 /* be sure to clear ATA interrupt */
718 if (!handled)
719 sata_rcar_check_status(ap);
720 }
721
722 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
723 {
724 struct ata_host *host = dev_instance;
725 struct sata_rcar_priv *priv = host->private_data;
726 void __iomem *base = priv->base;
727 unsigned int handled = 0;
728 struct ata_port *ap;
729 u32 sataintstat;
730 unsigned long flags;
731
732 spin_lock_irqsave(&host->lock, flags);
733
734 sataintstat = ioread32(base + SATAINTSTAT_REG);
735 sataintstat &= SATA_RCAR_INT_MASK;
736 if (!sataintstat)
737 goto done;
738 /* ack */
739 iowrite32(~sataintstat & 0x7ff, base + SATAINTSTAT_REG);
740
741 ap = host->ports[0];
742
743 if (sataintstat & SATAINTSTAT_ATA)
744 sata_rcar_ata_interrupt(ap);
745
746 if (sataintstat & SATAINTSTAT_SERR)
747 sata_rcar_serr_interrupt(ap);
748
749 handled = 1;
750 done:
751 spin_unlock_irqrestore(&host->lock, flags);
752
753 return IRQ_RETVAL(handled);
754 }
755
756 static void sata_rcar_setup_port(struct ata_host *host)
757 {
758 struct ata_port *ap = host->ports[0];
759 struct ata_ioports *ioaddr = &ap->ioaddr;
760 struct sata_rcar_priv *priv = host->private_data;
761 void __iomem *base = priv->base;
762
763 ap->ops = &sata_rcar_port_ops;
764 ap->pio_mask = ATA_PIO4;
765 ap->udma_mask = ATA_UDMA6;
766 ap->flags |= ATA_FLAG_SATA;
767
768 if (priv->type == RCAR_R8A7790_ES1_SATA)
769 ap->flags |= ATA_FLAG_NO_DIPM;
770
771 ioaddr->cmd_addr = base + SDATA_REG;
772 ioaddr->ctl_addr = base + SSDEVCON_REG;
773 ioaddr->scr_addr = base + SCRSSTS_REG;
774 ioaddr->altstatus_addr = ioaddr->ctl_addr;
775
776 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
777 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
778 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
779 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
780 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
781 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
782 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
783 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
784 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
785 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
786 }
787
788 static void sata_rcar_init_module(struct sata_rcar_priv *priv)
789 {
790 void __iomem *base = priv->base;
791 u32 val;
792
793 /* SATA-IP reset state */
794 val = ioread32(base + ATAPI_CONTROL1_REG);
795 val |= ATAPI_CONTROL1_RESET;
796 iowrite32(val, base + ATAPI_CONTROL1_REG);
797
798 /* ISM mode, PRD mode, DTEND flag at bit 0 */
799 val = ioread32(base + ATAPI_CONTROL1_REG);
800 val |= ATAPI_CONTROL1_ISM;
801 val |= ATAPI_CONTROL1_DESE;
802 val |= ATAPI_CONTROL1_DTA32M;
803 iowrite32(val, base + ATAPI_CONTROL1_REG);
804
805 /* Release the SATA-IP from the reset state */
806 val = ioread32(base + ATAPI_CONTROL1_REG);
807 val &= ~ATAPI_CONTROL1_RESET;
808 iowrite32(val, base + ATAPI_CONTROL1_REG);
809
810 /* ack and mask */
811 iowrite32(0, base + SATAINTSTAT_REG);
812 iowrite32(0x7ff, base + SATAINTMASK_REG);
813
814 /* enable interrupts */
815 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
816 }
817
818 static void sata_rcar_init_controller(struct ata_host *host)
819 {
820 struct sata_rcar_priv *priv = host->private_data;
821
822 /* reset and setup phy */
823 switch (priv->type) {
824 case RCAR_GEN1_SATA:
825 sata_rcar_gen1_phy_init(priv);
826 break;
827 case RCAR_GEN2_SATA:
828 case RCAR_GEN3_SATA:
829 case RCAR_R8A7790_ES1_SATA:
830 sata_rcar_gen2_phy_init(priv);
831 break;
832 default:
833 dev_warn(host->dev, "SATA phy is not initialized\n");
834 break;
835 }
836
837 sata_rcar_init_module(priv);
838 }
839
840 static const struct of_device_id sata_rcar_match[] = {
841 {
842 /* Deprecated by "renesas,sata-r8a7779" */
843 .compatible = "renesas,rcar-sata",
844 .data = (void *)RCAR_GEN1_SATA,
845 },
846 {
847 .compatible = "renesas,sata-r8a7779",
848 .data = (void *)RCAR_GEN1_SATA,
849 },
850 {
851 .compatible = "renesas,sata-r8a7790",
852 .data = (void *)RCAR_GEN2_SATA
853 },
854 {
855 .compatible = "renesas,sata-r8a7790-es1",
856 .data = (void *)RCAR_R8A7790_ES1_SATA
857 },
858 {
859 .compatible = "renesas,sata-r8a7791",
860 .data = (void *)RCAR_GEN2_SATA
861 },
862 {
863 .compatible = "renesas,sata-r8a7793",
864 .data = (void *)RCAR_GEN2_SATA
865 },
866 {
867 .compatible = "renesas,sata-r8a7795",
868 .data = (void *)RCAR_GEN3_SATA
869 },
870 {
871 .compatible = "renesas,rcar-gen2-sata",
872 .data = (void *)RCAR_GEN2_SATA
873 },
874 {
875 .compatible = "renesas,rcar-gen3-sata",
876 .data = (void *)RCAR_GEN3_SATA
877 },
878 { },
879 };
880 MODULE_DEVICE_TABLE(of, sata_rcar_match);
881
882 static int sata_rcar_probe(struct platform_device *pdev)
883 {
884 struct ata_host *host;
885 struct sata_rcar_priv *priv;
886 struct resource *mem;
887 int irq;
888 int ret = 0;
889
890 irq = platform_get_irq(pdev, 0);
891 if (irq <= 0)
892 return -EINVAL;
893
894 priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv),
895 GFP_KERNEL);
896 if (!priv)
897 return -ENOMEM;
898
899 priv->type = (enum sata_rcar_type)of_device_get_match_data(&pdev->dev);
900 priv->clk = devm_clk_get(&pdev->dev, NULL);
901 if (IS_ERR(priv->clk)) {
902 dev_err(&pdev->dev, "failed to get access to sata clock\n");
903 return PTR_ERR(priv->clk);
904 }
905
906 ret = clk_prepare_enable(priv->clk);
907 if (ret)
908 return ret;
909
910 host = ata_host_alloc(&pdev->dev, 1);
911 if (!host) {
912 dev_err(&pdev->dev, "ata_host_alloc failed\n");
913 ret = -ENOMEM;
914 goto cleanup;
915 }
916
917 host->private_data = priv;
918
919 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
920 priv->base = devm_ioremap_resource(&pdev->dev, mem);
921 if (IS_ERR(priv->base)) {
922 ret = PTR_ERR(priv->base);
923 goto cleanup;
924 }
925
926 /* setup port */
927 sata_rcar_setup_port(host);
928
929 /* initialize host controller */
930 sata_rcar_init_controller(host);
931
932 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
933 &sata_rcar_sht);
934 if (!ret)
935 return 0;
936
937 cleanup:
938 clk_disable_unprepare(priv->clk);
939
940 return ret;
941 }
942
943 static int sata_rcar_remove(struct platform_device *pdev)
944 {
945 struct ata_host *host = platform_get_drvdata(pdev);
946 struct sata_rcar_priv *priv = host->private_data;
947 void __iomem *base = priv->base;
948
949 ata_host_detach(host);
950
951 /* disable interrupts */
952 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
953 /* ack and mask */
954 iowrite32(0, base + SATAINTSTAT_REG);
955 iowrite32(0x7ff, base + SATAINTMASK_REG);
956
957 clk_disable_unprepare(priv->clk);
958
959 return 0;
960 }
961
962 #ifdef CONFIG_PM_SLEEP
963 static int sata_rcar_suspend(struct device *dev)
964 {
965 struct ata_host *host = dev_get_drvdata(dev);
966 struct sata_rcar_priv *priv = host->private_data;
967 void __iomem *base = priv->base;
968 int ret;
969
970 ret = ata_host_suspend(host, PMSG_SUSPEND);
971 if (!ret) {
972 /* disable interrupts */
973 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
974 /* mask */
975 iowrite32(0x7ff, base + SATAINTMASK_REG);
976
977 clk_disable_unprepare(priv->clk);
978 }
979
980 return ret;
981 }
982
983 static int sata_rcar_resume(struct device *dev)
984 {
985 struct ata_host *host = dev_get_drvdata(dev);
986 struct sata_rcar_priv *priv = host->private_data;
987 void __iomem *base = priv->base;
988 int ret;
989
990 ret = clk_prepare_enable(priv->clk);
991 if (ret)
992 return ret;
993
994 if (priv->type == RCAR_GEN3_SATA) {
995 sata_rcar_gen2_phy_init(priv);
996 sata_rcar_init_module(priv);
997 } else {
998 /* ack and mask */
999 iowrite32(0, base + SATAINTSTAT_REG);
1000 iowrite32(0x7ff, base + SATAINTMASK_REG);
1001
1002 /* enable interrupts */
1003 iowrite32(ATAPI_INT_ENABLE_SATAINT,
1004 base + ATAPI_INT_ENABLE_REG);
1005 }
1006
1007 ata_host_resume(host);
1008
1009 return 0;
1010 }
1011
1012 static int sata_rcar_restore(struct device *dev)
1013 {
1014 struct ata_host *host = dev_get_drvdata(dev);
1015 struct sata_rcar_priv *priv = host->private_data;
1016 int ret;
1017
1018 ret = clk_prepare_enable(priv->clk);
1019 if (ret)
1020 return ret;
1021
1022 sata_rcar_setup_port(host);
1023
1024 /* initialize host controller */
1025 sata_rcar_init_controller(host);
1026
1027 ata_host_resume(host);
1028
1029 return 0;
1030 }
1031
1032 static const struct dev_pm_ops sata_rcar_pm_ops = {
1033 .suspend = sata_rcar_suspend,
1034 .resume = sata_rcar_resume,
1035 .freeze = sata_rcar_suspend,
1036 .thaw = sata_rcar_resume,
1037 .poweroff = sata_rcar_suspend,
1038 .restore = sata_rcar_restore,
1039 };
1040 #endif
1041
1042 static struct platform_driver sata_rcar_driver = {
1043 .probe = sata_rcar_probe,
1044 .remove = sata_rcar_remove,
1045 .driver = {
1046 .name = DRV_NAME,
1047 .of_match_table = sata_rcar_match,
1048 #ifdef CONFIG_PM_SLEEP
1049 .pm = &sata_rcar_pm_ops,
1050 #endif
1051 },
1052 };
1053
1054 module_platform_driver(sata_rcar_driver);
1055
1056 MODULE_LICENSE("GPL");
1057 MODULE_AUTHOR("Vladimir Barinov");
1058 MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver");
Linux with added FPC-III support