drivers/clk/mediatek/clk-mt7622-hif.c

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Chen Zhong <chen.zhong@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21
  22 #include "clk-mtk.h"
  23 #include "clk-gate.h"
  24
  25 #include <dt-bindings/clock/mt7622-clk.h>
  26
  27 #define GATE_PCIE(_id, _name, _parent, _shift) {        \
  28                 .id = _id,                              \
  29                 .name = _name,                          \
  30                 .parent_name = _parent,                 \
  31                 .regs = &pcie_cg_regs,                  \
  32                 .shift = _shift,                        \
  33                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  34         }
  35
  36 #define GATE_SSUSB(_id, _name, _parent, _shift) {       \
  37                 .id = _id,                              \
  38                 .name = _name,                          \
  39                 .parent_name = _parent,                 \
  40                 .regs = &ssusb_cg_regs,                 \
  41                 .shift = _shift,                        \
  42                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  43         }
  44
  45 static const struct mtk_gate_regs pcie_cg_regs = {
  46         .set_ofs = 0x30,
  47         .clr_ofs = 0x30,
  48         .sta_ofs = 0x30,
  49 };
  50
  51 static const struct mtk_gate_regs ssusb_cg_regs = {
  52         .set_ofs = 0x30,
  53         .clr_ofs = 0x30,
  54         .sta_ofs = 0x30,
  55 };
  56
  57 static const struct mtk_gate ssusb_clks[] = {
  58         GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
  59                    "to_u2_phy_1p", 0),
  60         GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
  61         GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
  62         GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
  63         GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
  64         GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
  65 };
  66
  67 static const struct mtk_gate pcie_clks[] = {
  68         GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
  69         GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
  70         GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
  71         GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
  72         GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
  73         GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
  74         GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
  75         GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
  76         GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
  77         GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
  78         GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
  79         GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
  80         GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
  81         GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
  82         GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
  83         GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
  84         GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
  85 };
  86
  87 static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
  88 {
  89         struct clk_onecell_data *clk_data;
  90         struct device_node *node = pdev->dev.of_node;
  91         int r;
  92
  93         clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
  94
  95         mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
  96                                clk_data);
  97
  98         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  99         if (r)
 100                 dev_err(&pdev->dev,
 101                         "could not register clock provider: %s: %d\n",
 102                         pdev->name, r);
 103
 104         mtk_register_reset_controller(node, 1, 0x34);
 105
 106         return r;
 107 }
 108
 109 static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 110 {
 111         struct clk_onecell_data *clk_data;
 112         struct device_node *node = pdev->dev.of_node;
 113         int r;
 114
 115         clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
 116
 117         mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
 118                                clk_data);
 119
 120         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 121         if (r)
 122                 dev_err(&pdev->dev,
 123                         "could not register clock provider: %s: %d\n",
 124                         pdev->name, r);
 125
 126         mtk_register_reset_controller(node, 1, 0x34);
 127
 128         return r;
 129 }
 130
 131 static const struct of_device_id of_match_clk_mt7622_hif[] = {
 132         {
 133                 .compatible = "mediatek,mt7622-pciesys",
 134                 .data = clk_mt7622_pciesys_init,
 135         }, {
 136                 .compatible = "mediatek,mt7622-ssusbsys",
 137                 .data = clk_mt7622_ssusbsys_init,
 138         }, {
 139                 /* sentinel */
 140         }
 141 };
 142
 143 static int clk_mt7622_hif_probe(struct platform_device *pdev)
 144 {
 145         int (*clk_init)(struct platform_device *);
 146         int r;
 147
 148         clk_init = of_device_get_match_data(&pdev->dev);
 149         if (!clk_init)
 150                 return -EINVAL;
 151
 152         r = clk_init(pdev);
 153         if (r)
 154                 dev_err(&pdev->dev,
 155                         "could not register clock provider: %s: %d\n",
 156                         pdev->name, r);
 157
 158         return r;
 159 }
 160
 161 static struct platform_driver clk_mt7622_hif_drv = {
 162         .probe = clk_mt7622_hif_probe,
 163         .driver = {
 164                 .name = "clk-mt7622-hif",
 165                 .of_match_table = of_match_clk_mt7622_hif,
 166         },
 167 };
 168
 169 builtin_platform_driver(clk_mt7622_hif_drv);