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Linux 4.18.10
[linux/fpc-iii.git] / drivers / clk / qcom / clk-alpha-pll.c
blob3c49a60072f149fa699ce1de70915b4937b11615
1 /*
2 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/export.h>
16 #include <linux/clk-provider.h>
17 #include <linux/regmap.h>
18 #include <linux/delay.h>
19
20 #include "clk-alpha-pll.h"
21 #include "common.h"
22
23 #define PLL_MODE(p) ((p)->offset + 0x0)
24 # define PLL_OUTCTRL BIT(0)
25 # define PLL_BYPASSNL BIT(1)
26 # define PLL_RESET_N BIT(2)
27 # define PLL_OFFLINE_REQ BIT(7)
28 # define PLL_LOCK_COUNT_SHIFT 8
29 # define PLL_LOCK_COUNT_MASK 0x3f
30 # define PLL_BIAS_COUNT_SHIFT 14
31 # define PLL_BIAS_COUNT_MASK 0x3f
32 # define PLL_VOTE_FSM_ENA BIT(20)
33 # define PLL_FSM_ENA BIT(20)
34 # define PLL_VOTE_FSM_RESET BIT(21)
35 # define PLL_UPDATE BIT(22)
36 # define PLL_UPDATE_BYPASS BIT(23)
37 # define PLL_OFFLINE_ACK BIT(28)
38 # define ALPHA_PLL_ACK_LATCH BIT(29)
39 # define PLL_ACTIVE_FLAG BIT(30)
40 # define PLL_LOCK_DET BIT(31)
41
42 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
43 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
44 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
45
46 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
47 # define PLL_POST_DIV_SHIFT 8
48 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
49 # define PLL_ALPHA_EN BIT(24)
50 # define PLL_ALPHA_MODE BIT(25)
51 # define PLL_VCO_SHIFT 20
52 # define PLL_VCO_MASK 0x3
53
54 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
55
56 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
57 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
58 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
59 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
60 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
61 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
62 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
63
64 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
65 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
66 [PLL_OFF_L_VAL] = 0x04,
67 [PLL_OFF_ALPHA_VAL] = 0x08,
68 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
69 [PLL_OFF_USER_CTL] = 0x10,
70 [PLL_OFF_USER_CTL_U] = 0x14,
71 [PLL_OFF_CONFIG_CTL] = 0x18,
72 [PLL_OFF_TEST_CTL] = 0x1c,
73 [PLL_OFF_TEST_CTL_U] = 0x20,
74 [PLL_OFF_STATUS] = 0x24,
75 },
76 [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
77 [PLL_OFF_L_VAL] = 0x04,
78 [PLL_OFF_ALPHA_VAL] = 0x08,
79 [PLL_OFF_USER_CTL] = 0x10,
80 [PLL_OFF_CONFIG_CTL] = 0x14,
81 [PLL_OFF_CONFIG_CTL_U] = 0x18,
82 [PLL_OFF_TEST_CTL] = 0x1c,
83 [PLL_OFF_TEST_CTL_U] = 0x20,
84 [PLL_OFF_STATUS] = 0x24,
85 },
86 [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
87 [PLL_OFF_L_VAL] = 0x04,
88 [PLL_OFF_ALPHA_VAL] = 0x08,
89 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
90 [PLL_OFF_USER_CTL] = 0x10,
91 [PLL_OFF_CONFIG_CTL] = 0x18,
92 [PLL_OFF_TEST_CTL] = 0x1c,
93 [PLL_OFF_STATUS] = 0x24,
94 },
95 [CLK_ALPHA_PLL_TYPE_FABIA] = {
96 [PLL_OFF_L_VAL] = 0x04,
97 [PLL_OFF_USER_CTL] = 0x0c,
98 [PLL_OFF_USER_CTL_U] = 0x10,
99 [PLL_OFF_CONFIG_CTL] = 0x14,
100 [PLL_OFF_CONFIG_CTL_U] = 0x18,
101 [PLL_OFF_TEST_CTL] = 0x1c,
102 [PLL_OFF_TEST_CTL_U] = 0x20,
103 [PLL_OFF_STATUS] = 0x24,
104 [PLL_OFF_OPMODE] = 0x2c,
105 [PLL_OFF_FRAC] = 0x38,
106 },
107 };
108 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
109
110 /*
111 * Even though 40 bits are present, use only 32 for ease of calculation.
112 */
113 #define ALPHA_REG_BITWIDTH 40
114 #define ALPHA_REG_16BIT_WIDTH 16
115 #define ALPHA_BITWIDTH 32U
116 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
117
118 #define PLL_HUAYRA_M_WIDTH 8
119 #define PLL_HUAYRA_M_SHIFT 8
120 #define PLL_HUAYRA_M_MASK 0xff
121 #define PLL_HUAYRA_N_SHIFT 0
122 #define PLL_HUAYRA_N_MASK 0xff
123 #define PLL_HUAYRA_ALPHA_WIDTH 16
124
125 #define FABIA_OPMODE_STANDBY 0x0
126 #define FABIA_OPMODE_RUN 0x1
127
128 #define FABIA_PLL_OUT_MASK 0x7
129 #define FABIA_PLL_RATE_MARGIN 500
130
131 #define pll_alpha_width(p) \
132 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
133 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
134
135 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
136
137 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
138 struct clk_alpha_pll, clkr)
139
140 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
141 struct clk_alpha_pll_postdiv, clkr)
142
143 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
144 const char *action)
145 {
146 u32 val;
147 int count;
148 int ret;
149 const char *name = clk_hw_get_name(&pll->clkr.hw);
150
151 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
152 if (ret)
153 return ret;
154
155 for (count = 100; count > 0; count--) {
156 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
157 if (ret)
158 return ret;
159 if (inverse && !(val & mask))
160 return 0;
161 else if ((val & mask) == mask)
162 return 0;
163
164 udelay(1);
165 }
166
167 WARN(1, "%s failed to %s!\n", name, action);
168 return -ETIMEDOUT;
169 }
170
171 #define wait_for_pll_enable_active(pll) \
172 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
173
174 #define wait_for_pll_enable_lock(pll) \
175 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
176
177 #define wait_for_pll_disable(pll) \
178 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
179
180 #define wait_for_pll_offline(pll) \
181 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
182
183 #define wait_for_pll_update(pll) \
184 wait_for_pll(pll, PLL_UPDATE, 1, "update")
185
186 #define wait_for_pll_update_ack_set(pll) \
187 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
188
189 #define wait_for_pll_update_ack_clear(pll) \
190 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
191
192 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
193 const struct alpha_pll_config *config)
194 {
195 u32 val, mask;
196
197 regmap_write(regmap, PLL_L_VAL(pll), config->l);
198 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
199 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
200
201 if (pll_has_64bit_config(pll))
202 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
203 config->config_ctl_hi_val);
204
205 if (pll_alpha_width(pll) > 32)
206 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
207
208 val = config->main_output_mask;
209 val |= config->aux_output_mask;
210 val |= config->aux2_output_mask;
211 val |= config->early_output_mask;
212 val |= config->pre_div_val;
213 val |= config->post_div_val;
214 val |= config->vco_val;
215 val |= config->alpha_en_mask;
216 val |= config->alpha_mode_mask;
217
218 mask = config->main_output_mask;
219 mask |= config->aux_output_mask;
220 mask |= config->aux2_output_mask;
221 mask |= config->early_output_mask;
222 mask |= config->pre_div_mask;
223 mask |= config->post_div_mask;
224 mask |= config->vco_mask;
225
226 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
227
228 if (pll->flags & SUPPORTS_FSM_MODE)
229 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
230 }
231
232 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
233 {
234 int ret;
235 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
236 u32 val;
237
238 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
239 if (ret)
240 return ret;
241
242 val |= PLL_FSM_ENA;
243
244 if (pll->flags & SUPPORTS_OFFLINE_REQ)
245 val &= ~PLL_OFFLINE_REQ;
246
247 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
248 if (ret)
249 return ret;
250
251 /* Make sure enable request goes through before waiting for update */
252 mb();
253
254 return wait_for_pll_enable_active(pll);
255 }
256
257 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
258 {
259 int ret;
260 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
261 u32 val;
262
263 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
264 if (ret)
265 return;
266
267 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
268 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
269 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
270 if (ret)
271 return;
272
273 ret = wait_for_pll_offline(pll);
274 if (ret)
275 return;
276 }
277
278 /* Disable hwfsm */
279 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
280 PLL_FSM_ENA, 0);
281 if (ret)
282 return;
283
284 wait_for_pll_disable(pll);
285 }
286
287 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
288 {
289 int ret;
290 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
291 u32 val;
292
293 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
294 if (ret)
295 return ret;
296
297 return !!(val & mask);
298 }
299
300 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
301 {
302 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
303 }
304
305 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
306 {
307 return pll_is_enabled(hw, PLL_LOCK_DET);
308 }
309
310 static int clk_alpha_pll_enable(struct clk_hw *hw)
311 {
312 int ret;
313 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
314 u32 val, mask;
315
316 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
317 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
318 if (ret)
319 return ret;
320
321 /* If in FSM mode, just vote for it */
322 if (val & PLL_VOTE_FSM_ENA) {
323 ret = clk_enable_regmap(hw);
324 if (ret)
325 return ret;
326 return wait_for_pll_enable_active(pll);
327 }
328
329 /* Skip if already enabled */
330 if ((val & mask) == mask)
331 return 0;
332
333 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
334 PLL_BYPASSNL, PLL_BYPASSNL);
335 if (ret)
336 return ret;
337
338 /*
339 * H/W requires a 5us delay between disabling the bypass and
340 * de-asserting the reset.
341 */
342 mb();
343 udelay(5);
344
345 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
346 PLL_RESET_N, PLL_RESET_N);
347 if (ret)
348 return ret;
349
350 ret = wait_for_pll_enable_lock(pll);
351 if (ret)
352 return ret;
353
354 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
355 PLL_OUTCTRL, PLL_OUTCTRL);
356
357 /* Ensure that the write above goes through before returning. */
358 mb();
359 return ret;
360 }
361
362 static void clk_alpha_pll_disable(struct clk_hw *hw)
363 {
364 int ret;
365 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
366 u32 val, mask;
367
368 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
369 if (ret)
370 return;
371
372 /* If in FSM mode, just unvote it */
373 if (val & PLL_VOTE_FSM_ENA) {
374 clk_disable_regmap(hw);
375 return;
376 }
377
378 mask = PLL_OUTCTRL;
379 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
380
381 /* Delay of 2 output clock ticks required until output is disabled */
382 mb();
383 udelay(1);
384
385 mask = PLL_RESET_N | PLL_BYPASSNL;
386 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
387 }
388
389 static unsigned long
390 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
391 {
392 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
393 }
394
395 static unsigned long
396 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
397 u32 alpha_width)
398 {
399 u64 remainder;
400 u64 quotient;
401
402 quotient = rate;
403 remainder = do_div(quotient, prate);
404 *l = quotient;
405
406 if (!remainder) {
407 *a = 0;
408 return rate;
409 }
410
411 /* Upper ALPHA_BITWIDTH bits of Alpha */
412 quotient = remainder << ALPHA_SHIFT(alpha_width);
413
414 remainder = do_div(quotient, prate);
415
416 if (remainder)
417 quotient++;
418
419 *a = quotient;
420 return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
421 }
422
423 static const struct pll_vco *
424 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
425 {
426 const struct pll_vco *v = pll->vco_table;
427 const struct pll_vco *end = v + pll->num_vco;
428
429 for (; v < end; v++)
430 if (rate >= v->min_freq && rate <= v->max_freq)
431 return v;
432
433 return NULL;
434 }
435
436 static unsigned long
437 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
438 {
439 u32 l, low, high, ctl;
440 u64 a = 0, prate = parent_rate;
441 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
442 u32 alpha_width = pll_alpha_width(pll);
443
444 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
445
446 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
447 if (ctl & PLL_ALPHA_EN) {
448 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
449 if (alpha_width > 32) {
450 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
451 &high);
452 a = (u64)high << 32 | low;
453 } else {
454 a = low & GENMASK(alpha_width - 1, 0);
455 }
456
457 if (alpha_width > ALPHA_BITWIDTH)
458 a >>= alpha_width - ALPHA_BITWIDTH;
459 }
460
461 return alpha_pll_calc_rate(prate, l, a, alpha_width);
462 }
463
464
465 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
466 {
467 int ret;
468 u32 mode;
469
470 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
471
472 /* Latch the input to the PLL */
473 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
474 PLL_UPDATE);
475
476 /* Wait for 2 reference cycle before checking ACK bit */
477 udelay(1);
478
479 /*
480 * PLL will latch the new L, Alpha and freq control word.
481 * PLL will respond by raising PLL_ACK_LATCH output when new programming
482 * has been latched in and PLL is being updated. When
483 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
484 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
485 */
486 if (mode & PLL_UPDATE_BYPASS) {
487 ret = wait_for_pll_update_ack_set(pll);
488 if (ret)
489 return ret;
490
491 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
492 } else {
493 ret = wait_for_pll_update(pll);
494 if (ret)
495 return ret;
496 }
497
498 ret = wait_for_pll_update_ack_clear(pll);
499 if (ret)
500 return ret;
501
502 /* Wait for PLL output to stabilize */
503 udelay(10);
504
505 return 0;
506 }
507
508 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
509 int (*is_enabled)(struct clk_hw *))
510 {
511 if (!is_enabled(&pll->clkr.hw) ||
512 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
513 return 0;
514
515 return __clk_alpha_pll_update_latch(pll);
516 }
517
518 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
519 unsigned long prate,
520 int (*is_enabled)(struct clk_hw *))
521 {
522 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
523 const struct pll_vco *vco;
524 u32 l, alpha_width = pll_alpha_width(pll);
525 u64 a;
526
527 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
528 vco = alpha_pll_find_vco(pll, rate);
529 if (pll->vco_table && !vco) {
530 pr_err("alpha pll not in a valid vco range\n");
531 return -EINVAL;
532 }
533
534 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
535
536 if (alpha_width > ALPHA_BITWIDTH)
537 a <<= alpha_width - ALPHA_BITWIDTH;
538
539 if (alpha_width > 32)
540 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
541
542 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
543
544 if (vco) {
545 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
546 PLL_VCO_MASK << PLL_VCO_SHIFT,
547 vco->val << PLL_VCO_SHIFT);
548 }
549
550 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
551 PLL_ALPHA_EN, PLL_ALPHA_EN);
552
553 return clk_alpha_pll_update_latch(pll, is_enabled);
554 }
555
556 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
557 unsigned long prate)
558 {
559 return __clk_alpha_pll_set_rate(hw, rate, prate,
560 clk_alpha_pll_is_enabled);
561 }
562
563 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
564 unsigned long prate)
565 {
566 return __clk_alpha_pll_set_rate(hw, rate, prate,
567 clk_alpha_pll_hwfsm_is_enabled);
568 }
569
570 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
571 unsigned long *prate)
572 {
573 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
574 u32 l, alpha_width = pll_alpha_width(pll);
575 u64 a;
576 unsigned long min_freq, max_freq;
577
578 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
579 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
580 return rate;
581
582 min_freq = pll->vco_table[0].min_freq;
583 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
584
585 return clamp(rate, min_freq, max_freq);
586 }
587
588 static unsigned long
589 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
590 {
591 /*
592 * a contains 16 bit alpha_val in two’s compliment number in the range
593 * of [-0.5, 0.5).
594 */
595 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
596 l -= 1;
597
598 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
599 }
600
601 static unsigned long
602 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
603 u32 *l, u32 *a)
604 {
605 u64 remainder;
606 u64 quotient;
607
608 quotient = rate;
609 remainder = do_div(quotient, prate);
610 *l = quotient;
611
612 if (!remainder) {
613 *a = 0;
614 return rate;
615 }
616
617 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
618 remainder = do_div(quotient, prate);
619
620 if (remainder)
621 quotient++;
622
623 /*
624 * alpha_val should be in two’s compliment number in the range
625 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
626 * since alpha value will be subtracted in this case.
627 */
628 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
629 *l += 1;
630
631 *a = quotient;
632 return alpha_huayra_pll_calc_rate(prate, *l, *a);
633 }
634
635 static unsigned long
636 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
637 {
638 u64 rate = parent_rate, tmp;
639 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
640 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
641
642 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
643 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
644
645 if (ctl & PLL_ALPHA_EN) {
646 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
647 /*
648 * Depending upon alpha_mode, it can be treated as M/N value or
649 * as a two’s compliment number. When alpha_mode=1,
650 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
651 *
652 * Fout=FIN*(L+(M/N))
653 *
654 * M is a signed number (-128 to 127) and N is unsigned
655 * (0 to 255). M/N has to be within +/-0.5.
656 *
657 * When alpha_mode=0, it is a two’s compliment number in the
658 * range [-0.5, 0.5).
659 *
660 * Fout=FIN*(L+(alpha_val)/2^16)
661 *
662 * where alpha_val is two’s compliment number.
663 */
664 if (!(ctl & PLL_ALPHA_MODE))
665 return alpha_huayra_pll_calc_rate(rate, l, alpha);
666
667 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
668 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
669
670 rate *= l;
671 tmp = parent_rate;
672 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
673 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
674 tmp *= alpha_m;
675 do_div(tmp, alpha_n);
676 rate -= tmp;
677 } else {
678 tmp *= alpha_m;
679 do_div(tmp, alpha_n);
680 rate += tmp;
681 }
682
683 return rate;
684 }
685
686 return alpha_huayra_pll_calc_rate(rate, l, alpha);
687 }
688
689 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
690 unsigned long prate)
691 {
692 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
693 u32 l, a, ctl, cur_alpha = 0;
694
695 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
696
697 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
698
699 if (ctl & PLL_ALPHA_EN)
700 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
701
702 /*
703 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
704 * without having to go through the power on sequence.
705 */
706 if (clk_alpha_pll_is_enabled(hw)) {
707 if (cur_alpha != a) {
708 pr_err("clock needs to be gated %s\n",
709 clk_hw_get_name(hw));
710 return -EBUSY;
711 }
712
713 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
714 /* Ensure that the write above goes to detect L val change. */
715 mb();
716 return wait_for_pll_enable_lock(pll);
717 }
718
719 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
720 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
721
722 if (a == 0)
723 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
724 PLL_ALPHA_EN, 0x0);
725 else
726 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
727 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
728
729 return 0;
730 }
731
732 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
733 unsigned long *prate)
734 {
735 u32 l, a;
736
737 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
738 }
739
740 const struct clk_ops clk_alpha_pll_ops = {
741 .enable = clk_alpha_pll_enable,
742 .disable = clk_alpha_pll_disable,
743 .is_enabled = clk_alpha_pll_is_enabled,
744 .recalc_rate = clk_alpha_pll_recalc_rate,
745 .round_rate = clk_alpha_pll_round_rate,
746 .set_rate = clk_alpha_pll_set_rate,
747 };
748 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
749
750 const struct clk_ops clk_alpha_pll_huayra_ops = {
751 .enable = clk_alpha_pll_enable,
752 .disable = clk_alpha_pll_disable,
753 .is_enabled = clk_alpha_pll_is_enabled,
754 .recalc_rate = alpha_pll_huayra_recalc_rate,
755 .round_rate = alpha_pll_huayra_round_rate,
756 .set_rate = alpha_pll_huayra_set_rate,
757 };
758 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
759
760 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
761 .enable = clk_alpha_pll_hwfsm_enable,
762 .disable = clk_alpha_pll_hwfsm_disable,
763 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
764 .recalc_rate = clk_alpha_pll_recalc_rate,
765 .round_rate = clk_alpha_pll_round_rate,
766 .set_rate = clk_alpha_pll_hwfsm_set_rate,
767 };
768 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
769
770 static unsigned long
771 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
772 {
773 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
774 u32 ctl;
775
776 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
777
778 ctl >>= PLL_POST_DIV_SHIFT;
779 ctl &= PLL_POST_DIV_MASK(pll);
780
781 return parent_rate >> fls(ctl);
782 }
783
784 static const struct clk_div_table clk_alpha_div_table[] = {
785 { 0x0, 1 },
786 { 0x1, 2 },
787 { 0x3, 4 },
788 { 0x7, 8 },
789 { 0xf, 16 },
790 { }
791 };
792
793 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
794 { 0x0, 1 },
795 { 0x1, 2 },
796 { 0x3, 4 },
797 { }
798 };
799
800 static long
801 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
802 unsigned long *prate)
803 {
804 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
805 const struct clk_div_table *table;
806
807 if (pll->width == 2)
808 table = clk_alpha_2bit_div_table;
809 else
810 table = clk_alpha_div_table;
811
812 return divider_round_rate(hw, rate, prate, table,
813 pll->width, CLK_DIVIDER_POWER_OF_TWO);
814 }
815
816 static long
817 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
818 unsigned long *prate)
819 {
820 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
821 u32 ctl, div;
822
823 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
824
825 ctl >>= PLL_POST_DIV_SHIFT;
826 ctl &= BIT(pll->width) - 1;
827 div = 1 << fls(ctl);
828
829 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
830 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
831
832 return DIV_ROUND_UP_ULL((u64)*prate, div);
833 }
834
835 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
836 unsigned long parent_rate)
837 {
838 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
839 int div;
840
841 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
842 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
843
844 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
845 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
846 div << PLL_POST_DIV_SHIFT);
847 }
848
849 const struct clk_ops clk_alpha_pll_postdiv_ops = {
850 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
851 .round_rate = clk_alpha_pll_postdiv_round_rate,
852 .set_rate = clk_alpha_pll_postdiv_set_rate,
853 };
854 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
855
856 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
857 .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
858 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
859 };
860 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
861
862 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
863 const struct alpha_pll_config *config)
864 {
865 u32 val, mask;
866
867 if (config->l)
868 regmap_write(regmap, PLL_L_VAL(pll), config->l);
869
870 if (config->alpha)
871 regmap_write(regmap, PLL_FRAC(pll), config->alpha);
872
873 if (config->config_ctl_val)
874 regmap_write(regmap, PLL_CONFIG_CTL(pll),
875 config->config_ctl_val);
876
877 if (config->post_div_mask) {
878 mask = config->post_div_mask;
879 val = config->post_div_val;
880 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
881 }
882
883 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
884 PLL_UPDATE_BYPASS);
885
886 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
887 }
888 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
889
890 static int alpha_pll_fabia_enable(struct clk_hw *hw)
891 {
892 int ret;
893 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
894 u32 val, opmode_val;
895 struct regmap *regmap = pll->clkr.regmap;
896
897 ret = regmap_read(regmap, PLL_MODE(pll), &val);
898 if (ret)
899 return ret;
900
901 /* If in FSM mode, just vote for it */
902 if (val & PLL_VOTE_FSM_ENA) {
903 ret = clk_enable_regmap(hw);
904 if (ret)
905 return ret;
906 return wait_for_pll_enable_active(pll);
907 }
908
909 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
910 if (ret)
911 return ret;
912
913 /* Skip If PLL is already running */
914 if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
915 return 0;
916
917 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
918 if (ret)
919 return ret;
920
921 ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
922 if (ret)
923 return ret;
924
925 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
926 PLL_RESET_N);
927 if (ret)
928 return ret;
929
930 ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
931 if (ret)
932 return ret;
933
934 ret = wait_for_pll_enable_lock(pll);
935 if (ret)
936 return ret;
937
938 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
939 FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
940 if (ret)
941 return ret;
942
943 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
944 PLL_OUTCTRL);
945 }
946
947 static void alpha_pll_fabia_disable(struct clk_hw *hw)
948 {
949 int ret;
950 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
951 u32 val;
952 struct regmap *regmap = pll->clkr.regmap;
953
954 ret = regmap_read(regmap, PLL_MODE(pll), &val);
955 if (ret)
956 return;
957
958 /* If in FSM mode, just unvote it */
959 if (val & PLL_FSM_ENA) {
960 clk_disable_regmap(hw);
961 return;
962 }
963
964 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
965 if (ret)
966 return;
967
968 /* Disable main outputs */
969 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
970 0);
971 if (ret)
972 return;
973
974 /* Place the PLL in STANDBY */
975 regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
976 }
977
978 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
979 unsigned long parent_rate)
980 {
981 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
982 u32 l, frac, alpha_width = pll_alpha_width(pll);
983
984 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
985 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
986
987 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
988 }
989
990 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
991 unsigned long prate)
992 {
993 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
994 u32 val, l, alpha_width = pll_alpha_width(pll);
995 u64 a;
996 unsigned long rrate;
997 int ret = 0;
998
999 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1000 if (ret)
1001 return ret;
1002
1003 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1004
1005 /*
1006 * Due to limited number of bits for fractional rate programming, the
1007 * rounded up rate could be marginally higher than the requested rate.
1008 */
1009 if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
1010 pr_err("Call set rate on the PLL with rounded rates!\n");
1011 return -EINVAL;
1012 }
1013
1014 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1015 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1016
1017 return __clk_alpha_pll_update_latch(pll);
1018 }
1019
1020 const struct clk_ops clk_alpha_pll_fabia_ops = {
1021 .enable = alpha_pll_fabia_enable,
1022 .disable = alpha_pll_fabia_disable,
1023 .is_enabled = clk_alpha_pll_is_enabled,
1024 .set_rate = alpha_pll_fabia_set_rate,
1025 .recalc_rate = alpha_pll_fabia_recalc_rate,
1026 .round_rate = clk_alpha_pll_round_rate,
1027 };
1028 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1029
1030 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1031 .enable = alpha_pll_fabia_enable,
1032 .disable = alpha_pll_fabia_disable,
1033 .is_enabled = clk_alpha_pll_is_enabled,
1034 .recalc_rate = alpha_pll_fabia_recalc_rate,
1035 .round_rate = clk_alpha_pll_round_rate,
1036 };
1037 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1038
1039 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1040 unsigned long parent_rate)
1041 {
1042 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1043 u32 i, div = 1, val;
1044 int ret;
1045
1046 if (!pll->post_div_table) {
1047 pr_err("Missing the post_div_table for the PLL\n");
1048 return -EINVAL;
1049 }
1050
1051 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1052 if (ret)
1053 return ret;
1054
1055 val >>= pll->post_div_shift;
1056 val &= BIT(pll->width) - 1;
1057
1058 for (i = 0; i < pll->num_post_div; i++) {
1059 if (pll->post_div_table[i].val == val) {
1060 div = pll->post_div_table[i].div;
1061 break;
1062 }
1063 }
1064
1065 return (parent_rate / div);
1066 }
1067
1068 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1069 unsigned long rate, unsigned long *prate)
1070 {
1071 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1072
1073 if (!pll->post_div_table) {
1074 pr_err("Missing the post_div_table for the PLL\n");
1075 return -EINVAL;
1076 }
1077
1078 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1079 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1080 }
1081
1082 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1083 unsigned long rate, unsigned long parent_rate)
1084 {
1085 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1086 int i, val = 0, div, ret;
1087
1088 /*
1089 * If the PLL is in FSM mode, then treat set_rate callback as a
1090 * no-operation.
1091 */
1092 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1093 if (ret)
1094 return ret;
1095
1096 if (val & PLL_VOTE_FSM_ENA)
1097 return 0;
1098
1099 if (!pll->post_div_table) {
1100 pr_err("Missing the post_div_table for the PLL\n");
1101 return -EINVAL;
1102 }
1103
1104 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1105 for (i = 0; i < pll->num_post_div; i++) {
1106 if (pll->post_div_table[i].div == div) {
1107 val = pll->post_div_table[i].val;
1108 break;
1109 }
1110 }
1111
1112 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1113 (BIT(pll->width) - 1) << pll->post_div_shift,
1114 val << pll->post_div_shift);
1115 }
1116
1117 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1118 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1119 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1120 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1121 };
1122 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
Linux with added FPC-III support