drivers/clk/renesas/clk-mstp.c

   1 /*
   2  * R-Car MSTP clocks
   3  *
   4  * Copyright (C) 2013 Ideas On Board SPRL
   5  * Copyright (C) 2015 Glider bvba
   6  *
   7  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/clk/renesas.h>
  18 #include <linux/device.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/pm_clock.h>
  23 #include <linux/pm_domain.h>
  24 #include <linux/spinlock.h>
  25
  26 /*
  27  * MSTP clocks. We can't use standard gate clocks as we need to poll on the
  28  * status register when enabling the clock.
  29  */
  30
  31 #define MSTP_MAX_CLOCKS         32
  32
  33 /**
  34  * struct mstp_clock_group - MSTP gating clocks group
  35  *
  36  * @data: clocks in this group
  37  * @smstpcr: module stop control register
  38  * @mstpsr: module stop status register (optional)
  39  * @lock: protects writes to SMSTPCR
  40  * @width_8bit: registers are 8-bit, not 32-bit
  41  */
  42 struct mstp_clock_group {
  43         struct clk_onecell_data data;
  44         void __iomem *smstpcr;
  45         void __iomem *mstpsr;
  46         spinlock_t lock;
  47         bool width_8bit;
  48 };
  49
  50 /**
  51  * struct mstp_clock - MSTP gating clock
  52  * @hw: handle between common and hardware-specific interfaces
  53  * @bit_index: control bit index
  54  * @group: MSTP clocks group
  55  */
  56 struct mstp_clock {
  57         struct clk_hw hw;
  58         u32 bit_index;
  59         struct mstp_clock_group *group;
  60 };
  61
  62 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
  63
  64 static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
  65                                 u32 __iomem *reg)
  66 {
  67         return group->width_8bit ? readb(reg) : readl(reg);
  68 }
  69
  70 static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
  71                                   u32 __iomem *reg)
  72 {
  73         group->width_8bit ? writeb(val, reg) : writel(val, reg);
  74 }
  75
  76 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
  77 {
  78         struct mstp_clock *clock = to_mstp_clock(hw);
  79         struct mstp_clock_group *group = clock->group;
  80         u32 bitmask = BIT(clock->bit_index);
  81         unsigned long flags;
  82         unsigned int i;
  83         u32 value;
  84
  85         spin_lock_irqsave(&group->lock, flags);
  86
  87         value = cpg_mstp_read(group, group->smstpcr);
  88         if (enable)
  89                 value &= ~bitmask;
  90         else
  91                 value |= bitmask;
  92         cpg_mstp_write(group, value, group->smstpcr);
  93
  94         if (!group->mstpsr) {
  95                 /* dummy read to ensure write has completed */
  96                 cpg_mstp_read(group, group->smstpcr);
  97                 barrier_data(group->smstpcr);
  98         }
  99
 100         spin_unlock_irqrestore(&group->lock, flags);
 101
 102         if (!enable || !group->mstpsr)
 103                 return 0;
 104
 105         for (i = 1000; i > 0; --i) {
 106                 if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
 107                         break;
 108                 cpu_relax();
 109         }
 110
 111         if (!i) {
 112                 pr_err("%s: failed to enable %p[%d]\n", __func__,
 113                        group->smstpcr, clock->bit_index);
 114                 return -ETIMEDOUT;
 115         }
 116
 117         return 0;
 118 }
 119
 120 static int cpg_mstp_clock_enable(struct clk_hw *hw)
 121 {
 122         return cpg_mstp_clock_endisable(hw, true);
 123 }
 124
 125 static void cpg_mstp_clock_disable(struct clk_hw *hw)
 126 {
 127         cpg_mstp_clock_endisable(hw, false);
 128 }
 129
 130 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
 131 {
 132         struct mstp_clock *clock = to_mstp_clock(hw);
 133         struct mstp_clock_group *group = clock->group;
 134         u32 value;
 135
 136         if (group->mstpsr)
 137                 value = cpg_mstp_read(group, group->mstpsr);
 138         else
 139                 value = cpg_mstp_read(group, group->smstpcr);
 140
 141         return !(value & BIT(clock->bit_index));
 142 }
 143
 144 static const struct clk_ops cpg_mstp_clock_ops = {
 145         .enable = cpg_mstp_clock_enable,
 146         .disable = cpg_mstp_clock_disable,
 147         .is_enabled = cpg_mstp_clock_is_enabled,
 148 };
 149
 150 static struct clk * __init cpg_mstp_clock_register(const char *name,
 151         const char *parent_name, unsigned int index,
 152         struct mstp_clock_group *group)
 153 {
 154         struct clk_init_data init;
 155         struct mstp_clock *clock;
 156         struct clk *clk;
 157
 158         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 159         if (!clock)
 160                 return ERR_PTR(-ENOMEM);
 161
 162         init.name = name;
 163         init.ops = &cpg_mstp_clock_ops;
 164         init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
 165         /* INTC-SYS is the module clock of the GIC, and must not be disabled */
 166         if (!strcmp(name, "intc-sys")) {
 167                 pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
 168                 init.flags |= CLK_IS_CRITICAL;
 169         }
 170         init.parent_names = &parent_name;
 171         init.num_parents = 1;
 172
 173         clock->bit_index = index;
 174         clock->group = group;
 175         clock->hw.init = &init;
 176
 177         clk = clk_register(NULL, &clock->hw);
 178
 179         if (IS_ERR(clk))
 180                 kfree(clock);
 181
 182         return clk;
 183 }
 184
 185 static void __init cpg_mstp_clocks_init(struct device_node *np)
 186 {
 187         struct mstp_clock_group *group;
 188         const char *idxname;
 189         struct clk **clks;
 190         unsigned int i;
 191
 192         group = kzalloc(sizeof(*group), GFP_KERNEL);
 193         clks = kmalloc_array(MSTP_MAX_CLOCKS, sizeof(*clks), GFP_KERNEL);
 194         if (group == NULL || clks == NULL) {
 195                 kfree(group);
 196                 kfree(clks);
 197                 return;
 198         }
 199
 200         spin_lock_init(&group->lock);
 201         group->data.clks = clks;
 202
 203         group->smstpcr = of_iomap(np, 0);
 204         group->mstpsr = of_iomap(np, 1);
 205
 206         if (group->smstpcr == NULL) {
 207                 pr_err("%s: failed to remap SMSTPCR\n", __func__);
 208                 kfree(group);
 209                 kfree(clks);
 210                 return;
 211         }
 212
 213         if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
 214                 group->width_8bit = true;
 215
 216         for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
 217                 clks[i] = ERR_PTR(-ENOENT);
 218
 219         if (of_find_property(np, "clock-indices", &i))
 220                 idxname = "clock-indices";
 221         else
 222                 idxname = "renesas,clock-indices";
 223
 224         for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
 225                 const char *parent_name;
 226                 const char *name;
 227                 u32 clkidx;
 228                 int ret;
 229
 230                 /* Skip clocks with no name. */
 231                 ret = of_property_read_string_index(np, "clock-output-names",
 232                                                     i, &name);
 233                 if (ret < 0 || strlen(name) == 0)
 234                         continue;
 235
 236                 parent_name = of_clk_get_parent_name(np, i);
 237                 ret = of_property_read_u32_index(np, idxname, i, &clkidx);
 238                 if (parent_name == NULL || ret < 0)
 239                         break;
 240
 241                 if (clkidx >= MSTP_MAX_CLOCKS) {
 242                         pr_err("%s: invalid clock %s %s index %u\n",
 243                                __func__, np->name, name, clkidx);
 244                         continue;
 245                 }
 246
 247                 clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
 248                                                        clkidx, group);
 249                 if (!IS_ERR(clks[clkidx])) {
 250                         group->data.clk_num = max(group->data.clk_num,
 251                                                   clkidx + 1);
 252                         /*
 253                          * Register a clkdev to let board code retrieve the
 254                          * clock by name and register aliases for non-DT
 255                          * devices.
 256                          *
 257                          * FIXME: Remove this when all devices that require a
 258                          * clock will be instantiated from DT.
 259                          */
 260                         clk_register_clkdev(clks[clkidx], name, NULL);
 261                 } else {
 262                         pr_err("%s: failed to register %s %s clock (%ld)\n",
 263                                __func__, np->name, name, PTR_ERR(clks[clkidx]));
 264                 }
 265         }
 266
 267         of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
 268 }
 269 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
 270
 271 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 272 {
 273         struct device_node *np = dev->of_node;
 274         struct of_phandle_args clkspec;
 275         struct clk *clk;
 276         int i = 0;
 277         int error;
 278
 279         while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 280                                            &clkspec)) {
 281                 if (of_device_is_compatible(clkspec.np,
 282                                             "renesas,cpg-mstp-clocks"))
 283                         goto found;
 284
 285                 /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
 286                 if (!strcmp(clkspec.np->name, "zb_clk"))
 287                         goto found;
 288
 289                 of_node_put(clkspec.np);
 290                 i++;
 291         }
 292
 293         return 0;
 294
 295 found:
 296         clk = of_clk_get_from_provider(&clkspec);
 297         of_node_put(clkspec.np);
 298
 299         if (IS_ERR(clk))
 300                 return PTR_ERR(clk);
 301
 302         error = pm_clk_create(dev);
 303         if (error) {
 304                 dev_err(dev, "pm_clk_create failed %d\n", error);
 305                 goto fail_put;
 306         }
 307
 308         error = pm_clk_add_clk(dev, clk);
 309         if (error) {
 310                 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
 311                 goto fail_destroy;
 312         }
 313
 314         return 0;
 315
 316 fail_destroy:
 317         pm_clk_destroy(dev);
 318 fail_put:
 319         clk_put(clk);
 320         return error;
 321 }
 322
 323 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
 324 {
 325         if (!pm_clk_no_clocks(dev))
 326                 pm_clk_destroy(dev);
 327 }
 328
 329 void __init cpg_mstp_add_clk_domain(struct device_node *np)
 330 {
 331         struct generic_pm_domain *pd;
 332         u32 ncells;
 333
 334         if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
 335                 pr_warn("%pOF lacks #power-domain-cells\n", np);
 336                 return;
 337         }
 338
 339         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 340         if (!pd)
 341                 return;
 342
 343         pd->name = np->name;
 344         pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
 345         pd->attach_dev = cpg_mstp_attach_dev;
 346         pd->detach_dev = cpg_mstp_detach_dev;
 347         pm_genpd_init(pd, &pm_domain_always_on_gov, false);
 348
 349         of_genpd_add_provider_simple(np, pd);
 350 }