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Linux 4.18.10
[linux/fpc-iii.git] / drivers / clk / renesas / clk-rcar-gen2.c
blobbccd62f2cb092fac27416764d4eba89d98e305ba
1 /*
2 * rcar_gen2 Core CPG Clocks
3 *
4 * Copyright (C) 2013 Ideas On Board SPRL
5 *
6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */
12
13 #include <linux/clk-provider.h>
14 #include <linux/clk/renesas.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/math64.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/soc/renesas/rcar-rst.h>
23
24 struct rcar_gen2_cpg {
25 struct clk_onecell_data data;
26 spinlock_t lock;
27 void __iomem *reg;
28 };
29
30 #define CPG_FRQCRB 0x00000004
31 #define CPG_FRQCRB_KICK BIT(31)
32 #define CPG_SDCKCR 0x00000074
33 #define CPG_PLL0CR 0x000000d8
34 #define CPG_FRQCRC 0x000000e0
35 #define CPG_FRQCRC_ZFC_MASK (0x1f << 8)
36 #define CPG_FRQCRC_ZFC_SHIFT 8
37 #define CPG_ADSPCKCR 0x0000025c
38 #define CPG_RCANCKCR 0x00000270
39
40 /* -----------------------------------------------------------------------------
41 * Z Clock
42 *
43 * Traits of this clock:
44 * prepare - clk_prepare only ensures that parents are prepared
45 * enable - clk_enable only ensures that parents are enabled
46 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
47 * parent - fixed parent. No clk_set_parent support
48 */
49
50 struct cpg_z_clk {
51 struct clk_hw hw;
52 void __iomem *reg;
53 void __iomem *kick_reg;
54 };
55
56 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
57
58 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
59 unsigned long parent_rate)
60 {
61 struct cpg_z_clk *zclk = to_z_clk(hw);
62 unsigned int mult;
63 unsigned int val;
64
65 val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
66 mult = 32 - val;
67
68 return div_u64((u64)parent_rate * mult, 32);
69 }
70
71 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
72 unsigned long *parent_rate)
73 {
74 unsigned long prate = *parent_rate;
75 unsigned int mult;
76
77 if (!prate)
78 prate = 1;
79
80 mult = div_u64((u64)rate * 32, prate);
81 mult = clamp(mult, 1U, 32U);
82
83 return *parent_rate / 32 * mult;
84 }
85
86 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
87 unsigned long parent_rate)
88 {
89 struct cpg_z_clk *zclk = to_z_clk(hw);
90 unsigned int mult;
91 u32 val, kick;
92 unsigned int i;
93
94 mult = div_u64((u64)rate * 32, parent_rate);
95 mult = clamp(mult, 1U, 32U);
96
97 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
98 return -EBUSY;
99
100 val = readl(zclk->reg);
101 val &= ~CPG_FRQCRC_ZFC_MASK;
102 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
103 writel(val, zclk->reg);
104
105 /*
106 * Set KICK bit in FRQCRB to update hardware setting and wait for
107 * clock change completion.
108 */
109 kick = readl(zclk->kick_reg);
110 kick |= CPG_FRQCRB_KICK;
111 writel(kick, zclk->kick_reg);
112
113 /*
114 * Note: There is no HW information about the worst case latency.
115 *
116 * Using experimental measurements, it seems that no more than
117 * ~10 iterations are needed, independently of the CPU rate.
118 * Since this value might be dependent on external xtal rate, pll1
119 * rate or even the other emulation clocks rate, use 1000 as a
120 * "super" safe value.
121 */
122 for (i = 1000; i; i--) {
123 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
124 return 0;
125
126 cpu_relax();
127 }
128
129 return -ETIMEDOUT;
130 }
131
132 static const struct clk_ops cpg_z_clk_ops = {
133 .recalc_rate = cpg_z_clk_recalc_rate,
134 .round_rate = cpg_z_clk_round_rate,
135 .set_rate = cpg_z_clk_set_rate,
136 };
137
138 static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
139 {
140 static const char *parent_name = "pll0";
141 struct clk_init_data init;
142 struct cpg_z_clk *zclk;
143 struct clk *clk;
144
145 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
146 if (!zclk)
147 return ERR_PTR(-ENOMEM);
148
149 init.name = "z";
150 init.ops = &cpg_z_clk_ops;
151 init.flags = 0;
152 init.parent_names = &parent_name;
153 init.num_parents = 1;
154
155 zclk->reg = cpg->reg + CPG_FRQCRC;
156 zclk->kick_reg = cpg->reg + CPG_FRQCRB;
157 zclk->hw.init = &init;
158
159 clk = clk_register(NULL, &zclk->hw);
160 if (IS_ERR(clk))
161 kfree(zclk);
162
163 return clk;
164 }
165
166 static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg,
167 struct device_node *np)
168 {
169 const char *parent_name = of_clk_get_parent_name(np, 1);
170 struct clk_fixed_factor *fixed;
171 struct clk_gate *gate;
172 struct clk *clk;
173
174 fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
175 if (!fixed)
176 return ERR_PTR(-ENOMEM);
177
178 fixed->mult = 1;
179 fixed->div = 6;
180
181 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
182 if (!gate) {
183 kfree(fixed);
184 return ERR_PTR(-ENOMEM);
185 }
186
187 gate->reg = cpg->reg + CPG_RCANCKCR;
188 gate->bit_idx = 8;
189 gate->flags = CLK_GATE_SET_TO_DISABLE;
190 gate->lock = &cpg->lock;
191
192 clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL,
193 &fixed->hw, &clk_fixed_factor_ops,
194 &gate->hw, &clk_gate_ops, 0);
195 if (IS_ERR(clk)) {
196 kfree(gate);
197 kfree(fixed);
198 }
199
200 return clk;
201 }
202
203 /* ADSP divisors */
204 static const struct clk_div_table cpg_adsp_div_table[] = {
205 { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
206 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
207 { 10, 36 }, { 11, 48 }, { 0, 0 },
208 };
209
210 static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg)
211 {
212 const char *parent_name = "pll1";
213 struct clk_divider *div;
214 struct clk_gate *gate;
215 struct clk *clk;
216
217 div = kzalloc(sizeof(*div), GFP_KERNEL);
218 if (!div)
219 return ERR_PTR(-ENOMEM);
220
221 div->reg = cpg->reg + CPG_ADSPCKCR;
222 div->width = 4;
223 div->table = cpg_adsp_div_table;
224 div->lock = &cpg->lock;
225
226 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
227 if (!gate) {
228 kfree(div);
229 return ERR_PTR(-ENOMEM);
230 }
231
232 gate->reg = cpg->reg + CPG_ADSPCKCR;
233 gate->bit_idx = 8;
234 gate->flags = CLK_GATE_SET_TO_DISABLE;
235 gate->lock = &cpg->lock;
236
237 clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL,
238 &div->hw, &clk_divider_ops,
239 &gate->hw, &clk_gate_ops, 0);
240 if (IS_ERR(clk)) {
241 kfree(gate);
242 kfree(div);
243 }
244
245 return clk;
246 }
247
248 /* -----------------------------------------------------------------------------
249 * CPG Clock Data
250 */
251
252 /*
253 * MD EXTAL PLL0 PLL1 PLL3
254 * 14 13 19 (MHz) *1 *1
255 *---------------------------------------------------
256 * 0 0 0 15 x 1 x172/2 x208/2 x106
257 * 0 0 1 15 x 1 x172/2 x208/2 x88
258 * 0 1 0 20 x 1 x130/2 x156/2 x80
259 * 0 1 1 20 x 1 x130/2 x156/2 x66
260 * 1 0 0 26 / 2 x200/2 x240/2 x122
261 * 1 0 1 26 / 2 x200/2 x240/2 x102
262 * 1 1 0 30 / 2 x172/2 x208/2 x106
263 * 1 1 1 30 / 2 x172/2 x208/2 x88
264 *
265 * *1 : Table 7.6 indicates VCO output (PLLx = VCO/2)
266 */
267 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
268 (((md) & BIT(13)) >> 12) | \
269 (((md) & BIT(19)) >> 19))
270 struct cpg_pll_config {
271 unsigned int extal_div;
272 unsigned int pll1_mult;
273 unsigned int pll3_mult;
274 unsigned int pll0_mult; /* For R-Car V2H and E2 only */
275 };
276
277 static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
278 { 1, 208, 106, 200 }, { 1, 208, 88, 200 },
279 { 1, 156, 80, 150 }, { 1, 156, 66, 150 },
280 { 2, 240, 122, 230 }, { 2, 240, 102, 230 },
281 { 2, 208, 106, 200 }, { 2, 208, 88, 200 },
282 };
283
284 /* SDHI divisors */
285 static const struct clk_div_table cpg_sdh_div_table[] = {
286 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
287 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
288 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
289 };
290
291 static const struct clk_div_table cpg_sd01_div_table[] = {
292 { 4, 8 },
293 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
294 { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
295 };
296
297 /* -----------------------------------------------------------------------------
298 * Initialization
299 */
300
301 static u32 cpg_mode __initdata;
302
303 static const char * const pll0_mult_match[] = {
304 "renesas,r8a7792-cpg-clocks",
305 "renesas,r8a7794-cpg-clocks",
306 NULL
307 };
308
309 static struct clk * __init
310 rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
311 const struct cpg_pll_config *config,
312 const char *name)
313 {
314 const struct clk_div_table *table = NULL;
315 const char *parent_name;
316 unsigned int shift;
317 unsigned int mult = 1;
318 unsigned int div = 1;
319
320 if (!strcmp(name, "main")) {
321 parent_name = of_clk_get_parent_name(np, 0);
322 div = config->extal_div;
323 } else if (!strcmp(name, "pll0")) {
324 /* PLL0 is a configurable multiplier clock. Register it as a
325 * fixed factor clock for now as there's no generic multiplier
326 * clock implementation and we currently have no need to change
327 * the multiplier value.
328 */
329 if (of_device_compatible_match(np, pll0_mult_match)) {
330 /* R-Car V2H and E2 do not have PLL0CR */
331 mult = config->pll0_mult;
332 div = 3;
333 } else {
334 u32 value = readl(cpg->reg + CPG_PLL0CR);
335 mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
336 }
337 parent_name = "main";
338 } else if (!strcmp(name, "pll1")) {
339 parent_name = "main";
340 mult = config->pll1_mult / 2;
341 } else if (!strcmp(name, "pll3")) {
342 parent_name = "main";
343 mult = config->pll3_mult;
344 } else if (!strcmp(name, "lb")) {
345 parent_name = "pll1";
346 div = cpg_mode & BIT(18) ? 36 : 24;
347 } else if (!strcmp(name, "qspi")) {
348 parent_name = "pll1_div2";
349 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
350 ? 8 : 10;
351 } else if (!strcmp(name, "sdh")) {
352 parent_name = "pll1";
353 table = cpg_sdh_div_table;
354 shift = 8;
355 } else if (!strcmp(name, "sd0")) {
356 parent_name = "pll1";
357 table = cpg_sd01_div_table;
358 shift = 4;
359 } else if (!strcmp(name, "sd1")) {
360 parent_name = "pll1";
361 table = cpg_sd01_div_table;
362 shift = 0;
363 } else if (!strcmp(name, "z")) {
364 return cpg_z_clk_register(cpg);
365 } else if (!strcmp(name, "rcan")) {
366 return cpg_rcan_clk_register(cpg, np);
367 } else if (!strcmp(name, "adsp")) {
368 return cpg_adsp_clk_register(cpg);
369 } else {
370 return ERR_PTR(-EINVAL);
371 }
372
373 if (!table)
374 return clk_register_fixed_factor(NULL, name, parent_name, 0,
375 mult, div);
376 else
377 return clk_register_divider_table(NULL, name, parent_name, 0,
378 cpg->reg + CPG_SDCKCR, shift,
379 4, 0, table, &cpg->lock);
380 }
381
382 /*
383 * Reset register definitions.
384 */
385 #define MODEMR 0xe6160060
386
387 static u32 __init rcar_gen2_read_mode_pins(void)
388 {
389 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
390 u32 mode;
391
392 BUG_ON(!modemr);
393 mode = ioread32(modemr);
394 iounmap(modemr);
395
396 return mode;
397 }
398
399 static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
400 {
401 const struct cpg_pll_config *config;
402 struct rcar_gen2_cpg *cpg;
403 struct clk **clks;
404 unsigned int i;
405 int num_clks;
406
407 if (rcar_rst_read_mode_pins(&cpg_mode)) {
408 /* Backward-compatibility with old DT */
409 pr_warn("%pOF: failed to obtain mode pins from RST\n", np);
410 cpg_mode = rcar_gen2_read_mode_pins();
411 }
412
413 num_clks = of_property_count_strings(np, "clock-output-names");
414 if (num_clks < 0) {
415 pr_err("%s: failed to count clocks\n", __func__);
416 return;
417 }
418
419 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
420 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
421 if (cpg == NULL || clks == NULL) {
422 /* We're leaking memory on purpose, there's no point in cleaning
423 * up as the system won't boot anyway.
424 */
425 return;
426 }
427
428 spin_lock_init(&cpg->lock);
429
430 cpg->data.clks = clks;
431 cpg->data.clk_num = num_clks;
432
433 cpg->reg = of_iomap(np, 0);
434 if (WARN_ON(cpg->reg == NULL))
435 return;
436
437 config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
438
439 for (i = 0; i < num_clks; ++i) {
440 const char *name;
441 struct clk *clk;
442
443 of_property_read_string_index(np, "clock-output-names", i,
444 &name);
445
446 clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
447 if (IS_ERR(clk))
448 pr_err("%s: failed to register %s %s clock (%ld)\n",
449 __func__, np->name, name, PTR_ERR(clk));
450 else
451 cpg->data.clks[i] = clk;
452 }
453
454 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
455
456 cpg_mstp_add_clk_domain(np);
457 }
458 CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
459 rcar_gen2_cpg_clocks_init);
Linux with added FPC-III support