drivers/clk/rockchip/clk-mmc-phase.c

   1 /*
   2  * Copyright 2014 Google, Inc
   3  * Author: Alexandru M Stan <amstan@chromium.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/slab.h>
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include "clk.h"
  22
  23 struct rockchip_mmc_clock {
  24         struct clk_hw   hw;
  25         void __iomem    *reg;
  26         int             id;
  27         int             shift;
  28         int             cached_phase;
  29         struct notifier_block clk_rate_change_nb;
  30 };
  31
  32 #define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
  33
  34 #define RK3288_MMC_CLKGEN_DIV 2
  35
  36 static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
  37                                          unsigned long parent_rate)
  38 {
  39         return parent_rate / RK3288_MMC_CLKGEN_DIV;
  40 }
  41
  42 #define ROCKCHIP_MMC_DELAY_SEL BIT(10)
  43 #define ROCKCHIP_MMC_DEGREE_MASK 0x3
  44 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
  45 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
  46
  47 #define PSECS_PER_SEC 1000000000000LL
  48
  49 /*
  50  * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
  51  * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
  52  */
  53 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
  54
  55 static int rockchip_mmc_get_phase(struct clk_hw *hw)
  56 {
  57         struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
  58         unsigned long rate = clk_get_rate(hw->clk);
  59         u32 raw_value;
  60         u16 degrees;
  61         u32 delay_num = 0;
  62
  63         /* See the comment for rockchip_mmc_set_phase below */
  64         if (!rate) {
  65                 pr_err("%s: invalid clk rate\n", __func__);
  66                 return -EINVAL;
  67         }
  68
  69         raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
  70
  71         degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
  72
  73         if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
  74                 /* degrees/delaynum * 10000 */
  75                 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
  76                                         36 * (rate / 1000000);
  77
  78                 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
  79                 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
  80                 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
  81         }
  82
  83         return degrees % 360;
  84 }
  85
  86 static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
  87 {
  88         struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
  89         unsigned long rate = clk_get_rate(hw->clk);
  90         u8 nineties, remainder;
  91         u8 delay_num;
  92         u32 raw_value;
  93         u32 delay;
  94
  95         /*
  96          * The below calculation is based on the output clock from
  97          * MMC host to the card, which expects the phase clock inherits
  98          * the clock rate from its parent, namely the output clock
  99          * provider of MMC host. However, things may go wrong if
 100          * (1) It is orphan.
 101          * (2) It is assigned to the wrong parent.
 102          *
 103          * This check help debug the case (1), which seems to be the
 104          * most likely problem we often face and which makes it difficult
 105          * for people to debug unstable mmc tuning results.
 106          */
 107         if (!rate) {
 108                 pr_err("%s: invalid clk rate\n", __func__);
 109                 return -EINVAL;
 110         }
 111
 112         nineties = degrees / 90;
 113         remainder = (degrees % 90);
 114
 115         /*
 116          * Due to the inexact nature of the "fine" delay, we might
 117          * actually go non-monotonic.  We don't go _too_ monotonic
 118          * though, so we should be OK.  Here are options of how we may
 119          * work:
 120          *
 121          * Ideally we end up with:
 122          *   1.0, 2.0, ..., 69.0, 70.0, ...,  89.0, 90.0
 123          *
 124          * On one extreme (if delay is actually 44ps):
 125          *   .73, 1.5, ..., 50.6, 51.3, ...,  65.3, 90.0
 126          * The other (if delay is actually 77ps):
 127          *   1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
 128          *
 129          * It's possible we might make a delay that is up to 25
 130          * degrees off from what we think we're making.  That's OK
 131          * though because we should be REALLY far from any bad range.
 132          */
 133
 134         /*
 135          * Convert to delay; do a little extra work to make sure we
 136          * don't overflow 32-bit / 64-bit numbers.
 137          */
 138         delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
 139         delay *= remainder;
 140         delay = DIV_ROUND_CLOSEST(delay,
 141                         (rate / 1000) * 36 *
 142                                 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
 143
 144         delay_num = (u8) min_t(u32, delay, 255);
 145
 146         raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
 147         raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
 148         raw_value |= nineties;
 149         writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
 150                mmc_clock->reg);
 151
 152         pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
 153                 clk_hw_get_name(hw), degrees, delay_num,
 154                 mmc_clock->reg, raw_value>>(mmc_clock->shift),
 155                 rockchip_mmc_get_phase(hw)
 156         );
 157
 158         return 0;
 159 }
 160
 161 static const struct clk_ops rockchip_mmc_clk_ops = {
 162         .recalc_rate    = rockchip_mmc_recalc,
 163         .get_phase      = rockchip_mmc_get_phase,
 164         .set_phase      = rockchip_mmc_set_phase,
 165 };
 166
 167 #define to_rockchip_mmc_clock(x) \
 168         container_of(x, struct rockchip_mmc_clock, clk_rate_change_nb)
 169 static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb,
 170                                         unsigned long event, void *data)
 171 {
 172         struct rockchip_mmc_clock *mmc_clock = to_rockchip_mmc_clock(nb);
 173         struct clk_notifier_data *ndata = data;
 174
 175         /*
 176          * rockchip_mmc_clk is mostly used by mmc controllers to sample
 177          * the intput data, which expects the fixed phase after the tuning
 178          * process. However if the clock rate is changed, the phase is stale
 179          * and may break the data sampling. So here we try to restore the phase
 180          * for that case, except that
 181          * (1) cached_phase is invaild since we inevitably cached it when the
 182          * clock provider be reparented from orphan to its real parent in the
 183          * first place. Otherwise we may mess up the initialization of MMC cards
 184          * since we only set the default sample phase and drive phase later on.
 185          * (2) the new coming rate is higher than the older one since mmc driver
 186          * set the max-frequency to match the boards' ability but we can't go
 187          * over the heads of that, otherwise the tests smoke out the issue.
 188          */
 189         if (ndata->old_rate <= ndata->new_rate)
 190                 return NOTIFY_DONE;
 191
 192         if (event == PRE_RATE_CHANGE)
 193                 mmc_clock->cached_phase =
 194                         rockchip_mmc_get_phase(&mmc_clock->hw);
 195         else if (mmc_clock->cached_phase != -EINVAL &&
 196                  event == POST_RATE_CHANGE)
 197                 rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);
 198
 199         return NOTIFY_DONE;
 200 }
 201
 202 struct clk *rockchip_clk_register_mmc(const char *name,
 203                                 const char *const *parent_names, u8 num_parents,
 204                                 void __iomem *reg, int shift)
 205 {
 206         struct clk_init_data init;
 207         struct rockchip_mmc_clock *mmc_clock;
 208         struct clk *clk;
 209         int ret;
 210
 211         mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
 212         if (!mmc_clock)
 213                 return ERR_PTR(-ENOMEM);
 214
 215         init.name = name;
 216         init.flags = 0;
 217         init.num_parents = num_parents;
 218         init.parent_names = parent_names;
 219         init.ops = &rockchip_mmc_clk_ops;
 220
 221         mmc_clock->hw.init = &init;
 222         mmc_clock->reg = reg;
 223         mmc_clock->shift = shift;
 224
 225         clk = clk_register(NULL, &mmc_clock->hw);
 226         if (IS_ERR(clk)) {
 227                 ret = PTR_ERR(clk);
 228                 goto err_register;
 229         }
 230
 231         mmc_clock->clk_rate_change_nb.notifier_call =
 232                                 &rockchip_mmc_clk_rate_notify;
 233         ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);
 234         if (ret)
 235                 goto err_notifier;
 236
 237         return clk;
 238 err_notifier:
 239         clk_unregister(clk);
 240 err_register:
 241         kfree(mmc_clock);
 242         return ERR_PTR(ret);
 243 }