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Linux 4.18.10
[linux/fpc-iii.git] / drivers / clk / samsung / clk-exynos5433.c
blob162de44df099bff5be3a70e4fd5b010e1fc584f5
1 /*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5433 SoC.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19
20 #include <dt-bindings/clock/exynos5433.h>
21
22 #include "clk.h"
23 #include "clk-cpu.h"
24 #include "clk-pll.h"
25
26 /*
27 * Register offset definitions for CMU_TOP
28 */
29 #define ISP_PLL_LOCK 0x0000
30 #define AUD_PLL_LOCK 0x0004
31 #define ISP_PLL_CON0 0x0100
32 #define ISP_PLL_CON1 0x0104
33 #define ISP_PLL_FREQ_DET 0x0108
34 #define AUD_PLL_CON0 0x0110
35 #define AUD_PLL_CON1 0x0114
36 #define AUD_PLL_CON2 0x0118
37 #define AUD_PLL_FREQ_DET 0x011c
38 #define MUX_SEL_TOP0 0x0200
39 #define MUX_SEL_TOP1 0x0204
40 #define MUX_SEL_TOP2 0x0208
41 #define MUX_SEL_TOP3 0x020c
42 #define MUX_SEL_TOP4 0x0210
43 #define MUX_SEL_TOP_MSCL 0x0220
44 #define MUX_SEL_TOP_CAM1 0x0224
45 #define MUX_SEL_TOP_DISP 0x0228
46 #define MUX_SEL_TOP_FSYS0 0x0230
47 #define MUX_SEL_TOP_FSYS1 0x0234
48 #define MUX_SEL_TOP_PERIC0 0x0238
49 #define MUX_SEL_TOP_PERIC1 0x023c
50 #define MUX_ENABLE_TOP0 0x0300
51 #define MUX_ENABLE_TOP1 0x0304
52 #define MUX_ENABLE_TOP2 0x0308
53 #define MUX_ENABLE_TOP3 0x030c
54 #define MUX_ENABLE_TOP4 0x0310
55 #define MUX_ENABLE_TOP_MSCL 0x0320
56 #define MUX_ENABLE_TOP_CAM1 0x0324
57 #define MUX_ENABLE_TOP_DISP 0x0328
58 #define MUX_ENABLE_TOP_FSYS0 0x0330
59 #define MUX_ENABLE_TOP_FSYS1 0x0334
60 #define MUX_ENABLE_TOP_PERIC0 0x0338
61 #define MUX_ENABLE_TOP_PERIC1 0x033c
62 #define MUX_STAT_TOP0 0x0400
63 #define MUX_STAT_TOP1 0x0404
64 #define MUX_STAT_TOP2 0x0408
65 #define MUX_STAT_TOP3 0x040c
66 #define MUX_STAT_TOP4 0x0410
67 #define MUX_STAT_TOP_MSCL 0x0420
68 #define MUX_STAT_TOP_CAM1 0x0424
69 #define MUX_STAT_TOP_FSYS0 0x0430
70 #define MUX_STAT_TOP_FSYS1 0x0434
71 #define MUX_STAT_TOP_PERIC0 0x0438
72 #define MUX_STAT_TOP_PERIC1 0x043c
73 #define DIV_TOP0 0x0600
74 #define DIV_TOP1 0x0604
75 #define DIV_TOP2 0x0608
76 #define DIV_TOP3 0x060c
77 #define DIV_TOP4 0x0610
78 #define DIV_TOP_MSCL 0x0618
79 #define DIV_TOP_CAM10 0x061c
80 #define DIV_TOP_CAM11 0x0620
81 #define DIV_TOP_FSYS0 0x062c
82 #define DIV_TOP_FSYS1 0x0630
83 #define DIV_TOP_FSYS2 0x0634
84 #define DIV_TOP_PERIC0 0x0638
85 #define DIV_TOP_PERIC1 0x063c
86 #define DIV_TOP_PERIC2 0x0640
87 #define DIV_TOP_PERIC3 0x0644
88 #define DIV_TOP_PERIC4 0x0648
89 #define DIV_TOP_PLL_FREQ_DET 0x064c
90 #define DIV_STAT_TOP0 0x0700
91 #define DIV_STAT_TOP1 0x0704
92 #define DIV_STAT_TOP2 0x0708
93 #define DIV_STAT_TOP3 0x070c
94 #define DIV_STAT_TOP4 0x0710
95 #define DIV_STAT_TOP_MSCL 0x0718
96 #define DIV_STAT_TOP_CAM10 0x071c
97 #define DIV_STAT_TOP_CAM11 0x0720
98 #define DIV_STAT_TOP_FSYS0 0x072c
99 #define DIV_STAT_TOP_FSYS1 0x0730
100 #define DIV_STAT_TOP_FSYS2 0x0734
101 #define DIV_STAT_TOP_PERIC0 0x0738
102 #define DIV_STAT_TOP_PERIC1 0x073c
103 #define DIV_STAT_TOP_PERIC2 0x0740
104 #define DIV_STAT_TOP_PERIC3 0x0744
105 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
106 #define ENABLE_ACLK_TOP 0x0800
107 #define ENABLE_SCLK_TOP 0x0a00
108 #define ENABLE_SCLK_TOP_MSCL 0x0a04
109 #define ENABLE_SCLK_TOP_CAM1 0x0a08
110 #define ENABLE_SCLK_TOP_DISP 0x0a0c
111 #define ENABLE_SCLK_TOP_FSYS 0x0a10
112 #define ENABLE_SCLK_TOP_PERIC 0x0a14
113 #define ENABLE_IP_TOP 0x0b00
114 #define ENABLE_CMU_TOP 0x0c00
115 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
116
117 static const unsigned long top_clk_regs[] __initconst = {
118 ISP_PLL_LOCK,
119 AUD_PLL_LOCK,
120 ISP_PLL_CON0,
121 ISP_PLL_CON1,
122 ISP_PLL_FREQ_DET,
123 AUD_PLL_CON0,
124 AUD_PLL_CON1,
125 AUD_PLL_CON2,
126 AUD_PLL_FREQ_DET,
127 MUX_SEL_TOP0,
128 MUX_SEL_TOP1,
129 MUX_SEL_TOP2,
130 MUX_SEL_TOP3,
131 MUX_SEL_TOP4,
132 MUX_SEL_TOP_MSCL,
133 MUX_SEL_TOP_CAM1,
134 MUX_SEL_TOP_DISP,
135 MUX_SEL_TOP_FSYS0,
136 MUX_SEL_TOP_FSYS1,
137 MUX_SEL_TOP_PERIC0,
138 MUX_SEL_TOP_PERIC1,
139 MUX_ENABLE_TOP0,
140 MUX_ENABLE_TOP1,
141 MUX_ENABLE_TOP2,
142 MUX_ENABLE_TOP3,
143 MUX_ENABLE_TOP4,
144 MUX_ENABLE_TOP_MSCL,
145 MUX_ENABLE_TOP_CAM1,
146 MUX_ENABLE_TOP_DISP,
147 MUX_ENABLE_TOP_FSYS0,
148 MUX_ENABLE_TOP_FSYS1,
149 MUX_ENABLE_TOP_PERIC0,
150 MUX_ENABLE_TOP_PERIC1,
151 DIV_TOP0,
152 DIV_TOP1,
153 DIV_TOP2,
154 DIV_TOP3,
155 DIV_TOP4,
156 DIV_TOP_MSCL,
157 DIV_TOP_CAM10,
158 DIV_TOP_CAM11,
159 DIV_TOP_FSYS0,
160 DIV_TOP_FSYS1,
161 DIV_TOP_FSYS2,
162 DIV_TOP_PERIC0,
163 DIV_TOP_PERIC1,
164 DIV_TOP_PERIC2,
165 DIV_TOP_PERIC3,
166 DIV_TOP_PERIC4,
167 DIV_TOP_PLL_FREQ_DET,
168 ENABLE_ACLK_TOP,
169 ENABLE_SCLK_TOP,
170 ENABLE_SCLK_TOP_MSCL,
171 ENABLE_SCLK_TOP_CAM1,
172 ENABLE_SCLK_TOP_DISP,
173 ENABLE_SCLK_TOP_FSYS,
174 ENABLE_SCLK_TOP_PERIC,
175 ENABLE_IP_TOP,
176 ENABLE_CMU_TOP,
177 ENABLE_CMU_TOP_DIV_STAT,
178 };
179
180 /* list of all parent clock list */
181 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
182 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
183 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
184 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
185 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
186 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
187 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
188 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
189
190 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
191 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
192 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
193 "mout_mfc_pll_user", };
194 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
195
196 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
197 "mout_mphy_pll_user", };
198 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
199 "mout_bus_pll_user", };
200 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
201
202 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
203 "mout_mphy_pll_user", };
204 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
205 "mout_mphy_pll_user", };
206 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
207 "mout_mphy_pll_user", };
208
209 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
210 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
211
212 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
213 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
214 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
215 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
216 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
217
218 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
219 "oscclk", "ioclk_spdif_extclk", };
220 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
221 "mout_aud_pll_user_t",};
222 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
223 "mout_aud_pll_user_t",};
224
225 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
226
227 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
228 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
229 };
230
231 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
232 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
233 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
234 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
235 /* Xi2s1SDI input clock for SPDIF */
236 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
237 /* XspiCLK[4:0] input clock for SPI */
238 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
239 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
240 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
241 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
242 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
243 /* Xi2s1SCLK input clock for I2S1_BCLK */
244 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
245 };
246
247 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
248 /* MUX_SEL_TOP0 */
249 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
250 4, 1),
251 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
252 0, 1),
253
254 /* MUX_SEL_TOP1 */
255 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
256 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
257 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
258 MUX_SEL_TOP1, 8, 1),
259 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
260 MUX_SEL_TOP1, 4, 1),
261 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
262 MUX_SEL_TOP1, 0, 1),
263
264 /* MUX_SEL_TOP2 */
265 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
266 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
267 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
268 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
269 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
270 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
271 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
272 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
273 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
274 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
275 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
276 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
277
278 /* MUX_SEL_TOP3 */
279 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
280 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
281 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
282 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
283 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
284 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
285 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
286 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
287 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
288 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
289 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
290 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
291
292 /* MUX_SEL_TOP4 */
293 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
294 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
295 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
296 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
297 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
298 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
299
300 /* MUX_SEL_TOP_MSCL */
301 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
302 MUX_SEL_TOP_MSCL, 8, 1),
303 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
304 MUX_SEL_TOP_MSCL, 4, 1),
305 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
306 MUX_SEL_TOP_MSCL, 0, 1),
307
308 /* MUX_SEL_TOP_CAM1 */
309 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
310 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
311 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
312 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
313 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
314 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
315 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
316 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
317 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
318 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
319 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
320 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
321
322 /* MUX_SEL_TOP_FSYS0 */
323 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
324 MUX_SEL_TOP_FSYS0, 28, 1),
325 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
326 MUX_SEL_TOP_FSYS0, 24, 1),
327 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
328 MUX_SEL_TOP_FSYS0, 20, 1),
329 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
330 MUX_SEL_TOP_FSYS0, 16, 1),
331 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
332 MUX_SEL_TOP_FSYS0, 12, 1),
333 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
334 MUX_SEL_TOP_FSYS0, 8, 1),
335 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
336 MUX_SEL_TOP_FSYS0, 4, 1),
337 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
338 MUX_SEL_TOP_FSYS0, 0, 1),
339
340 /* MUX_SEL_TOP_FSYS1 */
341 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
342 MUX_SEL_TOP_FSYS1, 12, 1),
343 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
344 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
345 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
346 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
347 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
348 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
349
350 /* MUX_SEL_TOP_PERIC0 */
351 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
352 MUX_SEL_TOP_PERIC0, 28, 1),
353 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
354 MUX_SEL_TOP_PERIC0, 24, 1),
355 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
356 MUX_SEL_TOP_PERIC0, 20, 1),
357 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
358 MUX_SEL_TOP_PERIC0, 16, 1),
359 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
360 MUX_SEL_TOP_PERIC0, 12, 1),
361 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
362 MUX_SEL_TOP_PERIC0, 8, 1),
363 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
364 MUX_SEL_TOP_PERIC0, 4, 1),
365 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
366 MUX_SEL_TOP_PERIC0, 0, 1),
367
368 /* MUX_SEL_TOP_PERIC1 */
369 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
370 MUX_SEL_TOP_PERIC1, 16, 1),
371 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
372 MUX_SEL_TOP_PERIC1, 12, 2),
373 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
374 MUX_SEL_TOP_PERIC1, 4, 2),
375 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
376 MUX_SEL_TOP_PERIC1, 0, 2),
377
378 /* MUX_SEL_TOP_DISP */
379 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
380 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
381 };
382
383 static const struct samsung_div_clock top_div_clks[] __initconst = {
384 /* DIV_TOP0 */
385 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
386 DIV_TOP0, 28, 3),
387 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
388 DIV_TOP0, 24, 3),
389 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
390 DIV_TOP0, 20, 3),
391 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
392 DIV_TOP0, 16, 3),
393 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
394 DIV_TOP0, 12, 3),
395 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
396 DIV_TOP0, 8, 3),
397 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
398 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
399 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
400 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
401
402 /* DIV_TOP1 */
403 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
404 DIV_TOP1, 28, 3),
405 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
406 DIV_TOP1, 24, 3),
407 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
408 DIV_TOP1, 20, 3),
409 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
410 DIV_TOP1, 12, 3),
411 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
412 DIV_TOP1, 8, 3),
413 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
414 DIV_TOP1, 0, 3),
415
416 /* DIV_TOP2 */
417 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
418 DIV_TOP2, 4, 3),
419 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
420 DIV_TOP2, 0, 3),
421
422 /* DIV_TOP3 */
423 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
424 "mout_bus_pll_user", DIV_TOP3, 24, 3),
425 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
426 "mout_bus_pll_user", DIV_TOP3, 20, 3),
427 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
428 "mout_bus_pll_user", DIV_TOP3, 16, 3),
429 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
430 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
431 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
432 "mout_bus_pll_user", DIV_TOP3, 8, 3),
433 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
434 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
435 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
436 "mout_bus_pll_user", DIV_TOP3, 0, 3),
437
438 /* DIV_TOP4 */
439 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
440 DIV_TOP4, 8, 3),
441 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
442 DIV_TOP4, 4, 3),
443 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
444 DIV_TOP4, 0, 3),
445
446 /* DIV_TOP_MSCL */
447 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
448 DIV_TOP_MSCL, 0, 4),
449
450 /* DIV_TOP_CAM10 */
451 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
452 DIV_TOP_CAM10, 24, 5),
453 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
454 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
455 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
456 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
457 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
458 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
459 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
460 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
461
462 /* DIV_TOP_CAM11 */
463 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
464 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
465 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
466 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
467 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
468 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
469 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
470 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
471 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
472 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
473 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
474 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
475
476 /* DIV_TOP_FSYS0 */
477 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
478 DIV_TOP_FSYS0, 16, 8),
479 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
480 DIV_TOP_FSYS0, 12, 4),
481 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
482 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
483 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
484 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
485
486 /* DIV_TOP_FSYS1 */
487 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
488 DIV_TOP_FSYS1, 4, 8),
489 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
490 DIV_TOP_FSYS1, 0, 4),
491
492 /* DIV_TOP_FSYS2 */
493 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
494 DIV_TOP_FSYS2, 12, 3),
495 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
496 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
497 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
498 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
499 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
500 DIV_TOP_FSYS2, 0, 4),
501
502 /* DIV_TOP_PERIC0 */
503 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
504 DIV_TOP_PERIC0, 16, 8),
505 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
506 DIV_TOP_PERIC0, 12, 4),
507 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
508 DIV_TOP_PERIC0, 4, 8),
509 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
510 DIV_TOP_PERIC0, 0, 4),
511
512 /* DIV_TOP_PERIC1 */
513 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
514 DIV_TOP_PERIC1, 4, 8),
515 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
516 DIV_TOP_PERIC1, 0, 4),
517
518 /* DIV_TOP_PERIC2 */
519 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
520 DIV_TOP_PERIC2, 8, 4),
521 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
522 DIV_TOP_PERIC2, 4, 4),
523 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
524 DIV_TOP_PERIC2, 0, 4),
525
526 /* DIV_TOP_PERIC3 */
527 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
528 DIV_TOP_PERIC3, 16, 6),
529 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
530 DIV_TOP_PERIC3, 8, 8),
531 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
532 DIV_TOP_PERIC3, 4, 4),
533 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
534 DIV_TOP_PERIC3, 0, 4),
535
536 /* DIV_TOP_PERIC4 */
537 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
538 DIV_TOP_PERIC4, 16, 8),
539 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
540 DIV_TOP_PERIC4, 12, 4),
541 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
542 DIV_TOP_PERIC4, 4, 8),
543 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
544 DIV_TOP_PERIC4, 0, 4),
545 };
546
547 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
548 /* ENABLE_ACLK_TOP */
549 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
550 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
551 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
552 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
553 29, CLK_IGNORE_UNUSED, 0),
554 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
555 ENABLE_ACLK_TOP, 26,
556 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
557 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
558 ENABLE_ACLK_TOP, 25,
559 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
560 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
561 ENABLE_ACLK_TOP, 24,
562 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
563 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
564 ENABLE_ACLK_TOP, 23,
565 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
566 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
567 ENABLE_ACLK_TOP, 22,
568 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
569 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
570 ENABLE_ACLK_TOP, 21,
571 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
572 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
573 ENABLE_ACLK_TOP, 19,
574 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
575 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
576 ENABLE_ACLK_TOP, 18,
577 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
578 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
579 ENABLE_ACLK_TOP, 15,
580 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
581 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
582 ENABLE_ACLK_TOP, 14,
583 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
584 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
585 ENABLE_ACLK_TOP, 13,
586 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
587 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
588 ENABLE_ACLK_TOP, 12,
589 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
590 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
591 ENABLE_ACLK_TOP, 11,
592 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
593 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
594 ENABLE_ACLK_TOP, 10,
595 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
596 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
597 ENABLE_ACLK_TOP, 9,
598 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
599 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
600 ENABLE_ACLK_TOP, 8,
601 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
602 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
603 ENABLE_ACLK_TOP, 7,
604 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
605 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
606 ENABLE_ACLK_TOP, 6,
607 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
608 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
609 ENABLE_ACLK_TOP, 5,
610 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
611 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
612 ENABLE_ACLK_TOP, 3,
613 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
614 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
615 ENABLE_ACLK_TOP, 2,
616 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
617 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
618 ENABLE_ACLK_TOP, 0,
619 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
620
621 /* ENABLE_SCLK_TOP_MSCL */
622 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
623 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
624
625 /* ENABLE_SCLK_TOP_CAM1 */
626 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
627 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
628 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
629 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
630 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
631 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
632 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
633 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
634 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
635 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
636 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
637 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
638 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
639 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
640
641 /* ENABLE_SCLK_TOP_DISP */
642 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
643 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
644 CLK_IGNORE_UNUSED, 0),
645
646 /* ENABLE_SCLK_TOP_FSYS */
647 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
648 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
649 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
650 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
651 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
652 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
653 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
654 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
655 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
656 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
657 3, CLK_SET_RATE_PARENT, 0),
658 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
659 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
660 1, CLK_SET_RATE_PARENT, 0),
661 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
662 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
663 0, CLK_SET_RATE_PARENT, 0),
664
665 /* ENABLE_SCLK_TOP_PERIC */
666 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
667 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
668 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
669 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
670 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
671 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
672 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
673 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
674 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
675 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
676 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
677 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
678 CLK_IGNORE_UNUSED, 0),
679 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
680 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
681 CLK_IGNORE_UNUSED, 0),
682 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
683 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
684 CLK_IGNORE_UNUSED, 0),
685 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
686 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
687 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
688 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
689 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
690 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
691
692 /* MUX_ENABLE_TOP_PERIC1 */
693 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
694 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
695 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
696 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
697 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
698 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
699 };
700
701 /*
702 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
703 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
704 */
705 static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
706 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
707 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
708 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
709 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
710 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
711 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
712 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
713 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
714 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
715 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
716 PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0),
717 PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0),
718 PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0),
719 PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0),
720 PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5, 1),
721 PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6, 1),
722 PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4, 1),
723 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6, 1),
724 PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6, 1),
725 PLL_35XX_RATE(24 * MHZ, 933000000U, 311, 4, 1),
726 PLL_35XX_RATE(24 * MHZ, 921000000U, 307, 4, 1),
727 PLL_35XX_RATE(24 * MHZ, 900000000U, 375, 5, 1),
728 PLL_35XX_RATE(24 * MHZ, 825000000U, 275, 4, 1),
729 PLL_35XX_RATE(24 * MHZ, 800000000U, 400, 6, 1),
730 PLL_35XX_RATE(24 * MHZ, 733000000U, 733, 12, 1),
731 PLL_35XX_RATE(24 * MHZ, 700000000U, 175, 3, 1),
732 PLL_35XX_RATE(24 * MHZ, 666000000U, 222, 4, 1),
733 PLL_35XX_RATE(24 * MHZ, 633000000U, 211, 4, 1),
734 PLL_35XX_RATE(24 * MHZ, 600000000U, 500, 5, 2),
735 PLL_35XX_RATE(24 * MHZ, 552000000U, 460, 5, 2),
736 PLL_35XX_RATE(24 * MHZ, 550000000U, 550, 6, 2),
737 PLL_35XX_RATE(24 * MHZ, 543000000U, 362, 4, 2),
738 PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2),
739 PLL_35XX_RATE(24 * MHZ, 500000000U, 500, 6, 2),
740 PLL_35XX_RATE(24 * MHZ, 444000000U, 370, 5, 2),
741 PLL_35XX_RATE(24 * MHZ, 420000000U, 350, 5, 2),
742 PLL_35XX_RATE(24 * MHZ, 400000000U, 400, 6, 2),
743 PLL_35XX_RATE(24 * MHZ, 350000000U, 350, 6, 2),
744 PLL_35XX_RATE(24 * MHZ, 333000000U, 222, 4, 2),
745 PLL_35XX_RATE(24 * MHZ, 300000000U, 500, 5, 3),
746 PLL_35XX_RATE(24 * MHZ, 278000000U, 556, 6, 3),
747 PLL_35XX_RATE(24 * MHZ, 266000000U, 532, 6, 3),
748 PLL_35XX_RATE(24 * MHZ, 250000000U, 500, 6, 3),
749 PLL_35XX_RATE(24 * MHZ, 200000000U, 400, 6, 3),
750 PLL_35XX_RATE(24 * MHZ, 166000000U, 332, 6, 3),
751 PLL_35XX_RATE(24 * MHZ, 160000000U, 320, 6, 3),
752 PLL_35XX_RATE(24 * MHZ, 133000000U, 532, 6, 4),
753 PLL_35XX_RATE(24 * MHZ, 100000000U, 400, 6, 4),
754 { /* sentinel */ }
755 };
756
757 /* AUD_PLL */
758 static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
759 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
760 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
761 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
762 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
763 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
764 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
765 PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923),
766 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
767 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
768 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
769 { /* sentinel */ }
770 };
771
772 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
773 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
774 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates),
775 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
776 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates),
777 };
778
779 static const struct samsung_cmu_info top_cmu_info __initconst = {
780 .pll_clks = top_pll_clks,
781 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
782 .mux_clks = top_mux_clks,
783 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
784 .div_clks = top_div_clks,
785 .nr_div_clks = ARRAY_SIZE(top_div_clks),
786 .gate_clks = top_gate_clks,
787 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
788 .fixed_clks = top_fixed_clks,
789 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
790 .fixed_factor_clks = top_fixed_factor_clks,
791 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
792 .nr_clk_ids = TOP_NR_CLK,
793 .clk_regs = top_clk_regs,
794 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
795 };
796
797 static void __init exynos5433_cmu_top_init(struct device_node *np)
798 {
799 samsung_cmu_register_one(np, &top_cmu_info);
800 }
801 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
802 exynos5433_cmu_top_init);
803
804 /*
805 * Register offset definitions for CMU_CPIF
806 */
807 #define MPHY_PLL_LOCK 0x0000
808 #define MPHY_PLL_CON0 0x0100
809 #define MPHY_PLL_CON1 0x0104
810 #define MPHY_PLL_FREQ_DET 0x010c
811 #define MUX_SEL_CPIF0 0x0200
812 #define DIV_CPIF 0x0600
813 #define ENABLE_SCLK_CPIF 0x0a00
814
815 static const unsigned long cpif_clk_regs[] __initconst = {
816 MPHY_PLL_LOCK,
817 MPHY_PLL_CON0,
818 MPHY_PLL_CON1,
819 MPHY_PLL_FREQ_DET,
820 MUX_SEL_CPIF0,
821 DIV_CPIF,
822 ENABLE_SCLK_CPIF,
823 };
824
825 /* list of all parent clock list */
826 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
827
828 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
829 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
830 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates),
831 };
832
833 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
834 /* MUX_SEL_CPIF0 */
835 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
836 0, 1),
837 };
838
839 static const struct samsung_div_clock cpif_div_clks[] __initconst = {
840 /* DIV_CPIF */
841 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
842 0, 6),
843 };
844
845 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
846 /* ENABLE_SCLK_CPIF */
847 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
848 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
849 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
850 ENABLE_SCLK_CPIF, 4, 0, 0),
851 };
852
853 static const struct samsung_cmu_info cpif_cmu_info __initconst = {
854 .pll_clks = cpif_pll_clks,
855 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
856 .mux_clks = cpif_mux_clks,
857 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
858 .div_clks = cpif_div_clks,
859 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
860 .gate_clks = cpif_gate_clks,
861 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
862 .nr_clk_ids = CPIF_NR_CLK,
863 .clk_regs = cpif_clk_regs,
864 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
865 };
866
867 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
868 {
869 samsung_cmu_register_one(np, &cpif_cmu_info);
870 }
871 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
872 exynos5433_cmu_cpif_init);
873
874 /*
875 * Register offset definitions for CMU_MIF
876 */
877 #define MEM0_PLL_LOCK 0x0000
878 #define MEM1_PLL_LOCK 0x0004
879 #define BUS_PLL_LOCK 0x0008
880 #define MFC_PLL_LOCK 0x000c
881 #define MEM0_PLL_CON0 0x0100
882 #define MEM0_PLL_CON1 0x0104
883 #define MEM0_PLL_FREQ_DET 0x010c
884 #define MEM1_PLL_CON0 0x0110
885 #define MEM1_PLL_CON1 0x0114
886 #define MEM1_PLL_FREQ_DET 0x011c
887 #define BUS_PLL_CON0 0x0120
888 #define BUS_PLL_CON1 0x0124
889 #define BUS_PLL_FREQ_DET 0x012c
890 #define MFC_PLL_CON0 0x0130
891 #define MFC_PLL_CON1 0x0134
892 #define MFC_PLL_FREQ_DET 0x013c
893 #define MUX_SEL_MIF0 0x0200
894 #define MUX_SEL_MIF1 0x0204
895 #define MUX_SEL_MIF2 0x0208
896 #define MUX_SEL_MIF3 0x020c
897 #define MUX_SEL_MIF4 0x0210
898 #define MUX_SEL_MIF5 0x0214
899 #define MUX_SEL_MIF6 0x0218
900 #define MUX_SEL_MIF7 0x021c
901 #define MUX_ENABLE_MIF0 0x0300
902 #define MUX_ENABLE_MIF1 0x0304
903 #define MUX_ENABLE_MIF2 0x0308
904 #define MUX_ENABLE_MIF3 0x030c
905 #define MUX_ENABLE_MIF4 0x0310
906 #define MUX_ENABLE_MIF5 0x0314
907 #define MUX_ENABLE_MIF6 0x0318
908 #define MUX_ENABLE_MIF7 0x031c
909 #define MUX_STAT_MIF0 0x0400
910 #define MUX_STAT_MIF1 0x0404
911 #define MUX_STAT_MIF2 0x0408
912 #define MUX_STAT_MIF3 0x040c
913 #define MUX_STAT_MIF4 0x0410
914 #define MUX_STAT_MIF5 0x0414
915 #define MUX_STAT_MIF6 0x0418
916 #define MUX_STAT_MIF7 0x041c
917 #define DIV_MIF1 0x0604
918 #define DIV_MIF2 0x0608
919 #define DIV_MIF3 0x060c
920 #define DIV_MIF4 0x0610
921 #define DIV_MIF5 0x0614
922 #define DIV_MIF_PLL_FREQ_DET 0x0618
923 #define DIV_STAT_MIF1 0x0704
924 #define DIV_STAT_MIF2 0x0708
925 #define DIV_STAT_MIF3 0x070c
926 #define DIV_STAT_MIF4 0x0710
927 #define DIV_STAT_MIF5 0x0714
928 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
929 #define ENABLE_ACLK_MIF0 0x0800
930 #define ENABLE_ACLK_MIF1 0x0804
931 #define ENABLE_ACLK_MIF2 0x0808
932 #define ENABLE_ACLK_MIF3 0x080c
933 #define ENABLE_PCLK_MIF 0x0900
934 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
935 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
936 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
937 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
938 #define ENABLE_SCLK_MIF 0x0a00
939 #define ENABLE_IP_MIF0 0x0b00
940 #define ENABLE_IP_MIF1 0x0b04
941 #define ENABLE_IP_MIF2 0x0b08
942 #define ENABLE_IP_MIF3 0x0b0c
943 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
944 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
945 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
946 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
947 #define CLKOUT_CMU_MIF 0x0c00
948 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
949 #define DREX_FREQ_CTRL0 0x1000
950 #define DREX_FREQ_CTRL1 0x1004
951 #define PAUSE 0x1008
952 #define DDRPHY_LOCK_CTRL 0x100c
953
954 static const unsigned long mif_clk_regs[] __initconst = {
955 MEM0_PLL_LOCK,
956 MEM1_PLL_LOCK,
957 BUS_PLL_LOCK,
958 MFC_PLL_LOCK,
959 MEM0_PLL_CON0,
960 MEM0_PLL_CON1,
961 MEM0_PLL_FREQ_DET,
962 MEM1_PLL_CON0,
963 MEM1_PLL_CON1,
964 MEM1_PLL_FREQ_DET,
965 BUS_PLL_CON0,
966 BUS_PLL_CON1,
967 BUS_PLL_FREQ_DET,
968 MFC_PLL_CON0,
969 MFC_PLL_CON1,
970 MFC_PLL_FREQ_DET,
971 MUX_SEL_MIF0,
972 MUX_SEL_MIF1,
973 MUX_SEL_MIF2,
974 MUX_SEL_MIF3,
975 MUX_SEL_MIF4,
976 MUX_SEL_MIF5,
977 MUX_SEL_MIF6,
978 MUX_SEL_MIF7,
979 MUX_ENABLE_MIF0,
980 MUX_ENABLE_MIF1,
981 MUX_ENABLE_MIF2,
982 MUX_ENABLE_MIF3,
983 MUX_ENABLE_MIF4,
984 MUX_ENABLE_MIF5,
985 MUX_ENABLE_MIF6,
986 MUX_ENABLE_MIF7,
987 DIV_MIF1,
988 DIV_MIF2,
989 DIV_MIF3,
990 DIV_MIF4,
991 DIV_MIF5,
992 DIV_MIF_PLL_FREQ_DET,
993 ENABLE_ACLK_MIF0,
994 ENABLE_ACLK_MIF1,
995 ENABLE_ACLK_MIF2,
996 ENABLE_ACLK_MIF3,
997 ENABLE_PCLK_MIF,
998 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
999 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1000 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1001 ENABLE_PCLK_MIF_SECURE_RTC,
1002 ENABLE_SCLK_MIF,
1003 ENABLE_IP_MIF0,
1004 ENABLE_IP_MIF1,
1005 ENABLE_IP_MIF2,
1006 ENABLE_IP_MIF3,
1007 ENABLE_IP_MIF_SECURE_DREX0_TZ,
1008 ENABLE_IP_MIF_SECURE_DREX1_TZ,
1009 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1010 ENABLE_IP_MIF_SECURE_RTC,
1011 CLKOUT_CMU_MIF,
1012 CLKOUT_CMU_MIF_DIV_STAT,
1013 DREX_FREQ_CTRL0,
1014 DREX_FREQ_CTRL1,
1015 PAUSE,
1016 DDRPHY_LOCK_CTRL,
1017 };
1018
1019 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1020 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1021 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates),
1022 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1023 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates),
1024 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1025 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates),
1026 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1027 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates),
1028 };
1029
1030 /* list of all parent clock list */
1031 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
1032 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
1033 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
1034 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
1035 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
1036 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
1037 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
1038 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
1039
1040 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1041 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1042 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1043 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1044
1045 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
1046 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1047
1048 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
1049 "mout_bus_pll_div2", };
1050 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1051
1052 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1053 "sclk_mphy_pll", };
1054 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1055 "mout_mfc_pll_div2", };
1056 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
1057 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1058 "sclk_mphy_pll", };
1059 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1060 "mout_mfc_pll_div2", };
1061
1062 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1063 "sclk_mphy_pll", };
1064 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1065 "mout_mfc_pll_div2", };
1066 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1067 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1068 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1069
1070 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1071 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1072
1073 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1074 "sclk_mphy_pll", };
1075 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1076 "mout_mfc_pll_div2", };
1077 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1078 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1079
1080 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1081 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1082 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1083 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1084 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1085 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1086 };
1087
1088 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1089 /* MUX_SEL_MIF0 */
1090 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1091 MUX_SEL_MIF0, 28, 1),
1092 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1093 MUX_SEL_MIF0, 24, 1),
1094 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1095 MUX_SEL_MIF0, 20, 1),
1096 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1097 MUX_SEL_MIF0, 16, 1),
1098 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1099 12, 1),
1100 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1101 8, 1),
1102 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1103 4, 1),
1104 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1105 0, 1),
1106
1107 /* MUX_SEL_MIF1 */
1108 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1109 MUX_SEL_MIF1, 24, 1),
1110 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1111 MUX_SEL_MIF1, 20, 1),
1112 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1113 MUX_SEL_MIF1, 16, 1),
1114 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1115 MUX_SEL_MIF1, 12, 1),
1116 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1117 MUX_SEL_MIF1, 8, 1),
1118 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1119 MUX_SEL_MIF1, 4, 1),
1120
1121 /* MUX_SEL_MIF2 */
1122 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1123 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1124 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1125 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1126
1127 /* MUX_SEL_MIF3 */
1128 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1129 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1130 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1131 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1132
1133 /* MUX_SEL_MIF4 */
1134 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1135 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1136 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1137 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1138 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1139 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1140 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1141 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1142 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1143 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1144 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1145 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1146
1147 /* MUX_SEL_MIF5 */
1148 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1149 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1150 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1151 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1152 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1153 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1154 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1155 MUX_SEL_MIF5, 8, 1),
1156 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1157 MUX_SEL_MIF5, 4, 1),
1158 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1159 MUX_SEL_MIF5, 0, 1),
1160
1161 /* MUX_SEL_MIF6 */
1162 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1163 MUX_SEL_MIF6, 8, 1),
1164 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1165 MUX_SEL_MIF6, 4, 1),
1166 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1167 MUX_SEL_MIF6, 0, 1),
1168
1169 /* MUX_SEL_MIF7 */
1170 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1171 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1172 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1173 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1174 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1175 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1176 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1177 MUX_SEL_MIF7, 8, 1),
1178 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1179 MUX_SEL_MIF7, 4, 1),
1180 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1181 MUX_SEL_MIF7, 0, 1),
1182 };
1183
1184 static const struct samsung_div_clock mif_div_clks[] __initconst = {
1185 /* DIV_MIF1 */
1186 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1187 DIV_MIF1, 16, 2),
1188 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1189 12, 2),
1190 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1191 8, 2),
1192 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1193 4, 4),
1194
1195 /* DIV_MIF2 */
1196 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1197 DIV_MIF2, 20, 3),
1198 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1199 DIV_MIF2, 16, 4),
1200 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1201 DIV_MIF2, 12, 4),
1202 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1203 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1204 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1205 DIV_MIF2, 4, 2),
1206 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1207 DIV_MIF2, 0, 3),
1208
1209 /* DIV_MIF3 */
1210 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1211 DIV_MIF3, 16, 4),
1212 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1213 DIV_MIF3, 4, 3),
1214 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1215 DIV_MIF3, 0, 3),
1216
1217 /* DIV_MIF4 */
1218 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1219 DIV_MIF4, 24, 4),
1220 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1221 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1222 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1223 DIV_MIF4, 16, 4),
1224 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1225 DIV_MIF4, 12, 4),
1226 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1227 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1228 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1229 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1230 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1231 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1232
1233 /* DIV_MIF5 */
1234 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1235 0, 3),
1236 };
1237
1238 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1239 /* ENABLE_ACLK_MIF0 */
1240 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1241 19, CLK_IGNORE_UNUSED, 0),
1242 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1243 18, CLK_IGNORE_UNUSED, 0),
1244 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1245 17, CLK_IGNORE_UNUSED, 0),
1246 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1247 16, CLK_IGNORE_UNUSED, 0),
1248 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1249 15, CLK_IGNORE_UNUSED, 0),
1250 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1251 14, CLK_IGNORE_UNUSED, 0),
1252 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1253 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1254 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1255 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1256 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1257 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1258 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1259 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1260 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1261 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1262 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1263 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1264 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1265 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1266 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1267 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1268 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1269 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1270 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1271 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1272 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1273 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1274 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1275 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1276 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1277 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1278 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1279 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1280
1281 /* ENABLE_ACLK_MIF1 */
1282 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1283 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1284 CLK_IGNORE_UNUSED, 0),
1285 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1286 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1287 27, CLK_IGNORE_UNUSED, 0),
1288 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1289 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1290 26, CLK_IGNORE_UNUSED, 0),
1291 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1292 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1293 25, CLK_IGNORE_UNUSED, 0),
1294 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1295 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1296 24, CLK_IGNORE_UNUSED, 0),
1297 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1298 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1299 23, CLK_IGNORE_UNUSED, 0),
1300 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1301 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1302 22, CLK_IGNORE_UNUSED, 0),
1303 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1304 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1305 21, CLK_IGNORE_UNUSED, 0),
1306 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1307 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1308 20, CLK_IGNORE_UNUSED, 0),
1309 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1310 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1311 19, CLK_IGNORE_UNUSED, 0),
1312 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1313 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1314 18, CLK_IGNORE_UNUSED, 0),
1315 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1316 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1317 17, CLK_IGNORE_UNUSED, 0),
1318 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1319 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1320 16, CLK_IGNORE_UNUSED, 0),
1321 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1322 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1323 15, CLK_IGNORE_UNUSED, 0),
1324 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1325 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1326 14, CLK_IGNORE_UNUSED, 0),
1327 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1328 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1329 13, CLK_IGNORE_UNUSED, 0),
1330 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1331 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1332 12, CLK_IGNORE_UNUSED, 0),
1333 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1334 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1335 11, CLK_IGNORE_UNUSED, 0),
1336 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1337 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1338 10, CLK_IGNORE_UNUSED, 0),
1339 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1340 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1341 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1342 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1343 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1344 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1345 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1346 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1347 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1348 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1349 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1350 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1351 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1352 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1353 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1354 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1355 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1356 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1357 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1358 0, CLK_IGNORE_UNUSED, 0),
1359
1360 /* ENABLE_ACLK_MIF2 */
1361 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1362 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1363 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1364 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1365 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1366 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1367 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1368 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1369 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1370 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1371 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1372 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1373 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1374 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1375 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1376 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1377 CLK_IGNORE_UNUSED, 0),
1378 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1379 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1380 5, CLK_IGNORE_UNUSED, 0),
1381 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1382 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1383 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1384 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1385 3, CLK_IGNORE_UNUSED, 0),
1386 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1387 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1388
1389 /* ENABLE_ACLK_MIF3 */
1390 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1391 ENABLE_ACLK_MIF3, 4,
1392 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1393 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1394 ENABLE_ACLK_MIF3, 1,
1395 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1396 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1397 ENABLE_ACLK_MIF3, 0,
1398 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1399
1400 /* ENABLE_PCLK_MIF */
1401 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1402 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1403 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1404 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1405 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1406 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1407 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1408 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1409 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1410 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1411 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1412 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1413 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1414 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1415 CLK_IGNORE_UNUSED, 0),
1416 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1417 ENABLE_PCLK_MIF, 19, 0, 0),
1418 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1419 ENABLE_PCLK_MIF, 18, 0, 0),
1420 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1421 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1422 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1423 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1424 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1425 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1426 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1427 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1428 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1429 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1430 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1431 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1432 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1433 ENABLE_PCLK_MIF, 11, 0, 0),
1434 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1435 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1436 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1437 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1438 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1439 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1440 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1441 ENABLE_PCLK_MIF, 7, 0, 0),
1442 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1443 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1444 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1445 ENABLE_PCLK_MIF, 5, 0, 0),
1446 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1447 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1448 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1449 ENABLE_PCLK_MIF, 2, 0, 0),
1450 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1451 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1452
1453 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1454 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1455 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1456 CLK_IGNORE_UNUSED, 0),
1457
1458 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1459 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1460 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1461 CLK_IGNORE_UNUSED, 0),
1462
1463 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1464 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1465 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1466
1467 /* ENABLE_PCLK_MIF_SECURE_RTC */
1468 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1469 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1470
1471 /* ENABLE_SCLK_MIF */
1472 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1473 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1474 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1475 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1476 14, CLK_IGNORE_UNUSED, 0),
1477 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1478 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1479 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1480 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1481 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1482 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1483 7, CLK_IGNORE_UNUSED, 0),
1484 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1485 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1486 6, CLK_IGNORE_UNUSED, 0),
1487 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1488 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1489 5, CLK_IGNORE_UNUSED, 0),
1490 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1491 ENABLE_SCLK_MIF, 4,
1492 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1493 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1494 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1495 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1496 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1497 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1498 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1499 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1500 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1501 };
1502
1503 static const struct samsung_cmu_info mif_cmu_info __initconst = {
1504 .pll_clks = mif_pll_clks,
1505 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1506 .mux_clks = mif_mux_clks,
1507 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1508 .div_clks = mif_div_clks,
1509 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1510 .gate_clks = mif_gate_clks,
1511 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1512 .fixed_factor_clks = mif_fixed_factor_clks,
1513 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
1514 .nr_clk_ids = MIF_NR_CLK,
1515 .clk_regs = mif_clk_regs,
1516 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1517 };
1518
1519 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1520 {
1521 samsung_cmu_register_one(np, &mif_cmu_info);
1522 }
1523 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1524 exynos5433_cmu_mif_init);
1525
1526 /*
1527 * Register offset definitions for CMU_PERIC
1528 */
1529 #define DIV_PERIC 0x0600
1530 #define DIV_STAT_PERIC 0x0700
1531 #define ENABLE_ACLK_PERIC 0x0800
1532 #define ENABLE_PCLK_PERIC0 0x0900
1533 #define ENABLE_PCLK_PERIC1 0x0904
1534 #define ENABLE_SCLK_PERIC 0x0A00
1535 #define ENABLE_IP_PERIC0 0x0B00
1536 #define ENABLE_IP_PERIC1 0x0B04
1537 #define ENABLE_IP_PERIC2 0x0B08
1538
1539 static const unsigned long peric_clk_regs[] __initconst = {
1540 DIV_PERIC,
1541 ENABLE_ACLK_PERIC,
1542 ENABLE_PCLK_PERIC0,
1543 ENABLE_PCLK_PERIC1,
1544 ENABLE_SCLK_PERIC,
1545 ENABLE_IP_PERIC0,
1546 ENABLE_IP_PERIC1,
1547 ENABLE_IP_PERIC2,
1548 };
1549
1550 static const struct samsung_div_clock peric_div_clks[] __initconst = {
1551 /* DIV_PERIC */
1552 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1553 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1554 };
1555
1556 static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1557 /* ENABLE_ACLK_PERIC */
1558 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1559 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1560 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1561 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1562 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1563 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1564 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1565 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1566
1567 /* ENABLE_PCLK_PERIC0 */
1568 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1569 31, CLK_SET_RATE_PARENT, 0),
1570 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1571 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1572 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1573 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1574 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1575 28, CLK_SET_RATE_PARENT, 0),
1576 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1577 26, CLK_SET_RATE_PARENT, 0),
1578 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1579 25, CLK_SET_RATE_PARENT, 0),
1580 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1581 24, CLK_SET_RATE_PARENT, 0),
1582 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1583 23, CLK_SET_RATE_PARENT, 0),
1584 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1585 22, CLK_SET_RATE_PARENT, 0),
1586 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1587 21, CLK_SET_RATE_PARENT, 0),
1588 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1589 20, CLK_SET_RATE_PARENT, 0),
1590 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1591 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1592 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1593 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1594 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1595 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1596 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1597 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1598 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1599 ENABLE_PCLK_PERIC0, 15,
1600 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1601 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1602 14, CLK_SET_RATE_PARENT, 0),
1603 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1604 13, CLK_SET_RATE_PARENT, 0),
1605 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1606 12, CLK_SET_RATE_PARENT, 0),
1607 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1608 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1609 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1610 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1611 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1612 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1613 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1614 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1615 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1616 7, CLK_SET_RATE_PARENT, 0),
1617 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1618 6, CLK_SET_RATE_PARENT, 0),
1619 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1620 5, CLK_SET_RATE_PARENT, 0),
1621 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1622 4, CLK_SET_RATE_PARENT, 0),
1623 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1624 3, CLK_SET_RATE_PARENT, 0),
1625 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1626 2, CLK_SET_RATE_PARENT, 0),
1627 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1628 1, CLK_SET_RATE_PARENT, 0),
1629 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1630 0, CLK_SET_RATE_PARENT, 0),
1631
1632 /* ENABLE_PCLK_PERIC1 */
1633 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1634 9, CLK_SET_RATE_PARENT, 0),
1635 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1636 8, CLK_SET_RATE_PARENT, 0),
1637 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1638 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1639 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1640 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1641 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1642 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1643 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1644 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1645 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1646 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1647 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1648 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1649 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1650 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1651 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1652 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1653
1654 /* ENABLE_SCLK_PERIC */
1655 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1656 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1657 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1658 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1659 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1660 19, CLK_SET_RATE_PARENT, 0),
1661 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1662 18, CLK_SET_RATE_PARENT, 0),
1663 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1664 17, 0, 0),
1665 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1666 16, 0, 0),
1667 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1668 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1669 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1670 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1671 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1672 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1673 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1674 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1675 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1676 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1677 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1678 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1679 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1680 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1681 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1682 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1683 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1684 5, CLK_SET_RATE_PARENT, 0),
1685 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1686 4, CLK_SET_RATE_PARENT, 0),
1687 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1688 3, CLK_SET_RATE_PARENT, 0),
1689 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1690 ENABLE_SCLK_PERIC, 2,
1691 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1692 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1693 ENABLE_SCLK_PERIC, 1,
1694 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1695 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1696 ENABLE_SCLK_PERIC, 0,
1697 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1698 };
1699
1700 static const struct samsung_cmu_info peric_cmu_info __initconst = {
1701 .div_clks = peric_div_clks,
1702 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1703 .gate_clks = peric_gate_clks,
1704 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1705 .nr_clk_ids = PERIC_NR_CLK,
1706 .clk_regs = peric_clk_regs,
1707 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1708 };
1709
1710 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1711 {
1712 samsung_cmu_register_one(np, &peric_cmu_info);
1713 }
1714
1715 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1716 exynos5433_cmu_peric_init);
1717
1718 /*
1719 * Register offset definitions for CMU_PERIS
1720 */
1721 #define ENABLE_ACLK_PERIS 0x0800
1722 #define ENABLE_PCLK_PERIS 0x0900
1723 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1724 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1725 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1726 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1727 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1728 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1729 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1730 #define ENABLE_SCLK_PERIS 0x0a00
1731 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1732 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1733 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1734 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1735 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1736 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1737 #define ENABLE_IP_PERIS0 0x0b00
1738 #define ENABLE_IP_PERIS1 0x0b04
1739 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1740 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1741 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1742 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1743 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1744 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1745 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1746
1747 static const unsigned long peris_clk_regs[] __initconst = {
1748 ENABLE_ACLK_PERIS,
1749 ENABLE_PCLK_PERIS,
1750 ENABLE_PCLK_PERIS_SECURE_TZPC,
1751 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1752 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1753 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1754 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1755 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1756 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1757 ENABLE_SCLK_PERIS,
1758 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1759 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1760 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1761 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1762 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1763 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1764 ENABLE_IP_PERIS0,
1765 ENABLE_IP_PERIS1,
1766 ENABLE_IP_PERIS_SECURE_TZPC,
1767 ENABLE_IP_PERIS_SECURE_SECKEY,
1768 ENABLE_IP_PERIS_SECURE_CHIPID,
1769 ENABLE_IP_PERIS_SECURE_TOPRTC,
1770 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1771 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1772 ENABLE_IP_PERIS_SECURE_OTP_CON,
1773 };
1774
1775 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1776 /* ENABLE_ACLK_PERIS */
1777 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1778 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1779 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1780 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1781 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1782 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1783
1784 /* ENABLE_PCLK_PERIS */
1785 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1786 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1787 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1788 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1789 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1790 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1791 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1792 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1793 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1794 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1795 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1796 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1797 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1798 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1799 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1800 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1801 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1802 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1803 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1804 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1805
1806 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1807 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1808 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1809 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1810 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1811 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1812 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1813 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1814 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1815 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1816 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1817 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1818 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1819 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1820 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1821 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1822 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1823 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1824 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1825 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1826 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1827 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1828 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1829 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1830 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1831 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1832 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1833
1834 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1835 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1836 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1837
1838 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1839 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1840 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1841
1842 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1843 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1844 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1845
1846 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1847 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1848 "aclk_peris_66",
1849 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1850
1851 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1852 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1853 "aclk_peris_66",
1854 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1855
1856 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1857 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1858 "aclk_peris_66",
1859 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1860
1861 /* ENABLE_SCLK_PERIS */
1862 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1863 ENABLE_SCLK_PERIS, 10, 0, 0),
1864 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1865 ENABLE_SCLK_PERIS, 4, 0, 0),
1866 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1867 ENABLE_SCLK_PERIS, 3, 0, 0),
1868
1869 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1870 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1871 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1872
1873 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1874 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1875 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1876
1877 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1878 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1879 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1880
1881 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1882 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1883 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1884
1885 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1886 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1887 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1888
1889 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1890 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1891 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1892 };
1893
1894 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1895 .gate_clks = peris_gate_clks,
1896 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1897 .nr_clk_ids = PERIS_NR_CLK,
1898 .clk_regs = peris_clk_regs,
1899 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1900 };
1901
1902 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1903 {
1904 samsung_cmu_register_one(np, &peris_cmu_info);
1905 }
1906
1907 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1908 exynos5433_cmu_peris_init);
1909
1910 /*
1911 * Register offset definitions for CMU_FSYS
1912 */
1913 #define MUX_SEL_FSYS0 0x0200
1914 #define MUX_SEL_FSYS1 0x0204
1915 #define MUX_SEL_FSYS2 0x0208
1916 #define MUX_SEL_FSYS3 0x020c
1917 #define MUX_SEL_FSYS4 0x0210
1918 #define MUX_ENABLE_FSYS0 0x0300
1919 #define MUX_ENABLE_FSYS1 0x0304
1920 #define MUX_ENABLE_FSYS2 0x0308
1921 #define MUX_ENABLE_FSYS3 0x030c
1922 #define MUX_ENABLE_FSYS4 0x0310
1923 #define MUX_STAT_FSYS0 0x0400
1924 #define MUX_STAT_FSYS1 0x0404
1925 #define MUX_STAT_FSYS2 0x0408
1926 #define MUX_STAT_FSYS3 0x040c
1927 #define MUX_STAT_FSYS4 0x0410
1928 #define MUX_IGNORE_FSYS2 0x0508
1929 #define MUX_IGNORE_FSYS3 0x050c
1930 #define ENABLE_ACLK_FSYS0 0x0800
1931 #define ENABLE_ACLK_FSYS1 0x0804
1932 #define ENABLE_PCLK_FSYS 0x0900
1933 #define ENABLE_SCLK_FSYS 0x0a00
1934 #define ENABLE_IP_FSYS0 0x0b00
1935 #define ENABLE_IP_FSYS1 0x0b04
1936
1937 /* list of all parent clock list */
1938 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
1939 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", };
1940 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1941 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
1942 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1943 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1944 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1945 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1946 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1947
1948 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1949 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1950 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1951 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1952 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1953 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1954 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1955 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1956 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1957 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1958 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1959 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1960 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1961 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1962 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1963 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1964 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1965 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1966 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1967 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1968 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1969 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1970 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1971 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1972 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
1973 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
1974 PNAME(mout_sclk_mphy_p)
1975 = { "mout_sclk_ufs_mphy_user",
1976 "mout_phyclk_lli_mphy_to_ufs_user", };
1977
1978 static const unsigned long fsys_clk_regs[] __initconst = {
1979 MUX_SEL_FSYS0,
1980 MUX_SEL_FSYS1,
1981 MUX_SEL_FSYS2,
1982 MUX_SEL_FSYS3,
1983 MUX_SEL_FSYS4,
1984 MUX_ENABLE_FSYS0,
1985 MUX_ENABLE_FSYS1,
1986 MUX_ENABLE_FSYS2,
1987 MUX_ENABLE_FSYS3,
1988 MUX_ENABLE_FSYS4,
1989 MUX_IGNORE_FSYS2,
1990 MUX_IGNORE_FSYS3,
1991 ENABLE_ACLK_FSYS0,
1992 ENABLE_ACLK_FSYS1,
1993 ENABLE_PCLK_FSYS,
1994 ENABLE_SCLK_FSYS,
1995 ENABLE_IP_FSYS0,
1996 ENABLE_IP_FSYS1,
1997 };
1998
1999 static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {
2000 { MUX_SEL_FSYS0, 0 },
2001 { MUX_SEL_FSYS1, 0 },
2002 { MUX_SEL_FSYS2, 0 },
2003 { MUX_SEL_FSYS3, 0 },
2004 { MUX_SEL_FSYS4, 0 },
2005 };
2006
2007 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
2008 /* PHY clocks from USBDRD30_PHY */
2009 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2010 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2011 0, 60000000),
2012 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2013 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2014 0, 125000000),
2015 /* PHY clocks from USBHOST30_PHY */
2016 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2017 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2018 0, 60000000),
2019 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2020 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2021 0, 125000000),
2022 /* PHY clocks from USBHOST20_PHY */
2023 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2024 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2025 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2026 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2027 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2028 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2029 0, 48000000),
2030 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2031 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2032 60000000),
2033 /* PHY clocks from UFS_PHY */
2034 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2035 NULL, 0, 300000000),
2036 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2037 NULL, 0, 300000000),
2038 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2039 NULL, 0, 300000000),
2040 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2041 NULL, 0, 300000000),
2042 /* PHY clocks from LLI_PHY */
2043 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2044 NULL, 0, 26000000),
2045 };
2046
2047 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2048 /* MUX_SEL_FSYS0 */
2049 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2050 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2051 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2052 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2053
2054 /* MUX_SEL_FSYS1 */
2055 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2056 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2057 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2058 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2059 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2060 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2061 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2062 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2063 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2064 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2065 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2066 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2067 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2068 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2069
2070 /* MUX_SEL_FSYS2 */
2071 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2072 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2073 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2074 MUX_SEL_FSYS2, 28, 1),
2075 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2076 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2077 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2078 MUX_SEL_FSYS2, 24, 1),
2079 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2080 "mout_phyclk_usbhost20_phy_hsic1",
2081 mout_phyclk_usbhost20_phy_hsic1_p,
2082 MUX_SEL_FSYS2, 20, 1),
2083 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2084 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2085 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2086 MUX_SEL_FSYS2, 16, 1),
2087 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2088 "mout_phyclk_usbhost20_phy_phyclock_user",
2089 mout_phyclk_usbhost20_phy_phyclock_user_p,
2090 MUX_SEL_FSYS2, 12, 1),
2091 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2092 "mout_phyclk_usbhost20_phy_freeclk_user",
2093 mout_phyclk_usbhost20_phy_freeclk_user_p,
2094 MUX_SEL_FSYS2, 8, 1),
2095 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2096 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2097 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2098 MUX_SEL_FSYS2, 4, 1),
2099 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2100 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2101 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2102 MUX_SEL_FSYS2, 0, 1),
2103
2104 /* MUX_SEL_FSYS3 */
2105 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2106 "mout_phyclk_ufs_rx1_symbol_user",
2107 mout_phyclk_ufs_rx1_symbol_user_p,
2108 MUX_SEL_FSYS3, 16, 1),
2109 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2110 "mout_phyclk_ufs_rx0_symbol_user",
2111 mout_phyclk_ufs_rx0_symbol_user_p,
2112 MUX_SEL_FSYS3, 12, 1),
2113 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2114 "mout_phyclk_ufs_tx1_symbol_user",
2115 mout_phyclk_ufs_tx1_symbol_user_p,
2116 MUX_SEL_FSYS3, 8, 1),
2117 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2118 "mout_phyclk_ufs_tx0_symbol_user",
2119 mout_phyclk_ufs_tx0_symbol_user_p,
2120 MUX_SEL_FSYS3, 4, 1),
2121 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2122 "mout_phyclk_lli_mphy_to_ufs_user",
2123 mout_phyclk_lli_mphy_to_ufs_user_p,
2124 MUX_SEL_FSYS3, 0, 1),
2125
2126 /* MUX_SEL_FSYS4 */
2127 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2128 MUX_SEL_FSYS4, 0, 1),
2129 };
2130
2131 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2132 /* ENABLE_ACLK_FSYS0 */
2133 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2134 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2135 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2136 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2137 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2138 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2139 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2140 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2141 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2142 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2143 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2144 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2145 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2146 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2147 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2148 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2149 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2150 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2151 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2152 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2153 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2154 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2155
2156 /* ENABLE_ACLK_FSYS1 */
2157 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2158 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2159 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2160 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2161 26, CLK_IGNORE_UNUSED, 0),
2162 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2163 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2164 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2165 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2166 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2167 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2168 22, CLK_IGNORE_UNUSED, 0),
2169 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2170 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2171 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2172 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2173 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2174 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2175 13, 0, 0),
2176 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2177 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2178 12, 0, 0),
2179 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2180 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2181 11, CLK_IGNORE_UNUSED, 0),
2182 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2183 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2184 10, CLK_IGNORE_UNUSED, 0),
2185 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2186 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2187 9, CLK_IGNORE_UNUSED, 0),
2188 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2189 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2190 8, CLK_IGNORE_UNUSED, 0),
2191 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2192 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2193 7, CLK_IGNORE_UNUSED, 0),
2194 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2195 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2196 6, CLK_IGNORE_UNUSED, 0),
2197 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2198 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2199 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2200 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2201 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2202 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2203 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2204 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2205 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2206 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2207 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2208 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2209
2210 /* ENABLE_PCLK_FSYS */
2211 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2212 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2213 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2214 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2215 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2216 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2217 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2218 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2219 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2220 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2221 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2222 ENABLE_PCLK_FSYS, 5, 0, 0),
2223 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2224 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2225 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2226 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2227 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2228 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2229 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2230 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2231 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2232 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2233 0, CLK_IGNORE_UNUSED, 0),
2234
2235 /* ENABLE_SCLK_FSYS */
2236 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2237 ENABLE_SCLK_FSYS, 21, 0, 0),
2238 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2239 "phyclk_usbhost30_uhost30_pipe_pclk",
2240 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2241 ENABLE_SCLK_FSYS, 18, 0, 0),
2242 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2243 "phyclk_usbhost30_uhost30_phyclock",
2244 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2245 ENABLE_SCLK_FSYS, 17, 0, 0),
2246 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2247 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2248 16, 0, 0),
2249 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2250 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2251 15, 0, 0),
2252 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2253 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2254 14, 0, 0),
2255 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2256 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2257 13, 0, 0),
2258 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2259 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2260 12, 0, 0),
2261 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2262 "phyclk_usbhost20_phy_clk48mohci",
2263 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2264 ENABLE_SCLK_FSYS, 11, 0, 0),
2265 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2266 "phyclk_usbhost20_phy_phyclock",
2267 "mout_phyclk_usbhost20_phy_phyclock_user",
2268 ENABLE_SCLK_FSYS, 10, 0, 0),
2269 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2270 "phyclk_usbhost20_phy_freeclk",
2271 "mout_phyclk_usbhost20_phy_freeclk_user",
2272 ENABLE_SCLK_FSYS, 9, 0, 0),
2273 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2274 "phyclk_usbdrd30_udrd30_pipe_pclk",
2275 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2276 ENABLE_SCLK_FSYS, 8, 0, 0),
2277 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2278 "phyclk_usbdrd30_udrd30_phyclock",
2279 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2280 ENABLE_SCLK_FSYS, 7, 0, 0),
2281 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2282 ENABLE_SCLK_FSYS, 6, 0, 0),
2283 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2284 ENABLE_SCLK_FSYS, 5, 0, 0),
2285 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2286 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2287 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2288 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2289 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2290 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2291 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2292 ENABLE_SCLK_FSYS, 1, 0, 0),
2293 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2294 ENABLE_SCLK_FSYS, 0, 0, 0),
2295
2296 /* ENABLE_IP_FSYS0 */
2297 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2298 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2299 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2300 };
2301
2302 static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2303 .mux_clks = fsys_mux_clks,
2304 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2305 .gate_clks = fsys_gate_clks,
2306 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
2307 .fixed_clks = fsys_fixed_clks,
2308 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
2309 .nr_clk_ids = FSYS_NR_CLK,
2310 .clk_regs = fsys_clk_regs,
2311 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2312 .suspend_regs = fsys_suspend_regs,
2313 .nr_suspend_regs = ARRAY_SIZE(fsys_suspend_regs),
2314 .clk_name = "aclk_fsys_200",
2315 };
2316
2317 /*
2318 * Register offset definitions for CMU_G2D
2319 */
2320 #define MUX_SEL_G2D0 0x0200
2321 #define MUX_SEL_ENABLE_G2D0 0x0300
2322 #define MUX_SEL_STAT_G2D0 0x0400
2323 #define DIV_G2D 0x0600
2324 #define DIV_STAT_G2D 0x0700
2325 #define DIV_ENABLE_ACLK_G2D 0x0800
2326 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2327 #define DIV_ENABLE_PCLK_G2D 0x0900
2328 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2329 #define DIV_ENABLE_IP_G2D0 0x0b00
2330 #define DIV_ENABLE_IP_G2D1 0x0b04
2331 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2332
2333 static const unsigned long g2d_clk_regs[] __initconst = {
2334 MUX_SEL_G2D0,
2335 MUX_SEL_ENABLE_G2D0,
2336 DIV_G2D,
2337 DIV_ENABLE_ACLK_G2D,
2338 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2339 DIV_ENABLE_PCLK_G2D,
2340 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2341 DIV_ENABLE_IP_G2D0,
2342 DIV_ENABLE_IP_G2D1,
2343 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2344 };
2345
2346 static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {
2347 { MUX_SEL_G2D0, 0 },
2348 };
2349
2350 /* list of all parent clock list */
2351 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2352 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2353
2354 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2355 /* MUX_SEL_G2D0 */
2356 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2357 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2358 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2359 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2360 };
2361
2362 static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2363 /* DIV_G2D */
2364 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2365 DIV_G2D, 0, 2),
2366 };
2367
2368 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2369 /* DIV_ENABLE_ACLK_G2D */
2370 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2371 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2372 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2373 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2374 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2375 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2376 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2377 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2378 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2379 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2380 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2381 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2382 7, 0, 0),
2383 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2384 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2385 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2386 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2387 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2388 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2389 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2390 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2391 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2392 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2393 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2394 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2395 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2396 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2397
2398 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2399 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2400 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2401
2402 /* DIV_ENABLE_PCLK_G2D */
2403 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2404 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2405 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2406 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2407 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2408 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2409 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2410 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2411 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2412 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2413 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2414 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2415 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2416 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2417 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2418 0, 0, 0),
2419
2420 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2421 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2422 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2423 };
2424
2425 static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2426 .mux_clks = g2d_mux_clks,
2427 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2428 .div_clks = g2d_div_clks,
2429 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2430 .gate_clks = g2d_gate_clks,
2431 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2432 .nr_clk_ids = G2D_NR_CLK,
2433 .clk_regs = g2d_clk_regs,
2434 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2435 .suspend_regs = g2d_suspend_regs,
2436 .nr_suspend_regs = ARRAY_SIZE(g2d_suspend_regs),
2437 .clk_name = "aclk_g2d_400",
2438 };
2439
2440 /*
2441 * Register offset definitions for CMU_DISP
2442 */
2443 #define DISP_PLL_LOCK 0x0000
2444 #define DISP_PLL_CON0 0x0100
2445 #define DISP_PLL_CON1 0x0104
2446 #define DISP_PLL_FREQ_DET 0x0108
2447 #define MUX_SEL_DISP0 0x0200
2448 #define MUX_SEL_DISP1 0x0204
2449 #define MUX_SEL_DISP2 0x0208
2450 #define MUX_SEL_DISP3 0x020c
2451 #define MUX_SEL_DISP4 0x0210
2452 #define MUX_ENABLE_DISP0 0x0300
2453 #define MUX_ENABLE_DISP1 0x0304
2454 #define MUX_ENABLE_DISP2 0x0308
2455 #define MUX_ENABLE_DISP3 0x030c
2456 #define MUX_ENABLE_DISP4 0x0310
2457 #define MUX_STAT_DISP0 0x0400
2458 #define MUX_STAT_DISP1 0x0404
2459 #define MUX_STAT_DISP2 0x0408
2460 #define MUX_STAT_DISP3 0x040c
2461 #define MUX_STAT_DISP4 0x0410
2462 #define MUX_IGNORE_DISP2 0x0508
2463 #define DIV_DISP 0x0600
2464 #define DIV_DISP_PLL_FREQ_DET 0x0604
2465 #define DIV_STAT_DISP 0x0700
2466 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2467 #define ENABLE_ACLK_DISP0 0x0800
2468 #define ENABLE_ACLK_DISP1 0x0804
2469 #define ENABLE_PCLK_DISP 0x0900
2470 #define ENABLE_SCLK_DISP 0x0a00
2471 #define ENABLE_IP_DISP0 0x0b00
2472 #define ENABLE_IP_DISP1 0x0b04
2473 #define CLKOUT_CMU_DISP 0x0c00
2474 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2475
2476 static const unsigned long disp_clk_regs[] __initconst = {
2477 DISP_PLL_LOCK,
2478 DISP_PLL_CON0,
2479 DISP_PLL_CON1,
2480 DISP_PLL_FREQ_DET,
2481 MUX_SEL_DISP0,
2482 MUX_SEL_DISP1,
2483 MUX_SEL_DISP2,
2484 MUX_SEL_DISP3,
2485 MUX_SEL_DISP4,
2486 MUX_ENABLE_DISP0,
2487 MUX_ENABLE_DISP1,
2488 MUX_ENABLE_DISP2,
2489 MUX_ENABLE_DISP3,
2490 MUX_ENABLE_DISP4,
2491 MUX_IGNORE_DISP2,
2492 DIV_DISP,
2493 DIV_DISP_PLL_FREQ_DET,
2494 ENABLE_ACLK_DISP0,
2495 ENABLE_ACLK_DISP1,
2496 ENABLE_PCLK_DISP,
2497 ENABLE_SCLK_DISP,
2498 ENABLE_IP_DISP0,
2499 ENABLE_IP_DISP1,
2500 CLKOUT_CMU_DISP,
2501 CLKOUT_CMU_DISP_DIV_STAT,
2502 };
2503
2504 static const struct samsung_clk_reg_dump disp_suspend_regs[] = {
2505 /* PLL has to be enabled for suspend */
2506 { DISP_PLL_CON0, 0x85f40502 },
2507 /* ignore status of external PHY muxes during suspend to avoid hangs */
2508 { MUX_IGNORE_DISP2, 0x00111111 },
2509 { MUX_SEL_DISP0, 0 },
2510 { MUX_SEL_DISP1, 0 },
2511 { MUX_SEL_DISP2, 0 },
2512 { MUX_SEL_DISP3, 0 },
2513 { MUX_SEL_DISP4, 0 },
2514 };
2515
2516 /* list of all parent clock list */
2517 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2518 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2519 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2520 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2521 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2522 "sclk_decon_tv_eclk_disp", };
2523 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2524 "sclk_decon_vclk_disp", };
2525 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2526 "sclk_decon_eclk_disp", };
2527 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2528 "sclk_decon_tv_vclk_disp", };
2529 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2530
2531 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2532 "phyclk_mipidphy1_bitclkdiv8_phy", };
2533 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2534 "phyclk_mipidphy1_rxclkesc0_phy", };
2535 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2536 "phyclk_mipidphy0_bitclkdiv8_phy", };
2537 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2538 "phyclk_mipidphy0_rxclkesc0_phy", };
2539 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2540 "phyclk_hdmiphy_tmds_clko_phy", };
2541 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2542 "phyclk_hdmiphy_pixel_clko_phy", };
2543
2544 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2545 "mout_sclk_dsim0_user", };
2546 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2547 "mout_sclk_decon_tv_eclk_user", };
2548 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2549 "mout_sclk_decon_vclk_user", };
2550 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2551 "mout_sclk_decon_eclk_user", };
2552
2553 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2554 "mout_sclk_dsim1_user", };
2555 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2556 "mout_phyclk_hdmiphy_pixel_clko_user",
2557 "mout_sclk_decon_tv_vclk_b_disp", };
2558 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2559 "mout_sclk_decon_tv_vclk_user", };
2560
2561 static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2562 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2563 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates),
2564 };
2565
2566 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2567 /*
2568 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2569 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2570 * and sclk_decon_{vclk|tv_vclk}.
2571 */
2572 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2573 1, 2, 0),
2574 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2575 1, 2, 0),
2576 };
2577
2578 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2579 /* PHY clocks from MIPI_DPHY1 */
2580 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2581 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2582 /* PHY clocks from MIPI_DPHY0 */
2583 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
2584 NULL, 0, 188000000),
2585 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
2586 NULL, 0, 100000000),
2587 /* PHY clocks from HDMI_PHY */
2588 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2589 NULL, 0, 300000000),
2590 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
2591 NULL, 0, 166000000),
2592 };
2593
2594 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2595 /* MUX_SEL_DISP0 */
2596 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2597 0, 1),
2598
2599 /* MUX_SEL_DISP1 */
2600 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2601 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2602 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2603 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2604 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2605 MUX_SEL_DISP1, 20, 1),
2606 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2607 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2608 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2609 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2610 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2611 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2612 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2613 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2614 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2615 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2616
2617 /* MUX_SEL_DISP2 */
2618 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2619 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2620 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2621 20, 1),
2622 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2623 "mout_phyclk_mipidphy1_rxclkesc0_user",
2624 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2625 16, 1),
2626 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2627 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2628 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2629 12, 1),
2630 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2631 "mout_phyclk_mipidphy0_rxclkesc0_user",
2632 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2633 8, 1),
2634 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2635 "mout_phyclk_hdmiphy_tmds_clko_user",
2636 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2637 4, 1),
2638 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2639 "mout_phyclk_hdmiphy_pixel_clko_user",
2640 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2641 0, 1),
2642
2643 /* MUX_SEL_DISP3 */
2644 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2645 MUX_SEL_DISP3, 12, 1),
2646 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2647 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2648 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2649 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2650 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2651 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2652
2653 /* MUX_SEL_DISP4 */
2654 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2655 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2656 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2657 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2658 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2659 "mout_sclk_decon_tv_vclk_c_disp",
2660 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2661 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2662 "mout_sclk_decon_tv_vclk_b_disp",
2663 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2664 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2665 "mout_sclk_decon_tv_vclk_a_disp",
2666 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2667 };
2668
2669 static const struct samsung_div_clock disp_div_clks[] __initconst = {
2670 /* DIV_DISP */
2671 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2672 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2673 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2674 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2675 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2676 DIV_DISP, 16, 3),
2677 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2678 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2679 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2680 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2681 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2682 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2683 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2684 DIV_DISP, 0, 2),
2685 };
2686
2687 static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2688 /* ENABLE_ACLK_DISP0 */
2689 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2690 ENABLE_ACLK_DISP0, 2, 0, 0),
2691 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2692 ENABLE_ACLK_DISP0, 0, 0, 0),
2693
2694 /* ENABLE_ACLK_DISP1 */
2695 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2696 ENABLE_ACLK_DISP1, 25, 0, 0),
2697 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2698 ENABLE_ACLK_DISP1, 24, 0, 0),
2699 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2700 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2701 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2702 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2703 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2704 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2705 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2706 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2707 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2708 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2709 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2710 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2711 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2712 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2713 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2714 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2715 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2716 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2717 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2718 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2719 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2720 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2721 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2722 "div_pclk_disp", ENABLE_ACLK_DISP1,
2723 12, CLK_IGNORE_UNUSED, 0),
2724 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2725 "div_pclk_disp", ENABLE_ACLK_DISP1,
2726 11, CLK_IGNORE_UNUSED, 0),
2727 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2728 "div_pclk_disp", ENABLE_ACLK_DISP1,
2729 10, CLK_IGNORE_UNUSED, 0),
2730 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2731 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2732 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2733 ENABLE_ACLK_DISP1, 7, 0, 0),
2734 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2735 ENABLE_ACLK_DISP1, 6, 0, 0),
2736 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2737 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2738 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2739 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2740 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2741 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2742 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2743 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2744 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2745 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2746 CLK_IGNORE_UNUSED, 0),
2747 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2748 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2749 0, CLK_IGNORE_UNUSED, 0),
2750
2751 /* ENABLE_PCLK_DISP */
2752 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2753 ENABLE_PCLK_DISP, 23, 0, 0),
2754 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2755 ENABLE_PCLK_DISP, 22, 0, 0),
2756 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2757 ENABLE_PCLK_DISP, 21, 0, 0),
2758 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2759 ENABLE_PCLK_DISP, 20, 0, 0),
2760 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2761 ENABLE_PCLK_DISP, 19, 0, 0),
2762 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2763 ENABLE_PCLK_DISP, 18, 0, 0),
2764 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2765 ENABLE_PCLK_DISP, 17, 0, 0),
2766 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2767 ENABLE_PCLK_DISP, 16, 0, 0),
2768 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2769 ENABLE_PCLK_DISP, 15, 0, 0),
2770 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2771 ENABLE_PCLK_DISP, 14, 0, 0),
2772 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2773 ENABLE_PCLK_DISP, 13, 0, 0),
2774 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2775 ENABLE_PCLK_DISP, 12, 0, 0),
2776 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2777 ENABLE_PCLK_DISP, 11, 0, 0),
2778 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2779 ENABLE_PCLK_DISP, 10, 0, 0),
2780 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2781 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2782 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2783 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2784 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2785 ENABLE_PCLK_DISP, 7, 0, 0),
2786 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2787 ENABLE_PCLK_DISP, 6, 0, 0),
2788 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2789 ENABLE_PCLK_DISP, 5, 0, 0),
2790 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2791 ENABLE_PCLK_DISP, 3, 0, 0),
2792 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2793 ENABLE_PCLK_DISP, 2, 0, 0),
2794 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2795 ENABLE_PCLK_DISP, 1, 0, 0),
2796 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
2797 ENABLE_PCLK_DISP, 0, 0, 0),
2798
2799 /* ENABLE_SCLK_DISP */
2800 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2801 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2802 ENABLE_SCLK_DISP, 26, 0, 0),
2803 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2804 "mout_phyclk_mipidphy1_rxclkesc0_user",
2805 ENABLE_SCLK_DISP, 25, 0, 0),
2806 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2807 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2808 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2809 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2810 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2811 ENABLE_SCLK_DISP, 22, 0, 0),
2812 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2813 "div_sclk_decon_tv_vclk_disp",
2814 ENABLE_SCLK_DISP, 21, 0, 0),
2815 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2816 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2817 ENABLE_SCLK_DISP, 15, 0, 0),
2818 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2819 "mout_phyclk_mipidphy0_rxclkesc0_user",
2820 ENABLE_SCLK_DISP, 14, 0, 0),
2821 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2822 "mout_phyclk_hdmiphy_tmds_clko_user",
2823 ENABLE_SCLK_DISP, 13, 0, 0),
2824 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2825 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2826 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2827 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2828 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2829 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2830 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2831 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2832 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2833 ENABLE_SCLK_DISP, 7, 0, 0),
2834 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2835 ENABLE_SCLK_DISP, 6, 0, 0),
2836 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2837 ENABLE_SCLK_DISP, 5, 0, 0),
2838 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2839 "div_sclk_decon_tv_eclk_disp",
2840 ENABLE_SCLK_DISP, 4, 0, 0),
2841 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2842 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2843 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2844 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2845 };
2846
2847 static const struct samsung_cmu_info disp_cmu_info __initconst = {
2848 .pll_clks = disp_pll_clks,
2849 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2850 .mux_clks = disp_mux_clks,
2851 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2852 .div_clks = disp_div_clks,
2853 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2854 .gate_clks = disp_gate_clks,
2855 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2856 .fixed_clks = disp_fixed_clks,
2857 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2858 .fixed_factor_clks = disp_fixed_factor_clks,
2859 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2860 .nr_clk_ids = DISP_NR_CLK,
2861 .clk_regs = disp_clk_regs,
2862 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2863 .suspend_regs = disp_suspend_regs,
2864 .nr_suspend_regs = ARRAY_SIZE(disp_suspend_regs),
2865 .clk_name = "aclk_disp_333",
2866 };
2867
2868 /*
2869 * Register offset definitions for CMU_AUD
2870 */
2871 #define MUX_SEL_AUD0 0x0200
2872 #define MUX_SEL_AUD1 0x0204
2873 #define MUX_ENABLE_AUD0 0x0300
2874 #define MUX_ENABLE_AUD1 0x0304
2875 #define MUX_STAT_AUD0 0x0400
2876 #define DIV_AUD0 0x0600
2877 #define DIV_AUD1 0x0604
2878 #define DIV_STAT_AUD0 0x0700
2879 #define DIV_STAT_AUD1 0x0704
2880 #define ENABLE_ACLK_AUD 0x0800
2881 #define ENABLE_PCLK_AUD 0x0900
2882 #define ENABLE_SCLK_AUD0 0x0a00
2883 #define ENABLE_SCLK_AUD1 0x0a04
2884 #define ENABLE_IP_AUD0 0x0b00
2885 #define ENABLE_IP_AUD1 0x0b04
2886
2887 static const unsigned long aud_clk_regs[] __initconst = {
2888 MUX_SEL_AUD0,
2889 MUX_SEL_AUD1,
2890 MUX_ENABLE_AUD0,
2891 MUX_ENABLE_AUD1,
2892 DIV_AUD0,
2893 DIV_AUD1,
2894 ENABLE_ACLK_AUD,
2895 ENABLE_PCLK_AUD,
2896 ENABLE_SCLK_AUD0,
2897 ENABLE_SCLK_AUD1,
2898 ENABLE_IP_AUD0,
2899 ENABLE_IP_AUD1,
2900 };
2901
2902 static const struct samsung_clk_reg_dump aud_suspend_regs[] = {
2903 { MUX_SEL_AUD0, 0 },
2904 { MUX_SEL_AUD1, 0 },
2905 };
2906
2907 /* list of all parent clock list */
2908 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2909 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2910
2911 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2912 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2913 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2914 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2915 };
2916
2917 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2918 /* MUX_SEL_AUD0 */
2919 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2920 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2921
2922 /* MUX_SEL_AUD1 */
2923 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2924 MUX_SEL_AUD1, 8, 1),
2925 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2926 MUX_SEL_AUD1, 0, 1),
2927 };
2928
2929 static const struct samsung_div_clock aud_div_clks[] __initconst = {
2930 /* DIV_AUD0 */
2931 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2932 12, 4),
2933 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2934 8, 4),
2935 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2936 4, 4),
2937 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2938 0, 4),
2939
2940 /* DIV_AUD1 */
2941 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2942 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2943 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2944 DIV_AUD1, 12, 4),
2945 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2946 DIV_AUD1, 4, 8),
2947 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2948 DIV_AUD1, 0, 4),
2949 };
2950
2951 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
2952 /* ENABLE_ACLK_AUD */
2953 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2954 ENABLE_ACLK_AUD, 12, 0, 0),
2955 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2956 ENABLE_ACLK_AUD, 7, 0, 0),
2957 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2958 ENABLE_ACLK_AUD, 0, 4, 0),
2959 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2960 ENABLE_ACLK_AUD, 0, 3, 0),
2961 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2962 ENABLE_ACLK_AUD, 0, 2, 0),
2963 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2964 0, 1, 0),
2965 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2966 0, CLK_IGNORE_UNUSED, 0),
2967
2968 /* ENABLE_PCLK_AUD */
2969 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2970 13, 0, 0),
2971 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
2972 12, 0, 0),
2973 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
2974 11, 0, 0),
2975 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
2976 ENABLE_PCLK_AUD, 10, 0, 0),
2977 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
2978 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
2979 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
2980 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
2981 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
2982 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
2983 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
2984 ENABLE_PCLK_AUD, 6, 0, 0),
2985 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
2986 ENABLE_PCLK_AUD, 5, 0, 0),
2987 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
2988 ENABLE_PCLK_AUD, 4, 0, 0),
2989 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
2990 ENABLE_PCLK_AUD, 3, 0, 0),
2991 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
2992 2, 0, 0),
2993 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
2994 ENABLE_PCLK_AUD, 0, 0, 0),
2995
2996 /* ENABLE_SCLK_AUD0 */
2997 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2998 2, CLK_IGNORE_UNUSED, 0),
2999 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3000 ENABLE_SCLK_AUD0, 1, 0, 0),
3001 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3002 0, 0, 0),
3003
3004 /* ENABLE_SCLK_AUD1 */
3005 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3006 ENABLE_SCLK_AUD1, 6, 0, 0),
3007 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3008 ENABLE_SCLK_AUD1, 5, 0, 0),
3009 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3010 ENABLE_SCLK_AUD1, 4, 0, 0),
3011 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3012 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3013 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3014 ENABLE_SCLK_AUD1, 2, 0, 0),
3015 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3016 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3017 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3018 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3019 };
3020
3021 static const struct samsung_cmu_info aud_cmu_info __initconst = {
3022 .mux_clks = aud_mux_clks,
3023 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
3024 .div_clks = aud_div_clks,
3025 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
3026 .gate_clks = aud_gate_clks,
3027 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
3028 .fixed_clks = aud_fixed_clks,
3029 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
3030 .nr_clk_ids = AUD_NR_CLK,
3031 .clk_regs = aud_clk_regs,
3032 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
3033 .suspend_regs = aud_suspend_regs,
3034 .nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs),
3035 .clk_name = "fout_aud_pll",
3036 };
3037
3038 /*
3039 * Register offset definitions for CMU_BUS{0|1|2}
3040 */
3041 #define DIV_BUS 0x0600
3042 #define DIV_STAT_BUS 0x0700
3043 #define ENABLE_ACLK_BUS 0x0800
3044 #define ENABLE_PCLK_BUS 0x0900
3045 #define ENABLE_IP_BUS0 0x0b00
3046 #define ENABLE_IP_BUS1 0x0b04
3047
3048 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3049 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3050 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3051
3052 /* list of all parent clock list */
3053 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3054
3055 #define CMU_BUS_COMMON_CLK_REGS \
3056 DIV_BUS, \
3057 ENABLE_ACLK_BUS, \
3058 ENABLE_PCLK_BUS, \
3059 ENABLE_IP_BUS0, \
3060 ENABLE_IP_BUS1
3061
3062 static const unsigned long bus01_clk_regs[] __initconst = {
3063 CMU_BUS_COMMON_CLK_REGS,
3064 };
3065
3066 static const unsigned long bus2_clk_regs[] __initconst = {
3067 MUX_SEL_BUS2,
3068 MUX_ENABLE_BUS2,
3069 CMU_BUS_COMMON_CLK_REGS,
3070 };
3071
3072 static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3073 /* DIV_BUS0 */
3074 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3075 DIV_BUS, 0, 3),
3076 };
3077
3078 /* CMU_BUS0 clocks */
3079 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3080 /* ENABLE_ACLK_BUS0 */
3081 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3082 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3083 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3084 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3085 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3086 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3087
3088 /* ENABLE_PCLK_BUS0 */
3089 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3090 ENABLE_PCLK_BUS, 2, 0, 0),
3091 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3092 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3093 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3094 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3095 };
3096
3097 /* CMU_BUS1 clocks */
3098 static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3099 /* DIV_BUS1 */
3100 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3101 DIV_BUS, 0, 3),
3102 };
3103
3104 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3105 /* ENABLE_ACLK_BUS1 */
3106 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3107 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3108 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3109 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3110 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3111 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3112
3113 /* ENABLE_PCLK_BUS1 */
3114 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3115 ENABLE_PCLK_BUS, 2, 0, 0),
3116 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3117 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3118 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3119 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3120 };
3121
3122 /* CMU_BUS2 clocks */
3123 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3124 /* MUX_SEL_BUS2 */
3125 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3126 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3127 };
3128
3129 static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3130 /* DIV_BUS2 */
3131 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3132 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3133 };
3134
3135 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3136 /* ENABLE_ACLK_BUS2 */
3137 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3138 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3139 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3140 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3141 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3142 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3143 1, CLK_IGNORE_UNUSED, 0),
3144 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3145 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3146 0, CLK_IGNORE_UNUSED, 0),
3147
3148 /* ENABLE_PCLK_BUS2 */
3149 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3150 ENABLE_PCLK_BUS, 2, 0, 0),
3151 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3152 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3153 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3154 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3155 };
3156
3157 #define CMU_BUS_INFO_CLKS(id) \
3158 .div_clks = bus##id##_div_clks, \
3159 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3160 .gate_clks = bus##id##_gate_clks, \
3161 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3162 .nr_clk_ids = BUSx_NR_CLK
3163
3164 static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3165 CMU_BUS_INFO_CLKS(0),
3166 .clk_regs = bus01_clk_regs,
3167 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3168 };
3169
3170 static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3171 CMU_BUS_INFO_CLKS(1),
3172 .clk_regs = bus01_clk_regs,
3173 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3174 };
3175
3176 static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3177 CMU_BUS_INFO_CLKS(2),
3178 .mux_clks = bus2_mux_clks,
3179 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3180 .clk_regs = bus2_clk_regs,
3181 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3182 };
3183
3184 #define exynos5433_cmu_bus_init(id) \
3185 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3186 { \
3187 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3188 } \
3189 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3190 "samsung,exynos5433-cmu-bus"#id, \
3191 exynos5433_cmu_bus##id##_init)
3192
3193 exynos5433_cmu_bus_init(0);
3194 exynos5433_cmu_bus_init(1);
3195 exynos5433_cmu_bus_init(2);
3196
3197 /*
3198 * Register offset definitions for CMU_G3D
3199 */
3200 #define G3D_PLL_LOCK 0x0000
3201 #define G3D_PLL_CON0 0x0100
3202 #define G3D_PLL_CON1 0x0104
3203 #define G3D_PLL_FREQ_DET 0x010c
3204 #define MUX_SEL_G3D 0x0200
3205 #define MUX_ENABLE_G3D 0x0300
3206 #define MUX_STAT_G3D 0x0400
3207 #define DIV_G3D 0x0600
3208 #define DIV_G3D_PLL_FREQ_DET 0x0604
3209 #define DIV_STAT_G3D 0x0700
3210 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3211 #define ENABLE_ACLK_G3D 0x0800
3212 #define ENABLE_PCLK_G3D 0x0900
3213 #define ENABLE_SCLK_G3D 0x0a00
3214 #define ENABLE_IP_G3D0 0x0b00
3215 #define ENABLE_IP_G3D1 0x0b04
3216 #define CLKOUT_CMU_G3D 0x0c00
3217 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3218 #define CLK_STOPCTRL 0x1000
3219
3220 static const unsigned long g3d_clk_regs[] __initconst = {
3221 G3D_PLL_LOCK,
3222 G3D_PLL_CON0,
3223 G3D_PLL_CON1,
3224 G3D_PLL_FREQ_DET,
3225 MUX_SEL_G3D,
3226 MUX_ENABLE_G3D,
3227 DIV_G3D,
3228 DIV_G3D_PLL_FREQ_DET,
3229 ENABLE_ACLK_G3D,
3230 ENABLE_PCLK_G3D,
3231 ENABLE_SCLK_G3D,
3232 ENABLE_IP_G3D0,
3233 ENABLE_IP_G3D1,
3234 CLKOUT_CMU_G3D,
3235 CLKOUT_CMU_G3D_DIV_STAT,
3236 CLK_STOPCTRL,
3237 };
3238
3239 static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {
3240 { MUX_SEL_G3D, 0 },
3241 };
3242
3243 /* list of all parent clock list */
3244 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3245 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3246
3247 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3248 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3249 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates),
3250 };
3251
3252 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3253 /* MUX_SEL_G3D */
3254 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3255 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3256 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3257 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3258 };
3259
3260 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3261 /* DIV_G3D */
3262 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3263 8, 2),
3264 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3265 4, 3),
3266 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3267 0, 3, CLK_SET_RATE_PARENT, 0),
3268 };
3269
3270 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3271 /* ENABLE_ACLK_G3D */
3272 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3273 ENABLE_ACLK_G3D, 7, 0, 0),
3274 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3275 ENABLE_ACLK_G3D, 6, 0, 0),
3276 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3277 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3278 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3279 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3280 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3281 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3282 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3283 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3284 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3285 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3286 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3287 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3288
3289 /* ENABLE_PCLK_G3D */
3290 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3291 ENABLE_PCLK_G3D, 3, 0, 0),
3292 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3293 ENABLE_PCLK_G3D, 2, 0, 0),
3294 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3295 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3296 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3297 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3298
3299 /* ENABLE_SCLK_G3D */
3300 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3301 ENABLE_SCLK_G3D, 0, 0, 0),
3302 };
3303
3304 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3305 .pll_clks = g3d_pll_clks,
3306 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3307 .mux_clks = g3d_mux_clks,
3308 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3309 .div_clks = g3d_div_clks,
3310 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3311 .gate_clks = g3d_gate_clks,
3312 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3313 .nr_clk_ids = G3D_NR_CLK,
3314 .clk_regs = g3d_clk_regs,
3315 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3316 .suspend_regs = g3d_suspend_regs,
3317 .nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs),
3318 .clk_name = "aclk_g3d_400",
3319 };
3320
3321 /*
3322 * Register offset definitions for CMU_GSCL
3323 */
3324 #define MUX_SEL_GSCL 0x0200
3325 #define MUX_ENABLE_GSCL 0x0300
3326 #define MUX_STAT_GSCL 0x0400
3327 #define ENABLE_ACLK_GSCL 0x0800
3328 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3329 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3330 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3331 #define ENABLE_PCLK_GSCL 0x0900
3332 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3333 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3334 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3335 #define ENABLE_IP_GSCL0 0x0b00
3336 #define ENABLE_IP_GSCL1 0x0b04
3337 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3338 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3339 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3340
3341 static const unsigned long gscl_clk_regs[] __initconst = {
3342 MUX_SEL_GSCL,
3343 MUX_ENABLE_GSCL,
3344 ENABLE_ACLK_GSCL,
3345 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3346 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3347 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3348 ENABLE_PCLK_GSCL,
3349 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3350 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3351 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3352 ENABLE_IP_GSCL0,
3353 ENABLE_IP_GSCL1,
3354 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3355 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3356 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3357 };
3358
3359 static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {
3360 { MUX_SEL_GSCL, 0 },
3361 { ENABLE_ACLK_GSCL, 0xfff },
3362 { ENABLE_PCLK_GSCL, 0xff },
3363 };
3364
3365 /* list of all parent clock list */
3366 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3367 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3368
3369 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3370 /* MUX_SEL_GSCL */
3371 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3372 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3373 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3374 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3375 };
3376
3377 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3378 /* ENABLE_ACLK_GSCL */
3379 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3380 ENABLE_ACLK_GSCL, 11, 0, 0),
3381 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3382 ENABLE_ACLK_GSCL, 10, 0, 0),
3383 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3384 ENABLE_ACLK_GSCL, 9, 0, 0),
3385 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3386 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3387 8, CLK_IGNORE_UNUSED, 0),
3388 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3389 ENABLE_ACLK_GSCL, 7, 0, 0),
3390 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3391 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3392 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3393 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3394 CLK_IGNORE_UNUSED, 0),
3395 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3396 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3397 CLK_IGNORE_UNUSED, 0),
3398 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3399 ENABLE_ACLK_GSCL, 3, 0, 0),
3400 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3401 ENABLE_ACLK_GSCL, 2, 0, 0),
3402 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3403 ENABLE_ACLK_GSCL, 1, 0, 0),
3404 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3405 ENABLE_ACLK_GSCL, 0, 0, 0),
3406
3407 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3408 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3409 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3410
3411 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3412 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3413 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3414
3415 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3416 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3417 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3418
3419 /* ENABLE_PCLK_GSCL */
3420 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3421 ENABLE_PCLK_GSCL, 7, 0, 0),
3422 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3423 ENABLE_PCLK_GSCL, 6, 0, 0),
3424 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3425 ENABLE_PCLK_GSCL, 5, 0, 0),
3426 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3427 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3428 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3429 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3430 3, CLK_IGNORE_UNUSED, 0),
3431 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3432 ENABLE_PCLK_GSCL, 2, 0, 0),
3433 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3434 ENABLE_PCLK_GSCL, 1, 0, 0),
3435 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3436 ENABLE_PCLK_GSCL, 0, 0, 0),
3437
3438 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3439 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3440 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3441
3442 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3443 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3444 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3445
3446 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3447 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3448 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3449 };
3450
3451 static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3452 .mux_clks = gscl_mux_clks,
3453 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3454 .gate_clks = gscl_gate_clks,
3455 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3456 .nr_clk_ids = GSCL_NR_CLK,
3457 .clk_regs = gscl_clk_regs,
3458 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3459 .suspend_regs = gscl_suspend_regs,
3460 .nr_suspend_regs = ARRAY_SIZE(gscl_suspend_regs),
3461 .clk_name = "aclk_gscl_111",
3462 };
3463
3464 /*
3465 * Register offset definitions for CMU_APOLLO
3466 */
3467 #define APOLLO_PLL_LOCK 0x0000
3468 #define APOLLO_PLL_CON0 0x0100
3469 #define APOLLO_PLL_CON1 0x0104
3470 #define APOLLO_PLL_FREQ_DET 0x010c
3471 #define MUX_SEL_APOLLO0 0x0200
3472 #define MUX_SEL_APOLLO1 0x0204
3473 #define MUX_SEL_APOLLO2 0x0208
3474 #define MUX_ENABLE_APOLLO0 0x0300
3475 #define MUX_ENABLE_APOLLO1 0x0304
3476 #define MUX_ENABLE_APOLLO2 0x0308
3477 #define MUX_STAT_APOLLO0 0x0400
3478 #define MUX_STAT_APOLLO1 0x0404
3479 #define MUX_STAT_APOLLO2 0x0408
3480 #define DIV_APOLLO0 0x0600
3481 #define DIV_APOLLO1 0x0604
3482 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3483 #define DIV_STAT_APOLLO0 0x0700
3484 #define DIV_STAT_APOLLO1 0x0704
3485 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3486 #define ENABLE_ACLK_APOLLO 0x0800
3487 #define ENABLE_PCLK_APOLLO 0x0900
3488 #define ENABLE_SCLK_APOLLO 0x0a00
3489 #define ENABLE_IP_APOLLO0 0x0b00
3490 #define ENABLE_IP_APOLLO1 0x0b04
3491 #define CLKOUT_CMU_APOLLO 0x0c00
3492 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3493 #define ARMCLK_STOPCTRL 0x1000
3494 #define APOLLO_PWR_CTRL 0x1020
3495 #define APOLLO_PWR_CTRL2 0x1024
3496 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3497 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3498 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3499
3500 static const unsigned long apollo_clk_regs[] __initconst = {
3501 APOLLO_PLL_LOCK,
3502 APOLLO_PLL_CON0,
3503 APOLLO_PLL_CON1,
3504 APOLLO_PLL_FREQ_DET,
3505 MUX_SEL_APOLLO0,
3506 MUX_SEL_APOLLO1,
3507 MUX_SEL_APOLLO2,
3508 MUX_ENABLE_APOLLO0,
3509 MUX_ENABLE_APOLLO1,
3510 MUX_ENABLE_APOLLO2,
3511 DIV_APOLLO0,
3512 DIV_APOLLO1,
3513 DIV_APOLLO_PLL_FREQ_DET,
3514 ENABLE_ACLK_APOLLO,
3515 ENABLE_PCLK_APOLLO,
3516 ENABLE_SCLK_APOLLO,
3517 ENABLE_IP_APOLLO0,
3518 ENABLE_IP_APOLLO1,
3519 CLKOUT_CMU_APOLLO,
3520 CLKOUT_CMU_APOLLO_DIV_STAT,
3521 ARMCLK_STOPCTRL,
3522 APOLLO_PWR_CTRL,
3523 APOLLO_PWR_CTRL2,
3524 APOLLO_INTR_SPREAD_ENABLE,
3525 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3526 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3527 };
3528
3529 /* list of all parent clock list */
3530 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3531 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3532 PNAME(mout_apollo_p) = { "mout_apollo_pll",
3533 "mout_bus_pll_apollo_user", };
3534
3535 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3536 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3537 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates),
3538 };
3539
3540 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3541 /* MUX_SEL_APOLLO0 */
3542 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3543 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3544 CLK_RECALC_NEW_RATES, 0),
3545
3546 /* MUX_SEL_APOLLO1 */
3547 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3548 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3549
3550 /* MUX_SEL_APOLLO2 */
3551 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3552 0, 1, CLK_SET_RATE_PARENT, 0),
3553 };
3554
3555 static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3556 /* DIV_APOLLO0 */
3557 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3558 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3559 CLK_DIVIDER_READ_ONLY),
3560 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3561 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3562 CLK_DIVIDER_READ_ONLY),
3563 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3564 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3565 CLK_DIVIDER_READ_ONLY),
3566 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3567 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3568 CLK_DIVIDER_READ_ONLY),
3569 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3570 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3571 CLK_DIVIDER_READ_ONLY),
3572 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3573 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3574 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3575 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3576
3577 /* DIV_APOLLO1 */
3578 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3579 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3580 CLK_DIVIDER_READ_ONLY),
3581 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3582 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3583 CLK_DIVIDER_READ_ONLY),
3584 };
3585
3586 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3587 /* ENABLE_ACLK_APOLLO */
3588 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3589 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3590 6, CLK_IGNORE_UNUSED, 0),
3591 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3592 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3593 5, CLK_IGNORE_UNUSED, 0),
3594 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3595 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3596 4, CLK_IGNORE_UNUSED, 0),
3597 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3598 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3599 3, CLK_IGNORE_UNUSED, 0),
3600 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3601 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3602 2, CLK_IGNORE_UNUSED, 0),
3603 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3604 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3605 1, CLK_IGNORE_UNUSED, 0),
3606 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3607 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3608 0, CLK_IGNORE_UNUSED, 0),
3609
3610 /* ENABLE_PCLK_APOLLO */
3611 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3612 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3613 2, CLK_IGNORE_UNUSED, 0),
3614 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3615 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3616 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3617 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3618 0, CLK_IGNORE_UNUSED, 0),
3619
3620 /* ENABLE_SCLK_APOLLO */
3621 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3622 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3623 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3624 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3625 };
3626
3627 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3628 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3629 ((pclk) << 12) | ((aclk) << 8))
3630
3631 #define E5433_APOLLO_DIV1(hpm, copy) \
3632 (((hpm) << 4) | ((copy) << 0))
3633
3634 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
3635 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3636 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3637 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3638 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3639 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3640 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3641 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3642 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3643 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3644 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3645 { 0 },
3646 };
3647
3648 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3649 {
3650 void __iomem *reg_base;
3651 struct samsung_clk_provider *ctx;
3652
3653 reg_base = of_iomap(np, 0);
3654 if (!reg_base) {
3655 panic("%s: failed to map registers\n", __func__);
3656 return;
3657 }
3658
3659 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
3660 if (!ctx) {
3661 panic("%s: unable to allocate ctx\n", __func__);
3662 return;
3663 }
3664
3665 samsung_clk_register_pll(ctx, apollo_pll_clks,
3666 ARRAY_SIZE(apollo_pll_clks), reg_base);
3667 samsung_clk_register_mux(ctx, apollo_mux_clks,
3668 ARRAY_SIZE(apollo_mux_clks));
3669 samsung_clk_register_div(ctx, apollo_div_clks,
3670 ARRAY_SIZE(apollo_div_clks));
3671 samsung_clk_register_gate(ctx, apollo_gate_clks,
3672 ARRAY_SIZE(apollo_gate_clks));
3673
3674 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
3675 mout_apollo_p[0], mout_apollo_p[1], 0x200,
3676 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
3677 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3678
3679 samsung_clk_sleep_init(reg_base, apollo_clk_regs,
3680 ARRAY_SIZE(apollo_clk_regs));
3681
3682 samsung_clk_of_add_provider(np, ctx);
3683 }
3684 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3685 exynos5433_cmu_apollo_init);
3686
3687 /*
3688 * Register offset definitions for CMU_ATLAS
3689 */
3690 #define ATLAS_PLL_LOCK 0x0000
3691 #define ATLAS_PLL_CON0 0x0100
3692 #define ATLAS_PLL_CON1 0x0104
3693 #define ATLAS_PLL_FREQ_DET 0x010c
3694 #define MUX_SEL_ATLAS0 0x0200
3695 #define MUX_SEL_ATLAS1 0x0204
3696 #define MUX_SEL_ATLAS2 0x0208
3697 #define MUX_ENABLE_ATLAS0 0x0300
3698 #define MUX_ENABLE_ATLAS1 0x0304
3699 #define MUX_ENABLE_ATLAS2 0x0308
3700 #define MUX_STAT_ATLAS0 0x0400
3701 #define MUX_STAT_ATLAS1 0x0404
3702 #define MUX_STAT_ATLAS2 0x0408
3703 #define DIV_ATLAS0 0x0600
3704 #define DIV_ATLAS1 0x0604
3705 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3706 #define DIV_STAT_ATLAS0 0x0700
3707 #define DIV_STAT_ATLAS1 0x0704
3708 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3709 #define ENABLE_ACLK_ATLAS 0x0800
3710 #define ENABLE_PCLK_ATLAS 0x0900
3711 #define ENABLE_SCLK_ATLAS 0x0a00
3712 #define ENABLE_IP_ATLAS0 0x0b00
3713 #define ENABLE_IP_ATLAS1 0x0b04
3714 #define CLKOUT_CMU_ATLAS 0x0c00
3715 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3716 #define ARMCLK_STOPCTRL 0x1000
3717 #define ATLAS_PWR_CTRL 0x1020
3718 #define ATLAS_PWR_CTRL2 0x1024
3719 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3720 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3721 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3722
3723 static const unsigned long atlas_clk_regs[] __initconst = {
3724 ATLAS_PLL_LOCK,
3725 ATLAS_PLL_CON0,
3726 ATLAS_PLL_CON1,
3727 ATLAS_PLL_FREQ_DET,
3728 MUX_SEL_ATLAS0,
3729 MUX_SEL_ATLAS1,
3730 MUX_SEL_ATLAS2,
3731 MUX_ENABLE_ATLAS0,
3732 MUX_ENABLE_ATLAS1,
3733 MUX_ENABLE_ATLAS2,
3734 DIV_ATLAS0,
3735 DIV_ATLAS1,
3736 DIV_ATLAS_PLL_FREQ_DET,
3737 ENABLE_ACLK_ATLAS,
3738 ENABLE_PCLK_ATLAS,
3739 ENABLE_SCLK_ATLAS,
3740 ENABLE_IP_ATLAS0,
3741 ENABLE_IP_ATLAS1,
3742 CLKOUT_CMU_ATLAS,
3743 CLKOUT_CMU_ATLAS_DIV_STAT,
3744 ARMCLK_STOPCTRL,
3745 ATLAS_PWR_CTRL,
3746 ATLAS_PWR_CTRL2,
3747 ATLAS_INTR_SPREAD_ENABLE,
3748 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3749 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3750 };
3751
3752 /* list of all parent clock list */
3753 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3754 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3755 PNAME(mout_atlas_p) = { "mout_atlas_pll",
3756 "mout_bus_pll_atlas_user", };
3757
3758 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3759 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3760 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates),
3761 };
3762
3763 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3764 /* MUX_SEL_ATLAS0 */
3765 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3766 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3767 CLK_RECALC_NEW_RATES, 0),
3768
3769 /* MUX_SEL_ATLAS1 */
3770 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3771 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3772
3773 /* MUX_SEL_ATLAS2 */
3774 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3775 0, 1, CLK_SET_RATE_PARENT, 0),
3776 };
3777
3778 static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3779 /* DIV_ATLAS0 */
3780 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3781 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3782 CLK_DIVIDER_READ_ONLY),
3783 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3784 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3785 CLK_DIVIDER_READ_ONLY),
3786 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3787 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3788 CLK_DIVIDER_READ_ONLY),
3789 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3790 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3791 CLK_DIVIDER_READ_ONLY),
3792 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3793 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3794 CLK_DIVIDER_READ_ONLY),
3795 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3796 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3797 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3798 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3799
3800 /* DIV_ATLAS1 */
3801 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3802 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3803 CLK_DIVIDER_READ_ONLY),
3804 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3805 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3806 CLK_DIVIDER_READ_ONLY),
3807 };
3808
3809 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3810 /* ENABLE_ACLK_ATLAS */
3811 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3812 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3813 9, CLK_IGNORE_UNUSED, 0),
3814 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3815 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3816 8, CLK_IGNORE_UNUSED, 0),
3817 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3818 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3819 7, CLK_IGNORE_UNUSED, 0),
3820 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3821 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3822 6, CLK_IGNORE_UNUSED, 0),
3823 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3824 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3825 5, CLK_IGNORE_UNUSED, 0),
3826 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3827 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3828 4, CLK_IGNORE_UNUSED, 0),
3829 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3830 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3831 3, CLK_IGNORE_UNUSED, 0),
3832 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3833 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3834 2, CLK_IGNORE_UNUSED, 0),
3835 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3836 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3837 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3838 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3839
3840 /* ENABLE_PCLK_ATLAS */
3841 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3842 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3843 5, CLK_IGNORE_UNUSED, 0),
3844 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3845 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3846 4, CLK_IGNORE_UNUSED, 0),
3847 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3848 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3849 3, CLK_IGNORE_UNUSED, 0),
3850 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3851 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3852 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3853 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3854 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3855 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3856
3857 /* ENABLE_SCLK_ATLAS */
3858 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3859 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3860 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3861 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3862 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3863 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3864 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3865 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3866 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3867 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3868 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3869 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3870 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3871 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3872 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3873 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3874 };
3875
3876 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3877 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3878 ((pclk) << 12) | ((aclk) << 8))
3879
3880 #define E5433_ATLAS_DIV1(hpm, copy) \
3881 (((hpm) << 4) | ((copy) << 0))
3882
3883 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
3884 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3885 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3886 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3887 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3888 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3889 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3890 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3891 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3892 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3893 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3894 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3895 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3896 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3897 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3898 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3899 { 0 },
3900 };
3901
3902 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3903 {
3904 void __iomem *reg_base;
3905 struct samsung_clk_provider *ctx;
3906
3907 reg_base = of_iomap(np, 0);
3908 if (!reg_base) {
3909 panic("%s: failed to map registers\n", __func__);
3910 return;
3911 }
3912
3913 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
3914 if (!ctx) {
3915 panic("%s: unable to allocate ctx\n", __func__);
3916 return;
3917 }
3918
3919 samsung_clk_register_pll(ctx, atlas_pll_clks,
3920 ARRAY_SIZE(atlas_pll_clks), reg_base);
3921 samsung_clk_register_mux(ctx, atlas_mux_clks,
3922 ARRAY_SIZE(atlas_mux_clks));
3923 samsung_clk_register_div(ctx, atlas_div_clks,
3924 ARRAY_SIZE(atlas_div_clks));
3925 samsung_clk_register_gate(ctx, atlas_gate_clks,
3926 ARRAY_SIZE(atlas_gate_clks));
3927
3928 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
3929 mout_atlas_p[0], mout_atlas_p[1], 0x200,
3930 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
3931 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3932
3933 samsung_clk_sleep_init(reg_base, atlas_clk_regs,
3934 ARRAY_SIZE(atlas_clk_regs));
3935
3936 samsung_clk_of_add_provider(np, ctx);
3937 }
3938 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3939 exynos5433_cmu_atlas_init);
3940
3941 /*
3942 * Register offset definitions for CMU_MSCL
3943 */
3944 #define MUX_SEL_MSCL0 0x0200
3945 #define MUX_SEL_MSCL1 0x0204
3946 #define MUX_ENABLE_MSCL0 0x0300
3947 #define MUX_ENABLE_MSCL1 0x0304
3948 #define MUX_STAT_MSCL0 0x0400
3949 #define MUX_STAT_MSCL1 0x0404
3950 #define DIV_MSCL 0x0600
3951 #define DIV_STAT_MSCL 0x0700
3952 #define ENABLE_ACLK_MSCL 0x0800
3953 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3954 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3955 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3956 #define ENABLE_PCLK_MSCL 0x0900
3957 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3958 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3959 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3960 #define ENABLE_SCLK_MSCL 0x0a00
3961 #define ENABLE_IP_MSCL0 0x0b00
3962 #define ENABLE_IP_MSCL1 0x0b04
3963 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3964 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3965 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3966
3967 static const unsigned long mscl_clk_regs[] __initconst = {
3968 MUX_SEL_MSCL0,
3969 MUX_SEL_MSCL1,
3970 MUX_ENABLE_MSCL0,
3971 MUX_ENABLE_MSCL1,
3972 DIV_MSCL,
3973 ENABLE_ACLK_MSCL,
3974 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3975 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3976 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3977 ENABLE_PCLK_MSCL,
3978 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3979 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3980 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3981 ENABLE_SCLK_MSCL,
3982 ENABLE_IP_MSCL0,
3983 ENABLE_IP_MSCL1,
3984 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3985 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3986 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3987 };
3988
3989 static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {
3990 { MUX_SEL_MSCL0, 0 },
3991 { MUX_SEL_MSCL1, 0 },
3992 };
3993
3994 /* list of all parent clock list */
3995 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3996 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3997 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3998 "mout_aclk_mscl_400_user", };
3999
4000 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
4001 /* MUX_SEL_MSCL0 */
4002 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
4003 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
4004 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
4005 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4006
4007 /* MUX_SEL_MSCL1 */
4008 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
4009 MUX_SEL_MSCL1, 0, 1),
4010 };
4011
4012 static const struct samsung_div_clock mscl_div_clks[] __initconst = {
4013 /* DIV_MSCL */
4014 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
4015 DIV_MSCL, 0, 3),
4016 };
4017
4018 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
4019 /* ENABLE_ACLK_MSCL */
4020 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
4021 ENABLE_ACLK_MSCL, 9, 0, 0),
4022 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
4023 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4024 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
4025 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4026 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
4027 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4028 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
4029 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4030 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4031 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4032 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4033 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4034 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4035 ENABLE_ACLK_MSCL, 2, 0, 0),
4036 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4037 ENABLE_ACLK_MSCL, 1, 0, 0),
4038 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4039 ENABLE_ACLK_MSCL, 0, 0, 0),
4040
4041 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4042 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4043 "mout_aclk_mscl_400_user",
4044 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4045 0, CLK_IGNORE_UNUSED, 0),
4046
4047 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4048 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4049 "mout_aclk_mscl_400_user",
4050 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4051 0, CLK_IGNORE_UNUSED, 0),
4052
4053 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4054 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4055 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4056 0, CLK_IGNORE_UNUSED, 0),
4057
4058 /* ENABLE_PCLK_MSCL */
4059 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4060 ENABLE_PCLK_MSCL, 7, 0, 0),
4061 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4062 ENABLE_PCLK_MSCL, 6, 0, 0),
4063 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4064 ENABLE_PCLK_MSCL, 5, 0, 0),
4065 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4066 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4067 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4068 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4069 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4070 ENABLE_PCLK_MSCL, 2, 0, 0),
4071 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4072 ENABLE_PCLK_MSCL, 1, 0, 0),
4073 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4074 ENABLE_PCLK_MSCL, 0, 0, 0),
4075
4076 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4077 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4078 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4079 0, CLK_IGNORE_UNUSED, 0),
4080
4081 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4082 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4083 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4084 0, CLK_IGNORE_UNUSED, 0),
4085
4086 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4087 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4088 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4089 0, CLK_IGNORE_UNUSED, 0),
4090
4091 /* ENABLE_SCLK_MSCL */
4092 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4093 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4094 };
4095
4096 static const struct samsung_cmu_info mscl_cmu_info __initconst = {
4097 .mux_clks = mscl_mux_clks,
4098 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
4099 .div_clks = mscl_div_clks,
4100 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
4101 .gate_clks = mscl_gate_clks,
4102 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
4103 .nr_clk_ids = MSCL_NR_CLK,
4104 .clk_regs = mscl_clk_regs,
4105 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
4106 .suspend_regs = mscl_suspend_regs,
4107 .nr_suspend_regs = ARRAY_SIZE(mscl_suspend_regs),
4108 .clk_name = "aclk_mscl_400",
4109 };
4110
4111 /*
4112 * Register offset definitions for CMU_MFC
4113 */
4114 #define MUX_SEL_MFC 0x0200
4115 #define MUX_ENABLE_MFC 0x0300
4116 #define MUX_STAT_MFC 0x0400
4117 #define DIV_MFC 0x0600
4118 #define DIV_STAT_MFC 0x0700
4119 #define ENABLE_ACLK_MFC 0x0800
4120 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4121 #define ENABLE_PCLK_MFC 0x0900
4122 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4123 #define ENABLE_IP_MFC0 0x0b00
4124 #define ENABLE_IP_MFC1 0x0b04
4125 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4126
4127 static const unsigned long mfc_clk_regs[] __initconst = {
4128 MUX_SEL_MFC,
4129 MUX_ENABLE_MFC,
4130 DIV_MFC,
4131 ENABLE_ACLK_MFC,
4132 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4133 ENABLE_PCLK_MFC,
4134 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4135 ENABLE_IP_MFC0,
4136 ENABLE_IP_MFC1,
4137 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4138 };
4139
4140 static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {
4141 { MUX_SEL_MFC, 0 },
4142 };
4143
4144 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4145
4146 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4147 /* MUX_SEL_MFC */
4148 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4149 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4150 };
4151
4152 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4153 /* DIV_MFC */
4154 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4155 DIV_MFC, 0, 2),
4156 };
4157
4158 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4159 /* ENABLE_ACLK_MFC */
4160 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4161 ENABLE_ACLK_MFC, 6, 0, 0),
4162 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4163 ENABLE_ACLK_MFC, 5, 0, 0),
4164 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4165 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4166 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4167 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4168 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4169 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4170 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4171 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4172 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4173 ENABLE_ACLK_MFC, 0, 0, 0),
4174
4175 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4176 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4177 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4178 1, CLK_IGNORE_UNUSED, 0),
4179 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4180 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4181 0, CLK_IGNORE_UNUSED, 0),
4182
4183 /* ENABLE_PCLK_MFC */
4184 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4185 ENABLE_PCLK_MFC, 4, 0, 0),
4186 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4187 ENABLE_PCLK_MFC, 3, 0, 0),
4188 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4189 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4190 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4191 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4192 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4193 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4194
4195 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4196 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4197 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4198 1, CLK_IGNORE_UNUSED, 0),
4199 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4200 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4201 0, CLK_IGNORE_UNUSED, 0),
4202 };
4203
4204 static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4205 .mux_clks = mfc_mux_clks,
4206 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4207 .div_clks = mfc_div_clks,
4208 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4209 .gate_clks = mfc_gate_clks,
4210 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4211 .nr_clk_ids = MFC_NR_CLK,
4212 .clk_regs = mfc_clk_regs,
4213 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4214 .suspend_regs = mfc_suspend_regs,
4215 .nr_suspend_regs = ARRAY_SIZE(mfc_suspend_regs),
4216 .clk_name = "aclk_mfc_400",
4217 };
4218
4219 /*
4220 * Register offset definitions for CMU_HEVC
4221 */
4222 #define MUX_SEL_HEVC 0x0200
4223 #define MUX_ENABLE_HEVC 0x0300
4224 #define MUX_STAT_HEVC 0x0400
4225 #define DIV_HEVC 0x0600
4226 #define DIV_STAT_HEVC 0x0700
4227 #define ENABLE_ACLK_HEVC 0x0800
4228 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4229 #define ENABLE_PCLK_HEVC 0x0900
4230 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4231 #define ENABLE_IP_HEVC0 0x0b00
4232 #define ENABLE_IP_HEVC1 0x0b04
4233 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4234
4235 static const unsigned long hevc_clk_regs[] __initconst = {
4236 MUX_SEL_HEVC,
4237 MUX_ENABLE_HEVC,
4238 DIV_HEVC,
4239 ENABLE_ACLK_HEVC,
4240 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4241 ENABLE_PCLK_HEVC,
4242 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4243 ENABLE_IP_HEVC0,
4244 ENABLE_IP_HEVC1,
4245 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4246 };
4247
4248 static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {
4249 { MUX_SEL_HEVC, 0 },
4250 };
4251
4252 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4253
4254 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4255 /* MUX_SEL_HEVC */
4256 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4257 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4258 };
4259
4260 static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4261 /* DIV_HEVC */
4262 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4263 DIV_HEVC, 0, 2),
4264 };
4265
4266 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4267 /* ENABLE_ACLK_HEVC */
4268 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4269 ENABLE_ACLK_HEVC, 6, 0, 0),
4270 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4271 ENABLE_ACLK_HEVC, 5, 0, 0),
4272 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4273 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4274 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4275 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4276 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4277 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4278 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4279 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4280 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4281 ENABLE_ACLK_HEVC, 0, 0, 0),
4282
4283 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4284 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4285 "mout_aclk_hevc_400_user",
4286 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4287 1, CLK_IGNORE_UNUSED, 0),
4288 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4289 "mout_aclk_hevc_400_user",
4290 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4291 0, CLK_IGNORE_UNUSED, 0),
4292
4293 /* ENABLE_PCLK_HEVC */
4294 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4295 ENABLE_PCLK_HEVC, 4, 0, 0),
4296 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4297 ENABLE_PCLK_HEVC, 3, 0, 0),
4298 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4299 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4300 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4301 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4302 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4303 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4304
4305 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4306 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4307 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4308 1, CLK_IGNORE_UNUSED, 0),
4309 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4310 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4311 0, CLK_IGNORE_UNUSED, 0),
4312 };
4313
4314 static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4315 .mux_clks = hevc_mux_clks,
4316 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4317 .div_clks = hevc_div_clks,
4318 .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
4319 .gate_clks = hevc_gate_clks,
4320 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
4321 .nr_clk_ids = HEVC_NR_CLK,
4322 .clk_regs = hevc_clk_regs,
4323 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4324 .suspend_regs = hevc_suspend_regs,
4325 .nr_suspend_regs = ARRAY_SIZE(hevc_suspend_regs),
4326 .clk_name = "aclk_hevc_400",
4327 };
4328
4329 /*
4330 * Register offset definitions for CMU_ISP
4331 */
4332 #define MUX_SEL_ISP 0x0200
4333 #define MUX_ENABLE_ISP 0x0300
4334 #define MUX_STAT_ISP 0x0400
4335 #define DIV_ISP 0x0600
4336 #define DIV_STAT_ISP 0x0700
4337 #define ENABLE_ACLK_ISP0 0x0800
4338 #define ENABLE_ACLK_ISP1 0x0804
4339 #define ENABLE_ACLK_ISP2 0x0808
4340 #define ENABLE_PCLK_ISP 0x0900
4341 #define ENABLE_SCLK_ISP 0x0a00
4342 #define ENABLE_IP_ISP0 0x0b00
4343 #define ENABLE_IP_ISP1 0x0b04
4344 #define ENABLE_IP_ISP2 0x0b08
4345 #define ENABLE_IP_ISP3 0x0b0c
4346
4347 static const unsigned long isp_clk_regs[] __initconst = {
4348 MUX_SEL_ISP,
4349 MUX_ENABLE_ISP,
4350 DIV_ISP,
4351 ENABLE_ACLK_ISP0,
4352 ENABLE_ACLK_ISP1,
4353 ENABLE_ACLK_ISP2,
4354 ENABLE_PCLK_ISP,
4355 ENABLE_SCLK_ISP,
4356 ENABLE_IP_ISP0,
4357 ENABLE_IP_ISP1,
4358 ENABLE_IP_ISP2,
4359 ENABLE_IP_ISP3,
4360 };
4361
4362 static const struct samsung_clk_reg_dump isp_suspend_regs[] = {
4363 { MUX_SEL_ISP, 0 },
4364 };
4365
4366 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4367 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4368
4369 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4370 /* MUX_SEL_ISP */
4371 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4372 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4373 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4374 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4375 };
4376
4377 static const struct samsung_div_clock isp_div_clks[] __initconst = {
4378 /* DIV_ISP */
4379 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4380 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4381 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4382 DIV_ISP, 8, 3),
4383 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4384 "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4385 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4386 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4387 };
4388
4389 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4390 /* ENABLE_ACLK_ISP0 */
4391 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4392 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4393 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4394 ENABLE_ACLK_ISP0, 5, 0, 0),
4395 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4396 ENABLE_ACLK_ISP0, 4, 0, 0),
4397 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4398 ENABLE_ACLK_ISP0, 3, 0, 0),
4399 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4400 ENABLE_ACLK_ISP0, 2, 0, 0),
4401 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4402 ENABLE_ACLK_ISP0, 1, 0, 0),
4403 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4404 ENABLE_ACLK_ISP0, 0, 0, 0),
4405
4406 /* ENABLE_ACLK_ISP1 */
4407 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4408 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4409 17, CLK_IGNORE_UNUSED, 0),
4410 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4411 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4412 16, CLK_IGNORE_UNUSED, 0),
4413 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4414 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4415 15, CLK_IGNORE_UNUSED, 0),
4416 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4417 "div_pclk_isp", ENABLE_ACLK_ISP1,
4418 14, CLK_IGNORE_UNUSED, 0),
4419 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4420 "div_pclk_isp", ENABLE_ACLK_ISP1,
4421 13, CLK_IGNORE_UNUSED, 0),
4422 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4423 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4424 12, CLK_IGNORE_UNUSED, 0),
4425 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4426 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4427 11, CLK_IGNORE_UNUSED, 0),
4428 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4429 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4430 10, CLK_IGNORE_UNUSED, 0),
4431 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4432 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4433 9, CLK_IGNORE_UNUSED, 0),
4434 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4435 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4436 8, CLK_IGNORE_UNUSED, 0),
4437 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4438 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4439 7, CLK_IGNORE_UNUSED, 0),
4440 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4441 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4442 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4443 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4444 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4445 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4446 4, CLK_IGNORE_UNUSED, 0),
4447 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4448 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4449 3, CLK_IGNORE_UNUSED, 0),
4450 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4451 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4452 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4453 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4454 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4455 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4456
4457 /* ENABLE_ACLK_ISP2 */
4458 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4459 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4460 13, CLK_IGNORE_UNUSED, 0),
4461 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4462 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4463 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4464 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4465 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4466 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4467 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4468 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4469 9, CLK_IGNORE_UNUSED, 0),
4470 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4471 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4472 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4473 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4474 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4475 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4476 6, CLK_IGNORE_UNUSED, 0),
4477 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4478 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4479 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4480 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4481 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4482 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4483 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4484 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4485 2, CLK_IGNORE_UNUSED, 0),
4486 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4487 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4488 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4489 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4490
4491 /* ENABLE_PCLK_ISP */
4492 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4493 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4494 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4495 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4496 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4497 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4498 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4499 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4500 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4501 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4502 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4503 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4504 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4505 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4506 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4507 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4508 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4509 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4510 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4511 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4512 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4513 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4514 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4515 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4516 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4517 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4518 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4519 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4520 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4521 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4522 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4523 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4524 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4525 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4526 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4527 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4528 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4529 "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4530 7, CLK_IGNORE_UNUSED, 0),
4531 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4532 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4533 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4534 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4535 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4536 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4537 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4538 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4539 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4540 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4541 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4542 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4543 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4544 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4545
4546 /* ENABLE_SCLK_ISP */
4547 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4548 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4549 5, CLK_IGNORE_UNUSED, 0),
4550 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4551 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4552 4, CLK_IGNORE_UNUSED, 0),
4553 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4554 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4555 3, CLK_IGNORE_UNUSED, 0),
4556 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4557 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4558 2, CLK_IGNORE_UNUSED, 0),
4559 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4560 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4561 1, CLK_IGNORE_UNUSED, 0),
4562 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4563 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4564 0, CLK_IGNORE_UNUSED, 0),
4565 };
4566
4567 static const struct samsung_cmu_info isp_cmu_info __initconst = {
4568 .mux_clks = isp_mux_clks,
4569 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4570 .div_clks = isp_div_clks,
4571 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
4572 .gate_clks = isp_gate_clks,
4573 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
4574 .nr_clk_ids = ISP_NR_CLK,
4575 .clk_regs = isp_clk_regs,
4576 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
4577 .suspend_regs = isp_suspend_regs,
4578 .nr_suspend_regs = ARRAY_SIZE(isp_suspend_regs),
4579 .clk_name = "aclk_isp_400",
4580 };
4581
4582 /*
4583 * Register offset definitions for CMU_CAM0
4584 */
4585 #define MUX_SEL_CAM00 0x0200
4586 #define MUX_SEL_CAM01 0x0204
4587 #define MUX_SEL_CAM02 0x0208
4588 #define MUX_SEL_CAM03 0x020c
4589 #define MUX_SEL_CAM04 0x0210
4590 #define MUX_ENABLE_CAM00 0x0300
4591 #define MUX_ENABLE_CAM01 0x0304
4592 #define MUX_ENABLE_CAM02 0x0308
4593 #define MUX_ENABLE_CAM03 0x030c
4594 #define MUX_ENABLE_CAM04 0x0310
4595 #define MUX_STAT_CAM00 0x0400
4596 #define MUX_STAT_CAM01 0x0404
4597 #define MUX_STAT_CAM02 0x0408
4598 #define MUX_STAT_CAM03 0x040c
4599 #define MUX_STAT_CAM04 0x0410
4600 #define MUX_IGNORE_CAM01 0x0504
4601 #define DIV_CAM00 0x0600
4602 #define DIV_CAM01 0x0604
4603 #define DIV_CAM02 0x0608
4604 #define DIV_CAM03 0x060c
4605 #define DIV_STAT_CAM00 0x0700
4606 #define DIV_STAT_CAM01 0x0704
4607 #define DIV_STAT_CAM02 0x0708
4608 #define DIV_STAT_CAM03 0x070c
4609 #define ENABLE_ACLK_CAM00 0X0800
4610 #define ENABLE_ACLK_CAM01 0X0804
4611 #define ENABLE_ACLK_CAM02 0X0808
4612 #define ENABLE_PCLK_CAM0 0X0900
4613 #define ENABLE_SCLK_CAM0 0X0a00
4614 #define ENABLE_IP_CAM00 0X0b00
4615 #define ENABLE_IP_CAM01 0X0b04
4616 #define ENABLE_IP_CAM02 0X0b08
4617 #define ENABLE_IP_CAM03 0X0b0C
4618
4619 static const unsigned long cam0_clk_regs[] __initconst = {
4620 MUX_SEL_CAM00,
4621 MUX_SEL_CAM01,
4622 MUX_SEL_CAM02,
4623 MUX_SEL_CAM03,
4624 MUX_SEL_CAM04,
4625 MUX_ENABLE_CAM00,
4626 MUX_ENABLE_CAM01,
4627 MUX_ENABLE_CAM02,
4628 MUX_ENABLE_CAM03,
4629 MUX_ENABLE_CAM04,
4630 MUX_IGNORE_CAM01,
4631 DIV_CAM00,
4632 DIV_CAM01,
4633 DIV_CAM02,
4634 DIV_CAM03,
4635 ENABLE_ACLK_CAM00,
4636 ENABLE_ACLK_CAM01,
4637 ENABLE_ACLK_CAM02,
4638 ENABLE_PCLK_CAM0,
4639 ENABLE_SCLK_CAM0,
4640 ENABLE_IP_CAM00,
4641 ENABLE_IP_CAM01,
4642 ENABLE_IP_CAM02,
4643 ENABLE_IP_CAM03,
4644 };
4645
4646 static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {
4647 { MUX_SEL_CAM00, 0 },
4648 { MUX_SEL_CAM01, 0 },
4649 { MUX_SEL_CAM02, 0 },
4650 { MUX_SEL_CAM03, 0 },
4651 { MUX_SEL_CAM04, 0 },
4652 };
4653
4654 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
4655 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
4656 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
4657
4658 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4659 "phyclk_rxbyteclkhs0_s4_phy", };
4660 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4661 "phyclk_rxbyteclkhs0_s2a_phy", };
4662
4663 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
4664 "mout_aclk_cam0_333_user", };
4665 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
4666 "mout_aclk_cam0_400_user", };
4667 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
4668 "mout_aclk_cam0_333_user", };
4669 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
4670 "mout_aclk_cam0_400_user", };
4671 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
4672 "mout_aclk_cam0_333_user", };
4673 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
4674 "mout_aclk_cam0_400_user", };
4675 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
4676 "mout_aclk_cam0_333_user", };
4677
4678 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
4679 "mout_aclk_cam0_333_user" };
4680 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
4681 "mout_aclk_cam0_400_user", };
4682 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
4683 "mout_aclk_cam0_333_user", };
4684 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
4685 "mout_aclk-cam0_400_user", };
4686 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
4687 "mout_aclk_cam0_333_user", };
4688 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
4689 "mout_aclk_cam0_400_user", };
4690 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
4691 "mout_aclk_cam0_333_user", };
4692 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
4693 "mout_aclk_cam0_400_user", };
4694
4695 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
4696 "div_pclk_lite_d", };
4697 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
4698 "div_pclk_pixelasync_lite_c", };
4699 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
4700 "div_pclk_lite_b", };
4701 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
4702 "mout_aclk_cam0_333_user", };
4703 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
4704 "mout_aclk_cam0_400_user", };
4705 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4706 "mout_sclk_pixelasync_lite_c_init_a",
4707 "mout_aclk_cam0_400_user", };
4708 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4709 "mout_aclk_cam0_552_user",
4710 "mout_aclk_cam0_400_user", };
4711
4712 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4713 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4714 NULL, 0, 100000000),
4715 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4716 NULL, 0, 100000000),
4717 };
4718
4719 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4720 /* MUX_SEL_CAM00 */
4721 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4722 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4723 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4724 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4725 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4726 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4727
4728 /* MUX_SEL_CAM01 */
4729 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4730 "mout_phyclk_rxbyteclkhs0_s4_user",
4731 mout_phyclk_rxbyteclkhs0_s4_user_p,
4732 MUX_SEL_CAM01, 4, 1),
4733 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4734 "mout_phyclk_rxbyteclkhs0_s2a_user",
4735 mout_phyclk_rxbyteclkhs0_s2a_user_p,
4736 MUX_SEL_CAM01, 0, 1),
4737
4738 /* MUX_SEL_CAM02 */
4739 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4740 MUX_SEL_CAM02, 24, 1),
4741 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4742 MUX_SEL_CAM02, 20, 1),
4743 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4744 MUX_SEL_CAM02, 16, 1),
4745 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4746 MUX_SEL_CAM02, 12, 1),
4747 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4748 MUX_SEL_CAM02, 8, 1),
4749 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4750 MUX_SEL_CAM02, 4, 1),
4751 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4752 MUX_SEL_CAM02, 0, 1),
4753
4754 /* MUX_SEL_CAM03 */
4755 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4756 MUX_SEL_CAM03, 28, 1),
4757 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4758 MUX_SEL_CAM03, 24, 1),
4759 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4760 MUX_SEL_CAM03, 20, 1),
4761 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4762 MUX_SEL_CAM03, 16, 1),
4763 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4764 MUX_SEL_CAM03, 12, 1),
4765 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4766 MUX_SEL_CAM03, 8, 1),
4767 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4768 MUX_SEL_CAM03, 4, 1),
4769 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4770 MUX_SEL_CAM03, 0, 1),
4771
4772 /* MUX_SEL_CAM04 */
4773 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4774 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4775 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4776 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4777 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4778 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4779 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4780 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4781 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4782 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4783 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4784 "mout_sclk_pixelasync_lite_c_init_b",
4785 mout_sclk_pixelasync_lite_c_init_b_p,
4786 MUX_SEL_CAM04, 4, 1),
4787 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4788 "mout_sclk_pixelasync_lite_c_init_a",
4789 mout_sclk_pixelasync_lite_c_init_a_p,
4790 MUX_SEL_CAM04, 0, 1),
4791 };
4792
4793 static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4794 /* DIV_CAM00 */
4795 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4796 DIV_CAM00, 8, 2),
4797 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4798 DIV_CAM00, 4, 3),
4799 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4800 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4801
4802 /* DIV_CAM01 */
4803 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4804 DIV_CAM01, 20, 2),
4805 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4806 DIV_CAM01, 16, 3),
4807 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4808 DIV_CAM01, 12, 2),
4809 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4810 DIV_CAM01, 8, 3),
4811 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4812 DIV_CAM01, 4, 2),
4813 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4814 DIV_CAM01, 0, 3),
4815
4816 /* DIV_CAM02 */
4817 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4818 DIV_CAM02, 20, 3),
4819 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4820 DIV_CAM02, 16, 3),
4821 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4822 DIV_CAM02, 12, 2),
4823 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4824 DIV_CAM02, 8, 3),
4825 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4826 DIV_CAM02, 4, 2),
4827 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4828 DIV_CAM02, 0, 3),
4829
4830 /* DIV_CAM03 */
4831 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4832 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4833 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4834 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4835 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4836 "div_sclk_pixelasync_lite_c_init",
4837 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4838 };
4839
4840 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4841 /* ENABLE_ACLK_CAM00 */
4842 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4843 6, 0, 0),
4844 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4845 5, 0, 0),
4846 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4847 4, 0, 0),
4848 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4849 3, 0, 0),
4850 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4851 ENABLE_ACLK_CAM00, 2, 0, 0),
4852 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4853 ENABLE_ACLK_CAM00, 1, 0, 0),
4854 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4855 ENABLE_ACLK_CAM00, 0, 0, 0),
4856
4857 /* ENABLE_ACLK_CAM01 */
4858 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4859 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4860 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4861 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4862 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4863 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4864 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4865 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4866 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4867 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4868 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4869 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4870 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4871 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4872 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4873 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4874 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4875 "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4876 23, CLK_IGNORE_UNUSED, 0),
4877 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4878 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4879 22, CLK_IGNORE_UNUSED, 0),
4880 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4881 "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4882 21, CLK_IGNORE_UNUSED, 0),
4883 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4884 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4885 20, CLK_IGNORE_UNUSED, 0),
4886 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4887 "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4888 19, CLK_IGNORE_UNUSED, 0),
4889 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4890 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4891 18, CLK_IGNORE_UNUSED, 0),
4892 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4893 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4894 17, CLK_IGNORE_UNUSED, 0),
4895 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4896 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4897 16, CLK_IGNORE_UNUSED, 0),
4898 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4899 "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4900 15, CLK_IGNORE_UNUSED, 0),
4901 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4902 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4903 14, CLK_IGNORE_UNUSED, 0),
4904 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4905 "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4906 13, CLK_IGNORE_UNUSED, 0),
4907 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4908 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4909 12, CLK_IGNORE_UNUSED, 0),
4910 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4911 "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4912 11, CLK_IGNORE_UNUSED, 0),
4913 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4914 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4915 10, CLK_IGNORE_UNUSED, 0),
4916 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4917 "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4918 9, CLK_IGNORE_UNUSED, 0),
4919 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4920 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4921 8, CLK_IGNORE_UNUSED, 0),
4922 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4923 "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4924 7, CLK_IGNORE_UNUSED, 0),
4925 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4926 "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4927 6, CLK_IGNORE_UNUSED, 0),
4928 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4929 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4930 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4931 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4932 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4933 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4934 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4935 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4936 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4937 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4938 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4939 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4940
4941 /* ENABLE_ACLK_CAM02 */
4942 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4943 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4944 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4945 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4946 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4947 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4948 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4949 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4950 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4951 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4952 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4953 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4954 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4955 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4956 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4957 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4958 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4959 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4960 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4961 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4962
4963 /* ENABLE_PCLK_CAM0 */
4964 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4965 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4966 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4967 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4968 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4969 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
4970 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
4971 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
4972 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
4973 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
4974 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
4975 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
4976 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
4977 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
4978 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
4979 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
4980 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
4981 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
4982 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
4983 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
4984 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
4985 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
4986 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
4987 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
4988 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
4989 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
4990 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
4991 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4992 12, CLK_IGNORE_UNUSED, 0),
4993 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
4994 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4995 11, CLK_IGNORE_UNUSED, 0),
4996 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
4997 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4998 10, CLK_IGNORE_UNUSED, 0),
4999 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
5000 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5001 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
5002 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5003 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
5004 "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
5005 7, CLK_IGNORE_UNUSED, 0),
5006 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
5007 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5008 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
5009 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5010 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
5011 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5012 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
5013 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5014 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
5015 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5016 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
5017 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5018 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
5019 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5020
5021 /* ENABLE_SCLK_CAM0 */
5022 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
5023 "mout_phyclk_rxbyteclkhs0_s4_user",
5024 ENABLE_SCLK_CAM0, 8, 0, 0),
5025 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5026 "mout_phyclk_rxbyteclkhs0_s2a_user",
5027 ENABLE_SCLK_CAM0, 7, 0, 0),
5028 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5029 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5030 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5031 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5032 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5033 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5034 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5035 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5036 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5037 "div_sclk_pixelasync_lite_c",
5038 ENABLE_SCLK_CAM0, 2, 0, 0),
5039 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5040 "div_sclk_pixelasync_lite_c_init",
5041 ENABLE_SCLK_CAM0, 1, 0, 0),
5042 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5043 "div_sclk_pixelasync_lite_c",
5044 ENABLE_SCLK_CAM0, 0, 0, 0),
5045 };
5046
5047 static const struct samsung_cmu_info cam0_cmu_info __initconst = {
5048 .mux_clks = cam0_mux_clks,
5049 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
5050 .div_clks = cam0_div_clks,
5051 .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
5052 .gate_clks = cam0_gate_clks,
5053 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
5054 .fixed_clks = cam0_fixed_clks,
5055 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
5056 .nr_clk_ids = CAM0_NR_CLK,
5057 .clk_regs = cam0_clk_regs,
5058 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
5059 .suspend_regs = cam0_suspend_regs,
5060 .nr_suspend_regs = ARRAY_SIZE(cam0_suspend_regs),
5061 .clk_name = "aclk_cam0_400",
5062 };
5063
5064 /*
5065 * Register offset definitions for CMU_CAM1
5066 */
5067 #define MUX_SEL_CAM10 0x0200
5068 #define MUX_SEL_CAM11 0x0204
5069 #define MUX_SEL_CAM12 0x0208
5070 #define MUX_ENABLE_CAM10 0x0300
5071 #define MUX_ENABLE_CAM11 0x0304
5072 #define MUX_ENABLE_CAM12 0x0308
5073 #define MUX_STAT_CAM10 0x0400
5074 #define MUX_STAT_CAM11 0x0404
5075 #define MUX_STAT_CAM12 0x0408
5076 #define MUX_IGNORE_CAM11 0x0504
5077 #define DIV_CAM10 0x0600
5078 #define DIV_CAM11 0x0604
5079 #define DIV_STAT_CAM10 0x0700
5080 #define DIV_STAT_CAM11 0x0704
5081 #define ENABLE_ACLK_CAM10 0X0800
5082 #define ENABLE_ACLK_CAM11 0X0804
5083 #define ENABLE_ACLK_CAM12 0X0808
5084 #define ENABLE_PCLK_CAM1 0X0900
5085 #define ENABLE_SCLK_CAM1 0X0a00
5086 #define ENABLE_IP_CAM10 0X0b00
5087 #define ENABLE_IP_CAM11 0X0b04
5088 #define ENABLE_IP_CAM12 0X0b08
5089
5090 static const unsigned long cam1_clk_regs[] __initconst = {
5091 MUX_SEL_CAM10,
5092 MUX_SEL_CAM11,
5093 MUX_SEL_CAM12,
5094 MUX_ENABLE_CAM10,
5095 MUX_ENABLE_CAM11,
5096 MUX_ENABLE_CAM12,
5097 MUX_IGNORE_CAM11,
5098 DIV_CAM10,
5099 DIV_CAM11,
5100 ENABLE_ACLK_CAM10,
5101 ENABLE_ACLK_CAM11,
5102 ENABLE_ACLK_CAM12,
5103 ENABLE_PCLK_CAM1,
5104 ENABLE_SCLK_CAM1,
5105 ENABLE_IP_CAM10,
5106 ENABLE_IP_CAM11,
5107 ENABLE_IP_CAM12,
5108 };
5109
5110 static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {
5111 { MUX_SEL_CAM10, 0 },
5112 { MUX_SEL_CAM11, 0 },
5113 { MUX_SEL_CAM12, 0 },
5114 };
5115
5116 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
5117 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
5118 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
5119
5120 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
5121 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
5122 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
5123
5124 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5125 "phyclk_rxbyteclkhs0_s2b_phy", };
5126
5127 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
5128 "mout_aclk_cam1_333_user", };
5129 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
5130 "mout_aclk_cam1_400_user", };
5131
5132 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
5133 "mout_aclk_cam1_333_user", };
5134 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
5135 "mout_aclk_cam1_400_user", };
5136
5137 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5138 "mout_aclk_cam1_333_user", };
5139 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5140 "mout_aclk_cam1_400_user", };
5141
5142 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5143 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5144 0, 100000000),
5145 };
5146
5147 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5148 /* MUX_SEL_CAM10 */
5149 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5150 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5151 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5152 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5153 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5154 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5155 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5156 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5157 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5158 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
5159 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5160 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5161
5162 /* MUX_SEL_CAM11 */
5163 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5164 "mout_phyclk_rxbyteclkhs0_s2b_user",
5165 mout_phyclk_rxbyteclkhs0_s2b_user_p,
5166 MUX_SEL_CAM11, 0, 1),
5167
5168 /* MUX_SEL_CAM12 */
5169 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5170 MUX_SEL_CAM12, 20, 1),
5171 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5172 MUX_SEL_CAM12, 16, 1),
5173 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5174 MUX_SEL_CAM12, 12, 1),
5175 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5176 MUX_SEL_CAM12, 8, 1),
5177 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5178 MUX_SEL_CAM12, 4, 1),
5179 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5180 MUX_SEL_CAM12, 0, 1),
5181 };
5182
5183 static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5184 /* DIV_CAM10 */
5185 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5186 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5187 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5188 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5189 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5190 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5191 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5192 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5193 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5194 DIV_CAM10, 0, 3),
5195
5196 /* DIV_CAM11 */
5197 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5198 DIV_CAM11, 16, 3),
5199 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5200 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5201 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5202 DIV_CAM11, 4, 2),
5203 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5204 DIV_CAM11, 0, 3),
5205 };
5206
5207 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5208 /* ENABLE_ACLK_CAM10 */
5209 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5210 ENABLE_ACLK_CAM10, 4, 0, 0),
5211 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5212 ENABLE_ACLK_CAM10, 3, 0, 0),
5213 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5214 ENABLE_ACLK_CAM10, 1, 0, 0),
5215 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5216 ENABLE_ACLK_CAM10, 0, 0, 0),
5217
5218 /* ENABLE_ACLK_CAM11 */
5219 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5220 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5221 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5222 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5223 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5224 "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5225 27, CLK_IGNORE_UNUSED, 0),
5226 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5227 "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5228 26, CLK_IGNORE_UNUSED, 0),
5229 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5230 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5231 25, CLK_IGNORE_UNUSED, 0),
5232 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5233 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5234 24, CLK_IGNORE_UNUSED, 0),
5235 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5236 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5237 23, CLK_IGNORE_UNUSED, 0),
5238 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5239 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5240 22, CLK_IGNORE_UNUSED, 0),
5241 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5242 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5243 21, CLK_IGNORE_UNUSED, 0),
5244 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5245 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5246 20, CLK_IGNORE_UNUSED, 0),
5247 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5248 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5249 19, CLK_IGNORE_UNUSED, 0),
5250 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5251 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5252 18, CLK_IGNORE_UNUSED, 0),
5253 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5254 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5255 17, CLK_IGNORE_UNUSED, 0),
5256 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5257 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5258 16, CLK_IGNORE_UNUSED, 0),
5259 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5260 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5261 15, CLK_IGNORE_UNUSED, 0),
5262 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5263 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5264 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5265 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5266 13, CLK_IGNORE_UNUSED, 0),
5267 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5268 "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5269 12, CLK_IGNORE_UNUSED, 0),
5270 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5271 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5272 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5273 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5274 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5275 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5276 9, CLK_IGNORE_UNUSED, 0),
5277 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5278 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5279 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5280 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5281 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5282 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5283 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5284 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5285 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5286 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5287 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5288 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5289 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5290 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5291 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5292 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5293 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5294 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5295
5296 /* ENABLE_ACLK_CAM12 */
5297 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5298 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5299 10, CLK_IGNORE_UNUSED, 0),
5300 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5301 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5302 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5303 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5304 8, CLK_IGNORE_UNUSED, 0),
5305 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5306 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5307 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5308 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5309 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5310 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5311 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5312 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5313 4, CLK_IGNORE_UNUSED, 0),
5314 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5315 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5316 3, CLK_IGNORE_UNUSED, 0),
5317 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5318 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5319 2, CLK_IGNORE_UNUSED, 0),
5320 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5321 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5322 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5323 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5324 0, CLK_IGNORE_UNUSED, 0),
5325
5326 /* ENABLE_PCLK_CAM1 */
5327 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5328 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5329 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5330 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5331 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5332 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5333 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5334 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5335 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5336 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5337 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5338 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5339 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5340 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5341 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5342 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5343 20, CLK_IGNORE_UNUSED, 0),
5344 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5345 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5346 19, CLK_IGNORE_UNUSED, 0),
5347 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5348 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5349 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5350 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5351 17, CLK_IGNORE_UNUSED, 0),
5352 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5353 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5354 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5355 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5356 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5357 "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5358 14, CLK_IGNORE_UNUSED, 0),
5359 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5360 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5361 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5362 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5363 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5364 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5365 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5366 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5367 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5368 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5369 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5370 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5371 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5372 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5373 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5374 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5375 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5376 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5377 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5378 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5379 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
5380 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5381 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5382 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5383 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5384 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5385 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5386 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5387
5388 /* ENABLE_SCLK_CAM1 */
5389 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5390 15, 0, 0),
5391 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5392 14, 0, 0),
5393 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5394 13, 0, 0),
5395 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5396 12, 0, 0),
5397 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5398 "mout_phyclk_rxbyteclkhs0_s2b_user",
5399 ENABLE_SCLK_CAM1, 11, 0, 0),
5400 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5401 ENABLE_SCLK_CAM1, 10, 0, 0),
5402 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5403 ENABLE_SCLK_CAM1, 9, 0, 0),
5404 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5405 ENABLE_SCLK_CAM1, 7, 0, 0),
5406 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5407 ENABLE_SCLK_CAM1, 6, 0, 0),
5408 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5409 ENABLE_SCLK_CAM1, 5, 0, 0),
5410 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5411 ENABLE_SCLK_CAM1, 4, 0, 0),
5412 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
5413 ENABLE_SCLK_CAM1, 3, 0, 0),
5414 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5415 ENABLE_SCLK_CAM1, 2, 0, 0),
5416 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5417 ENABLE_SCLK_CAM1, 1, 0, 0),
5418 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5419 ENABLE_SCLK_CAM1, 0, 0, 0),
5420 };
5421
5422 static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5423 .mux_clks = cam1_mux_clks,
5424 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5425 .div_clks = cam1_div_clks,
5426 .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
5427 .gate_clks = cam1_gate_clks,
5428 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
5429 .fixed_clks = cam1_fixed_clks,
5430 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
5431 .nr_clk_ids = CAM1_NR_CLK,
5432 .clk_regs = cam1_clk_regs,
5433 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
5434 .suspend_regs = cam1_suspend_regs,
5435 .nr_suspend_regs = ARRAY_SIZE(cam1_suspend_regs),
5436 .clk_name = "aclk_cam1_400",
5437 };
5438
5439
5440 struct exynos5433_cmu_data {
5441 struct samsung_clk_reg_dump *clk_save;
5442 unsigned int nr_clk_save;
5443 const struct samsung_clk_reg_dump *clk_suspend;
5444 unsigned int nr_clk_suspend;
5445
5446 struct clk *clk;
5447 struct clk **pclks;
5448 int nr_pclks;
5449
5450 /* must be the last entry */
5451 struct samsung_clk_provider ctx;
5452 };
5453
5454 static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
5455 {
5456 struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5457 int i;
5458
5459 samsung_clk_save(data->ctx.reg_base, data->clk_save,
5460 data->nr_clk_save);
5461
5462 for (i = 0; i < data->nr_pclks; i++)
5463 clk_prepare_enable(data->pclks[i]);
5464
5465 /* for suspend some registers have to be set to certain values */
5466 samsung_clk_restore(data->ctx.reg_base, data->clk_suspend,
5467 data->nr_clk_suspend);
5468
5469 for (i = 0; i < data->nr_pclks; i++)
5470 clk_disable_unprepare(data->pclks[i]);
5471
5472 clk_disable_unprepare(data->clk);
5473
5474 return 0;
5475 }
5476
5477 static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
5478 {
5479 struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5480 int i;
5481
5482 clk_prepare_enable(data->clk);
5483
5484 for (i = 0; i < data->nr_pclks; i++)
5485 clk_prepare_enable(data->pclks[i]);
5486
5487 samsung_clk_restore(data->ctx.reg_base, data->clk_save,
5488 data->nr_clk_save);
5489
5490 for (i = 0; i < data->nr_pclks; i++)
5491 clk_disable_unprepare(data->pclks[i]);
5492
5493 return 0;
5494 }
5495
5496 static int __init exynos5433_cmu_probe(struct platform_device *pdev)
5497 {
5498 const struct samsung_cmu_info *info;
5499 struct exynos5433_cmu_data *data;
5500 struct samsung_clk_provider *ctx;
5501 struct device *dev = &pdev->dev;
5502 struct resource *res;
5503 void __iomem *reg_base;
5504 int i;
5505
5506 info = of_device_get_match_data(dev);
5507
5508 data = devm_kzalloc(dev,
5509 struct_size(data, ctx.clk_data.hws, info->nr_clk_ids),
5510 GFP_KERNEL);
5511 if (!data)
5512 return -ENOMEM;
5513 ctx = &data->ctx;
5514
5515 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5516 reg_base = devm_ioremap_resource(dev, res);
5517 if (IS_ERR(reg_base))
5518 return PTR_ERR(reg_base);
5519
5520 for (i = 0; i < info->nr_clk_ids; ++i)
5521 ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
5522
5523 ctx->clk_data.num = info->nr_clk_ids;
5524 ctx->reg_base = reg_base;
5525 ctx->dev = dev;
5526 spin_lock_init(&ctx->lock);
5527
5528 data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
5529 info->nr_clk_regs);
5530 data->nr_clk_save = info->nr_clk_regs;
5531 data->clk_suspend = info->suspend_regs;
5532 data->nr_clk_suspend = info->nr_suspend_regs;
5533 data->nr_pclks = of_count_phandle_with_args(dev->of_node, "clocks",
5534 "#clock-cells");
5535 if (data->nr_pclks > 0) {
5536 data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
5537 data->nr_pclks, GFP_KERNEL);
5538
5539 for (i = 0; i < data->nr_pclks; i++) {
5540 struct clk *clk = of_clk_get(dev->of_node, i);
5541
5542 if (IS_ERR(clk))
5543 return PTR_ERR(clk);
5544 data->pclks[i] = clk;
5545 }
5546 }
5547
5548 if (info->clk_name)
5549 data->clk = clk_get(dev, info->clk_name);
5550 clk_prepare_enable(data->clk);
5551
5552 platform_set_drvdata(pdev, data);
5553
5554 /*
5555 * Enable runtime PM here to allow the clock core using runtime PM
5556 * for the registered clocks. Additionally, we increase the runtime
5557 * PM usage count before registering the clocks, to prevent the
5558 * clock core from runtime suspending the device.
5559 */
5560 pm_runtime_get_noresume(dev);
5561 pm_runtime_set_active(dev);
5562 pm_runtime_enable(dev);
5563
5564 if (info->pll_clks)
5565 samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,
5566 reg_base);
5567 if (info->mux_clks)
5568 samsung_clk_register_mux(ctx, info->mux_clks,
5569 info->nr_mux_clks);
5570 if (info->div_clks)
5571 samsung_clk_register_div(ctx, info->div_clks,
5572 info->nr_div_clks);
5573 if (info->gate_clks)
5574 samsung_clk_register_gate(ctx, info->gate_clks,
5575 info->nr_gate_clks);
5576 if (info->fixed_clks)
5577 samsung_clk_register_fixed_rate(ctx, info->fixed_clks,
5578 info->nr_fixed_clks);
5579 if (info->fixed_factor_clks)
5580 samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks,
5581 info->nr_fixed_factor_clks);
5582
5583 samsung_clk_of_add_provider(dev->of_node, ctx);
5584 pm_runtime_put_sync(dev);
5585
5586 return 0;
5587 }
5588
5589 static const struct of_device_id exynos5433_cmu_of_match[] = {
5590 {
5591 .compatible = "samsung,exynos5433-cmu-aud",
5592 .data = &aud_cmu_info,
5593 }, {
5594 .compatible = "samsung,exynos5433-cmu-cam0",
5595 .data = &cam0_cmu_info,
5596 }, {
5597 .compatible = "samsung,exynos5433-cmu-cam1",
5598 .data = &cam1_cmu_info,
5599 }, {
5600 .compatible = "samsung,exynos5433-cmu-disp",
5601 .data = &disp_cmu_info,
5602 }, {
5603 .compatible = "samsung,exynos5433-cmu-g2d",
5604 .data = &g2d_cmu_info,
5605 }, {
5606 .compatible = "samsung,exynos5433-cmu-g3d",
5607 .data = &g3d_cmu_info,
5608 }, {
5609 .compatible = "samsung,exynos5433-cmu-fsys",
5610 .data = &fsys_cmu_info,
5611 }, {
5612 .compatible = "samsung,exynos5433-cmu-gscl",
5613 .data = &gscl_cmu_info,
5614 }, {
5615 .compatible = "samsung,exynos5433-cmu-mfc",
5616 .data = &mfc_cmu_info,
5617 }, {
5618 .compatible = "samsung,exynos5433-cmu-hevc",
5619 .data = &hevc_cmu_info,
5620 }, {
5621 .compatible = "samsung,exynos5433-cmu-isp",
5622 .data = &isp_cmu_info,
5623 }, {
5624 .compatible = "samsung,exynos5433-cmu-mscl",
5625 .data = &mscl_cmu_info,
5626 }, {
5627 },
5628 };
5629
5630 static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
5631 SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
5632 NULL)
5633 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5634 pm_runtime_force_resume)
5635 };
5636
5637 static struct platform_driver exynos5433_cmu_driver __refdata = {
5638 .driver = {
5639 .name = "exynos5433-cmu",
5640 .of_match_table = exynos5433_cmu_of_match,
5641 .suppress_bind_attrs = true,
5642 .pm = &exynos5433_cmu_pm_ops,
5643 },
5644 .probe = exynos5433_cmu_probe,
5645 };
5646
5647 static int __init exynos5433_cmu_init(void)
5648 {
5649 return platform_driver_register(&exynos5433_cmu_driver);
5650 }
5651 core_initcall(exynos5433_cmu_init);
Linux with added FPC-III support