drivers/clk/samsung/clk-s3c2412.c

   1 /*
   2  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Common Clock Framework support for S3C2412 and S3C2413.
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/syscore_ops.h>
  15 #include <linux/reboot.h>
  16
  17 #include <dt-bindings/clock/s3c2412.h>
  18
  19 #include "clk.h"
  20 #include "clk-pll.h"
  21
  22 #define LOCKTIME        0x00
  23 #define MPLLCON         0x04
  24 #define UPLLCON         0x08
  25 #define CLKCON          0x0c
  26 #define CLKDIVN         0x14
  27 #define CLKSRC          0x1c
  28 #define SWRST           0x30
  29
  30 static void __iomem *reg_base;
  31
  32 #ifdef CONFIG_PM_SLEEP
  33 static struct samsung_clk_reg_dump *s3c2412_save;
  34
  35 /*
  36  * list of controller registers to be saved and restored during a
  37  * suspend/resume cycle.
  38  */
  39 static unsigned long s3c2412_clk_regs[] __initdata = {
  40         LOCKTIME,
  41         MPLLCON,
  42         UPLLCON,
  43         CLKCON,
  44         CLKDIVN,
  45         CLKSRC,
  46 };
  47
  48 static int s3c2412_clk_suspend(void)
  49 {
  50         samsung_clk_save(reg_base, s3c2412_save,
  51                                 ARRAY_SIZE(s3c2412_clk_regs));
  52
  53         return 0;
  54 }
  55
  56 static void s3c2412_clk_resume(void)
  57 {
  58         samsung_clk_restore(reg_base, s3c2412_save,
  59                                 ARRAY_SIZE(s3c2412_clk_regs));
  60 }
  61
  62 static struct syscore_ops s3c2412_clk_syscore_ops = {
  63         .suspend = s3c2412_clk_suspend,
  64         .resume = s3c2412_clk_resume,
  65 };
  66
  67 static void __init s3c2412_clk_sleep_init(void)
  68 {
  69         s3c2412_save = samsung_clk_alloc_reg_dump(s3c2412_clk_regs,
  70                                                 ARRAY_SIZE(s3c2412_clk_regs));
  71         if (!s3c2412_save) {
  72                 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
  73                         __func__);
  74                 return;
  75         }
  76
  77         register_syscore_ops(&s3c2412_clk_syscore_ops);
  78         return;
  79 }
  80 #else
  81 static void __init s3c2412_clk_sleep_init(void) {}
  82 #endif
  83
  84 static struct clk_div_table divxti_d[] = {
  85         { .val = 0, .div = 1 },
  86         { .val = 1, .div = 2 },
  87         { .val = 2, .div = 4 },
  88         { .val = 3, .div = 6 },
  89         { .val = 4, .div = 8 },
  90         { .val = 5, .div = 10 },
  91         { .val = 6, .div = 12 },
  92         { .val = 7, .div = 14 },
  93         { /* sentinel */ },
  94 };
  95
  96 static struct samsung_div_clock s3c2412_dividers[] __initdata = {
  97         DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d),
  98         DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4),
  99         DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4),
 100         DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4),
 101         DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1),
 102         DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1),
 103         DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1),
 104         DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
 105         DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
 106 };
 107
 108 static struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = {
 109         FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
 110 };
 111
 112 /*
 113  * The first two use the OM[4] setting, which is not readable from
 114  * software, so assume it is set to xti.
 115  */
 116 PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
 117 PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
 118
 119 PNAME(camclk_p) = { "usysclk", "hclk" };
 120 PNAME(usbclk_p) = { "usysclk", "hclk" };
 121 PNAME(i2sclk_p) = { "erefclk", "mpll" };
 122 PNAME(uartclk_p) = { "erefclk", "mpll" };
 123 PNAME(usysclk_p) = { "urefclk", "upll" };
 124 PNAME(msysclk_p) = { "mdivclk", "mpll" };
 125 PNAME(mdivclk_p) = { "xti", "div_xti" };
 126 PNAME(armclk_p) = { "armdiv", "hclk" };
 127
 128 static struct samsung_mux_clock s3c2412_muxes[] __initdata = {
 129         MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
 130         MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
 131         MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
 132         MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
 133         MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
 134         MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
 135         MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
 136         MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
 137         MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
 138         MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
 139 };
 140
 141 static struct samsung_pll_clock s3c2412_plls[] __initdata = {
 142         PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
 143         PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
 144 };
 145
 146 static struct samsung_gate_clock s3c2412_gates[] __initdata = {
 147         GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
 148         GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
 149         GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
 150         GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
 151         GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
 152         GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
 153         GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
 154         GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
 155         GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
 156         GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
 157         GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0),
 158         GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
 159         GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0),
 160         GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0),
 161         GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0),
 162         GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0),
 163         GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0),
 164         GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0),
 165         GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0),
 166         GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0),
 167         GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
 168         GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
 169         GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
 170         GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
 171         GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0),
 172         GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0),
 173         GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0),
 174         GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0),
 175 };
 176
 177 static struct samsung_clock_alias s3c2412_aliases[] __initdata = {
 178         ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
 179         ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
 180         ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"),
 181         ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
 182         ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
 183         ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"),
 184         ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
 185         ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
 186         ALIAS(PCLK_ADC, NULL, "adc"),
 187         ALIAS(PCLK_RTC, NULL, "rtc"),
 188         ALIAS(PCLK_PWM, NULL, "timers"),
 189         ALIAS(HCLK_LCD, NULL, "lcd"),
 190         ALIAS(PCLK_USBD, NULL, "usb-device"),
 191         ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"),
 192         ALIAS(HCLK_USBH, NULL, "usb-host"),
 193         ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
 194         ALIAS(ARMCLK, NULL, "armclk"),
 195         ALIAS(HCLK, NULL, "hclk"),
 196         ALIAS(MPLL, NULL, "mpll"),
 197         ALIAS(MSYSCLK, NULL, "fclk"),
 198 };
 199
 200 static int s3c2412_restart(struct notifier_block *this,
 201                            unsigned long mode, void *cmd)
 202 {
 203         /* errata "Watch-dog/Software Reset Problem" specifies that
 204          * this reset must be done with the SYSCLK sourced from
 205          * EXTCLK instead of FOUT to avoid a glitch in the reset
 206          * mechanism.
 207          *
 208          * See the watchdog section of the S3C2412 manual for more
 209          * information on this fix.
 210          */
 211
 212         __raw_writel(0x00, reg_base + CLKSRC);
 213         __raw_writel(0x533C2412, reg_base + SWRST);
 214         return NOTIFY_DONE;
 215 }
 216
 217 static struct notifier_block s3c2412_restart_handler = {
 218         .notifier_call = s3c2412_restart,
 219         .priority = 129,
 220 };
 221
 222 /*
 223  * fixed rate clocks generated outside the soc
 224  * Only necessary until the devicetree-move is complete
 225  */
 226 #define XTI     1
 227 static struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
 228         FRATE(XTI, "xti", NULL, 0, 0),
 229         FRATE(0, "ext", NULL, 0, 0),
 230 };
 231
 232 static void __init s3c2412_common_clk_register_fixed_ext(
 233                 struct samsung_clk_provider *ctx,
 234                 unsigned long xti_f, unsigned long ext_f)
 235 {
 236         /* xtal alias is necessary for the current cpufreq driver */
 237         struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
 238
 239         s3c2412_common_frate_clks[0].fixed_rate = xti_f;
 240         s3c2412_common_frate_clks[1].fixed_rate = ext_f;
 241         samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
 242                                 ARRAY_SIZE(s3c2412_common_frate_clks));
 243
 244         samsung_clk_register_alias(ctx, &xti_alias, 1);
 245 }
 246
 247 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
 248                                     unsigned long ext_f, void __iomem *base)
 249 {
 250         struct samsung_clk_provider *ctx;
 251         int ret;
 252         reg_base = base;
 253
 254         if (np) {
 255                 reg_base = of_iomap(np, 0);
 256                 if (!reg_base)
 257                         panic("%s: failed to map registers\n", __func__);
 258         }
 259
 260         ctx = samsung_clk_init(np, reg_base, NR_CLKS);
 261
 262         /* Register external clocks only in non-dt cases */
 263         if (!np)
 264                 s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
 265
 266         /* Register PLLs. */
 267         samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
 268                                  reg_base);
 269
 270         /* Register common internal clocks. */
 271         samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
 272         samsung_clk_register_div(ctx, s3c2412_dividers,
 273                                           ARRAY_SIZE(s3c2412_dividers));
 274         samsung_clk_register_gate(ctx, s3c2412_gates,
 275                                         ARRAY_SIZE(s3c2412_gates));
 276         samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
 277                                           ARRAY_SIZE(s3c2412_ffactor));
 278         samsung_clk_register_alias(ctx, s3c2412_aliases,
 279                                    ARRAY_SIZE(s3c2412_aliases));
 280
 281         s3c2412_clk_sleep_init();
 282
 283         samsung_clk_of_add_provider(np, ctx);
 284
 285         ret = register_restart_handler(&s3c2412_restart_handler);
 286         if (ret)
 287                 pr_warn("cannot register restart handler, %d\n", ret);
 288 }
 289
 290 static void __init s3c2412_clk_init(struct device_node *np)
 291 {
 292         s3c2412_common_clk_init(np, 0, 0, NULL);
 293 }
 294 CLK_OF_DECLARE(s3c2412_clk, "samsung,s3c2412-clock", s3c2412_clk_init);