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Linux 4.18.10
[linux/fpc-iii.git] / drivers / clk / sunxi-ng / ccu-sun6i-a31.c
blob3b97f60540ad8cd29aeb06a69620dcf940a15213
1 /*
2 * Copyright (c) 2016 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * Based on ccu-sun8i-h3.c by Maxime Ripard.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/clk-provider.h>
19 #include <linux/of_address.h>
20
21 #include "ccu_common.h"
22 #include "ccu_reset.h"
23
24 #include "ccu_div.h"
25 #include "ccu_gate.h"
26 #include "ccu_mp.h"
27 #include "ccu_mult.h"
28 #include "ccu_mux.h"
29 #include "ccu_nk.h"
30 #include "ccu_nkm.h"
31 #include "ccu_nkmp.h"
32 #include "ccu_nm.h"
33 #include "ccu_phase.h"
34 #include "ccu_sdm.h"
35
36 #include "ccu-sun6i-a31.h"
37
38 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
39 "osc24M", 0x000,
40 8, 5, /* N */
41 4, 2, /* K */
42 0, 2, /* M */
43 BIT(31), /* gate */
44 BIT(28), /* lock */
45 0);
46
47 /*
48 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
49 * the base (2x, 4x and 8x), and one variable divider (the one true
50 * pll audio).
51 *
52 * With sigma-delta modulation for fractional-N on the audio PLL,
53 * we have to use specific dividers. This means the variable divider
54 * can no longer be used, as the audio codec requests the exact clock
55 * rates we support through this mechanism. So we now hard code the
56 * variable divider to 1. This means the clock rates will no longer
57 * match the clock names.
58 */
59 #define SUN6I_A31_PLL_AUDIO_REG 0x008
60
61 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
62 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
63 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
64 };
65
66 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
67 "osc24M", 0x008,
68 8, 7, /* N */
69 0, 5, /* M */
70 pll_audio_sdm_table, BIT(24),
71 0x284, BIT(31),
72 BIT(31), /* gate */
73 BIT(28), /* lock */
74 CLK_SET_RATE_UNGATE);
75
76 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
77 "osc24M", 0x010,
78 8, 7, /* N */
79 0, 4, /* M */
80 BIT(24), /* frac enable */
81 BIT(25), /* frac select */
82 270000000, /* frac rate 0 */
83 297000000, /* frac rate 1 */
84 BIT(31), /* gate */
85 BIT(28), /* lock */
86 CLK_SET_RATE_UNGATE);
87
88 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
89 "osc24M", 0x018,
90 8, 7, /* N */
91 0, 4, /* M */
92 BIT(24), /* frac enable */
93 BIT(25), /* frac select */
94 270000000, /* frac rate 0 */
95 297000000, /* frac rate 1 */
96 BIT(31), /* gate */
97 BIT(28), /* lock */
98 CLK_SET_RATE_UNGATE);
99
100 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
101 "osc24M", 0x020,
102 8, 5, /* N */
103 4, 2, /* K */
104 0, 2, /* M */
105 BIT(31), /* gate */
106 BIT(28), /* lock */
107 CLK_SET_RATE_UNGATE);
108
109 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
110 "osc24M", 0x028,
111 8, 5, /* N */
112 4, 2, /* K */
113 BIT(31), /* gate */
114 BIT(28), /* lock */
115 2, /* post-div */
116 CLK_SET_RATE_UNGATE);
117
118 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
119 "osc24M", 0x030,
120 8, 7, /* N */
121 0, 4, /* M */
122 BIT(24), /* frac enable */
123 BIT(25), /* frac select */
124 270000000, /* frac rate 0 */
125 297000000, /* frac rate 1 */
126 BIT(31), /* gate */
127 BIT(28), /* lock */
128 CLK_SET_RATE_UNGATE);
129
130 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
131 "osc24M", 0x038,
132 8, 7, /* N */
133 0, 4, /* M */
134 BIT(24), /* frac enable */
135 BIT(25), /* frac select */
136 270000000, /* frac rate 0 */
137 297000000, /* frac rate 1 */
138 BIT(31), /* gate */
139 BIT(28), /* lock */
140 CLK_SET_RATE_UNGATE);
141
142 /*
143 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
144 *
145 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
146 * integer / fractional clock with switchable multipliers and dividers.
147 * This is not supported here. We hardcode the PLL to MIPI mode.
148 */
149 #define SUN6I_A31_PLL_MIPI_REG 0x040
150
151 static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
152 static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
153 pll_mipi_parents, 0x040,
154 8, 4, /* N */
155 4, 2, /* K */
156 0, 4, /* M */
157 21, 0, /* mux */
158 BIT(31) | BIT(23) | BIT(22), /* gate */
159 BIT(28), /* lock */
160 CLK_SET_RATE_UNGATE);
161
162 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9",
163 "osc24M", 0x044,
164 8, 7, /* N */
165 0, 4, /* M */
166 BIT(24), /* frac enable */
167 BIT(25), /* frac select */
168 270000000, /* frac rate 0 */
169 297000000, /* frac rate 1 */
170 BIT(31), /* gate */
171 BIT(28), /* lock */
172 CLK_SET_RATE_UNGATE);
173
174 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10",
175 "osc24M", 0x048,
176 8, 7, /* N */
177 0, 4, /* M */
178 BIT(24), /* frac enable */
179 BIT(25), /* frac select */
180 270000000, /* frac rate 0 */
181 297000000, /* frac rate 1 */
182 BIT(31), /* gate */
183 BIT(28), /* lock */
184 CLK_SET_RATE_UNGATE);
185
186 static const char * const cpux_parents[] = { "osc32k", "osc24M",
187 "pll-cpu", "pll-cpu" };
188 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents,
189 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
190
191 static struct clk_div_table axi_div_table[] = {
192 { .val = 0, .div = 1 },
193 { .val = 1, .div = 2 },
194 { .val = 2, .div = 3 },
195 { .val = 3, .div = 4 },
196 { .val = 4, .div = 4 },
197 { .val = 5, .div = 4 },
198 { .val = 6, .div = 4 },
199 { .val = 7, .div = 4 },
200 { /* Sentinel */ },
201 };
202
203 static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
204 0x050, 0, 3, axi_div_table, 0);
205
206 #define SUN6I_A31_AHB1_REG 0x054
207
208 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
209 "axi", "pll-periph" };
210 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
211 { .index = 3, .shift = 6, .width = 2 },
212 };
213
214 static struct ccu_div ahb1_clk = {
215 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
216
217 .mux = {
218 .shift = 12,
219 .width = 2,
220
221 .var_predivs = ahb1_predivs,
222 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
223 },
224
225 .common = {
226 .reg = 0x054,
227 .features = CCU_FEATURE_VARIABLE_PREDIV,
228 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
229 ahb1_parents,
230 &ccu_div_ops,
231 0),
232 },
233 };
234
235 static struct clk_div_table apb1_div_table[] = {
236 { .val = 0, .div = 2 },
237 { .val = 1, .div = 2 },
238 { .val = 2, .div = 4 },
239 { .val = 3, .div = 8 },
240 { /* Sentinel */ },
241 };
242
243 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
244 0x054, 8, 2, apb1_div_table, 0);
245
246 static const char * const apb2_parents[] = { "osc32k", "osc24M",
247 "pll-periph", "pll-periph" };
248 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
249 0, 5, /* M */
250 16, 2, /* P */
251 24, 2, /* mux */
252 0);
253
254 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
255 0x060, BIT(1), 0);
256 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
257 0x060, BIT(5), 0);
258 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
259 0x060, BIT(6), 0);
260 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
261 0x060, BIT(8), 0);
262 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
263 0x060, BIT(9), 0);
264 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
265 0x060, BIT(10), 0);
266 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
267 0x060, BIT(12), 0);
268 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
269 0x060, BIT(13), 0);
270 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
271 0x060, BIT(13), 0);
272 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
273 0x060, BIT(14), 0);
274 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
275 0x060, BIT(17), 0);
276 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
277 0x060, BIT(18), 0);
278 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
279 0x060, BIT(19), 0);
280 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
281 0x060, BIT(20), 0);
282 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
283 0x060, BIT(21), 0);
284 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
285 0x060, BIT(22), 0);
286 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
287 0x060, BIT(23), 0);
288 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
289 0x060, BIT(24), 0);
290 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
291 0x060, BIT(26), 0);
292 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
293 0x060, BIT(27), 0);
294 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
295 0x060, BIT(29), 0);
296 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
297 0x060, BIT(30), 0);
298 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
299 0x060, BIT(31), 0);
300
301 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
302 0x064, BIT(0), 0);
303 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
304 0x064, BIT(4), 0);
305 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
306 0x064, BIT(5), 0);
307 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
308 0x064, BIT(8), 0);
309 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
310 0x064, BIT(11), 0);
311 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
312 0x064, BIT(12), 0);
313 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
314 0x064, BIT(13), 0);
315 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
316 0x064, BIT(14), 0);
317 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
318 0x064, BIT(15), 0);
319 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
320 0x064, BIT(18), 0);
321 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
322 0x064, BIT(20), 0);
323 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
324 0x064, BIT(23), 0);
325 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
326 0x064, BIT(24), 0);
327 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
328 0x064, BIT(25), 0);
329 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
330 0x064, BIT(26), 0);
331
332 static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
333 0x068, BIT(0), 0);
334 static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
335 0x068, BIT(1), 0);
336 static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
337 0x068, BIT(4), 0);
338 static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
339 0x068, BIT(5), 0);
340 static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
341 0x068, BIT(12), 0);
342 static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
343 0x068, BIT(13), 0);
344
345 static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
346 0x06c, BIT(0), 0);
347 static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
348 0x06c, BIT(1), 0);
349 static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
350 0x06c, BIT(2), 0);
351 static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
352 0x06c, BIT(3), 0);
353 static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
354 0x06c, BIT(16), 0);
355 static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
356 0x06c, BIT(17), 0);
357 static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
358 0x06c, BIT(18), 0);
359 static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
360 0x06c, BIT(19), 0);
361 static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
362 0x06c, BIT(20), 0);
363 static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
364 0x06c, BIT(21), 0);
365
366 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
367 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents,
368 0x080,
369 0, 4, /* M */
370 16, 2, /* P */
371 24, 2, /* mux */
372 BIT(31), /* gate */
373 0);
374
375 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents,
376 0x084,
377 0, 4, /* M */
378 16, 2, /* P */
379 24, 2, /* mux */
380 BIT(31), /* gate */
381 0);
382
383 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
384 0x088,
385 0, 4, /* M */
386 16, 2, /* P */
387 24, 2, /* mux */
388 BIT(31), /* gate */
389 0);
390
391 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
392 0x088, 20, 3, 0);
393 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
394 0x088, 8, 3, 0);
395
396 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
397 0x08c,
398 0, 4, /* M */
399 16, 2, /* P */
400 24, 2, /* mux */
401 BIT(31), /* gate */
402 0);
403
404 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
405 0x08c, 20, 3, 0);
406 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
407 0x08c, 8, 3, 0);
408
409 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
410 0x090,
411 0, 4, /* M */
412 16, 2, /* P */
413 24, 2, /* mux */
414 BIT(31), /* gate */
415 0);
416
417 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
418 0x090, 20, 3, 0);
419 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
420 0x090, 8, 3, 0);
421
422 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
423 0x094,
424 0, 4, /* M */
425 16, 2, /* P */
426 24, 2, /* mux */
427 BIT(31), /* gate */
428 0);
429
430 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
431 0x094, 20, 3, 0);
432 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
433 0x094, 8, 3, 0);
434
435 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
436 0, 4, /* M */
437 16, 2, /* P */
438 24, 2, /* mux */
439 BIT(31), /* gate */
440 0);
441
442 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
443 0, 4, /* M */
444 16, 2, /* P */
445 24, 2, /* mux */
446 BIT(31), /* gate */
447 0);
448
449 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
450 0, 4, /* M */
451 16, 2, /* P */
452 24, 2, /* mux */
453 BIT(31), /* gate */
454 0);
455
456 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
457 0, 4, /* M */
458 16, 2, /* P */
459 24, 2, /* mux */
460 BIT(31), /* gate */
461 0);
462 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
463 0, 4, /* M */
464 16, 2, /* P */
465 24, 2, /* mux */
466 BIT(31), /* gate */
467 0);
468
469 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
470 0, 4, /* M */
471 16, 2, /* P */
472 24, 2, /* mux */
473 BIT(31), /* gate */
474 0);
475
476 static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
477 "pll-audio-2x", "pll-audio" };
478 static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
479 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
480 static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
481 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
482
483 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents,
484 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
485
486 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
487 0x0cc, BIT(8), 0);
488 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
489 0x0cc, BIT(9), 0);
490 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
491 0x0cc, BIT(10), 0);
492 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
493 0x0cc, BIT(16), 0);
494 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
495 0x0cc, BIT(17), 0);
496 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
497 0x0cc, BIT(18), 0);
498
499 /* TODO emac clk not supported yet */
500
501 static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
502 static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0,
503 0, 4, /* M */
504 16, 2, /* P */
505 24, 2, /* mux */
506 BIT(31), /* gate */
507 CLK_IS_CRITICAL);
508
509 static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents,
510 0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL);
511 static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents,
512 0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL);
513
514 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
515 0x100, BIT(0), 0);
516 static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
517 0x100, BIT(1), 0);
518 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
519 0x100, BIT(3), 0);
520 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
521 0x100, BIT(16), 0);
522 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
523 0x100, BIT(17), 0);
524 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
525 0x100, BIT(18), 0);
526 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
527 0x100, BIT(19), 0);
528 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
529 0x100, BIT(24), 0);
530 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
531 0x100, BIT(25), 0);
532 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
533 0x100, BIT(26), 0);
534 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
535 0x100, BIT(27), 0);
536 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
537 0x100, BIT(28), 0);
538
539 static const char * const de_parents[] = { "pll-video0", "pll-video1",
540 "pll-periph-2x", "pll-gpu",
541 "pll9", "pll10" };
542 static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents,
543 0x104, 0, 4, 24, 3, BIT(31), 0);
544 static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents,
545 0x108, 0, 4, 24, 3, BIT(31), 0);
546 static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents,
547 0x10c, 0, 4, 24, 3, BIT(31), 0);
548 static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents,
549 0x110, 0, 4, 24, 3, BIT(31), 0);
550
551 static const char * const mp_parents[] = { "pll-video0", "pll-video1",
552 "pll9", "pll10" };
553 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
554 0x114, 0, 4, 24, 3, BIT(31), 0);
555
556 static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
557 "pll-video0-2x",
558 "pll-video1-2x", "pll-mipi" };
559 static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
560 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
561 static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
562 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
563
564 static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
565 "pll-video0-2x",
566 "pll-video1-2x" };
567 static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
568 0x12c, 0, 4, 24, 3, BIT(31),
569 CLK_SET_RATE_PARENT);
570 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
571 0x130, 0, 4, 24, 3, BIT(31),
572 CLK_SET_RATE_PARENT);
573
574 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
575 "pll9", "pll10", "pll-mipi",
576 "pll-ve" };
577 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
578 0x134, 16, 4, 24, 3, BIT(31), 0);
579
580 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
581 "osc24M" };
582 static const u8 csi_mclk_table[] = { 0, 1, 5 };
583 static struct ccu_div csi0_mclk_clk = {
584 .enable = BIT(15),
585 .div = _SUNXI_CCU_DIV(0, 4),
586 .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
587 .common = {
588 .reg = 0x134,
589 .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
590 csi_mclk_parents,
591 &ccu_div_ops,
592 0),
593 },
594 };
595
596 static struct ccu_div csi1_mclk_clk = {
597 .enable = BIT(15),
598 .div = _SUNXI_CCU_DIV(0, 4),
599 .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
600 .common = {
601 .reg = 0x138,
602 .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
603 csi_mclk_parents,
604 &ccu_div_ops,
605 0),
606 },
607 };
608
609 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
610 0x13c, 16, 3, BIT(31), 0);
611
612 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
613 0x140, BIT(31), CLK_SET_RATE_PARENT);
614 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
615 0x144, BIT(31), 0);
616 static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
617 0x148, BIT(31), CLK_SET_RATE_PARENT);
618
619 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
620 0x150, 0, 4, 24, 2, BIT(31),
621 CLK_SET_RATE_PARENT);
622
623 static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
624
625 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
626
627 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
628 "pll-ddr" };
629 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c,
630 0, 3, /* M */
631 16, 2, /* P */
632 24, 2, /* mux */
633 BIT(31), /* gate */
634 CLK_IS_CRITICAL);
635
636 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160,
637 0, 3, /* M */
638 16, 2, /* P */
639 24, 2, /* mux */
640 BIT(31), /* gate */
641 CLK_IS_CRITICAL);
642
643 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
644 0x168, 16, 3, 24, 2, BIT(31),
645 CLK_SET_RATE_PARENT);
646 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
647 lcd_ch1_parents, 0x168, 0, 3, 8, 2,
648 BIT(15), CLK_SET_RATE_PARENT);
649 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
650 lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
651 BIT(15), 0);
652
653 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
654 0x180, 0, 3, 24, 2, BIT(31), 0);
655 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
656 0x184, 0, 3, 24, 2, BIT(31), 0);
657 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
658 0x188, 0, 3, 24, 2, BIT(31), 0);
659 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
660 0x18c, 0, 3, 24, 2, BIT(31), 0);
661
662 static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
663 "pll-video0", "pll-video1",
664 "pll9", "pll10" };
665 static const struct ccu_mux_fixed_prediv gpu_predivs[] = {
666 { .index = 1, .div = 3, },
667 };
668
669 static struct ccu_div gpu_core_clk = {
670 .enable = BIT(31),
671 .div = _SUNXI_CCU_DIV(0, 3),
672 .mux = {
673 .shift = 24,
674 .width = 3,
675 .fixed_predivs = gpu_predivs,
676 .n_predivs = ARRAY_SIZE(gpu_predivs),
677 },
678 .common = {
679 .reg = 0x1a0,
680 .features = CCU_FEATURE_FIXED_PREDIV,
681 .hw.init = CLK_HW_INIT_PARENTS("gpu-core",
682 gpu_parents,
683 &ccu_div_ops,
684 0),
685 },
686 };
687
688 static struct ccu_div gpu_memory_clk = {
689 .enable = BIT(31),
690 .div = _SUNXI_CCU_DIV(0, 3),
691 .mux = {
692 .shift = 24,
693 .width = 3,
694 .fixed_predivs = gpu_predivs,
695 .n_predivs = ARRAY_SIZE(gpu_predivs),
696 },
697 .common = {
698 .reg = 0x1a4,
699 .features = CCU_FEATURE_FIXED_PREDIV,
700 .hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
701 gpu_parents,
702 &ccu_div_ops,
703 0),
704 },
705 };
706
707 static struct ccu_div gpu_hyd_clk = {
708 .enable = BIT(31),
709 .div = _SUNXI_CCU_DIV(0, 3),
710 .mux = {
711 .shift = 24,
712 .width = 3,
713 .fixed_predivs = gpu_predivs,
714 .n_predivs = ARRAY_SIZE(gpu_predivs),
715 },
716 .common = {
717 .reg = 0x1a8,
718 .features = CCU_FEATURE_FIXED_PREDIV,
719 .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
720 gpu_parents,
721 &ccu_div_ops,
722 0),
723 },
724 };
725
726 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0,
727 0, 3, /* M */
728 24, 2, /* mux */
729 BIT(31), /* gate */
730 0);
731
732 static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents,
733 0x1b0,
734 0, 3, /* M */
735 24, 2, /* mux */
736 BIT(31), /* gate */
737 0);
738
739 static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M",
740 "axi", "ahb1" };
741 static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
742
743 static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
744 { .index = 0, .div = 750, },
745 { .index = 3, .div = 4, },
746 { .index = 4, .div = 4, },
747 };
748
749 static struct ccu_mp out_a_clk = {
750 .enable = BIT(31),
751 .m = _SUNXI_CCU_DIV(8, 5),
752 .p = _SUNXI_CCU_DIV(20, 2),
753 .mux = {
754 .shift = 24,
755 .width = 4,
756 .table = clk_out_table,
757 .fixed_predivs = clk_out_predivs,
758 .n_predivs = ARRAY_SIZE(clk_out_predivs),
759 },
760 .common = {
761 .reg = 0x300,
762 .features = CCU_FEATURE_FIXED_PREDIV,
763 .hw.init = CLK_HW_INIT_PARENTS("out-a",
764 clk_out_parents,
765 &ccu_mp_ops,
766 0),
767 },
768 };
769
770 static struct ccu_mp out_b_clk = {
771 .enable = BIT(31),
772 .m = _SUNXI_CCU_DIV(8, 5),
773 .p = _SUNXI_CCU_DIV(20, 2),
774 .mux = {
775 .shift = 24,
776 .width = 4,
777 .table = clk_out_table,
778 .fixed_predivs = clk_out_predivs,
779 .n_predivs = ARRAY_SIZE(clk_out_predivs),
780 },
781 .common = {
782 .reg = 0x304,
783 .features = CCU_FEATURE_FIXED_PREDIV,
784 .hw.init = CLK_HW_INIT_PARENTS("out-b",
785 clk_out_parents,
786 &ccu_mp_ops,
787 0),
788 },
789 };
790
791 static struct ccu_mp out_c_clk = {
792 .enable = BIT(31),
793 .m = _SUNXI_CCU_DIV(8, 5),
794 .p = _SUNXI_CCU_DIV(20, 2),
795 .mux = {
796 .shift = 24,
797 .width = 4,
798 .table = clk_out_table,
799 .fixed_predivs = clk_out_predivs,
800 .n_predivs = ARRAY_SIZE(clk_out_predivs),
801 },
802 .common = {
803 .reg = 0x308,
804 .features = CCU_FEATURE_FIXED_PREDIV,
805 .hw.init = CLK_HW_INIT_PARENTS("out-c",
806 clk_out_parents,
807 &ccu_mp_ops,
808 0),
809 },
810 };
811
812 static struct ccu_common *sun6i_a31_ccu_clks[] = {
813 &pll_cpu_clk.common,
814 &pll_audio_base_clk.common,
815 &pll_video0_clk.common,
816 &pll_ve_clk.common,
817 &pll_ddr_clk.common,
818 &pll_periph_clk.common,
819 &pll_video1_clk.common,
820 &pll_gpu_clk.common,
821 &pll_mipi_clk.common,
822 &pll9_clk.common,
823 &pll10_clk.common,
824 &cpu_clk.common,
825 &axi_clk.common,
826 &ahb1_clk.common,
827 &apb1_clk.common,
828 &apb2_clk.common,
829 &ahb1_mipidsi_clk.common,
830 &ahb1_ss_clk.common,
831 &ahb1_dma_clk.common,
832 &ahb1_mmc0_clk.common,
833 &ahb1_mmc1_clk.common,
834 &ahb1_mmc2_clk.common,
835 &ahb1_mmc3_clk.common,
836 &ahb1_nand1_clk.common,
837 &ahb1_nand0_clk.common,
838 &ahb1_sdram_clk.common,
839 &ahb1_emac_clk.common,
840 &ahb1_ts_clk.common,
841 &ahb1_hstimer_clk.common,
842 &ahb1_spi0_clk.common,
843 &ahb1_spi1_clk.common,
844 &ahb1_spi2_clk.common,
845 &ahb1_spi3_clk.common,
846 &ahb1_otg_clk.common,
847 &ahb1_ehci0_clk.common,
848 &ahb1_ehci1_clk.common,
849 &ahb1_ohci0_clk.common,
850 &ahb1_ohci1_clk.common,
851 &ahb1_ohci2_clk.common,
852 &ahb1_ve_clk.common,
853 &ahb1_lcd0_clk.common,
854 &ahb1_lcd1_clk.common,
855 &ahb1_csi_clk.common,
856 &ahb1_hdmi_clk.common,
857 &ahb1_be0_clk.common,
858 &ahb1_be1_clk.common,
859 &ahb1_fe0_clk.common,
860 &ahb1_fe1_clk.common,
861 &ahb1_mp_clk.common,
862 &ahb1_gpu_clk.common,
863 &ahb1_deu0_clk.common,
864 &ahb1_deu1_clk.common,
865 &ahb1_drc0_clk.common,
866 &ahb1_drc1_clk.common,
867 &apb1_codec_clk.common,
868 &apb1_spdif_clk.common,
869 &apb1_digital_mic_clk.common,
870 &apb1_pio_clk.common,
871 &apb1_daudio0_clk.common,
872 &apb1_daudio1_clk.common,
873 &apb2_i2c0_clk.common,
874 &apb2_i2c1_clk.common,
875 &apb2_i2c2_clk.common,
876 &apb2_i2c3_clk.common,
877 &apb2_uart0_clk.common,
878 &apb2_uart1_clk.common,
879 &apb2_uart2_clk.common,
880 &apb2_uart3_clk.common,
881 &apb2_uart4_clk.common,
882 &apb2_uart5_clk.common,
883 &nand0_clk.common,
884 &nand1_clk.common,
885 &mmc0_clk.common,
886 &mmc0_sample_clk.common,
887 &mmc0_output_clk.common,
888 &mmc1_clk.common,
889 &mmc1_sample_clk.common,
890 &mmc1_output_clk.common,
891 &mmc2_clk.common,
892 &mmc2_sample_clk.common,
893 &mmc2_output_clk.common,
894 &mmc3_clk.common,
895 &mmc3_sample_clk.common,
896 &mmc3_output_clk.common,
897 &ts_clk.common,
898 &ss_clk.common,
899 &spi0_clk.common,
900 &spi1_clk.common,
901 &spi2_clk.common,
902 &spi3_clk.common,
903 &daudio0_clk.common,
904 &daudio1_clk.common,
905 &spdif_clk.common,
906 &usb_phy0_clk.common,
907 &usb_phy1_clk.common,
908 &usb_phy2_clk.common,
909 &usb_ohci0_clk.common,
910 &usb_ohci1_clk.common,
911 &usb_ohci2_clk.common,
912 &mdfs_clk.common,
913 &sdram0_clk.common,
914 &sdram1_clk.common,
915 &dram_ve_clk.common,
916 &dram_csi_isp_clk.common,
917 &dram_ts_clk.common,
918 &dram_drc0_clk.common,
919 &dram_drc1_clk.common,
920 &dram_deu0_clk.common,
921 &dram_deu1_clk.common,
922 &dram_fe0_clk.common,
923 &dram_fe1_clk.common,
924 &dram_be0_clk.common,
925 &dram_be1_clk.common,
926 &dram_mp_clk.common,
927 &be0_clk.common,
928 &be1_clk.common,
929 &fe0_clk.common,
930 &fe1_clk.common,
931 &mp_clk.common,
932 &lcd0_ch0_clk.common,
933 &lcd1_ch0_clk.common,
934 &lcd0_ch1_clk.common,
935 &lcd1_ch1_clk.common,
936 &csi0_sclk_clk.common,
937 &csi0_mclk_clk.common,
938 &csi1_mclk_clk.common,
939 &ve_clk.common,
940 &codec_clk.common,
941 &avs_clk.common,
942 &digital_mic_clk.common,
943 &hdmi_clk.common,
944 &hdmi_ddc_clk.common,
945 &ps_clk.common,
946 &mbus0_clk.common,
947 &mbus1_clk.common,
948 &mipi_dsi_clk.common,
949 &mipi_dsi_dphy_clk.common,
950 &mipi_csi_dphy_clk.common,
951 &iep_drc0_clk.common,
952 &iep_drc1_clk.common,
953 &iep_deu0_clk.common,
954 &iep_deu1_clk.common,
955 &gpu_core_clk.common,
956 &gpu_memory_clk.common,
957 &gpu_hyd_clk.common,
958 &ats_clk.common,
959 &trace_clk.common,
960 &out_a_clk.common,
961 &out_b_clk.common,
962 &out_c_clk.common,
963 };
964
965 /* We hardcode the divider to 1 for now */
966 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
967 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
968 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
969 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
970 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
971 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
972 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
973 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
974 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
975 "pll-periph", 1, 2, 0);
976 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
977 "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
978 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
979 "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
980
981 static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
982 .hws = {
983 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
984 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
985 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
986 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
987 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
988 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
989 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
990 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
991 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
992 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
993 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
994 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
995 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
996 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
997 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
998 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
999 [CLK_PLL9] = &pll9_clk.common.hw,
1000 [CLK_PLL10] = &pll10_clk.common.hw,
1001 [CLK_CPU] = &cpu_clk.common.hw,
1002 [CLK_AXI] = &axi_clk.common.hw,
1003 [CLK_AHB1] = &ahb1_clk.common.hw,
1004 [CLK_APB1] = &apb1_clk.common.hw,
1005 [CLK_APB2] = &apb2_clk.common.hw,
1006 [CLK_AHB1_MIPIDSI] = &ahb1_mipidsi_clk.common.hw,
1007 [CLK_AHB1_SS] = &ahb1_ss_clk.common.hw,
1008 [CLK_AHB1_DMA] = &ahb1_dma_clk.common.hw,
1009 [CLK_AHB1_MMC0] = &ahb1_mmc0_clk.common.hw,
1010 [CLK_AHB1_MMC1] = &ahb1_mmc1_clk.common.hw,
1011 [CLK_AHB1_MMC2] = &ahb1_mmc2_clk.common.hw,
1012 [CLK_AHB1_MMC3] = &ahb1_mmc3_clk.common.hw,
1013 [CLK_AHB1_NAND1] = &ahb1_nand1_clk.common.hw,
1014 [CLK_AHB1_NAND0] = &ahb1_nand0_clk.common.hw,
1015 [CLK_AHB1_SDRAM] = &ahb1_sdram_clk.common.hw,
1016 [CLK_AHB1_EMAC] = &ahb1_emac_clk.common.hw,
1017 [CLK_AHB1_TS] = &ahb1_ts_clk.common.hw,
1018 [CLK_AHB1_HSTIMER] = &ahb1_hstimer_clk.common.hw,
1019 [CLK_AHB1_SPI0] = &ahb1_spi0_clk.common.hw,
1020 [CLK_AHB1_SPI1] = &ahb1_spi1_clk.common.hw,
1021 [CLK_AHB1_SPI2] = &ahb1_spi2_clk.common.hw,
1022 [CLK_AHB1_SPI3] = &ahb1_spi3_clk.common.hw,
1023 [CLK_AHB1_OTG] = &ahb1_otg_clk.common.hw,
1024 [CLK_AHB1_EHCI0] = &ahb1_ehci0_clk.common.hw,
1025 [CLK_AHB1_EHCI1] = &ahb1_ehci1_clk.common.hw,
1026 [CLK_AHB1_OHCI0] = &ahb1_ohci0_clk.common.hw,
1027 [CLK_AHB1_OHCI1] = &ahb1_ohci1_clk.common.hw,
1028 [CLK_AHB1_OHCI2] = &ahb1_ohci2_clk.common.hw,
1029 [CLK_AHB1_VE] = &ahb1_ve_clk.common.hw,
1030 [CLK_AHB1_LCD0] = &ahb1_lcd0_clk.common.hw,
1031 [CLK_AHB1_LCD1] = &ahb1_lcd1_clk.common.hw,
1032 [CLK_AHB1_CSI] = &ahb1_csi_clk.common.hw,
1033 [CLK_AHB1_HDMI] = &ahb1_hdmi_clk.common.hw,
1034 [CLK_AHB1_BE0] = &ahb1_be0_clk.common.hw,
1035 [CLK_AHB1_BE1] = &ahb1_be1_clk.common.hw,
1036 [CLK_AHB1_FE0] = &ahb1_fe0_clk.common.hw,
1037 [CLK_AHB1_FE1] = &ahb1_fe1_clk.common.hw,
1038 [CLK_AHB1_MP] = &ahb1_mp_clk.common.hw,
1039 [CLK_AHB1_GPU] = &ahb1_gpu_clk.common.hw,
1040 [CLK_AHB1_DEU0] = &ahb1_deu0_clk.common.hw,
1041 [CLK_AHB1_DEU1] = &ahb1_deu1_clk.common.hw,
1042 [CLK_AHB1_DRC0] = &ahb1_drc0_clk.common.hw,
1043 [CLK_AHB1_DRC1] = &ahb1_drc1_clk.common.hw,
1044 [CLK_APB1_CODEC] = &apb1_codec_clk.common.hw,
1045 [CLK_APB1_SPDIF] = &apb1_spdif_clk.common.hw,
1046 [CLK_APB1_DIGITAL_MIC] = &apb1_digital_mic_clk.common.hw,
1047 [CLK_APB1_PIO] = &apb1_pio_clk.common.hw,
1048 [CLK_APB1_DAUDIO0] = &apb1_daudio0_clk.common.hw,
1049 [CLK_APB1_DAUDIO1] = &apb1_daudio1_clk.common.hw,
1050 [CLK_APB2_I2C0] = &apb2_i2c0_clk.common.hw,
1051 [CLK_APB2_I2C1] = &apb2_i2c1_clk.common.hw,
1052 [CLK_APB2_I2C2] = &apb2_i2c2_clk.common.hw,
1053 [CLK_APB2_I2C3] = &apb2_i2c3_clk.common.hw,
1054 [CLK_APB2_UART0] = &apb2_uart0_clk.common.hw,
1055 [CLK_APB2_UART1] = &apb2_uart1_clk.common.hw,
1056 [CLK_APB2_UART2] = &apb2_uart2_clk.common.hw,
1057 [CLK_APB2_UART3] = &apb2_uart3_clk.common.hw,
1058 [CLK_APB2_UART4] = &apb2_uart4_clk.common.hw,
1059 [CLK_APB2_UART5] = &apb2_uart5_clk.common.hw,
1060 [CLK_NAND0] = &nand0_clk.common.hw,
1061 [CLK_NAND1] = &nand1_clk.common.hw,
1062 [CLK_MMC0] = &mmc0_clk.common.hw,
1063 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
1064 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
1065 [CLK_MMC1] = &mmc1_clk.common.hw,
1066 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
1067 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
1068 [CLK_MMC2] = &mmc2_clk.common.hw,
1069 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
1070 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
1071 [CLK_MMC3] = &mmc3_clk.common.hw,
1072 [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
1073 [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
1074 [CLK_TS] = &ts_clk.common.hw,
1075 [CLK_SS] = &ss_clk.common.hw,
1076 [CLK_SPI0] = &spi0_clk.common.hw,
1077 [CLK_SPI1] = &spi1_clk.common.hw,
1078 [CLK_SPI2] = &spi2_clk.common.hw,
1079 [CLK_SPI3] = &spi3_clk.common.hw,
1080 [CLK_DAUDIO0] = &daudio0_clk.common.hw,
1081 [CLK_DAUDIO1] = &daudio1_clk.common.hw,
1082 [CLK_SPDIF] = &spdif_clk.common.hw,
1083 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
1084 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
1085 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
1086 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1087 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1088 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
1089 [CLK_MDFS] = &mdfs_clk.common.hw,
1090 [CLK_SDRAM0] = &sdram0_clk.common.hw,
1091 [CLK_SDRAM1] = &sdram1_clk.common.hw,
1092 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1093 [CLK_DRAM_CSI_ISP] = &dram_csi_isp_clk.common.hw,
1094 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1095 [CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw,
1096 [CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw,
1097 [CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw,
1098 [CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw,
1099 [CLK_DRAM_FE0] = &dram_fe0_clk.common.hw,
1100 [CLK_DRAM_FE1] = &dram_fe1_clk.common.hw,
1101 [CLK_DRAM_BE0] = &dram_be0_clk.common.hw,
1102 [CLK_DRAM_BE1] = &dram_be1_clk.common.hw,
1103 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1104 [CLK_BE0] = &be0_clk.common.hw,
1105 [CLK_BE1] = &be1_clk.common.hw,
1106 [CLK_FE0] = &fe0_clk.common.hw,
1107 [CLK_FE1] = &fe1_clk.common.hw,
1108 [CLK_MP] = &mp_clk.common.hw,
1109 [CLK_LCD0_CH0] = &lcd0_ch0_clk.common.hw,
1110 [CLK_LCD1_CH0] = &lcd1_ch0_clk.common.hw,
1111 [CLK_LCD0_CH1] = &lcd0_ch1_clk.common.hw,
1112 [CLK_LCD1_CH1] = &lcd1_ch1_clk.common.hw,
1113 [CLK_CSI0_SCLK] = &csi0_sclk_clk.common.hw,
1114 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
1115 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
1116 [CLK_VE] = &ve_clk.common.hw,
1117 [CLK_CODEC] = &codec_clk.common.hw,
1118 [CLK_AVS] = &avs_clk.common.hw,
1119 [CLK_DIGITAL_MIC] = &digital_mic_clk.common.hw,
1120 [CLK_HDMI] = &hdmi_clk.common.hw,
1121 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
1122 [CLK_PS] = &ps_clk.common.hw,
1123 [CLK_MBUS0] = &mbus0_clk.common.hw,
1124 [CLK_MBUS1] = &mbus1_clk.common.hw,
1125 [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
1126 [CLK_MIPI_DSI_DPHY] = &mipi_dsi_dphy_clk.common.hw,
1127 [CLK_MIPI_CSI_DPHY] = &mipi_csi_dphy_clk.common.hw,
1128 [CLK_IEP_DRC0] = &iep_drc0_clk.common.hw,
1129 [CLK_IEP_DRC1] = &iep_drc1_clk.common.hw,
1130 [CLK_IEP_DEU0] = &iep_deu0_clk.common.hw,
1131 [CLK_IEP_DEU1] = &iep_deu1_clk.common.hw,
1132 [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
1133 [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
1134 [CLK_GPU_HYD] = &gpu_hyd_clk.common.hw,
1135 [CLK_ATS] = &ats_clk.common.hw,
1136 [CLK_TRACE] = &trace_clk.common.hw,
1137 [CLK_OUT_A] = &out_a_clk.common.hw,
1138 [CLK_OUT_B] = &out_b_clk.common.hw,
1139 [CLK_OUT_C] = &out_c_clk.common.hw,
1140 },
1141 .num = CLK_NUMBER,
1142 };
1143
1144 static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
1145 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1146 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1147 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1148
1149 [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) },
1150 [RST_AHB1_SS] = { 0x2c0, BIT(5) },
1151 [RST_AHB1_DMA] = { 0x2c0, BIT(6) },
1152 [RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
1153 [RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
1154 [RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
1155 [RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
1156 [RST_AHB1_NAND1] = { 0x2c0, BIT(12) },
1157 [RST_AHB1_NAND0] = { 0x2c0, BIT(13) },
1158 [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) },
1159 [RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
1160 [RST_AHB1_TS] = { 0x2c0, BIT(18) },
1161 [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) },
1162 [RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
1163 [RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
1164 [RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
1165 [RST_AHB1_SPI3] = { 0x2c0, BIT(23) },
1166 [RST_AHB1_OTG] = { 0x2c0, BIT(24) },
1167 [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
1168 [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
1169 [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) },
1170 [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) },
1171 [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) },
1172
1173 [RST_AHB1_VE] = { 0x2c4, BIT(0) },
1174 [RST_AHB1_LCD0] = { 0x2c4, BIT(4) },
1175 [RST_AHB1_LCD1] = { 0x2c4, BIT(5) },
1176 [RST_AHB1_CSI] = { 0x2c4, BIT(8) },
1177 [RST_AHB1_HDMI] = { 0x2c4, BIT(11) },
1178 [RST_AHB1_BE0] = { 0x2c4, BIT(12) },
1179 [RST_AHB1_BE1] = { 0x2c4, BIT(13) },
1180 [RST_AHB1_FE0] = { 0x2c4, BIT(14) },
1181 [RST_AHB1_FE1] = { 0x2c4, BIT(15) },
1182 [RST_AHB1_MP] = { 0x2c4, BIT(18) },
1183 [RST_AHB1_GPU] = { 0x2c4, BIT(20) },
1184 [RST_AHB1_DEU0] = { 0x2c4, BIT(23) },
1185 [RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
1186 [RST_AHB1_DRC0] = { 0x2c4, BIT(25) },
1187 [RST_AHB1_DRC1] = { 0x2c4, BIT(26) },
1188 [RST_AHB1_LVDS] = { 0x2c8, BIT(0) },
1189
1190 [RST_APB1_CODEC] = { 0x2d0, BIT(0) },
1191 [RST_APB1_SPDIF] = { 0x2d0, BIT(1) },
1192 [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) },
1193 [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) },
1194 [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) },
1195
1196 [RST_APB2_I2C0] = { 0x2d8, BIT(0) },
1197 [RST_APB2_I2C1] = { 0x2d8, BIT(1) },
1198 [RST_APB2_I2C2] = { 0x2d8, BIT(2) },
1199 [RST_APB2_I2C3] = { 0x2d8, BIT(3) },
1200 [RST_APB2_UART0] = { 0x2d8, BIT(16) },
1201 [RST_APB2_UART1] = { 0x2d8, BIT(17) },
1202 [RST_APB2_UART2] = { 0x2d8, BIT(18) },
1203 [RST_APB2_UART3] = { 0x2d8, BIT(19) },
1204 [RST_APB2_UART4] = { 0x2d8, BIT(20) },
1205 [RST_APB2_UART5] = { 0x2d8, BIT(21) },
1206 };
1207
1208 static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = {
1209 .ccu_clks = sun6i_a31_ccu_clks,
1210 .num_ccu_clks = ARRAY_SIZE(sun6i_a31_ccu_clks),
1211
1212 .hw_clks = &sun6i_a31_hw_clks,
1213
1214 .resets = sun6i_a31_ccu_resets,
1215 .num_resets = ARRAY_SIZE(sun6i_a31_ccu_resets),
1216 };
1217
1218 static struct ccu_mux_nb sun6i_a31_cpu_nb = {
1219 .common = &cpu_clk.common,
1220 .cm = &cpu_clk.mux,
1221 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1222 .bypass_index = 1, /* index of 24 MHz oscillator */
1223 };
1224
1225 static void __init sun6i_a31_ccu_setup(struct device_node *node)
1226 {
1227 void __iomem *reg;
1228 u32 val;
1229
1230 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1231 if (IS_ERR(reg)) {
1232 pr_err("%pOF: Could not map the clock registers\n", node);
1233 return;
1234 }
1235
1236 /* Force the PLL-Audio-1x divider to 1 */
1237 val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
1238 val &= ~GENMASK(19, 16);
1239 writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
1240
1241 /* Force PLL-MIPI to MIPI mode */
1242 val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
1243 val &= BIT(16);
1244 writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
1245
1246 /* Force AHB1 to PLL6 / 3 */
1247 val = readl(reg + SUN6I_A31_AHB1_REG);
1248 /* set PLL6 pre-div = 3 */
1249 val &= ~GENMASK(7, 6);
1250 val |= 0x2 << 6;
1251 /* select PLL6 / pre-div */
1252 val &= ~GENMASK(13, 12);
1253 val |= 0x3 << 12;
1254 writel(val, reg + SUN6I_A31_AHB1_REG);
1255
1256 sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
1257
1258 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1259 &sun6i_a31_cpu_nb);
1260 }
1261 CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",
1262 sun6i_a31_ccu_setup);
Linux with added FPC-III support