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Linux 4.18.10
[linux/fpc-iii.git] / drivers / clk / sunxi-ng / ccu-sun8i-r40.c
blob65ba6455feb790ee4ef944dc1f36c49c5b4a26f2
1 /*
2 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk-provider.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17
18 #include "ccu_common.h"
19 #include "ccu_reset.h"
20
21 #include "ccu_div.h"
22 #include "ccu_gate.h"
23 #include "ccu_mp.h"
24 #include "ccu_mult.h"
25 #include "ccu_nk.h"
26 #include "ccu_nkm.h"
27 #include "ccu_nkmp.h"
28 #include "ccu_nm.h"
29 #include "ccu_phase.h"
30
31 #include "ccu-sun8i-r40.h"
32
33 /* TODO: The result of N*K is required to be in [10, 88] range. */
34 static struct ccu_nkmp pll_cpu_clk = {
35 .enable = BIT(31),
36 .lock = BIT(28),
37 .n = _SUNXI_CCU_MULT(8, 5),
38 .k = _SUNXI_CCU_MULT(4, 2),
39 .m = _SUNXI_CCU_DIV(0, 2),
40 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
41 .common = {
42 .reg = 0x000,
43 .hw.init = CLK_HW_INIT("pll-cpu",
44 "osc24M",
45 &ccu_nkmp_ops,
46 CLK_SET_RATE_UNGATE),
47 },
48 };
49
50 /*
51 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
52 * the base (2x, 4x and 8x), and one variable divider (the one true
53 * pll audio).
54 *
55 * We don't have any need for the variable divider for now, so we just
56 * hardcode it to match with the clock names
57 */
58 #define SUN8I_R40_PLL_AUDIO_REG 0x008
59
60 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
61 "osc24M", 0x008,
62 8, 7, /* N */
63 0, 5, /* M */
64 BIT(31), /* gate */
65 BIT(28), /* lock */
66 CLK_SET_RATE_UNGATE);
67
68 /* TODO: The result of N/M is required to be in [8, 25] range. */
69 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
70 "osc24M", 0x0010,
71 8, 7, /* N */
72 0, 4, /* M */
73 BIT(24), /* frac enable */
74 BIT(25), /* frac select */
75 270000000, /* frac rate 0 */
76 297000000, /* frac rate 1 */
77 BIT(31), /* gate */
78 BIT(28), /* lock */
79 CLK_SET_RATE_UNGATE);
80
81 /* TODO: The result of N/M is required to be in [8, 25] range. */
82 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
83 "osc24M", 0x0018,
84 8, 7, /* N */
85 0, 4, /* M */
86 BIT(24), /* frac enable */
87 BIT(25), /* frac select */
88 270000000, /* frac rate 0 */
89 297000000, /* frac rate 1 */
90 BIT(31), /* gate */
91 BIT(28), /* lock */
92 CLK_SET_RATE_UNGATE);
93
94 /* TODO: The result of N*K is required to be in [10, 77] range. */
95 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
96 "osc24M", 0x020,
97 8, 5, /* N */
98 4, 2, /* K */
99 0, 2, /* M */
100 BIT(31), /* gate */
101 BIT(28), /* lock */
102 CLK_SET_RATE_UNGATE);
103
104 /* TODO: The result of N*K is required to be in [21, 58] range. */
105 static struct ccu_nk pll_periph0_clk = {
106 .enable = BIT(31),
107 .lock = BIT(28),
108 .n = _SUNXI_CCU_MULT(8, 5),
109 .k = _SUNXI_CCU_MULT(4, 2),
110 .fixed_post_div = 2,
111 .common = {
112 .reg = 0x028,
113 .features = CCU_FEATURE_FIXED_POSTDIV,
114 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
115 &ccu_nk_ops,
116 CLK_SET_RATE_UNGATE),
117 },
118 };
119
120 static struct ccu_div pll_periph0_sata_clk = {
121 .enable = BIT(24),
122 .div = _SUNXI_CCU_DIV(0, 2),
123 /*
124 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
125 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
126 * 6/2 = 3.
127 */
128 .fixed_post_div = 3,
129 .common = {
130 .reg = 0x028,
131 .features = CCU_FEATURE_FIXED_POSTDIV,
132 .hw.init = CLK_HW_INIT("pll-periph0-sata",
133 "pll-periph0",
134 &ccu_div_ops, 0),
135 },
136 };
137
138 /* TODO: The result of N*K is required to be in [21, 58] range. */
139 static struct ccu_nk pll_periph1_clk = {
140 .enable = BIT(31),
141 .lock = BIT(28),
142 .n = _SUNXI_CCU_MULT(8, 5),
143 .k = _SUNXI_CCU_MULT(4, 2),
144 .fixed_post_div = 2,
145 .common = {
146 .reg = 0x02c,
147 .features = CCU_FEATURE_FIXED_POSTDIV,
148 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
149 &ccu_nk_ops,
150 CLK_SET_RATE_UNGATE),
151 },
152 };
153
154 /* TODO: The result of N/M is required to be in [8, 25] range. */
155 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
156 "osc24M", 0x030,
157 8, 7, /* N */
158 0, 4, /* M */
159 BIT(24), /* frac enable */
160 BIT(25), /* frac select */
161 270000000, /* frac rate 0 */
162 297000000, /* frac rate 1 */
163 BIT(31), /* gate */
164 BIT(28), /* lock */
165 CLK_SET_RATE_UNGATE);
166
167 static struct ccu_nkm pll_sata_clk = {
168 .enable = BIT(31),
169 .lock = BIT(28),
170 .n = _SUNXI_CCU_MULT(8, 5),
171 .k = _SUNXI_CCU_MULT(4, 2),
172 .m = _SUNXI_CCU_DIV(0, 2),
173 .fixed_post_div = 6,
174 .common = {
175 .reg = 0x034,
176 .features = CCU_FEATURE_FIXED_POSTDIV,
177 .hw.init = CLK_HW_INIT("pll-sata", "osc24M",
178 &ccu_nkm_ops,
179 CLK_SET_RATE_UNGATE),
180 },
181 };
182
183 static const char * const pll_sata_out_parents[] = { "pll-sata",
184 "pll-periph0-sata" };
185 static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
186 pll_sata_out_parents, 0x034,
187 30, 1, /* mux */
188 BIT(14), /* gate */
189 CLK_SET_RATE_PARENT);
190
191 /* TODO: The result of N/M is required to be in [8, 25] range. */
192 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
193 "osc24M", 0x038,
194 8, 7, /* N */
195 0, 4, /* M */
196 BIT(24), /* frac enable */
197 BIT(25), /* frac select */
198 270000000, /* frac rate 0 */
199 297000000, /* frac rate 1 */
200 BIT(31), /* gate */
201 BIT(28), /* lock */
202 CLK_SET_RATE_UNGATE);
203
204 /*
205 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
206 *
207 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
208 * integer / fractional clock with switchable multipliers and dividers.
209 * This is not supported here. We hardcode the PLL to MIPI mode.
210 *
211 * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
212 * which cannot be implemented now.
213 */
214 #define SUN8I_R40_PLL_MIPI_REG 0x040
215
216 static const char * const pll_mipi_parents[] = { "pll-video0" };
217 static struct ccu_nkm pll_mipi_clk = {
218 .enable = BIT(31) | BIT(23) | BIT(22),
219 .lock = BIT(28),
220 .n = _SUNXI_CCU_MULT(8, 4),
221 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
222 .m = _SUNXI_CCU_DIV(0, 4),
223 .mux = _SUNXI_CCU_MUX(21, 1),
224 .common = {
225 .reg = 0x040,
226 .hw.init = CLK_HW_INIT_PARENTS("pll-mipi",
227 pll_mipi_parents,
228 &ccu_nkm_ops,
229 CLK_SET_RATE_UNGATE)
230 },
231 };
232
233 /* TODO: The result of N/M is required to be in [8, 25] range. */
234 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
235 "osc24M", 0x048,
236 8, 7, /* N */
237 0, 4, /* M */
238 BIT(24), /* frac enable */
239 BIT(25), /* frac select */
240 270000000, /* frac rate 0 */
241 297000000, /* frac rate 1 */
242 BIT(31), /* gate */
243 BIT(28), /* lock */
244 CLK_SET_RATE_UNGATE);
245
246 /* TODO: The N factor is required to be in [16, 75] range. */
247 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
248 "osc24M", 0x04c,
249 8, 7, /* N */
250 0, 2, /* M */
251 BIT(31), /* gate */
252 BIT(28), /* lock */
253 CLK_SET_RATE_UNGATE);
254
255 static const char * const cpu_parents[] = { "osc32k", "osc24M",
256 "pll-cpu", "pll-cpu" };
257 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
258 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
259
260 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
261
262 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
263 "axi", "pll-periph0" };
264 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
265 { .index = 3, .shift = 6, .width = 2 },
266 };
267 static struct ccu_div ahb1_clk = {
268 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
269
270 .mux = {
271 .shift = 12,
272 .width = 2,
273
274 .var_predivs = ahb1_predivs,
275 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
276 },
277
278 .common = {
279 .reg = 0x054,
280 .features = CCU_FEATURE_VARIABLE_PREDIV,
281 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
282 ahb1_parents,
283 &ccu_div_ops,
284 0),
285 },
286 };
287
288 static struct clk_div_table apb1_div_table[] = {
289 { .val = 0, .div = 2 },
290 { .val = 1, .div = 2 },
291 { .val = 2, .div = 4 },
292 { .val = 3, .div = 8 },
293 { /* Sentinel */ },
294 };
295 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
296 0x054, 8, 2, apb1_div_table, 0);
297
298 static const char * const apb2_parents[] = { "osc32k", "osc24M",
299 "pll-periph0-2x",
300 "pll-periph0-2x" };
301 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
302 0, 5, /* M */
303 16, 2, /* P */
304 24, 2, /* mux */
305 0);
306
307 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
308 0x060, BIT(1), 0);
309 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
310 0x060, BIT(5), 0);
311 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
312 0x060, BIT(6), 0);
313 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
314 0x060, BIT(8), 0);
315 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
316 0x060, BIT(9), 0);
317 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
318 0x060, BIT(10), 0);
319 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
320 0x060, BIT(11), 0);
321 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
322 0x060, BIT(13), 0);
323 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
324 0x060, BIT(14), 0);
325 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1",
326 0x060, BIT(17), 0);
327 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
328 0x060, BIT(18), 0);
329 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
330 0x060, BIT(19), 0);
331 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
332 0x060, BIT(20), 0);
333 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
334 0x060, BIT(21), 0);
335 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1",
336 0x060, BIT(22), 0);
337 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1",
338 0x060, BIT(23), 0);
339 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1",
340 0x060, BIT(24), 0);
341 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
342 0x060, BIT(25), 0);
343 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
344 0x060, BIT(26), 0);
345 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1",
346 0x060, BIT(27), 0);
347 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1",
348 0x060, BIT(28), 0);
349 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
350 0x060, BIT(29), 0);
351 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1",
352 0x060, BIT(30), 0);
353 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1",
354 0x060, BIT(31), 0);
355
356 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
357 0x064, BIT(0), 0);
358 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1",
359 0x064, BIT(2), 0);
360 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
361 0x064, BIT(5), 0);
362 static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1",
363 0x064, BIT(8), 0);
364 static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1",
365 0x064, BIT(9), 0);
366 static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1",
367 0x064, BIT(10), 0);
368 static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1",
369 0x064, BIT(11), 0);
370 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
371 0x064, BIT(12), 0);
372 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
373 0x064, BIT(13), 0);
374 static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1",
375 0x064, BIT(14), 0);
376 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1",
377 0x064, BIT(15), 0);
378 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
379 0x064, BIT(17), 0);
380 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
381 0x064, BIT(20), 0);
382 static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1",
383 0x064, BIT(21), 0);
384 static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1",
385 0x064, BIT(22), 0);
386 static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1",
387 0x064, BIT(23), 0);
388 static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1",
389 0x064, BIT(24), 0);
390 static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1",
391 0x064, BIT(25), 0);
392 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1",
393 0x064, BIT(26), 0);
394 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1",
395 0x064, BIT(27), 0);
396 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
397 0x064, BIT(28), 0);
398 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
399 0x064, BIT(29), 0);
400 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
401 0x064, BIT(30), 0);
402
403 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
404 0x068, BIT(0), 0);
405 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
406 0x068, BIT(1), 0);
407 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1",
408 0x068, BIT(2), 0);
409 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
410 0x068, BIT(5), 0);
411 static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1",
412 0x068, BIT(6), 0);
413 static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1",
414 0x068, BIT(7), 0);
415 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
416 0x068, BIT(8), 0);
417 static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1",
418 0x068, BIT(10), 0);
419 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
420 0x068, BIT(12), 0);
421 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
422 0x068, BIT(13), 0);
423 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
424 0x068, BIT(14), 0);
425
426 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
427 0x06c, BIT(0), 0);
428 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
429 0x06c, BIT(1), 0);
430 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
431 0x06c, BIT(2), 0);
432 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
433 0x06c, BIT(3), 0);
434 /*
435 * In datasheet here's "Reserved", however the gate exists in BSP soucre
436 * code.
437 */
438 static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2",
439 0x06c, BIT(4), 0);
440 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
441 0x06c, BIT(5), 0);
442 static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
443 0x06c, BIT(6), 0);
444 static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
445 0x06c, BIT(7), 0);
446 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
447 0x06c, BIT(15), 0);
448 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
449 0x06c, BIT(16), 0);
450 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
451 0x06c, BIT(17), 0);
452 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
453 0x06c, BIT(18), 0);
454 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
455 0x06c, BIT(19), 0);
456 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
457 0x06c, BIT(20), 0);
458 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2",
459 0x06c, BIT(21), 0);
460 static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2",
461 0x06c, BIT(22), 0);
462 static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2",
463 0x06c, BIT(23), 0);
464
465 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
466 0x070, BIT(7), 0);
467
468 static const char * const ths_parents[] = { "osc24M" };
469 static struct ccu_div ths_clk = {
470 .enable = BIT(31),
471 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
472 .mux = _SUNXI_CCU_MUX(24, 2),
473 .common = {
474 .reg = 0x074,
475 .hw.init = CLK_HW_INIT_PARENTS("ths",
476 ths_parents,
477 &ccu_div_ops,
478 0),
479 },
480 };
481
482 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
483 "pll-periph1" };
484 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
485 0, 4, /* M */
486 16, 2, /* P */
487 24, 2, /* mux */
488 BIT(31), /* gate */
489 0);
490
491 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
492 0, 4, /* M */
493 16, 2, /* P */
494 24, 2, /* mux */
495 BIT(31), /* gate */
496 0);
497
498 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
499 0, 4, /* M */
500 16, 2, /* P */
501 24, 2, /* mux */
502 BIT(31), /* gate */
503 0);
504
505 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
506 0, 4, /* M */
507 16, 2, /* P */
508 24, 2, /* mux */
509 BIT(31), /* gate */
510 0);
511
512 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
513 0, 4, /* M */
514 16, 2, /* P */
515 24, 2, /* mux */
516 BIT(31), /* gate */
517 0);
518
519 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
520 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
521 0, 4, /* M */
522 16, 2, /* P */
523 24, 4, /* mux */
524 BIT(31), /* gate */
525 0);
526
527 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
528 "pll-periph1-2x" };
529 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
530 0, 4, /* M */
531 16, 2, /* P */
532 24, 2, /* mux */
533 BIT(31), /* gate */
534 0);
535
536 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
537 0, 4, /* M */
538 16, 2, /* P */
539 24, 2, /* mux */
540 BIT(31), /* gate */
541 0);
542
543 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
544 0, 4, /* M */
545 16, 2, /* P */
546 24, 2, /* mux */
547 BIT(31), /* gate */
548 0);
549
550 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
551 0, 4, /* M */
552 16, 2, /* P */
553 24, 2, /* mux */
554 BIT(31), /* gate */
555 0);
556
557 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
558 0, 4, /* M */
559 16, 2, /* P */
560 24, 2, /* mux */
561 BIT(31), /* gate */
562 0);
563
564 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
565 "pll-audio-2x", "pll-audio" };
566 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
567 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
568
569 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
570 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
571
572 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
573 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
574
575 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents,
576 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
577
578 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents,
579 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
580
581 static const char * const keypad_parents[] = { "osc24M", "osc32k" };
582 static const u8 keypad_table[] = { 0, 2 };
583 static struct ccu_mp keypad_clk = {
584 .enable = BIT(31),
585 .m = _SUNXI_CCU_DIV(0, 5),
586 .p = _SUNXI_CCU_DIV(16, 2),
587 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
588 .common = {
589 .reg = 0x0c4,
590 .hw.init = CLK_HW_INIT_PARENTS("keypad",
591 keypad_parents,
592 &ccu_mp_ops,
593 0),
594 }
595 };
596
597 static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
598 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
599 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
600
601 /*
602 * There are 3 OHCI 12M clock source selection bits in this register.
603 * We will force them to 0 (12M divided from 48M).
604 */
605 #define SUN8I_R40_USB_CLK_REG 0x0cc
606
607 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
608 0x0cc, BIT(8), 0);
609 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
610 0x0cc, BIT(9), 0);
611 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
612 0x0cc, BIT(10), 0);
613 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
614 0x0cc, BIT(16), 0);
615 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M",
616 0x0cc, BIT(17), 0);
617 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M",
618 0x0cc, BIT(18), 0);
619
620 static const char * const ir_parents[] = { "osc24M", "pll-periph0",
621 "pll-periph1", "osc32k" };
622 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
623 0, 4, /* M */
624 16, 2, /* P */
625 24, 2, /* mux */
626 BIT(31), /* gate */
627 0);
628
629 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
630 0, 4, /* M */
631 16, 2, /* P */
632 24, 2, /* mux */
633 BIT(31), /* gate */
634 0);
635
636 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
637 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
638 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
639
640 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
641 0x100, BIT(0), 0);
642 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram",
643 0x100, BIT(1), 0);
644 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram",
645 0x100, BIT(2), 0);
646 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
647 0x100, BIT(3), 0);
648 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram",
649 0x100, BIT(4), 0);
650 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram",
651 0x100, BIT(5), 0);
652 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
653 0x100, BIT(6), 0);
654
655 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
656 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
657 0x104, 0, 4, 24, 3, BIT(31), 0);
658 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
659 0x108, 0, 4, 24, 3, BIT(31), 0);
660
661 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
662 "pll-video0-2x", "pll-video1-2x",
663 "pll-mipi" };
664 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
665 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
666 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
667 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
668 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
669 0x118, 0, 4, 24, 3, BIT(31), 0);
670 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
671 0x11c, 0, 4, 24, 3, BIT(31), 0);
672
673 static const char * const deinterlace_parents[] = { "pll-periph0",
674 "pll-periph1" };
675 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
676 deinterlace_parents, 0x124, 0, 4, 24, 3,
677 BIT(31), 0);
678
679 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
680 "pll-periph1" };
681 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
682 0x130, 0, 5, 8, 3, BIT(15), 0);
683
684 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
685 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
686 0x134, 16, 4, 24, 3, BIT(31), 0);
687
688 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
689 0x134, 0, 5, 8, 3, BIT(15), 0);
690
691 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
692 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
693
694 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
695 0x140, BIT(31), CLK_SET_RATE_PARENT);
696 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
697 0x144, BIT(31), 0);
698
699 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
700 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
701 0x150, 0, 4, 24, 2, BIT(31), 0);
702
703 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
704 0x154, BIT(31), 0);
705
706 /*
707 * In the SoC's user manual, the P factor is mentioned, but not used in
708 * the frequency formula.
709 *
710 * Here the factor is included, according to the BSP kernel source,
711 * which contains the P factor of this clock.
712 */
713 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
714 "pll-ddr0" };
715 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
716 0, 4, /* M */
717 16, 2, /* P */
718 24, 2, /* mux */
719 BIT(31), /* gate */
720 CLK_IS_CRITICAL);
721
722 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
723 "pll-periph0" };
724 static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
725 0x168, 0, 4, 8, 2, BIT(15), 0);
726
727 static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,
728 0x180, 0, 4, 24, 3, BIT(31), 0);
729 static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents,
730 0x184, 0, 4, 24, 3, BIT(31), 0);
731
732 static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
733 "pll-video0-2x", "pll-video1-2x" };
734 static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents,
735 0x188, 0, 4, 24, 3, BIT(31), 0);
736 static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents,
737 0x18c, 0, 4, 24, 3, BIT(31), 0);
738 static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents,
739 0x190, 0, 4, 24, 3, BIT(31), 0);
740 static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents,
741 0x194, 0, 4, 24, 3, BIT(31), 0);
742
743 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
744 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
745
746 static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
747 static const struct ccu_mux_fixed_prediv out_predivs[] = {
748 { .index = 0, .div = 750, },
749 };
750
751 static struct ccu_mp outa_clk = {
752 .enable = BIT(31),
753 .m = _SUNXI_CCU_DIV(8, 5),
754 .p = _SUNXI_CCU_DIV(20, 2),
755 .mux = {
756 .shift = 24,
757 .width = 2,
758 .fixed_predivs = out_predivs,
759 .n_predivs = ARRAY_SIZE(out_predivs),
760 },
761 .common = {
762 .reg = 0x1f0,
763 .features = CCU_FEATURE_FIXED_PREDIV,
764 .hw.init = CLK_HW_INIT_PARENTS("outa", out_parents,
765 &ccu_mp_ops, 0),
766 }
767 };
768
769 static struct ccu_mp outb_clk = {
770 .enable = BIT(31),
771 .m = _SUNXI_CCU_DIV(8, 5),
772 .p = _SUNXI_CCU_DIV(20, 2),
773 .mux = {
774 .shift = 24,
775 .width = 2,
776 .fixed_predivs = out_predivs,
777 .n_predivs = ARRAY_SIZE(out_predivs),
778 },
779 .common = {
780 .reg = 0x1f4,
781 .features = CCU_FEATURE_FIXED_PREDIV,
782 .hw.init = CLK_HW_INIT_PARENTS("outb", out_parents,
783 &ccu_mp_ops, 0),
784 }
785 };
786
787 static struct ccu_common *sun8i_r40_ccu_clks[] = {
788 &pll_cpu_clk.common,
789 &pll_audio_base_clk.common,
790 &pll_video0_clk.common,
791 &pll_ve_clk.common,
792 &pll_ddr0_clk.common,
793 &pll_periph0_clk.common,
794 &pll_periph0_sata_clk.common,
795 &pll_periph1_clk.common,
796 &pll_video1_clk.common,
797 &pll_sata_clk.common,
798 &pll_sata_out_clk.common,
799 &pll_gpu_clk.common,
800 &pll_mipi_clk.common,
801 &pll_de_clk.common,
802 &pll_ddr1_clk.common,
803 &cpu_clk.common,
804 &axi_clk.common,
805 &ahb1_clk.common,
806 &apb1_clk.common,
807 &apb2_clk.common,
808 &bus_mipi_dsi_clk.common,
809 &bus_ce_clk.common,
810 &bus_dma_clk.common,
811 &bus_mmc0_clk.common,
812 &bus_mmc1_clk.common,
813 &bus_mmc2_clk.common,
814 &bus_mmc3_clk.common,
815 &bus_nand_clk.common,
816 &bus_dram_clk.common,
817 &bus_emac_clk.common,
818 &bus_ts_clk.common,
819 &bus_hstimer_clk.common,
820 &bus_spi0_clk.common,
821 &bus_spi1_clk.common,
822 &bus_spi2_clk.common,
823 &bus_spi3_clk.common,
824 &bus_sata_clk.common,
825 &bus_otg_clk.common,
826 &bus_ehci0_clk.common,
827 &bus_ehci1_clk.common,
828 &bus_ehci2_clk.common,
829 &bus_ohci0_clk.common,
830 &bus_ohci1_clk.common,
831 &bus_ohci2_clk.common,
832 &bus_ve_clk.common,
833 &bus_mp_clk.common,
834 &bus_deinterlace_clk.common,
835 &bus_csi0_clk.common,
836 &bus_csi1_clk.common,
837 &bus_hdmi0_clk.common,
838 &bus_hdmi1_clk.common,
839 &bus_de_clk.common,
840 &bus_tve0_clk.common,
841 &bus_tve1_clk.common,
842 &bus_tve_top_clk.common,
843 &bus_gmac_clk.common,
844 &bus_gpu_clk.common,
845 &bus_tvd0_clk.common,
846 &bus_tvd1_clk.common,
847 &bus_tvd2_clk.common,
848 &bus_tvd3_clk.common,
849 &bus_tvd_top_clk.common,
850 &bus_tcon_lcd0_clk.common,
851 &bus_tcon_lcd1_clk.common,
852 &bus_tcon_tv0_clk.common,
853 &bus_tcon_tv1_clk.common,
854 &bus_tcon_top_clk.common,
855 &bus_codec_clk.common,
856 &bus_spdif_clk.common,
857 &bus_ac97_clk.common,
858 &bus_pio_clk.common,
859 &bus_ir0_clk.common,
860 &bus_ir1_clk.common,
861 &bus_ths_clk.common,
862 &bus_keypad_clk.common,
863 &bus_i2s0_clk.common,
864 &bus_i2s1_clk.common,
865 &bus_i2s2_clk.common,
866 &bus_i2c0_clk.common,
867 &bus_i2c1_clk.common,
868 &bus_i2c2_clk.common,
869 &bus_i2c3_clk.common,
870 &bus_can_clk.common,
871 &bus_scr_clk.common,
872 &bus_ps20_clk.common,
873 &bus_ps21_clk.common,
874 &bus_i2c4_clk.common,
875 &bus_uart0_clk.common,
876 &bus_uart1_clk.common,
877 &bus_uart2_clk.common,
878 &bus_uart3_clk.common,
879 &bus_uart4_clk.common,
880 &bus_uart5_clk.common,
881 &bus_uart6_clk.common,
882 &bus_uart7_clk.common,
883 &bus_dbg_clk.common,
884 &ths_clk.common,
885 &nand_clk.common,
886 &mmc0_clk.common,
887 &mmc1_clk.common,
888 &mmc2_clk.common,
889 &mmc3_clk.common,
890 &ts_clk.common,
891 &ce_clk.common,
892 &spi0_clk.common,
893 &spi1_clk.common,
894 &spi2_clk.common,
895 &spi3_clk.common,
896 &i2s0_clk.common,
897 &i2s1_clk.common,
898 &i2s2_clk.common,
899 &ac97_clk.common,
900 &spdif_clk.common,
901 &keypad_clk.common,
902 &sata_clk.common,
903 &usb_phy0_clk.common,
904 &usb_phy1_clk.common,
905 &usb_phy2_clk.common,
906 &usb_ohci0_clk.common,
907 &usb_ohci1_clk.common,
908 &usb_ohci2_clk.common,
909 &ir0_clk.common,
910 &ir1_clk.common,
911 &dram_clk.common,
912 &dram_ve_clk.common,
913 &dram_csi0_clk.common,
914 &dram_csi1_clk.common,
915 &dram_ts_clk.common,
916 &dram_tvd_clk.common,
917 &dram_mp_clk.common,
918 &dram_deinterlace_clk.common,
919 &de_clk.common,
920 &mp_clk.common,
921 &tcon_lcd0_clk.common,
922 &tcon_lcd1_clk.common,
923 &tcon_tv0_clk.common,
924 &tcon_tv1_clk.common,
925 &deinterlace_clk.common,
926 &csi1_mclk_clk.common,
927 &csi_sclk_clk.common,
928 &csi0_mclk_clk.common,
929 &ve_clk.common,
930 &codec_clk.common,
931 &avs_clk.common,
932 &hdmi_clk.common,
933 &hdmi_slow_clk.common,
934 &mbus_clk.common,
935 &dsi_dphy_clk.common,
936 &tve0_clk.common,
937 &tve1_clk.common,
938 &tvd0_clk.common,
939 &tvd1_clk.common,
940 &tvd2_clk.common,
941 &tvd3_clk.common,
942 &gpu_clk.common,
943 &outa_clk.common,
944 &outb_clk.common,
945 };
946
947 /* Fixed Factor clocks */
948 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
949
950 /* We hardcode the divider to 4 for now */
951 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
952 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
953 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
954 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
955 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
956 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
957 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
958 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
959 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
960 "pll-periph0", 1, 2, 0);
961 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
962 "pll-periph1", 1, 2, 0);
963 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
964 "pll-video0", 1, 2, 0);
965 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
966 "pll-video1", 1, 2, 0);
967
968 static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
969 .hws = {
970 [CLK_OSC_12M] = &osc12M_clk.hw,
971 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
972 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
973 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
974 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
975 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
976 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
977 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
978 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
979 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
980 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
981 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
982 [CLK_PLL_PERIPH0_SATA] = &pll_periph0_sata_clk.common.hw,
983 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
984 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
985 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
986 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
987 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
988 [CLK_PLL_SATA] = &pll_sata_clk.common.hw,
989 [CLK_PLL_SATA_OUT] = &pll_sata_out_clk.common.hw,
990 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
991 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
992 [CLK_PLL_DE] = &pll_de_clk.common.hw,
993 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
994 [CLK_CPU] = &cpu_clk.common.hw,
995 [CLK_AXI] = &axi_clk.common.hw,
996 [CLK_AHB1] = &ahb1_clk.common.hw,
997 [CLK_APB1] = &apb1_clk.common.hw,
998 [CLK_APB2] = &apb2_clk.common.hw,
999 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
1000 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
1001 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
1002 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
1003 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
1004 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
1005 [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw,
1006 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
1007 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
1008 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
1009 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
1010 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
1011 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
1012 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
1013 [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
1014 [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
1015 [CLK_BUS_SATA] = &bus_sata_clk.common.hw,
1016 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
1017 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
1018 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
1019 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
1020 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
1021 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
1022 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
1023 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
1024 [CLK_BUS_MP] = &bus_mp_clk.common.hw,
1025 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
1026 [CLK_BUS_CSI0] = &bus_csi0_clk.common.hw,
1027 [CLK_BUS_CSI1] = &bus_csi1_clk.common.hw,
1028 [CLK_BUS_HDMI0] = &bus_hdmi0_clk.common.hw,
1029 [CLK_BUS_HDMI1] = &bus_hdmi1_clk.common.hw,
1030 [CLK_BUS_DE] = &bus_de_clk.common.hw,
1031 [CLK_BUS_TVE0] = &bus_tve0_clk.common.hw,
1032 [CLK_BUS_TVE1] = &bus_tve1_clk.common.hw,
1033 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
1034 [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw,
1035 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
1036 [CLK_BUS_TVD0] = &bus_tvd0_clk.common.hw,
1037 [CLK_BUS_TVD1] = &bus_tvd1_clk.common.hw,
1038 [CLK_BUS_TVD2] = &bus_tvd2_clk.common.hw,
1039 [CLK_BUS_TVD3] = &bus_tvd3_clk.common.hw,
1040 [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
1041 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1042 [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
1043 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
1044 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
1045 [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
1046 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
1047 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
1048 [CLK_BUS_AC97] = &bus_ac97_clk.common.hw,
1049 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
1050 [CLK_BUS_IR0] = &bus_ir0_clk.common.hw,
1051 [CLK_BUS_IR1] = &bus_ir1_clk.common.hw,
1052 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
1053 [CLK_BUS_KEYPAD] = &bus_keypad_clk.common.hw,
1054 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
1055 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
1056 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
1057 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
1058 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
1059 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
1060 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
1061 [CLK_BUS_CAN] = &bus_can_clk.common.hw,
1062 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
1063 [CLK_BUS_PS20] = &bus_ps20_clk.common.hw,
1064 [CLK_BUS_PS21] = &bus_ps21_clk.common.hw,
1065 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
1066 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
1067 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
1068 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
1069 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
1070 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
1071 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
1072 [CLK_BUS_UART6] = &bus_uart6_clk.common.hw,
1073 [CLK_BUS_UART7] = &bus_uart7_clk.common.hw,
1074 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
1075 [CLK_THS] = &ths_clk.common.hw,
1076 [CLK_NAND] = &nand_clk.common.hw,
1077 [CLK_MMC0] = &mmc0_clk.common.hw,
1078 [CLK_MMC1] = &mmc1_clk.common.hw,
1079 [CLK_MMC2] = &mmc2_clk.common.hw,
1080 [CLK_MMC3] = &mmc3_clk.common.hw,
1081 [CLK_TS] = &ts_clk.common.hw,
1082 [CLK_CE] = &ce_clk.common.hw,
1083 [CLK_SPI0] = &spi0_clk.common.hw,
1084 [CLK_SPI1] = &spi1_clk.common.hw,
1085 [CLK_SPI2] = &spi2_clk.common.hw,
1086 [CLK_SPI3] = &spi3_clk.common.hw,
1087 [CLK_I2S0] = &i2s0_clk.common.hw,
1088 [CLK_I2S1] = &i2s1_clk.common.hw,
1089 [CLK_I2S2] = &i2s2_clk.common.hw,
1090 [CLK_AC97] = &ac97_clk.common.hw,
1091 [CLK_SPDIF] = &spdif_clk.common.hw,
1092 [CLK_KEYPAD] = &keypad_clk.common.hw,
1093 [CLK_SATA] = &sata_clk.common.hw,
1094 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
1095 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
1096 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
1097 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1098 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1099 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
1100 [CLK_IR0] = &ir0_clk.common.hw,
1101 [CLK_IR1] = &ir1_clk.common.hw,
1102 [CLK_DRAM] = &dram_clk.common.hw,
1103 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1104 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
1105 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
1106 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1107 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
1108 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1109 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
1110 [CLK_DE] = &de_clk.common.hw,
1111 [CLK_MP] = &mp_clk.common.hw,
1112 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
1113 [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
1114 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
1115 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
1116 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
1117 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
1118 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
1119 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
1120 [CLK_VE] = &ve_clk.common.hw,
1121 [CLK_CODEC] = &codec_clk.common.hw,
1122 [CLK_AVS] = &avs_clk.common.hw,
1123 [CLK_HDMI] = &hdmi_clk.common.hw,
1124 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
1125 [CLK_MBUS] = &mbus_clk.common.hw,
1126 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
1127 [CLK_TVE0] = &tve0_clk.common.hw,
1128 [CLK_TVE1] = &tve1_clk.common.hw,
1129 [CLK_TVD0] = &tvd0_clk.common.hw,
1130 [CLK_TVD1] = &tvd1_clk.common.hw,
1131 [CLK_TVD2] = &tvd2_clk.common.hw,
1132 [CLK_TVD3] = &tvd3_clk.common.hw,
1133 [CLK_GPU] = &gpu_clk.common.hw,
1134 [CLK_OUTA] = &outa_clk.common.hw,
1135 [CLK_OUTB] = &outb_clk.common.hw,
1136 },
1137 .num = CLK_NUMBER,
1138 };
1139
1140 static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
1141 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1142 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1143 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1144
1145 [RST_DRAM] = { 0x0f4, BIT(31) },
1146 [RST_MBUS] = { 0x0fc, BIT(31) },
1147
1148 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
1149 [RST_BUS_CE] = { 0x2c0, BIT(5) },
1150 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
1151 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
1152 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
1153 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
1154 [RST_BUS_MMC3] = { 0x2c0, BIT(11) },
1155 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
1156 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
1157 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
1158 [RST_BUS_TS] = { 0x2c0, BIT(18) },
1159 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
1160 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
1161 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
1162 [RST_BUS_SPI2] = { 0x2c0, BIT(22) },
1163 [RST_BUS_SPI3] = { 0x2c0, BIT(23) },
1164 [RST_BUS_SATA] = { 0x2c0, BIT(24) },
1165 [RST_BUS_OTG] = { 0x2c0, BIT(25) },
1166 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
1167 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
1168 [RST_BUS_EHCI2] = { 0x2c0, BIT(28) },
1169 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
1170 [RST_BUS_OHCI1] = { 0x2c0, BIT(30) },
1171 [RST_BUS_OHCI2] = { 0x2c0, BIT(31) },
1172
1173 [RST_BUS_VE] = { 0x2c4, BIT(0) },
1174 [RST_BUS_MP] = { 0x2c4, BIT(2) },
1175 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
1176 [RST_BUS_CSI0] = { 0x2c4, BIT(8) },
1177 [RST_BUS_CSI1] = { 0x2c4, BIT(9) },
1178 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
1179 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
1180 [RST_BUS_DE] = { 0x2c4, BIT(12) },
1181 [RST_BUS_TVE0] = { 0x2c4, BIT(13) },
1182 [RST_BUS_TVE1] = { 0x2c4, BIT(14) },
1183 [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) },
1184 [RST_BUS_GMAC] = { 0x2c4, BIT(17) },
1185 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
1186 [RST_BUS_TVD0] = { 0x2c4, BIT(21) },
1187 [RST_BUS_TVD1] = { 0x2c4, BIT(22) },
1188 [RST_BUS_TVD2] = { 0x2c4, BIT(23) },
1189 [RST_BUS_TVD3] = { 0x2c4, BIT(24) },
1190 [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) },
1191 [RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) },
1192 [RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) },
1193 [RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) },
1194 [RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) },
1195 [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) },
1196 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
1197
1198 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
1199
1200 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
1201 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
1202 [RST_BUS_AC97] = { 0x2d0, BIT(2) },
1203 [RST_BUS_IR0] = { 0x2d0, BIT(6) },
1204 [RST_BUS_IR1] = { 0x2d0, BIT(7) },
1205 [RST_BUS_THS] = { 0x2d0, BIT(8) },
1206 [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) },
1207 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
1208 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
1209 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
1210
1211 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
1212 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
1213 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
1214 [RST_BUS_I2C3] = { 0x2d8, BIT(3) },
1215 [RST_BUS_CAN] = { 0x2d8, BIT(4) },
1216 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
1217 [RST_BUS_PS20] = { 0x2d8, BIT(6) },
1218 [RST_BUS_PS21] = { 0x2d8, BIT(7) },
1219 [RST_BUS_I2C4] = { 0x2d8, BIT(15) },
1220 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
1221 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
1222 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
1223 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
1224 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
1225 [RST_BUS_UART5] = { 0x2d8, BIT(21) },
1226 [RST_BUS_UART6] = { 0x2d8, BIT(22) },
1227 [RST_BUS_UART7] = { 0x2d8, BIT(23) },
1228 };
1229
1230 static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
1231 .ccu_clks = sun8i_r40_ccu_clks,
1232 .num_ccu_clks = ARRAY_SIZE(sun8i_r40_ccu_clks),
1233
1234 .hw_clks = &sun8i_r40_hw_clks,
1235
1236 .resets = sun8i_r40_ccu_resets,
1237 .num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets),
1238 };
1239
1240 static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = {
1241 .common = &pll_cpu_clk.common,
1242 /* copy from pll_cpu_clk */
1243 .enable = BIT(31),
1244 .lock = BIT(28),
1245 };
1246
1247 static struct ccu_mux_nb sun8i_r40_cpu_nb = {
1248 .common = &cpu_clk.common,
1249 .cm = &cpu_clk.mux,
1250 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1251 .bypass_index = 1, /* index of 24 MHz oscillator */
1252 };
1253
1254 /*
1255 * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
1256 * GMAC configuration register.
1257 * Only this register is allowed to be written, in order to
1258 * prevent overriding critical clock configuration.
1259 */
1260
1261 #define SUN8I_R40_GMAC_CFG_REG 0x164
1262 static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
1263 unsigned int reg)
1264 {
1265 if (reg == SUN8I_R40_GMAC_CFG_REG)
1266 return true;
1267 return false;
1268 }
1269
1270 static struct regmap_config sun8i_r40_ccu_regmap_config = {
1271 .reg_bits = 32,
1272 .val_bits = 32,
1273 .reg_stride = 4,
1274 .max_register = 0x320, /* PLL_LOCK_CTRL_REG */
1275
1276 /* other devices have no business accessing other registers */
1277 .readable_reg = sun8i_r40_ccu_regmap_accessible_reg,
1278 .writeable_reg = sun8i_r40_ccu_regmap_accessible_reg,
1279 };
1280
1281 static int sun8i_r40_ccu_probe(struct platform_device *pdev)
1282 {
1283 struct resource *res;
1284 struct regmap *regmap;
1285 void __iomem *reg;
1286 u32 val;
1287 int ret;
1288
1289 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1290 reg = devm_ioremap_resource(&pdev->dev, res);
1291 if (IS_ERR(reg))
1292 return PTR_ERR(reg);
1293
1294 /* Force the PLL-Audio-1x divider to 4 */
1295 val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
1296 val &= ~GENMASK(19, 16);
1297 writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
1298
1299 /* Force PLL-MIPI to MIPI mode */
1300 val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
1301 val &= ~BIT(16);
1302 writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
1303
1304 /* Force OHCI 12M parent to 12M divided from 48M */
1305 val = readl(reg + SUN8I_R40_USB_CLK_REG);
1306 val &= ~GENMASK(25, 20);
1307 writel(val, reg + SUN8I_R40_USB_CLK_REG);
1308
1309 regmap = devm_regmap_init_mmio(&pdev->dev, reg,
1310 &sun8i_r40_ccu_regmap_config);
1311 if (IS_ERR(regmap))
1312 return PTR_ERR(regmap);
1313
1314 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc);
1315 if (ret)
1316 return ret;
1317
1318 /* Gate then ungate PLL CPU after any rate changes */
1319 ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
1320
1321 /* Reparent CPU during PLL CPU rate changes */
1322 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1323 &sun8i_r40_cpu_nb);
1324
1325 return 0;
1326 }
1327
1328 static const struct of_device_id sun8i_r40_ccu_ids[] = {
1329 { .compatible = "allwinner,sun8i-r40-ccu" },
1330 { }
1331 };
1332
1333 static struct platform_driver sun8i_r40_ccu_driver = {
1334 .probe = sun8i_r40_ccu_probe,
1335 .driver = {
1336 .name = "sun8i-r40-ccu",
1337 .of_match_table = sun8i_r40_ccu_ids,
1338 },
1339 };
1340 builtin_platform_driver(sun8i_r40_ccu_driver);
Linux with added FPC-III support