Linux 4.18.10
[linux/fpc-iii.git] / drivers / clk / tegra / clk-dfll.c
blob48ee43734e05117bec4d783431b7fc617daf3fb4
1 /*
2 * clk-dfll.c - Tegra DFLL clock source common code
4 * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
6 * Aleksandr Frid <afrid@nvidia.com>
7 * Paul Walmsley <pwalmsley@nvidia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
18 * This library is for the DVCO and DFLL IP blocks on the Tegra124
19 * SoC. These IP blocks together are also known at NVIDIA as
20 * "CL-DVFS". To try to avoid confusion, this code refers to them
21 * collectively as the "DFLL."
23 * The DFLL is a root clocksource which tolerates some amount of
24 * supply voltage noise. Tegra124 uses it to clock the fast CPU
25 * complex when the target CPU speed is above a particular rate. The
26 * DFLL can be operated in either open-loop mode or closed-loop mode.
27 * In open-loop mode, the DFLL generates an output clock appropriate
28 * to the supply voltage. In closed-loop mode, when configured with a
29 * target frequency, the DFLL minimizes supply voltage while
30 * delivering an average frequency equal to the target.
32 * Devices clocked by the DFLL must be able to tolerate frequency
33 * variation. In the case of the CPU, it's important to note that the
34 * CPU cycle time will vary. This has implications for
35 * performance-measurement code and any code that relies on the CPU
36 * cycle time to delay for a certain length of time.
40 #include <linux/clk.h>
41 #include <linux/clk-provider.h>
42 #include <linux/debugfs.h>
43 #include <linux/device.h>
44 #include <linux/err.h>
45 #include <linux/i2c.h>
46 #include <linux/io.h>
47 #include <linux/kernel.h>
48 #include <linux/module.h>
49 #include <linux/of.h>
50 #include <linux/pm_opp.h>
51 #include <linux/pm_runtime.h>
52 #include <linux/regmap.h>
53 #include <linux/regulator/consumer.h>
54 #include <linux/reset.h>
55 #include <linux/seq_file.h>
57 #include "clk-dfll.h"
58 #include "cvb.h"
61 * DFLL control registers - access via dfll_{readl,writel}
64 /* DFLL_CTRL: DFLL control register */
65 #define DFLL_CTRL 0x00
66 #define DFLL_CTRL_MODE_MASK 0x03
68 /* DFLL_CONFIG: DFLL sample rate control */
69 #define DFLL_CONFIG 0x04
70 #define DFLL_CONFIG_DIV_MASK 0xff
71 #define DFLL_CONFIG_DIV_PRESCALE 32
73 /* DFLL_PARAMS: tuning coefficients for closed loop integrator */
74 #define DFLL_PARAMS 0x08
75 #define DFLL_PARAMS_CG_SCALE (0x1 << 24)
76 #define DFLL_PARAMS_FORCE_MODE_SHIFT 22
77 #define DFLL_PARAMS_FORCE_MODE_MASK (0x3 << DFLL_PARAMS_FORCE_MODE_SHIFT)
78 #define DFLL_PARAMS_CF_PARAM_SHIFT 16
79 #define DFLL_PARAMS_CF_PARAM_MASK (0x3f << DFLL_PARAMS_CF_PARAM_SHIFT)
80 #define DFLL_PARAMS_CI_PARAM_SHIFT 8
81 #define DFLL_PARAMS_CI_PARAM_MASK (0x7 << DFLL_PARAMS_CI_PARAM_SHIFT)
82 #define DFLL_PARAMS_CG_PARAM_SHIFT 0
83 #define DFLL_PARAMS_CG_PARAM_MASK (0xff << DFLL_PARAMS_CG_PARAM_SHIFT)
85 /* DFLL_TUNE0: delay line configuration register 0 */
86 #define DFLL_TUNE0 0x0c
88 /* DFLL_TUNE1: delay line configuration register 1 */
89 #define DFLL_TUNE1 0x10
91 /* DFLL_FREQ_REQ: target DFLL frequency control */
92 #define DFLL_FREQ_REQ 0x14
93 #define DFLL_FREQ_REQ_FORCE_ENABLE (0x1 << 28)
94 #define DFLL_FREQ_REQ_FORCE_SHIFT 16
95 #define DFLL_FREQ_REQ_FORCE_MASK (0xfff << DFLL_FREQ_REQ_FORCE_SHIFT)
96 #define FORCE_MAX 2047
97 #define FORCE_MIN -2048
98 #define DFLL_FREQ_REQ_SCALE_SHIFT 8
99 #define DFLL_FREQ_REQ_SCALE_MASK (0xff << DFLL_FREQ_REQ_SCALE_SHIFT)
100 #define DFLL_FREQ_REQ_SCALE_MAX 256
101 #define DFLL_FREQ_REQ_FREQ_VALID (0x1 << 7)
102 #define DFLL_FREQ_REQ_MULT_SHIFT 0
103 #define DFLL_FREQ_REG_MULT_MASK (0x7f << DFLL_FREQ_REQ_MULT_SHIFT)
104 #define FREQ_MAX 127
106 /* DFLL_DROOP_CTRL: droop prevention control */
107 #define DFLL_DROOP_CTRL 0x1c
109 /* DFLL_OUTPUT_CFG: closed loop mode control registers */
110 /* NOTE: access via dfll_i2c_{readl,writel} */
111 #define DFLL_OUTPUT_CFG 0x20
112 #define DFLL_OUTPUT_CFG_I2C_ENABLE (0x1 << 30)
113 #define OUT_MASK 0x3f
114 #define DFLL_OUTPUT_CFG_SAFE_SHIFT 24
115 #define DFLL_OUTPUT_CFG_SAFE_MASK \
116 (OUT_MASK << DFLL_OUTPUT_CFG_SAFE_SHIFT)
117 #define DFLL_OUTPUT_CFG_MAX_SHIFT 16
118 #define DFLL_OUTPUT_CFG_MAX_MASK \
119 (OUT_MASK << DFLL_OUTPUT_CFG_MAX_SHIFT)
120 #define DFLL_OUTPUT_CFG_MIN_SHIFT 8
121 #define DFLL_OUTPUT_CFG_MIN_MASK \
122 (OUT_MASK << DFLL_OUTPUT_CFG_MIN_SHIFT)
123 #define DFLL_OUTPUT_CFG_PWM_DELTA (0x1 << 7)
124 #define DFLL_OUTPUT_CFG_PWM_ENABLE (0x1 << 6)
125 #define DFLL_OUTPUT_CFG_PWM_DIV_SHIFT 0
126 #define DFLL_OUTPUT_CFG_PWM_DIV_MASK \
127 (OUT_MASK << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)
129 /* DFLL_OUTPUT_FORCE: closed loop mode voltage forcing control */
130 #define DFLL_OUTPUT_FORCE 0x24
131 #define DFLL_OUTPUT_FORCE_ENABLE (0x1 << 6)
132 #define DFLL_OUTPUT_FORCE_VALUE_SHIFT 0
133 #define DFLL_OUTPUT_FORCE_VALUE_MASK \
134 (OUT_MASK << DFLL_OUTPUT_FORCE_VALUE_SHIFT)
136 /* DFLL_MONITOR_CTRL: internal monitor data source control */
137 #define DFLL_MONITOR_CTRL 0x28
138 #define DFLL_MONITOR_CTRL_FREQ 6
140 /* DFLL_MONITOR_DATA: internal monitor data output */
141 #define DFLL_MONITOR_DATA 0x2c
142 #define DFLL_MONITOR_DATA_NEW_MASK (0x1 << 16)
143 #define DFLL_MONITOR_DATA_VAL_SHIFT 0
144 #define DFLL_MONITOR_DATA_VAL_MASK (0xFFFF << DFLL_MONITOR_DATA_VAL_SHIFT)
147 * I2C output control registers - access via dfll_i2c_{readl,writel}
150 /* DFLL_I2C_CFG: I2C controller configuration register */
151 #define DFLL_I2C_CFG 0x40
152 #define DFLL_I2C_CFG_ARB_ENABLE (0x1 << 20)
153 #define DFLL_I2C_CFG_HS_CODE_SHIFT 16
154 #define DFLL_I2C_CFG_HS_CODE_MASK (0x7 << DFLL_I2C_CFG_HS_CODE_SHIFT)
155 #define DFLL_I2C_CFG_PACKET_ENABLE (0x1 << 15)
156 #define DFLL_I2C_CFG_SIZE_SHIFT 12
157 #define DFLL_I2C_CFG_SIZE_MASK (0x7 << DFLL_I2C_CFG_SIZE_SHIFT)
158 #define DFLL_I2C_CFG_SLAVE_ADDR_10 (0x1 << 10)
159 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT 1
160 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT 0
162 /* DFLL_I2C_VDD_REG_ADDR: PMIC I2C address for closed loop mode */
163 #define DFLL_I2C_VDD_REG_ADDR 0x44
165 /* DFLL_I2C_STS: I2C controller status */
166 #define DFLL_I2C_STS 0x48
167 #define DFLL_I2C_STS_I2C_LAST_SHIFT 1
168 #define DFLL_I2C_STS_I2C_REQ_PENDING 0x1
170 /* DFLL_INTR_STS: DFLL interrupt status register */
171 #define DFLL_INTR_STS 0x5c
173 /* DFLL_INTR_EN: DFLL interrupt enable register */
174 #define DFLL_INTR_EN 0x60
175 #define DFLL_INTR_MIN_MASK 0x1
176 #define DFLL_INTR_MAX_MASK 0x2
179 * Integrated I2C controller registers - relative to td->i2c_controller_base
182 /* DFLL_I2C_CLK_DIVISOR: I2C controller clock divisor */
183 #define DFLL_I2C_CLK_DIVISOR 0x6c
184 #define DFLL_I2C_CLK_DIVISOR_MASK 0xffff
185 #define DFLL_I2C_CLK_DIVISOR_FS_SHIFT 16
186 #define DFLL_I2C_CLK_DIVISOR_HS_SHIFT 0
187 #define DFLL_I2C_CLK_DIVISOR_PREDIV 8
188 #define DFLL_I2C_CLK_DIVISOR_HSMODE_PREDIV 12
191 * Other constants
194 /* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */
195 #define MAX_DFLL_VOLTAGES 33
198 * REF_CLK_CYC_PER_DVCO_SAMPLE: the number of ref_clk cycles that the hardware
199 * integrates the DVCO counter over - used for debug rate monitoring and
200 * droop control
202 #define REF_CLK_CYC_PER_DVCO_SAMPLE 4
205 * REF_CLOCK_RATE: the DFLL reference clock rate currently supported by this
206 * driver, in Hz
208 #define REF_CLOCK_RATE 51000000UL
210 #define DVCO_RATE_TO_MULT(rate, ref_rate) ((rate) / ((ref_rate) / 2))
211 #define MULT_TO_DVCO_RATE(mult, ref_rate) ((mult) * ((ref_rate) / 2))
214 * enum dfll_ctrl_mode - DFLL hardware operating mode
215 * @DFLL_UNINITIALIZED: (uninitialized state - not in hardware bitfield)
216 * @DFLL_DISABLED: DFLL not generating an output clock
217 * @DFLL_OPEN_LOOP: DVCO running, but DFLL not adjusting voltage
218 * @DFLL_CLOSED_LOOP: DVCO running, and DFLL adjusting voltage to match
219 * the requested rate
221 * The integer corresponding to the last two states, minus one, is
222 * written to the DFLL hardware to change operating modes.
224 enum dfll_ctrl_mode {
225 DFLL_UNINITIALIZED = 0,
226 DFLL_DISABLED = 1,
227 DFLL_OPEN_LOOP = 2,
228 DFLL_CLOSED_LOOP = 3,
232 * enum dfll_tune_range - voltage range that the driver believes it's in
233 * @DFLL_TUNE_UNINITIALIZED: DFLL tuning not yet programmed
234 * @DFLL_TUNE_LOW: DFLL in the low-voltage range (or open-loop mode)
236 * Some DFLL tuning parameters may need to change depending on the
237 * DVCO's voltage; these states represent the ranges that the driver
238 * supports. These are software states; these values are never
239 * written into registers.
241 enum dfll_tune_range {
242 DFLL_TUNE_UNINITIALIZED = 0,
243 DFLL_TUNE_LOW = 1,
247 * struct dfll_rate_req - target DFLL rate request data
248 * @rate: target frequency, after the postscaling
249 * @dvco_target_rate: target frequency, after the postscaling
250 * @lut_index: LUT index at which voltage the dvco_target_rate will be reached
251 * @mult_bits: value to program to the MULT bits of the DFLL_FREQ_REQ register
252 * @scale_bits: value to program to the SCALE bits of the DFLL_FREQ_REQ register
254 struct dfll_rate_req {
255 unsigned long rate;
256 unsigned long dvco_target_rate;
257 int lut_index;
258 u8 mult_bits;
259 u8 scale_bits;
262 struct tegra_dfll {
263 struct device *dev;
264 struct tegra_dfll_soc_data *soc;
266 void __iomem *base;
267 void __iomem *i2c_base;
268 void __iomem *i2c_controller_base;
269 void __iomem *lut_base;
271 struct regulator *vdd_reg;
272 struct clk *soc_clk;
273 struct clk *ref_clk;
274 struct clk *i2c_clk;
275 struct clk *dfll_clk;
276 struct reset_control *dvco_rst;
277 unsigned long ref_rate;
278 unsigned long i2c_clk_rate;
279 unsigned long dvco_rate_min;
281 enum dfll_ctrl_mode mode;
282 enum dfll_tune_range tune_range;
283 struct dentry *debugfs_dir;
284 struct clk_hw dfll_clk_hw;
285 const char *output_clock_name;
286 struct dfll_rate_req last_req;
287 unsigned long last_unrounded_rate;
289 /* Parameters from DT */
290 u32 droop_ctrl;
291 u32 sample_rate;
292 u32 force_mode;
293 u32 cf;
294 u32 ci;
295 u32 cg;
296 bool cg_scale;
298 /* I2C interface parameters */
299 u32 i2c_fs_rate;
300 u32 i2c_reg;
301 u32 i2c_slave_addr;
303 /* i2c_lut array entries are regulator framework selectors */
304 unsigned i2c_lut[MAX_DFLL_VOLTAGES];
305 int i2c_lut_size;
306 u8 lut_min, lut_max, lut_safe;
309 #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)
311 /* mode_name: map numeric DFLL modes to names for friendly console messages */
312 static const char * const mode_name[] = {
313 [DFLL_UNINITIALIZED] = "uninitialized",
314 [DFLL_DISABLED] = "disabled",
315 [DFLL_OPEN_LOOP] = "open_loop",
316 [DFLL_CLOSED_LOOP] = "closed_loop",
320 * Register accessors
323 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs)
325 return __raw_readl(td->base + offs);
328 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs)
330 WARN_ON(offs >= DFLL_I2C_CFG);
331 __raw_writel(val, td->base + offs);
334 static inline void dfll_wmb(struct tegra_dfll *td)
336 dfll_readl(td, DFLL_CTRL);
339 /* I2C output control registers - for addresses above DFLL_I2C_CFG */
341 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs)
343 return __raw_readl(td->i2c_base + offs);
346 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs)
348 __raw_writel(val, td->i2c_base + offs);
351 static inline void dfll_i2c_wmb(struct tegra_dfll *td)
353 dfll_i2c_readl(td, DFLL_I2C_CFG);
357 * dfll_is_running - is the DFLL currently generating a clock?
358 * @td: DFLL instance
360 * If the DFLL is currently generating an output clock signal, return
361 * true; otherwise return false.
363 static bool dfll_is_running(struct tegra_dfll *td)
365 return td->mode >= DFLL_OPEN_LOOP;
369 * Runtime PM suspend/resume callbacks
373 * tegra_dfll_runtime_resume - enable all clocks needed by the DFLL
374 * @dev: DFLL device *
376 * Enable all clocks needed by the DFLL. Assumes that clk_prepare()
377 * has already been called on all the clocks.
379 * XXX Should also handle context restore when returning from off.
381 int tegra_dfll_runtime_resume(struct device *dev)
383 struct tegra_dfll *td = dev_get_drvdata(dev);
384 int ret;
386 ret = clk_enable(td->ref_clk);
387 if (ret) {
388 dev_err(dev, "could not enable ref clock: %d\n", ret);
389 return ret;
392 ret = clk_enable(td->soc_clk);
393 if (ret) {
394 dev_err(dev, "could not enable register clock: %d\n", ret);
395 clk_disable(td->ref_clk);
396 return ret;
399 ret = clk_enable(td->i2c_clk);
400 if (ret) {
401 dev_err(dev, "could not enable i2c clock: %d\n", ret);
402 clk_disable(td->soc_clk);
403 clk_disable(td->ref_clk);
404 return ret;
407 return 0;
409 EXPORT_SYMBOL(tegra_dfll_runtime_resume);
412 * tegra_dfll_runtime_suspend - disable all clocks needed by the DFLL
413 * @dev: DFLL device *
415 * Disable all clocks needed by the DFLL. Assumes that other code
416 * will later call clk_unprepare().
418 int tegra_dfll_runtime_suspend(struct device *dev)
420 struct tegra_dfll *td = dev_get_drvdata(dev);
422 clk_disable(td->ref_clk);
423 clk_disable(td->soc_clk);
424 clk_disable(td->i2c_clk);
426 return 0;
428 EXPORT_SYMBOL(tegra_dfll_runtime_suspend);
431 * DFLL tuning operations (per-voltage-range tuning settings)
435 * dfll_tune_low - tune to DFLL and CPU settings valid for any voltage
436 * @td: DFLL instance
438 * Tune the DFLL oscillator parameters and the CPU clock shaper for
439 * the low-voltage range. These settings are valid for any voltage,
440 * but may not be optimal.
442 static void dfll_tune_low(struct tegra_dfll *td)
444 td->tune_range = DFLL_TUNE_LOW;
446 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0);
447 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1);
448 dfll_wmb(td);
450 if (td->soc->set_clock_trimmers_low)
451 td->soc->set_clock_trimmers_low();
455 * Output clock scaler helpers
459 * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate
460 * @scale_bits: clock scaler value (bits in the DFLL_FREQ_REQ_SCALE field)
461 * @dvco_rate: the DVCO rate
463 * Apply the same scaling formula that the DFLL hardware uses to scale
464 * the DVCO rate.
466 static unsigned long dfll_scale_dvco_rate(int scale_bits,
467 unsigned long dvco_rate)
469 return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;
473 * DFLL mode switching
477 * dfll_set_mode - change the DFLL control mode
478 * @td: DFLL instance
479 * @mode: DFLL control mode (see enum dfll_ctrl_mode)
481 * Change the DFLL's operating mode between disabled, open-loop mode,
482 * and closed-loop mode, or vice versa.
484 static void dfll_set_mode(struct tegra_dfll *td,
485 enum dfll_ctrl_mode mode)
487 td->mode = mode;
488 dfll_writel(td, mode - 1, DFLL_CTRL);
489 dfll_wmb(td);
493 * DFLL-to-I2C controller interface
497 * dfll_i2c_set_output_enabled - enable/disable I2C PMIC voltage requests
498 * @td: DFLL instance
499 * @enable: whether to enable or disable the I2C voltage requests
501 * Set the master enable control for I2C control value updates. If disabled,
502 * then I2C control messages are inhibited, regardless of the DFLL mode.
504 static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable)
506 u32 val;
508 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG);
510 if (enable)
511 val |= DFLL_OUTPUT_CFG_I2C_ENABLE;
512 else
513 val &= ~DFLL_OUTPUT_CFG_I2C_ENABLE;
515 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG);
516 dfll_i2c_wmb(td);
518 return 0;
522 * dfll_load_lut - load the voltage lookup table
523 * @td: struct tegra_dfll *
525 * Load the voltage-to-PMIC register value lookup table into the DFLL
526 * IP block memory. Look-up tables can be loaded at any time.
528 static void dfll_load_i2c_lut(struct tegra_dfll *td)
530 int i, lut_index;
531 u32 val;
533 for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
534 if (i < td->lut_min)
535 lut_index = td->lut_min;
536 else if (i > td->lut_max)
537 lut_index = td->lut_max;
538 else
539 lut_index = i;
541 val = regulator_list_hardware_vsel(td->vdd_reg,
542 td->i2c_lut[lut_index]);
543 __raw_writel(val, td->lut_base + i * 4);
546 dfll_i2c_wmb(td);
550 * dfll_init_i2c_if - set up the DFLL's DFLL-I2C interface
551 * @td: DFLL instance
553 * During DFLL driver initialization, program the DFLL-I2C interface
554 * with the PMU slave address, vdd register offset, and transfer mode.
555 * This data is used by the DFLL to automatically construct I2C
556 * voltage-set commands, which are then passed to the DFLL's internal
557 * I2C controller.
559 static void dfll_init_i2c_if(struct tegra_dfll *td)
561 u32 val;
563 if (td->i2c_slave_addr > 0x7f) {
564 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT;
565 val |= DFLL_I2C_CFG_SLAVE_ADDR_10;
566 } else {
567 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT;
569 val |= DFLL_I2C_CFG_SIZE_MASK;
570 val |= DFLL_I2C_CFG_ARB_ENABLE;
571 dfll_i2c_writel(td, val, DFLL_I2C_CFG);
573 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR);
575 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8);
576 BUG_ON(!val || (val > DFLL_I2C_CLK_DIVISOR_MASK));
577 val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT;
579 /* default hs divisor just in case */
580 val |= 1 << DFLL_I2C_CLK_DIVISOR_HS_SHIFT;
581 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR);
582 dfll_i2c_wmb(td);
586 * dfll_init_out_if - prepare DFLL-to-PMIC interface
587 * @td: DFLL instance
589 * During DFLL driver initialization or resume from context loss,
590 * disable the I2C command output to the PMIC, set safe voltage and
591 * output limits, and disable and clear limit interrupts.
593 static void dfll_init_out_if(struct tegra_dfll *td)
595 u32 val;
597 td->lut_min = 0;
598 td->lut_max = td->i2c_lut_size - 1;
599 td->lut_safe = td->lut_min + 1;
601 dfll_i2c_writel(td, 0, DFLL_OUTPUT_CFG);
602 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) |
603 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) |
604 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT);
605 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG);
606 dfll_i2c_wmb(td);
608 dfll_writel(td, 0, DFLL_OUTPUT_FORCE);
609 dfll_i2c_writel(td, 0, DFLL_INTR_EN);
610 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK,
611 DFLL_INTR_STS);
613 dfll_load_i2c_lut(td);
614 dfll_init_i2c_if(td);
618 * Set/get the DFLL's targeted output clock rate
622 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
623 * @td: DFLL instance
624 * @rate: clock rate
626 * Determines the index of a I2C LUT entry for a voltage that approximately
627 * produces the given DFLL clock rate. This is used when forcing a value
628 * to the integrator during rate changes. Returns -ENOENT if a suitable
629 * LUT index is not found.
631 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
633 struct dev_pm_opp *opp;
634 int i, uv;
636 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
637 if (IS_ERR(opp))
638 return PTR_ERR(opp);
640 uv = dev_pm_opp_get_voltage(opp);
641 dev_pm_opp_put(opp);
643 for (i = 0; i < td->i2c_lut_size; i++) {
644 if (regulator_list_voltage(td->vdd_reg, td->i2c_lut[i]) == uv)
645 return i;
648 return -ENOENT;
652 * dfll_calculate_rate_request - calculate DFLL parameters for a given rate
653 * @td: DFLL instance
654 * @req: DFLL-rate-request structure
655 * @rate: the desired DFLL rate
657 * Populate the DFLL-rate-request record @req fields with the scale_bits
658 * and mult_bits fields, based on the target input rate. Returns 0 upon
659 * success, or -EINVAL if the requested rate in req->rate is too high
660 * or low for the DFLL to generate.
662 static int dfll_calculate_rate_request(struct tegra_dfll *td,
663 struct dfll_rate_req *req,
664 unsigned long rate)
666 u32 val;
669 * If requested rate is below the minimum DVCO rate, active the scaler.
670 * In the future the DVCO minimum voltage should be selected based on
671 * chip temperature and the actual minimum rate should be calibrated
672 * at runtime.
674 req->scale_bits = DFLL_FREQ_REQ_SCALE_MAX - 1;
675 if (rate < td->dvco_rate_min) {
676 int scale;
678 scale = DIV_ROUND_CLOSEST(rate / 1000 * DFLL_FREQ_REQ_SCALE_MAX,
679 td->dvco_rate_min / 1000);
680 if (!scale) {
681 dev_err(td->dev, "%s: Rate %lu is too low\n",
682 __func__, rate);
683 return -EINVAL;
685 req->scale_bits = scale - 1;
686 rate = td->dvco_rate_min;
689 /* Convert requested rate into frequency request and scale settings */
690 val = DVCO_RATE_TO_MULT(rate, td->ref_rate);
691 if (val > FREQ_MAX) {
692 dev_err(td->dev, "%s: Rate %lu is above dfll range\n",
693 __func__, rate);
694 return -EINVAL;
696 req->mult_bits = val;
697 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate);
698 req->rate = dfll_scale_dvco_rate(req->scale_bits,
699 req->dvco_target_rate);
700 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate);
701 if (req->lut_index < 0)
702 return req->lut_index;
704 return 0;
708 * dfll_set_frequency_request - start the frequency change operation
709 * @td: DFLL instance
710 * @req: rate request structure
712 * Tell the DFLL to try to change its output frequency to the
713 * frequency represented by @req. DFLL must be in closed-loop mode.
715 static void dfll_set_frequency_request(struct tegra_dfll *td,
716 struct dfll_rate_req *req)
718 u32 val = 0;
719 int force_val;
720 int coef = 128; /* FIXME: td->cg_scale? */;
722 force_val = (req->lut_index - td->lut_safe) * coef / td->cg;
723 force_val = clamp(force_val, FORCE_MIN, FORCE_MAX);
725 val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT;
726 val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT;
727 val |= ((u32)force_val << DFLL_FREQ_REQ_FORCE_SHIFT) &
728 DFLL_FREQ_REQ_FORCE_MASK;
729 val |= DFLL_FREQ_REQ_FREQ_VALID | DFLL_FREQ_REQ_FORCE_ENABLE;
731 dfll_writel(td, val, DFLL_FREQ_REQ);
732 dfll_wmb(td);
736 * tegra_dfll_request_rate - set the next rate for the DFLL to tune to
737 * @td: DFLL instance
738 * @rate: clock rate to target
740 * Convert the requested clock rate @rate into the DFLL control logic
741 * settings. In closed-loop mode, update new settings immediately to
742 * adjust DFLL output rate accordingly. Otherwise, just save them
743 * until the next switch to closed loop. Returns 0 upon success,
744 * -EPERM if the DFLL driver has not yet been initialized, or -EINVAL
745 * if @rate is outside the DFLL's tunable range.
747 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate)
749 int ret;
750 struct dfll_rate_req req;
752 if (td->mode == DFLL_UNINITIALIZED) {
753 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n",
754 __func__, mode_name[td->mode]);
755 return -EPERM;
758 ret = dfll_calculate_rate_request(td, &req, rate);
759 if (ret)
760 return ret;
762 td->last_unrounded_rate = rate;
763 td->last_req = req;
765 if (td->mode == DFLL_CLOSED_LOOP)
766 dfll_set_frequency_request(td, &td->last_req);
768 return 0;
772 * DFLL enable/disable & open-loop <-> closed-loop transitions
776 * dfll_disable - switch from open-loop mode to disabled mode
777 * @td: DFLL instance
779 * Switch from OPEN_LOOP state to DISABLED state. Returns 0 upon success
780 * or -EPERM if the DFLL is not currently in open-loop mode.
782 static int dfll_disable(struct tegra_dfll *td)
784 if (td->mode != DFLL_OPEN_LOOP) {
785 dev_err(td->dev, "cannot disable DFLL in %s mode\n",
786 mode_name[td->mode]);
787 return -EINVAL;
790 dfll_set_mode(td, DFLL_DISABLED);
791 pm_runtime_put_sync(td->dev);
793 return 0;
797 * dfll_enable - switch a disabled DFLL to open-loop mode
798 * @td: DFLL instance
800 * Switch from DISABLED state to OPEN_LOOP state. Returns 0 upon success
801 * or -EPERM if the DFLL is not currently disabled.
803 static int dfll_enable(struct tegra_dfll *td)
805 if (td->mode != DFLL_DISABLED) {
806 dev_err(td->dev, "cannot enable DFLL in %s mode\n",
807 mode_name[td->mode]);
808 return -EPERM;
811 pm_runtime_get_sync(td->dev);
812 dfll_set_mode(td, DFLL_OPEN_LOOP);
814 return 0;
818 * dfll_set_open_loop_config - prepare to switch to open-loop mode
819 * @td: DFLL instance
821 * Prepare to switch the DFLL to open-loop mode. This switches the
822 * DFLL to the low-voltage tuning range, ensures that I2C output
823 * forcing is disabled, and disables the output clock rate scaler.
824 * The DFLL's low-voltage tuning range parameters must be
825 * characterized to keep the downstream device stable at any DVCO
826 * input voltage. No return value.
828 static void dfll_set_open_loop_config(struct tegra_dfll *td)
830 u32 val;
832 /* always tune low (safe) in open loop */
833 if (td->tune_range != DFLL_TUNE_LOW)
834 dfll_tune_low(td);
836 val = dfll_readl(td, DFLL_FREQ_REQ);
837 val |= DFLL_FREQ_REQ_SCALE_MASK;
838 val &= ~DFLL_FREQ_REQ_FORCE_ENABLE;
839 dfll_writel(td, val, DFLL_FREQ_REQ);
840 dfll_wmb(td);
844 * tegra_dfll_lock - switch from open-loop to closed-loop mode
845 * @td: DFLL instance
847 * Switch from OPEN_LOOP state to CLOSED_LOOP state. Returns 0 upon success,
848 * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the
849 * DFLL is not currently in open-loop mode.
851 static int dfll_lock(struct tegra_dfll *td)
853 struct dfll_rate_req *req = &td->last_req;
855 switch (td->mode) {
856 case DFLL_CLOSED_LOOP:
857 return 0;
859 case DFLL_OPEN_LOOP:
860 if (req->rate == 0) {
861 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n",
862 __func__);
863 return -EINVAL;
866 dfll_i2c_set_output_enabled(td, true);
867 dfll_set_mode(td, DFLL_CLOSED_LOOP);
868 dfll_set_frequency_request(td, req);
869 return 0;
871 default:
872 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
873 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n",
874 __func__, mode_name[td->mode]);
875 return -EPERM;
880 * tegra_dfll_unlock - switch from closed-loop to open-loop mode
881 * @td: DFLL instance
883 * Switch from CLOSED_LOOP state to OPEN_LOOP state. Returns 0 upon success,
884 * or -EPERM if the DFLL is not currently in open-loop mode.
886 static int dfll_unlock(struct tegra_dfll *td)
888 switch (td->mode) {
889 case DFLL_CLOSED_LOOP:
890 dfll_set_open_loop_config(td);
891 dfll_set_mode(td, DFLL_OPEN_LOOP);
892 dfll_i2c_set_output_enabled(td, false);
893 return 0;
895 case DFLL_OPEN_LOOP:
896 return 0;
898 default:
899 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
900 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n",
901 __func__, mode_name[td->mode]);
902 return -EPERM;
907 * Clock framework integration
909 * When the DFLL is being controlled by the CCF, always enter closed loop
910 * mode when the clk is enabled. This requires that a DFLL rate request
911 * has been set beforehand, which implies that a clk_set_rate() call is
912 * always required before a clk_enable().
915 static int dfll_clk_is_enabled(struct clk_hw *hw)
917 struct tegra_dfll *td = clk_hw_to_dfll(hw);
919 return dfll_is_running(td);
922 static int dfll_clk_enable(struct clk_hw *hw)
924 struct tegra_dfll *td = clk_hw_to_dfll(hw);
925 int ret;
927 ret = dfll_enable(td);
928 if (ret)
929 return ret;
931 ret = dfll_lock(td);
932 if (ret)
933 dfll_disable(td);
935 return ret;
938 static void dfll_clk_disable(struct clk_hw *hw)
940 struct tegra_dfll *td = clk_hw_to_dfll(hw);
941 int ret;
943 ret = dfll_unlock(td);
944 if (!ret)
945 dfll_disable(td);
948 static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw,
949 unsigned long parent_rate)
951 struct tegra_dfll *td = clk_hw_to_dfll(hw);
953 return td->last_unrounded_rate;
956 /* Must use determine_rate since it allows for rates exceeding 2^31-1 */
957 static int dfll_clk_determine_rate(struct clk_hw *hw,
958 struct clk_rate_request *clk_req)
960 struct tegra_dfll *td = clk_hw_to_dfll(hw);
961 struct dfll_rate_req req;
962 int ret;
964 ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
965 if (ret)
966 return ret;
969 * Don't set the rounded rate, since it doesn't really matter as
970 * the output rate will be voltage controlled anyway, and cpufreq
971 * freaks out if any rounding happens.
974 return 0;
977 static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
978 unsigned long parent_rate)
980 struct tegra_dfll *td = clk_hw_to_dfll(hw);
982 return dfll_request_rate(td, rate);
985 static const struct clk_ops dfll_clk_ops = {
986 .is_enabled = dfll_clk_is_enabled,
987 .enable = dfll_clk_enable,
988 .disable = dfll_clk_disable,
989 .recalc_rate = dfll_clk_recalc_rate,
990 .determine_rate = dfll_clk_determine_rate,
991 .set_rate = dfll_clk_set_rate,
994 static struct clk_init_data dfll_clk_init_data = {
995 .ops = &dfll_clk_ops,
996 .num_parents = 0,
1000 * dfll_register_clk - register the DFLL output clock with the clock framework
1001 * @td: DFLL instance
1003 * Register the DFLL's output clock with the Linux clock framework and register
1004 * the DFLL driver as an OF clock provider. Returns 0 upon success or -EINVAL
1005 * or -ENOMEM upon failure.
1007 static int dfll_register_clk(struct tegra_dfll *td)
1009 int ret;
1011 dfll_clk_init_data.name = td->output_clock_name;
1012 td->dfll_clk_hw.init = &dfll_clk_init_data;
1014 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw);
1015 if (IS_ERR(td->dfll_clk)) {
1016 dev_err(td->dev, "DFLL clock registration error\n");
1017 return -EINVAL;
1020 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get,
1021 td->dfll_clk);
1022 if (ret) {
1023 dev_err(td->dev, "of_clk_add_provider() failed\n");
1025 clk_unregister(td->dfll_clk);
1026 return ret;
1029 return 0;
1033 * dfll_unregister_clk - unregister the DFLL output clock
1034 * @td: DFLL instance
1036 * Unregister the DFLL's output clock from the Linux clock framework
1037 * and from clkdev. No return value.
1039 static void dfll_unregister_clk(struct tegra_dfll *td)
1041 of_clk_del_provider(td->dev->of_node);
1042 clk_unregister(td->dfll_clk);
1043 td->dfll_clk = NULL;
1047 * Debugfs interface
1050 #ifdef CONFIG_DEBUG_FS
1052 * Monitor control
1056 * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
1057 * @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
1058 * @ref_rate: DFLL reference clock rate
1060 * Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
1061 * per second. Returns the converted value.
1063 static u64 dfll_calc_monitored_rate(u32 monitor_data,
1064 unsigned long ref_rate)
1066 return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
1070 * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
1071 * @td: DFLL instance
1073 * If the DFLL is enabled, return the last rate reported by the DFLL's
1074 * internal monitoring hardware. This works in both open-loop and
1075 * closed-loop mode, and takes the output scaler setting into account.
1076 * Assumes that the monitor was programmed to monitor frequency before
1077 * the sample period started. If the driver believes that the DFLL is
1078 * currently uninitialized or disabled, it will return 0, since
1079 * otherwise the DFLL monitor data register will return the last
1080 * measured rate from when the DFLL was active.
1082 static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
1084 u32 v, s;
1085 u64 pre_scaler_rate, post_scaler_rate;
1087 if (!dfll_is_running(td))
1088 return 0;
1090 v = dfll_readl(td, DFLL_MONITOR_DATA);
1091 v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
1092 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
1094 s = dfll_readl(td, DFLL_FREQ_REQ);
1095 s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
1096 post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
1098 return post_scaler_rate;
1101 static int attr_enable_get(void *data, u64 *val)
1103 struct tegra_dfll *td = data;
1105 *val = dfll_is_running(td);
1107 return 0;
1109 static int attr_enable_set(void *data, u64 val)
1111 struct tegra_dfll *td = data;
1113 return val ? dfll_enable(td) : dfll_disable(td);
1115 DEFINE_SIMPLE_ATTRIBUTE(enable_fops, attr_enable_get, attr_enable_set,
1116 "%llu\n");
1118 static int attr_lock_get(void *data, u64 *val)
1120 struct tegra_dfll *td = data;
1122 *val = (td->mode == DFLL_CLOSED_LOOP);
1124 return 0;
1126 static int attr_lock_set(void *data, u64 val)
1128 struct tegra_dfll *td = data;
1130 return val ? dfll_lock(td) : dfll_unlock(td);
1132 DEFINE_SIMPLE_ATTRIBUTE(lock_fops, attr_lock_get, attr_lock_set,
1133 "%llu\n");
1135 static int attr_rate_get(void *data, u64 *val)
1137 struct tegra_dfll *td = data;
1139 *val = dfll_read_monitor_rate(td);
1141 return 0;
1144 static int attr_rate_set(void *data, u64 val)
1146 struct tegra_dfll *td = data;
1148 return dfll_request_rate(td, val);
1150 DEFINE_SIMPLE_ATTRIBUTE(rate_fops, attr_rate_get, attr_rate_set, "%llu\n");
1152 static int attr_registers_show(struct seq_file *s, void *data)
1154 u32 val, offs;
1155 struct tegra_dfll *td = s->private;
1157 seq_puts(s, "CONTROL REGISTERS:\n");
1158 for (offs = 0; offs <= DFLL_MONITOR_DATA; offs += 4) {
1159 if (offs == DFLL_OUTPUT_CFG)
1160 val = dfll_i2c_readl(td, offs);
1161 else
1162 val = dfll_readl(td, offs);
1163 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, val);
1166 seq_puts(s, "\nI2C and INTR REGISTERS:\n");
1167 for (offs = DFLL_I2C_CFG; offs <= DFLL_I2C_STS; offs += 4)
1168 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1169 dfll_i2c_readl(td, offs));
1170 for (offs = DFLL_INTR_STS; offs <= DFLL_INTR_EN; offs += 4)
1171 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1172 dfll_i2c_readl(td, offs));
1174 seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n");
1175 offs = DFLL_I2C_CLK_DIVISOR;
1176 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1177 __raw_readl(td->i2c_controller_base + offs));
1179 seq_puts(s, "\nLUT:\n");
1180 for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4)
1181 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1182 __raw_readl(td->lut_base + offs));
1184 return 0;
1187 static int attr_registers_open(struct inode *inode, struct file *file)
1189 return single_open(file, attr_registers_show, inode->i_private);
1192 static const struct file_operations attr_registers_fops = {
1193 .open = attr_registers_open,
1194 .read = seq_read,
1195 .llseek = seq_lseek,
1196 .release = single_release,
1199 static void dfll_debug_init(struct tegra_dfll *td)
1201 struct dentry *root;
1203 if (!td || (td->mode == DFLL_UNINITIALIZED))
1204 return;
1206 root = debugfs_create_dir("tegra_dfll_fcpu", NULL);
1207 td->debugfs_dir = root;
1209 debugfs_create_file("enable", S_IRUGO | S_IWUSR, root, td, &enable_fops);
1210 debugfs_create_file("lock", S_IRUGO, root, td, &lock_fops);
1211 debugfs_create_file("rate", S_IRUGO, root, td, &rate_fops);
1212 debugfs_create_file("registers", S_IRUGO, root, td, &attr_registers_fops);
1215 #else
1216 static void inline dfll_debug_init(struct tegra_dfll *td) { }
1217 #endif /* CONFIG_DEBUG_FS */
1220 * DFLL initialization
1224 * dfll_set_default_params - program non-output related DFLL parameters
1225 * @td: DFLL instance
1227 * During DFLL driver initialization or resume from context loss,
1228 * program parameters for the closed loop integrator, DVCO tuning,
1229 * voltage droop control and monitor control.
1231 static void dfll_set_default_params(struct tegra_dfll *td)
1233 u32 val;
1235 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32);
1236 BUG_ON(val > DFLL_CONFIG_DIV_MASK);
1237 dfll_writel(td, val, DFLL_CONFIG);
1239 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) |
1240 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) |
1241 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) |
1242 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) |
1243 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0);
1244 dfll_writel(td, val, DFLL_PARAMS);
1246 dfll_tune_low(td);
1247 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL);
1248 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL);
1252 * dfll_init_clks - clk_get() the DFLL source clocks
1253 * @td: DFLL instance
1255 * Call clk_get() on the DFLL source clocks and save the pointers for later
1256 * use. Returns 0 upon success or error (see devm_clk_get) if one or more
1257 * of the clocks couldn't be looked up.
1259 static int dfll_init_clks(struct tegra_dfll *td)
1261 td->ref_clk = devm_clk_get(td->dev, "ref");
1262 if (IS_ERR(td->ref_clk)) {
1263 dev_err(td->dev, "missing ref clock\n");
1264 return PTR_ERR(td->ref_clk);
1267 td->soc_clk = devm_clk_get(td->dev, "soc");
1268 if (IS_ERR(td->soc_clk)) {
1269 dev_err(td->dev, "missing soc clock\n");
1270 return PTR_ERR(td->soc_clk);
1273 td->i2c_clk = devm_clk_get(td->dev, "i2c");
1274 if (IS_ERR(td->i2c_clk)) {
1275 dev_err(td->dev, "missing i2c clock\n");
1276 return PTR_ERR(td->i2c_clk);
1278 td->i2c_clk_rate = clk_get_rate(td->i2c_clk);
1280 return 0;
1284 * dfll_init - Prepare the DFLL IP block for use
1285 * @td: DFLL instance
1287 * Do everything necessary to prepare the DFLL IP block for use. The
1288 * DFLL will be left in DISABLED state. Called by dfll_probe().
1289 * Returns 0 upon success, or passes along the error from whatever
1290 * function returned it.
1292 static int dfll_init(struct tegra_dfll *td)
1294 int ret;
1296 td->ref_rate = clk_get_rate(td->ref_clk);
1297 if (td->ref_rate != REF_CLOCK_RATE) {
1298 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu",
1299 td->ref_rate, REF_CLOCK_RATE);
1300 return -EINVAL;
1303 reset_control_deassert(td->dvco_rst);
1305 ret = clk_prepare(td->ref_clk);
1306 if (ret) {
1307 dev_err(td->dev, "failed to prepare ref_clk\n");
1308 return ret;
1311 ret = clk_prepare(td->soc_clk);
1312 if (ret) {
1313 dev_err(td->dev, "failed to prepare soc_clk\n");
1314 goto di_err1;
1317 ret = clk_prepare(td->i2c_clk);
1318 if (ret) {
1319 dev_err(td->dev, "failed to prepare i2c_clk\n");
1320 goto di_err2;
1323 td->last_unrounded_rate = 0;
1325 pm_runtime_enable(td->dev);
1326 pm_runtime_get_sync(td->dev);
1328 dfll_set_mode(td, DFLL_DISABLED);
1329 dfll_set_default_params(td);
1331 if (td->soc->init_clock_trimmers)
1332 td->soc->init_clock_trimmers();
1334 dfll_set_open_loop_config(td);
1336 dfll_init_out_if(td);
1338 pm_runtime_put_sync(td->dev);
1340 return 0;
1342 di_err2:
1343 clk_unprepare(td->soc_clk);
1344 di_err1:
1345 clk_unprepare(td->ref_clk);
1347 reset_control_assert(td->dvco_rst);
1349 return ret;
1353 * DT data fetch
1357 * Find a PMIC voltage register-to-voltage mapping for the given voltage.
1358 * An exact voltage match is required.
1360 static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
1362 int i, n_voltages, reg_uV;
1364 n_voltages = regulator_count_voltages(td->vdd_reg);
1365 for (i = 0; i < n_voltages; i++) {
1366 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1367 if (reg_uV < 0)
1368 break;
1370 if (uV == reg_uV)
1371 return i;
1374 dev_err(td->dev, "no voltage map entry for %d uV\n", uV);
1375 return -EINVAL;
1379 * Find a PMIC voltage register-to-voltage mapping for the given voltage,
1380 * rounding up to the closest supported voltage.
1381 * */
1382 static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
1384 int i, n_voltages, reg_uV;
1386 n_voltages = regulator_count_voltages(td->vdd_reg);
1387 for (i = 0; i < n_voltages; i++) {
1388 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1389 if (reg_uV < 0)
1390 break;
1392 if (uV <= reg_uV)
1393 return i;
1396 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV);
1397 return -EINVAL;
1401 * dfll_build_i2c_lut - build the I2C voltage register lookup table
1402 * @td: DFLL instance
1404 * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with
1405 * PMIC voltage register values that span the entire DFLL operating range.
1406 * This function builds the look-up table based on the OPP table provided by
1407 * the soc-specific platform driver (td->soc->opp_dev) and the PMIC
1408 * register-to-voltage mapping queried from the regulator framework.
1410 * On success, fills in td->i2c_lut and returns 0, or -err on failure.
1412 static int dfll_build_i2c_lut(struct tegra_dfll *td)
1414 int ret = -EINVAL;
1415 int j, v, v_max, v_opp;
1416 int selector;
1417 unsigned long rate;
1418 struct dev_pm_opp *opp;
1419 int lut;
1421 rate = ULONG_MAX;
1422 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
1423 if (IS_ERR(opp)) {
1424 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
1425 goto out;
1427 v_max = dev_pm_opp_get_voltage(opp);
1428 dev_pm_opp_put(opp);
1430 v = td->soc->cvb->min_millivolts * 1000;
1431 lut = find_vdd_map_entry_exact(td, v);
1432 if (lut < 0)
1433 goto out;
1434 td->i2c_lut[0] = lut;
1436 for (j = 1, rate = 0; ; rate++) {
1437 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
1438 if (IS_ERR(opp))
1439 break;
1440 v_opp = dev_pm_opp_get_voltage(opp);
1442 if (v_opp <= td->soc->cvb->min_millivolts * 1000)
1443 td->dvco_rate_min = dev_pm_opp_get_freq(opp);
1445 dev_pm_opp_put(opp);
1447 for (;;) {
1448 v += max(1, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
1449 if (v >= v_opp)
1450 break;
1452 selector = find_vdd_map_entry_min(td, v);
1453 if (selector < 0)
1454 goto out;
1455 if (selector != td->i2c_lut[j - 1])
1456 td->i2c_lut[j++] = selector;
1459 v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp;
1460 selector = find_vdd_map_entry_exact(td, v);
1461 if (selector < 0)
1462 goto out;
1463 if (selector != td->i2c_lut[j - 1])
1464 td->i2c_lut[j++] = selector;
1466 if (v >= v_max)
1467 break;
1469 td->i2c_lut_size = j;
1471 if (!td->dvco_rate_min)
1472 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
1473 td->soc->cvb->min_millivolts);
1474 else
1475 ret = 0;
1477 out:
1478 return ret;
1482 * read_dt_param - helper function for reading required parameters from the DT
1483 * @td: DFLL instance
1484 * @param: DT property name
1485 * @dest: output pointer for the value read
1487 * Read a required numeric parameter from the DFLL device node, or complain
1488 * if the property doesn't exist. Returns a boolean indicating success for
1489 * easy chaining of multiple calls to this function.
1491 static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest)
1493 int err = of_property_read_u32(td->dev->of_node, param, dest);
1495 if (err < 0) {
1496 dev_err(td->dev, "failed to read DT parameter %s: %d\n",
1497 param, err);
1498 return false;
1501 return true;
1505 * dfll_fetch_i2c_params - query PMIC I2C params from DT & regulator subsystem
1506 * @td: DFLL instance
1508 * Read all the parameters required for operation in I2C mode. The parameters
1509 * can originate from the device tree or the regulator subsystem.
1510 * Returns 0 on success or -err on failure.
1512 static int dfll_fetch_i2c_params(struct tegra_dfll *td)
1514 struct regmap *regmap;
1515 struct device *i2c_dev;
1516 struct i2c_client *i2c_client;
1517 int vsel_reg, vsel_mask;
1518 int ret;
1520 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate))
1521 return -EINVAL;
1523 regmap = regulator_get_regmap(td->vdd_reg);
1524 i2c_dev = regmap_get_device(regmap);
1525 i2c_client = to_i2c_client(i2c_dev);
1527 td->i2c_slave_addr = i2c_client->addr;
1529 ret = regulator_get_hardware_vsel_register(td->vdd_reg,
1530 &vsel_reg,
1531 &vsel_mask);
1532 if (ret < 0) {
1533 dev_err(td->dev,
1534 "regulator unsuitable for DFLL I2C operation\n");
1535 return -EINVAL;
1537 td->i2c_reg = vsel_reg;
1539 ret = dfll_build_i2c_lut(td);
1540 if (ret) {
1541 dev_err(td->dev, "couldn't build I2C LUT\n");
1542 return ret;
1545 return 0;
1549 * dfll_fetch_common_params - read DFLL parameters from the device tree
1550 * @td: DFLL instance
1552 * Read all the DT parameters that are common to both I2C and PWM operation.
1553 * Returns 0 on success or -EINVAL on any failure.
1555 static int dfll_fetch_common_params(struct tegra_dfll *td)
1557 bool ok = true;
1559 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl);
1560 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate);
1561 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode);
1562 ok &= read_dt_param(td, "nvidia,cf", &td->cf);
1563 ok &= read_dt_param(td, "nvidia,ci", &td->ci);
1564 ok &= read_dt_param(td, "nvidia,cg", &td->cg);
1565 td->cg_scale = of_property_read_bool(td->dev->of_node,
1566 "nvidia,cg-scale");
1568 if (of_property_read_string(td->dev->of_node, "clock-output-names",
1569 &td->output_clock_name)) {
1570 dev_err(td->dev, "missing clock-output-names property\n");
1571 ok = false;
1574 return ok ? 0 : -EINVAL;
1578 * API exported to per-SoC platform drivers
1582 * tegra_dfll_register - probe a Tegra DFLL device
1583 * @pdev: DFLL platform_device *
1584 * @soc: Per-SoC integration and characterization data for this DFLL instance
1586 * Probe and initialize a DFLL device instance. Intended to be called
1587 * by a SoC-specific shim driver that passes in per-SoC integration
1588 * and configuration data via @soc. Returns 0 on success or -err on failure.
1590 int tegra_dfll_register(struct platform_device *pdev,
1591 struct tegra_dfll_soc_data *soc)
1593 struct resource *mem;
1594 struct tegra_dfll *td;
1595 int ret;
1597 if (!soc) {
1598 dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n");
1599 return -EINVAL;
1602 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL);
1603 if (!td)
1604 return -ENOMEM;
1605 td->dev = &pdev->dev;
1606 platform_set_drvdata(pdev, td);
1608 td->soc = soc;
1610 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu");
1611 if (IS_ERR(td->vdd_reg)) {
1612 dev_err(td->dev, "couldn't get vdd_cpu regulator\n");
1613 return PTR_ERR(td->vdd_reg);
1616 td->dvco_rst = devm_reset_control_get(td->dev, "dvco");
1617 if (IS_ERR(td->dvco_rst)) {
1618 dev_err(td->dev, "couldn't get dvco reset\n");
1619 return PTR_ERR(td->dvco_rst);
1622 ret = dfll_fetch_common_params(td);
1623 if (ret) {
1624 dev_err(td->dev, "couldn't parse device tree parameters\n");
1625 return ret;
1628 ret = dfll_fetch_i2c_params(td);
1629 if (ret)
1630 return ret;
1632 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1633 if (!mem) {
1634 dev_err(td->dev, "no control register resource\n");
1635 return -ENODEV;
1638 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem));
1639 if (!td->base) {
1640 dev_err(td->dev, "couldn't ioremap DFLL control registers\n");
1641 return -ENODEV;
1644 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1645 if (!mem) {
1646 dev_err(td->dev, "no i2c_base resource\n");
1647 return -ENODEV;
1650 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
1651 if (!td->i2c_base) {
1652 dev_err(td->dev, "couldn't ioremap i2c_base resource\n");
1653 return -ENODEV;
1656 mem = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1657 if (!mem) {
1658 dev_err(td->dev, "no i2c_controller_base resource\n");
1659 return -ENODEV;
1662 td->i2c_controller_base = devm_ioremap(td->dev, mem->start,
1663 resource_size(mem));
1664 if (!td->i2c_controller_base) {
1665 dev_err(td->dev,
1666 "couldn't ioremap i2c_controller_base resource\n");
1667 return -ENODEV;
1670 mem = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1671 if (!mem) {
1672 dev_err(td->dev, "no lut_base resource\n");
1673 return -ENODEV;
1676 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
1677 if (!td->lut_base) {
1678 dev_err(td->dev,
1679 "couldn't ioremap lut_base resource\n");
1680 return -ENODEV;
1683 ret = dfll_init_clks(td);
1684 if (ret) {
1685 dev_err(&pdev->dev, "DFLL clock init error\n");
1686 return ret;
1689 /* Enable the clocks and set the device up */
1690 ret = dfll_init(td);
1691 if (ret)
1692 return ret;
1694 ret = dfll_register_clk(td);
1695 if (ret) {
1696 dev_err(&pdev->dev, "DFLL clk registration failed\n");
1697 return ret;
1700 dfll_debug_init(td);
1702 return 0;
1704 EXPORT_SYMBOL(tegra_dfll_register);
1707 * tegra_dfll_unregister - release all of the DFLL driver resources for a device
1708 * @pdev: DFLL platform_device *
1710 * Unbind this driver from the DFLL hardware device represented by
1711 * @pdev. The DFLL must be disabled for this to succeed. Returns a
1712 * soc pointer upon success or -EBUSY if the DFLL is still active.
1714 struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev)
1716 struct tegra_dfll *td = platform_get_drvdata(pdev);
1718 /* Try to prevent removal while the DFLL is active */
1719 if (td->mode != DFLL_DISABLED) {
1720 dev_err(&pdev->dev,
1721 "must disable DFLL before removing driver\n");
1722 return ERR_PTR(-EBUSY);
1725 debugfs_remove_recursive(td->debugfs_dir);
1727 dfll_unregister_clk(td);
1728 pm_runtime_disable(&pdev->dev);
1730 clk_unprepare(td->ref_clk);
1731 clk_unprepare(td->soc_clk);
1732 clk_unprepare(td->i2c_clk);
1734 reset_control_assert(td->dvco_rst);
1736 return td->soc;
1738 EXPORT_SYMBOL(tegra_dfll_unregister);