drivers/clk/uniphier/clk-uniphier-sys.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/stddef.h>
  17
  18 #include "clk-uniphier.h"
  19
  20 #define UNIPHIER_LD4_SYS_CLK_SD                                 \
  21         UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8),               \
  22         UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
  23
  24 #define UNIPHIER_PRO5_SYS_CLK_SD                                        \
  25         UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12),              \
  26         UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
  27
  28 #define UNIPHIER_LD20_SYS_CLK_SD                                        \
  29         UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10),              \
  30         UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
  31
  32 /* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
  33 #define UNIPHIER_LD4_SYS_CLK_NAND(idx)                                  \
  34         UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8),             \
  35         UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
  36
  37 #define UNIPHIER_PRO5_SYS_CLK_NAND(idx)                                 \
  38         UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 12),            \
  39         UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
  40
  41 #define UNIPHIER_LD11_SYS_CLK_NAND(idx)                                 \
  42         UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 10),            \
  43         UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x210c, 0)
  44
  45 #define UNIPHIER_LD11_SYS_CLK_EMMC(idx)                                 \
  46         UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
  47
  48 #define UNIPHIER_LD4_SYS_CLK_STDMAC(idx)                                \
  49         UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
  50
  51 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx)                               \
  52         UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
  53
  54 #define UNIPHIER_LD11_SYS_CLK_HSC(idx)                                  \
  55         UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
  56
  57 #define UNIPHIER_PRO4_SYS_CLK_GIO(idx)                                  \
  58         UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
  59
  60 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch)                             \
  61         UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
  62
  63 #define UNIPHIER_PRO4_SYS_CLK_AIO(idx)                                  \
  64         UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8),            \
  65         UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
  66
  67 #define UNIPHIER_PRO5_SYS_CLK_AIO(idx)                                  \
  68         UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12),           \
  69         UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
  70
  71 #define UNIPHIER_LD11_SYS_CLK_AIO(idx)                                  \
  72         UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10),           \
  73         UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
  74
  75 #define UNIPHIER_LD11_SYS_CLK_EVEA(idx)                                 \
  76         UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20),          \
  77         UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
  78
  79 #define UNIPHIER_LD11_SYS_CLK_EXIV(idx)                                 \
  80         UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10),          \
  81         UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
  82
  83 #define UNIPHIER_PRO4_SYS_CLK_ETHER(idx)                                \
  84         UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
  85
  86 #define UNIPHIER_LD11_SYS_CLK_ETHER(idx)                                \
  87         UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
  88
  89 const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
  90         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1),          /* 1597.44 MHz */
  91         UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512),      /* 288 MHz */
  92         UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1),         /* 589.824 MHz */
  93         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512),   /* 270 MHz */
  94         UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
  95         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
  96         UNIPHIER_LD4_SYS_CLK_NAND(2),
  97         UNIPHIER_LD4_SYS_CLK_SD,
  98         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
  99         UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* Ether, HSC, MIO */
 100         { /* sentinel */ }
 101 };
 102
 103 const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
 104         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1),          /* 1600 MHz */
 105         UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25),        /* 288 MHz */
 106         UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125),     /* 589.824 MHz */
 107         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
 108         UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1),          /* 250 MHz */
 109         UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
 110         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
 111         UNIPHIER_LD4_SYS_CLK_NAND(2),
 112         UNIPHIER_LD4_SYS_CLK_SD,
 113         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
 114         UNIPHIER_PRO4_SYS_CLK_ETHER(6),
 115         UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
 116         UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* HSC, MIO, RLE */
 117         UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
 118         UNIPHIER_PRO4_SYS_CLK_GIO(12),                  /* Ether, SATA, USB3 */
 119         UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
 120         UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
 121         UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
 122         UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
 123         UNIPHIER_PRO4_SYS_CLK_AIO(40),
 124         { /* sentinel */ }
 125 };
 126
 127 const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
 128         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1),          /* 1600 MHz */
 129         UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25),        /* 288 MHz */
 130         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
 131         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
 132         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
 133         UNIPHIER_LD4_SYS_CLK_NAND(2),
 134         UNIPHIER_LD4_SYS_CLK_SD,
 135         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
 136         UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* Ether, HSC, MIO */
 137         { /* sentinel */ }
 138 };
 139
 140 const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
 141         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1),         /* 2400 MHz */
 142         UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1),       /* 2560 MHz */
 143         UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125),  /* 2949.12 MHz */
 144         UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
 145         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
 146         UNIPHIER_PRO5_SYS_CLK_NAND(2),
 147         UNIPHIER_PRO5_SYS_CLK_SD,
 148         UNIPHIER_LD4_SYS_CLK_STDMAC(8),                         /* HSC */
 149         UNIPHIER_PRO4_SYS_CLK_GIO(12),                          /* PCIe, USB3 */
 150         UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
 151         UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
 152         UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),
 153         UNIPHIER_PRO5_SYS_CLK_AIO(40),
 154         { /* sentinel */ }
 155 };
 156
 157 const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
 158         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1),          /* 2400 MHz */
 159         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
 160         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
 161         UNIPHIER_PRO5_SYS_CLK_NAND(2),
 162         UNIPHIER_PRO5_SYS_CLK_SD,
 163         UNIPHIER_PRO4_SYS_CLK_ETHER(6),
 164         UNIPHIER_LD4_SYS_CLK_STDMAC(8),                         /* HSC, RLE */
 165         /* GIO is always clock-enabled: no function for 0x2104 bit6 */
 166         UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
 167         UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
 168         /* The document mentions 0x2104 bit 18, but not functional */
 169         UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
 170         UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
 171         UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
 172         UNIPHIER_PRO5_SYS_CLK_AIO(40),
 173         { /* sentinel */ }
 174 };
 175
 176 const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
 177         UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5),         /* 1960 MHz */
 178         UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1),          /* 1600 MHz */
 179         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),          /* 2000 MHz */
 180         UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1),         /* 2000 MHz */
 181         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
 182         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
 183         UNIPHIER_LD11_SYS_CLK_NAND(2),
 184         UNIPHIER_LD11_SYS_CLK_EMMC(4),
 185         /* Index 5 reserved for eMMC PHY */
 186         UNIPHIER_LD11_SYS_CLK_ETHER(6),
 187         UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC, MIO */
 188         UNIPHIER_LD11_SYS_CLK_HSC(9),
 189         UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
 190         UNIPHIER_LD11_SYS_CLK_AIO(40),
 191         UNIPHIER_LD11_SYS_CLK_EVEA(41),
 192         UNIPHIER_LD11_SYS_CLK_EXIV(42),
 193         /* CPU gears */
 194         UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 195         UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
 196         UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
 197         /* Note: both gear1 and gear4 are spll/4.  This is not a bug. */
 198         UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
 199                              "cpll/2", "spll/4", "cpll/3", "spll/3",
 200                              "spll/4", "spll/8", "cpll/4", "cpll/8"),
 201         UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
 202                              "mpll/2", "spll/4", "mpll/3", "spll/3",
 203                              "spll/4", "spll/8", "mpll/4", "mpll/8"),
 204         { /* sentinel */ }
 205 };
 206
 207 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 208         UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1),          /* ARM: 2200 MHz */
 209         UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1),         /* Mali: 1300 MHz */
 210         UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1),          /* Codec: 1600 MHz */
 211         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),          /* 2000 MHz */
 212         UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),         /* IPP: 2200 MHz */
 213         UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5),        /* 2520 MHz */
 214         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
 215         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
 216         UNIPHIER_LD11_SYS_CLK_NAND(2),
 217         UNIPHIER_LD11_SYS_CLK_EMMC(4),
 218         /* Index 5 reserved for eMMC PHY */
 219         UNIPHIER_LD20_SYS_CLK_SD,
 220         UNIPHIER_LD11_SYS_CLK_ETHER(6),
 221         UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC */
 222         UNIPHIER_LD11_SYS_CLK_HSC(9),
 223         /* GIO is always clock-enabled: no function for 0x210c bit5 */
 224         /*
 225          * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
 226          * We do not use bit 15 here.
 227          */
 228         UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
 229         UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
 230         UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
 231         UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
 232         UNIPHIER_LD11_SYS_CLK_AIO(40),
 233         UNIPHIER_LD11_SYS_CLK_EVEA(41),
 234         UNIPHIER_LD11_SYS_CLK_EXIV(42),
 235         /* CPU gears */
 236         UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 237         UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
 238         UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
 239         UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
 240                              "cpll/2", "spll/2", "cpll/3", "spll/3",
 241                              "spll/4", "spll/8", "cpll/4", "cpll/8"),
 242         UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
 243                              "cpll/2", "spll/2", "cpll/3", "spll/3",
 244                              "spll/4", "spll/8", "cpll/4", "cpll/8"),
 245         UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
 246                              "s2pll/2", "spll/2", "s2pll/3", "spll/3",
 247                              "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
 248         { /* sentinel */ }
 249 };
 250
 251 const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
 252         UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1),         /* ARM: 2600 MHz */
 253         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),          /* 2000 MHz */
 254         UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),         /* IPP: 2400 MHz */
 255         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
 256         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
 257         UNIPHIER_LD20_SYS_CLK_SD,
 258         UNIPHIER_LD11_SYS_CLK_NAND(2),
 259         UNIPHIER_LD11_SYS_CLK_EMMC(4),
 260         UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
 261         UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
 262         UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4),        /* =GIO0 */
 263         UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5),      /* =GIO1 */
 264         UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6),      /* =GIO1-1 */
 265         UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 16),
 266         UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 18),
 267         UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20),
 268         UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
 269         UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
 270         UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
 271         UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
 272         UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
 273         UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
 274         /* CPU gears */
 275         UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 276         UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
 277         UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
 278         UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
 279                              "cpll/2", "spll/2", "cpll/3", "spll/3",
 280                              "spll/4", "spll/8", "cpll/4", "cpll/8"),
 281         UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
 282                              "s2pll/2", "spll/2", "s2pll/3", "spll/3",
 283                              "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
 284         { /* sentinel */ }
 285 };