2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/cpufreq.h>
16 #include <linux/cpu_cooling.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
23 #include <linux/slab.h>
24 #include <linux/smp.h>
28 * @pclk: the parent clock of cpu
29 * @table: frequency table
33 struct cpufreq_frequency_table
*table
;
34 struct thermal_cooling_device
*cdev
;
38 * Don't use cpufreq on this SoC -- used when the SoC would have otherwise
39 * matched a more generic compatible.
41 #define SOC_BLACKLIST 1
44 * struct soc_data - SoC specific data
51 static u32
get_bus_freq(void)
53 struct device_node
*soc
;
58 /* get platform freq by searching bus-frequency property */
59 soc
= of_find_node_by_type(NULL
, "soc");
61 ret
= of_property_read_u32(soc
, "bus-frequency", &sysfreq
);
67 /* get platform freq by its clock name */
68 pltclk
= clk_get(NULL
, "cg-pll0-div1");
70 pr_err("%s: can't get bus frequency %ld\n",
71 __func__
, PTR_ERR(pltclk
));
72 return PTR_ERR(pltclk
);
75 return clk_get_rate(pltclk
);
78 static struct clk
*cpu_to_clk(int cpu
)
80 struct device_node
*np
;
83 if (!cpu_present(cpu
))
86 np
= of_get_cpu_node(cpu
, NULL
);
90 clk
= of_clk_get(np
, 0);
95 /* traverse cpu nodes to get cpu mask of sharing clock wire */
96 static void set_affected_cpus(struct cpufreq_policy
*policy
)
98 struct cpumask
*dstp
= policy
->cpus
;
102 for_each_present_cpu(i
) {
105 pr_err("%s: no clock for cpu %d\n", __func__
, i
);
109 if (clk_is_match(policy
->clk
, clk
))
110 cpumask_set_cpu(i
, dstp
);
114 /* reduce the duplicated frequencies in frequency table */
115 static void freq_table_redup(struct cpufreq_frequency_table
*freq_table
,
120 for (i
= 1; i
< count
; i
++) {
121 for (j
= 0; j
< i
; j
++) {
122 if (freq_table
[j
].frequency
== CPUFREQ_ENTRY_INVALID
||
123 freq_table
[j
].frequency
!=
124 freq_table
[i
].frequency
)
127 freq_table
[i
].frequency
= CPUFREQ_ENTRY_INVALID
;
133 /* sort the frequencies in frequency table in descenting order */
134 static void freq_table_sort(struct cpufreq_frequency_table
*freq_table
,
138 unsigned int freq
, max_freq
;
139 struct cpufreq_frequency_table table
;
141 for (i
= 0; i
< count
- 1; i
++) {
142 max_freq
= freq_table
[i
].frequency
;
144 for (j
= i
+ 1; j
< count
; j
++) {
145 freq
= freq_table
[j
].frequency
;
146 if (freq
== CPUFREQ_ENTRY_INVALID
||
154 /* exchange the frequencies */
155 table
.driver_data
= freq_table
[i
].driver_data
;
156 table
.frequency
= freq_table
[i
].frequency
;
157 freq_table
[i
].driver_data
= freq_table
[ind
].driver_data
;
158 freq_table
[i
].frequency
= freq_table
[ind
].frequency
;
159 freq_table
[ind
].driver_data
= table
.driver_data
;
160 freq_table
[ind
].frequency
= table
.frequency
;
165 static int qoriq_cpufreq_cpu_init(struct cpufreq_policy
*policy
)
167 struct device_node
*np
;
171 const struct clk_hw
*hwclk
;
172 struct cpufreq_frequency_table
*table
;
173 struct cpu_data
*data
;
174 unsigned int cpu
= policy
->cpu
;
177 np
= of_get_cpu_node(cpu
, NULL
);
181 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
185 policy
->clk
= of_clk_get(np
, 0);
186 if (IS_ERR(policy
->clk
)) {
187 pr_err("%s: no clock information\n", __func__
);
191 hwclk
= __clk_get_hw(policy
->clk
);
192 count
= clk_hw_get_num_parents(hwclk
);
194 data
->pclk
= kcalloc(count
, sizeof(struct clk
*), GFP_KERNEL
);
198 table
= kcalloc(count
+ 1, sizeof(*table
), GFP_KERNEL
);
202 for (i
= 0; i
< count
; i
++) {
203 clk
= clk_hw_get_parent_by_index(hwclk
, i
)->clk
;
205 freq
= clk_get_rate(clk
);
206 table
[i
].frequency
= freq
/ 1000;
207 table
[i
].driver_data
= i
;
209 freq_table_redup(table
, count
);
210 freq_table_sort(table
, count
);
211 table
[i
].frequency
= CPUFREQ_TABLE_END
;
212 policy
->freq_table
= table
;
215 /* update ->cpus if we have cluster, no harm if not */
216 set_affected_cpus(policy
);
217 policy
->driver_data
= data
;
219 /* Minimum transition latency is 12 platform clocks */
220 u64temp
= 12ULL * NSEC_PER_SEC
;
221 do_div(u64temp
, get_bus_freq());
222 policy
->cpuinfo
.transition_latency
= u64temp
+ 1;
238 static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy
*policy
)
240 struct cpu_data
*data
= policy
->driver_data
;
242 cpufreq_cooling_unregister(data
->cdev
);
246 policy
->driver_data
= NULL
;
251 static int qoriq_cpufreq_target(struct cpufreq_policy
*policy
,
255 struct cpu_data
*data
= policy
->driver_data
;
257 parent
= data
->pclk
[data
->table
[index
].driver_data
];
258 return clk_set_parent(policy
->clk
, parent
);
262 static void qoriq_cpufreq_ready(struct cpufreq_policy
*policy
)
264 struct cpu_data
*cpud
= policy
->driver_data
;
266 cpud
->cdev
= of_cpufreq_cooling_register(policy
);
269 static struct cpufreq_driver qoriq_cpufreq_driver
= {
270 .name
= "qoriq_cpufreq",
271 .flags
= CPUFREQ_CONST_LOOPS
,
272 .init
= qoriq_cpufreq_cpu_init
,
273 .exit
= qoriq_cpufreq_cpu_exit
,
274 .verify
= cpufreq_generic_frequency_table_verify
,
275 .target_index
= qoriq_cpufreq_target
,
276 .get
= cpufreq_generic_get
,
277 .ready
= qoriq_cpufreq_ready
,
278 .attr
= cpufreq_generic_attr
,
281 static const struct soc_data blacklist
= {
282 .flags
= SOC_BLACKLIST
,
285 static const struct of_device_id node_matches
[] __initconst
= {
286 /* e6500 cannot use cpufreq due to erratum A-008083 */
287 { .compatible
= "fsl,b4420-clockgen", &blacklist
},
288 { .compatible
= "fsl,b4860-clockgen", &blacklist
},
289 { .compatible
= "fsl,t2080-clockgen", &blacklist
},
290 { .compatible
= "fsl,t4240-clockgen", &blacklist
},
292 { .compatible
= "fsl,ls1012a-clockgen", },
293 { .compatible
= "fsl,ls1021a-clockgen", },
294 { .compatible
= "fsl,ls1043a-clockgen", },
295 { .compatible
= "fsl,ls1046a-clockgen", },
296 { .compatible
= "fsl,ls1088a-clockgen", },
297 { .compatible
= "fsl,ls2080a-clockgen", },
298 { .compatible
= "fsl,p4080-clockgen", },
299 { .compatible
= "fsl,qoriq-clockgen-1.0", },
300 { .compatible
= "fsl,qoriq-clockgen-2.0", },
304 static int __init
qoriq_cpufreq_init(void)
307 struct device_node
*np
;
308 const struct of_device_id
*match
;
309 const struct soc_data
*data
;
311 np
= of_find_matching_node(NULL
, node_matches
);
315 match
= of_match_node(node_matches
, np
);
320 if (data
&& data
->flags
& SOC_BLACKLIST
)
323 ret
= cpufreq_register_driver(&qoriq_cpufreq_driver
);
325 pr_info("Freescale QorIQ CPU frequency scaling driver\n");
329 module_init(qoriq_cpufreq_init
);
331 static void __exit
qoriq_cpufreq_exit(void)
333 cpufreq_unregister_driver(&qoriq_cpufreq_driver
);
335 module_exit(qoriq_cpufreq_exit
);
337 MODULE_LICENSE("GPL");
338 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
339 MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");