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Linux 4.18.10
[linux/fpc-iii.git] / drivers / hwtracing / coresight / coresight-etm3x.c
blob15ed64d51a5b4f08da570950563da3fd33566499
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 *
5 * Description: CoreSight Program Flow Trace driver
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/moduleparam.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/err.h>
15 #include <linux/fs.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/smp.h>
19 #include <linux/sysfs.h>
20 #include <linux/stat.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/cpu.h>
23 #include <linux/of.h>
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
26 #include <linux/amba/bus.h>
27 #include <linux/seq_file.h>
28 #include <linux/uaccess.h>
29 #include <linux/clk.h>
30 #include <linux/perf_event.h>
31 #include <asm/sections.h>
32
33 #include "coresight-etm.h"
34 #include "coresight-etm-perf.h"
35
36 /*
37 * Not really modular but using module_param is the easiest way to
38 * remain consistent with existing use cases for now.
39 */
40 static int boot_enable;
41 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
42
43 /* The number of ETM/PTM currently registered */
44 static int etm_count;
45 static struct etm_drvdata *etmdrvdata[NR_CPUS];
46
47 static enum cpuhp_state hp_online;
48
49 /*
50 * Memory mapped writes to clear os lock are not supported on some processors
51 * and OS lock must be unlocked before any memory mapped access on such
52 * processors, otherwise memory mapped reads/writes will be invalid.
53 */
54 static void etm_os_unlock(struct etm_drvdata *drvdata)
55 {
56 /* Writing any value to ETMOSLAR unlocks the trace registers */
57 etm_writel(drvdata, 0x0, ETMOSLAR);
58 drvdata->os_unlock = true;
59 isb();
60 }
61
62 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
63 {
64 u32 etmcr;
65
66 /* Ensure pending cp14 accesses complete before setting pwrdwn */
67 mb();
68 isb();
69 etmcr = etm_readl(drvdata, ETMCR);
70 etmcr |= ETMCR_PWD_DWN;
71 etm_writel(drvdata, etmcr, ETMCR);
72 }
73
74 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
75 {
76 u32 etmcr;
77
78 etmcr = etm_readl(drvdata, ETMCR);
79 etmcr &= ~ETMCR_PWD_DWN;
80 etm_writel(drvdata, etmcr, ETMCR);
81 /* Ensure pwrup completes before subsequent cp14 accesses */
82 mb();
83 isb();
84 }
85
86 static void etm_set_pwrup(struct etm_drvdata *drvdata)
87 {
88 u32 etmpdcr;
89
90 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
91 etmpdcr |= ETMPDCR_PWD_UP;
92 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
93 /* Ensure pwrup completes before subsequent cp14 accesses */
94 mb();
95 isb();
96 }
97
98 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
99 {
100 u32 etmpdcr;
101
102 /* Ensure pending cp14 accesses complete before clearing pwrup */
103 mb();
104 isb();
105 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
106 etmpdcr &= ~ETMPDCR_PWD_UP;
107 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
108 }
109
110 /**
111 * coresight_timeout_etm - loop until a bit has changed to a specific state.
112 * @drvdata: etm's private data structure.
113 * @offset: address of a register, starting from @addr.
114 * @position: the position of the bit of interest.
115 * @value: the value the bit should have.
116 *
117 * Basically the same as @coresight_timeout except for the register access
118 * method where we have to account for CP14 configurations.
119
120 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
121 * TIMEOUT_US has elapsed, which ever happens first.
122 */
123
124 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
125 int position, int value)
126 {
127 int i;
128 u32 val;
129
130 for (i = TIMEOUT_US; i > 0; i--) {
131 val = etm_readl(drvdata, offset);
132 /* Waiting on the bit to go from 0 to 1 */
133 if (value) {
134 if (val & BIT(position))
135 return 0;
136 /* Waiting on the bit to go from 1 to 0 */
137 } else {
138 if (!(val & BIT(position)))
139 return 0;
140 }
141
142 /*
143 * Delay is arbitrary - the specification doesn't say how long
144 * we are expected to wait. Extra check required to make sure
145 * we don't wait needlessly on the last iteration.
146 */
147 if (i - 1)
148 udelay(1);
149 }
150
151 return -EAGAIN;
152 }
153
154
155 static void etm_set_prog(struct etm_drvdata *drvdata)
156 {
157 u32 etmcr;
158
159 etmcr = etm_readl(drvdata, ETMCR);
160 etmcr |= ETMCR_ETM_PRG;
161 etm_writel(drvdata, etmcr, ETMCR);
162 /*
163 * Recommended by spec for cp14 accesses to ensure etmcr write is
164 * complete before polling etmsr
165 */
166 isb();
167 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
168 dev_err(drvdata->dev,
169 "%s: timeout observed when probing at offset %#x\n",
170 __func__, ETMSR);
171 }
172 }
173
174 static void etm_clr_prog(struct etm_drvdata *drvdata)
175 {
176 u32 etmcr;
177
178 etmcr = etm_readl(drvdata, ETMCR);
179 etmcr &= ~ETMCR_ETM_PRG;
180 etm_writel(drvdata, etmcr, ETMCR);
181 /*
182 * Recommended by spec for cp14 accesses to ensure etmcr write is
183 * complete before polling etmsr
184 */
185 isb();
186 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
187 dev_err(drvdata->dev,
188 "%s: timeout observed when probing at offset %#x\n",
189 __func__, ETMSR);
190 }
191 }
192
193 void etm_set_default(struct etm_config *config)
194 {
195 int i;
196
197 if (WARN_ON_ONCE(!config))
198 return;
199
200 /*
201 * Taken verbatim from the TRM:
202 *
203 * To trace all memory:
204 * set bit [24] in register 0x009, the ETMTECR1, to 1
205 * set all other bits in register 0x009, the ETMTECR1, to 0
206 * set all bits in register 0x007, the ETMTECR2, to 0
207 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
208 */
209 config->enable_ctrl1 = BIT(24);
210 config->enable_ctrl2 = 0x0;
211 config->enable_event = ETM_HARD_WIRE_RES_A;
212
213 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
214 config->enable_event = ETM_HARD_WIRE_RES_A;
215
216 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
219 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
220 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
221 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
222 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
223
224 for (i = 0; i < ETM_MAX_CNTR; i++) {
225 config->cntr_rld_val[i] = 0x0;
226 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
227 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
228 config->cntr_val[i] = 0x0;
229 }
230
231 config->seq_curr_state = 0x0;
232 config->ctxid_idx = 0x0;
233 for (i = 0; i < ETM_MAX_CTXID_CMP; i++) {
234 config->ctxid_pid[i] = 0x0;
235 config->ctxid_vpid[i] = 0x0;
236 }
237
238 config->ctxid_mask = 0x0;
239 /* Setting default to 1024 as per TRM recommendation */
240 config->sync_freq = 0x400;
241 }
242
243 void etm_config_trace_mode(struct etm_config *config)
244 {
245 u32 flags, mode;
246
247 mode = config->mode;
248
249 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
250
251 /* excluding kernel AND user space doesn't make sense */
252 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
253 return;
254
255 /* nothing to do if neither flags are set */
256 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
257 return;
258
259 flags = (1 << 0 | /* instruction execute */
260 3 << 3 | /* ARM instruction */
261 0 << 5 | /* No data value comparison */
262 0 << 7 | /* No exact mach */
263 0 << 8); /* Ignore context ID */
264
265 /* No need to worry about single address comparators. */
266 config->enable_ctrl2 = 0x0;
267
268 /* Bit 0 is address range comparator 1 */
269 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
270
271 /*
272 * On ETMv3.5:
273 * ETMACTRn[13,11] == Non-secure state comparison control
274 * ETMACTRn[12,10] == Secure state comparison control
275 *
276 * b00 == Match in all modes in this state
277 * b01 == Do not match in any more in this state
278 * b10 == Match in all modes excepts user mode in this state
279 * b11 == Match only in user mode in this state
280 */
281
282 /* Tracing in secure mode is not supported at this time */
283 flags |= (0 << 12 | 1 << 10);
284
285 if (mode & ETM_MODE_EXCL_USER) {
286 /* exclude user, match all modes except user mode */
287 flags |= (1 << 13 | 0 << 11);
288 } else {
289 /* exclude kernel, match only in user mode */
290 flags |= (1 << 13 | 1 << 11);
291 }
292
293 /*
294 * The ETMEEVR register is already set to "hard wire A". As such
295 * all there is to do is setup an address comparator that spans
296 * the entire address range and configure the state and mode bits.
297 */
298 config->addr_val[0] = (u32) 0x0;
299 config->addr_val[1] = (u32) ~0x0;
300 config->addr_acctype[0] = flags;
301 config->addr_acctype[1] = flags;
302 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
303 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
304 }
305
306 #define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | \
307 ETMCR_TIMESTAMP_EN | \
308 ETMCR_RETURN_STACK)
309
310 static int etm_parse_event_config(struct etm_drvdata *drvdata,
311 struct perf_event *event)
312 {
313 struct etm_config *config = &drvdata->config;
314 struct perf_event_attr *attr = &event->attr;
315
316 if (!attr)
317 return -EINVAL;
318
319 /* Clear configuration from previous run */
320 memset(config, 0, sizeof(struct etm_config));
321
322 if (attr->exclude_kernel)
323 config->mode = ETM_MODE_EXCL_KERN;
324
325 if (attr->exclude_user)
326 config->mode = ETM_MODE_EXCL_USER;
327
328 /* Always start from the default config */
329 etm_set_default(config);
330
331 /*
332 * By default the tracers are configured to trace the whole address
333 * range. Narrow the field only if requested by user space.
334 */
335 if (config->mode)
336 etm_config_trace_mode(config);
337
338 /*
339 * At this time only cycle accurate, return stack and timestamp
340 * options are available.
341 */
342 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
343 return -EINVAL;
344
345 config->ctrl = attr->config;
346
347 /*
348 * Possible to have cores with PTM (supports ret stack) and ETM
349 * (never has ret stack) on the same SoC. So if we have a request
350 * for return stack that can't be honoured on this core then
351 * clear the bit - trace will still continue normally
352 */
353 if ((config->ctrl & ETMCR_RETURN_STACK) &&
354 !(drvdata->etmccer & ETMCCER_RETSTACK))
355 config->ctrl &= ~ETMCR_RETURN_STACK;
356
357 return 0;
358 }
359
360 static void etm_enable_hw(void *info)
361 {
362 int i;
363 u32 etmcr;
364 struct etm_drvdata *drvdata = info;
365 struct etm_config *config = &drvdata->config;
366
367 CS_UNLOCK(drvdata->base);
368
369 /* Turn engine on */
370 etm_clr_pwrdwn(drvdata);
371 /* Apply power to trace registers */
372 etm_set_pwrup(drvdata);
373 /* Make sure all registers are accessible */
374 etm_os_unlock(drvdata);
375
376 etm_set_prog(drvdata);
377
378 etmcr = etm_readl(drvdata, ETMCR);
379 /* Clear setting from a previous run if need be */
380 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
381 etmcr |= drvdata->port_size;
382 etmcr |= ETMCR_ETM_EN;
383 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
384 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
385 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
386 etm_writel(drvdata, config->enable_event, ETMTEEVR);
387 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
388 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
389 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
390 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
391 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
392 }
393 for (i = 0; i < drvdata->nr_cntr; i++) {
394 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
395 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
396 etm_writel(drvdata, config->cntr_rld_event[i],
397 ETMCNTRLDEVRn(i));
398 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
399 }
400 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
401 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
402 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
403 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
404 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
405 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
406 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
407 for (i = 0; i < drvdata->nr_ext_out; i++)
408 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
409 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
410 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
411 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
412 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
413 /* No external input selected */
414 etm_writel(drvdata, 0x0, ETMEXTINSELR);
415 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
416 /* No auxiliary control selected */
417 etm_writel(drvdata, 0x0, ETMAUXCR);
418 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
419 /* No VMID comparator value selected */
420 etm_writel(drvdata, 0x0, ETMVMIDCVR);
421
422 etm_clr_prog(drvdata);
423 CS_LOCK(drvdata->base);
424
425 dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
426 }
427
428 static int etm_cpu_id(struct coresight_device *csdev)
429 {
430 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
431
432 return drvdata->cpu;
433 }
434
435 int etm_get_trace_id(struct etm_drvdata *drvdata)
436 {
437 unsigned long flags;
438 int trace_id = -1;
439
440 if (!drvdata)
441 goto out;
442
443 if (!local_read(&drvdata->mode))
444 return drvdata->traceid;
445
446 pm_runtime_get_sync(drvdata->dev);
447
448 spin_lock_irqsave(&drvdata->spinlock, flags);
449
450 CS_UNLOCK(drvdata->base);
451 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
452 CS_LOCK(drvdata->base);
453
454 spin_unlock_irqrestore(&drvdata->spinlock, flags);
455 pm_runtime_put(drvdata->dev);
456
457 out:
458 return trace_id;
459
460 }
461
462 static int etm_trace_id(struct coresight_device *csdev)
463 {
464 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
465
466 return etm_get_trace_id(drvdata);
467 }
468
469 static int etm_enable_perf(struct coresight_device *csdev,
470 struct perf_event *event)
471 {
472 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
473
474 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
475 return -EINVAL;
476
477 /* Configure the tracer based on the session's specifics */
478 etm_parse_event_config(drvdata, event);
479 /* And enable it */
480 etm_enable_hw(drvdata);
481
482 return 0;
483 }
484
485 static int etm_enable_sysfs(struct coresight_device *csdev)
486 {
487 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
488 int ret;
489
490 spin_lock(&drvdata->spinlock);
491
492 /*
493 * Configure the ETM only if the CPU is online. If it isn't online
494 * hw configuration will take place on the local CPU during bring up.
495 */
496 if (cpu_online(drvdata->cpu)) {
497 ret = smp_call_function_single(drvdata->cpu,
498 etm_enable_hw, drvdata, 1);
499 if (ret)
500 goto err;
501 }
502
503 drvdata->sticky_enable = true;
504 spin_unlock(&drvdata->spinlock);
505
506 dev_info(drvdata->dev, "ETM tracing enabled\n");
507 return 0;
508
509 err:
510 spin_unlock(&drvdata->spinlock);
511 return ret;
512 }
513
514 static int etm_enable(struct coresight_device *csdev,
515 struct perf_event *event, u32 mode)
516 {
517 int ret;
518 u32 val;
519 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
520
521 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
522
523 /* Someone is already using the tracer */
524 if (val)
525 return -EBUSY;
526
527 switch (mode) {
528 case CS_MODE_SYSFS:
529 ret = etm_enable_sysfs(csdev);
530 break;
531 case CS_MODE_PERF:
532 ret = etm_enable_perf(csdev, event);
533 break;
534 default:
535 ret = -EINVAL;
536 }
537
538 /* The tracer didn't start */
539 if (ret)
540 local_set(&drvdata->mode, CS_MODE_DISABLED);
541
542 return ret;
543 }
544
545 static void etm_disable_hw(void *info)
546 {
547 int i;
548 struct etm_drvdata *drvdata = info;
549 struct etm_config *config = &drvdata->config;
550
551 CS_UNLOCK(drvdata->base);
552 etm_set_prog(drvdata);
553
554 /* Read back sequencer and counters for post trace analysis */
555 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
556
557 for (i = 0; i < drvdata->nr_cntr; i++)
558 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
559
560 etm_set_pwrdwn(drvdata);
561 CS_LOCK(drvdata->base);
562
563 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
564 }
565
566 static void etm_disable_perf(struct coresight_device *csdev)
567 {
568 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
569
570 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
571 return;
572
573 CS_UNLOCK(drvdata->base);
574
575 /* Setting the prog bit disables tracing immediately */
576 etm_set_prog(drvdata);
577
578 /*
579 * There is no way to know when the tracer will be used again so
580 * power down the tracer.
581 */
582 etm_set_pwrdwn(drvdata);
583
584 CS_LOCK(drvdata->base);
585 }
586
587 static void etm_disable_sysfs(struct coresight_device *csdev)
588 {
589 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
590
591 /*
592 * Taking hotplug lock here protects from clocks getting disabled
593 * with tracing being left on (crash scenario) if user disable occurs
594 * after cpu online mask indicates the cpu is offline but before the
595 * DYING hotplug callback is serviced by the ETM driver.
596 */
597 cpus_read_lock();
598 spin_lock(&drvdata->spinlock);
599
600 /*
601 * Executing etm_disable_hw on the cpu whose ETM is being disabled
602 * ensures that register writes occur when cpu is powered.
603 */
604 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
605
606 spin_unlock(&drvdata->spinlock);
607 cpus_read_unlock();
608
609 dev_info(drvdata->dev, "ETM tracing disabled\n");
610 }
611
612 static void etm_disable(struct coresight_device *csdev,
613 struct perf_event *event)
614 {
615 u32 mode;
616 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
617
618 /*
619 * For as long as the tracer isn't disabled another entity can't
620 * change its status. As such we can read the status here without
621 * fearing it will change under us.
622 */
623 mode = local_read(&drvdata->mode);
624
625 switch (mode) {
626 case CS_MODE_DISABLED:
627 break;
628 case CS_MODE_SYSFS:
629 etm_disable_sysfs(csdev);
630 break;
631 case CS_MODE_PERF:
632 etm_disable_perf(csdev);
633 break;
634 default:
635 WARN_ON_ONCE(mode);
636 return;
637 }
638
639 if (mode)
640 local_set(&drvdata->mode, CS_MODE_DISABLED);
641 }
642
643 static const struct coresight_ops_source etm_source_ops = {
644 .cpu_id = etm_cpu_id,
645 .trace_id = etm_trace_id,
646 .enable = etm_enable,
647 .disable = etm_disable,
648 };
649
650 static const struct coresight_ops etm_cs_ops = {
651 .source_ops = &etm_source_ops,
652 };
653
654 static int etm_online_cpu(unsigned int cpu)
655 {
656 if (!etmdrvdata[cpu])
657 return 0;
658
659 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
660 coresight_enable(etmdrvdata[cpu]->csdev);
661 return 0;
662 }
663
664 static int etm_starting_cpu(unsigned int cpu)
665 {
666 if (!etmdrvdata[cpu])
667 return 0;
668
669 spin_lock(&etmdrvdata[cpu]->spinlock);
670 if (!etmdrvdata[cpu]->os_unlock) {
671 etm_os_unlock(etmdrvdata[cpu]);
672 etmdrvdata[cpu]->os_unlock = true;
673 }
674
675 if (local_read(&etmdrvdata[cpu]->mode))
676 etm_enable_hw(etmdrvdata[cpu]);
677 spin_unlock(&etmdrvdata[cpu]->spinlock);
678 return 0;
679 }
680
681 static int etm_dying_cpu(unsigned int cpu)
682 {
683 if (!etmdrvdata[cpu])
684 return 0;
685
686 spin_lock(&etmdrvdata[cpu]->spinlock);
687 if (local_read(&etmdrvdata[cpu]->mode))
688 etm_disable_hw(etmdrvdata[cpu]);
689 spin_unlock(&etmdrvdata[cpu]->spinlock);
690 return 0;
691 }
692
693 static bool etm_arch_supported(u8 arch)
694 {
695 switch (arch) {
696 case ETM_ARCH_V3_3:
697 break;
698 case ETM_ARCH_V3_5:
699 break;
700 case PFT_ARCH_V1_0:
701 break;
702 case PFT_ARCH_V1_1:
703 break;
704 default:
705 return false;
706 }
707 return true;
708 }
709
710 static void etm_init_arch_data(void *info)
711 {
712 u32 etmidr;
713 u32 etmccr;
714 struct etm_drvdata *drvdata = info;
715
716 /* Make sure all registers are accessible */
717 etm_os_unlock(drvdata);
718
719 CS_UNLOCK(drvdata->base);
720
721 /* First dummy read */
722 (void)etm_readl(drvdata, ETMPDSR);
723 /* Provide power to ETM: ETMPDCR[3] == 1 */
724 etm_set_pwrup(drvdata);
725 /*
726 * Clear power down bit since when this bit is set writes to
727 * certain registers might be ignored.
728 */
729 etm_clr_pwrdwn(drvdata);
730 /*
731 * Set prog bit. It will be set from reset but this is included to
732 * ensure it is set
733 */
734 etm_set_prog(drvdata);
735
736 /* Find all capabilities */
737 etmidr = etm_readl(drvdata, ETMIDR);
738 drvdata->arch = BMVAL(etmidr, 4, 11);
739 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
740
741 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
742 etmccr = etm_readl(drvdata, ETMCCR);
743 drvdata->etmccr = etmccr;
744 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
745 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
746 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
747 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
748 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
749
750 etm_set_pwrdwn(drvdata);
751 etm_clr_pwrup(drvdata);
752 CS_LOCK(drvdata->base);
753 }
754
755 static void etm_init_trace_id(struct etm_drvdata *drvdata)
756 {
757 drvdata->traceid = coresight_get_trace_id(drvdata->cpu);
758 }
759
760 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
761 {
762 int ret;
763 void __iomem *base;
764 struct device *dev = &adev->dev;
765 struct coresight_platform_data *pdata = NULL;
766 struct etm_drvdata *drvdata;
767 struct resource *res = &adev->res;
768 struct coresight_desc desc = { 0 };
769 struct device_node *np = adev->dev.of_node;
770
771 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
772 if (!drvdata)
773 return -ENOMEM;
774
775 if (np) {
776 pdata = of_get_coresight_platform_data(dev, np);
777 if (IS_ERR(pdata))
778 return PTR_ERR(pdata);
779
780 adev->dev.platform_data = pdata;
781 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
782 }
783
784 drvdata->dev = &adev->dev;
785 dev_set_drvdata(dev, drvdata);
786
787 /* Validity for the resource is already checked by the AMBA core */
788 base = devm_ioremap_resource(dev, res);
789 if (IS_ERR(base))
790 return PTR_ERR(base);
791
792 drvdata->base = base;
793
794 spin_lock_init(&drvdata->spinlock);
795
796 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
797 if (!IS_ERR(drvdata->atclk)) {
798 ret = clk_prepare_enable(drvdata->atclk);
799 if (ret)
800 return ret;
801 }
802
803 drvdata->cpu = pdata ? pdata->cpu : 0;
804
805 cpus_read_lock();
806 etmdrvdata[drvdata->cpu] = drvdata;
807
808 if (smp_call_function_single(drvdata->cpu,
809 etm_init_arch_data, drvdata, 1))
810 dev_err(dev, "ETM arch init failed\n");
811
812 if (!etm_count++) {
813 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
814 "arm/coresight:starting",
815 etm_starting_cpu, etm_dying_cpu);
816 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
817 "arm/coresight:online",
818 etm_online_cpu, NULL);
819 if (ret < 0)
820 goto err_arch_supported;
821 hp_online = ret;
822 }
823 cpus_read_unlock();
824
825 if (etm_arch_supported(drvdata->arch) == false) {
826 ret = -EINVAL;
827 goto err_arch_supported;
828 }
829
830 etm_init_trace_id(drvdata);
831 etm_set_default(&drvdata->config);
832
833 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
834 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
835 desc.ops = &etm_cs_ops;
836 desc.pdata = pdata;
837 desc.dev = dev;
838 desc.groups = coresight_etm_groups;
839 drvdata->csdev = coresight_register(&desc);
840 if (IS_ERR(drvdata->csdev)) {
841 ret = PTR_ERR(drvdata->csdev);
842 goto err_arch_supported;
843 }
844
845 ret = etm_perf_symlink(drvdata->csdev, true);
846 if (ret) {
847 coresight_unregister(drvdata->csdev);
848 goto err_arch_supported;
849 }
850
851 pm_runtime_put(&adev->dev);
852 dev_info(dev, "%s initialized\n", (char *)id->data);
853 if (boot_enable) {
854 coresight_enable(drvdata->csdev);
855 drvdata->boot_enable = true;
856 }
857
858 return 0;
859
860 err_arch_supported:
861 if (--etm_count == 0) {
862 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
863 if (hp_online)
864 cpuhp_remove_state_nocalls(hp_online);
865 }
866 return ret;
867 }
868
869 #ifdef CONFIG_PM
870 static int etm_runtime_suspend(struct device *dev)
871 {
872 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
873
874 if (drvdata && !IS_ERR(drvdata->atclk))
875 clk_disable_unprepare(drvdata->atclk);
876
877 return 0;
878 }
879
880 static int etm_runtime_resume(struct device *dev)
881 {
882 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
883
884 if (drvdata && !IS_ERR(drvdata->atclk))
885 clk_prepare_enable(drvdata->atclk);
886
887 return 0;
888 }
889 #endif
890
891 static const struct dev_pm_ops etm_dev_pm_ops = {
892 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
893 };
894
895 static const struct amba_id etm_ids[] = {
896 { /* ETM 3.3 */
897 .id = 0x000bb921,
898 .mask = 0x000fffff,
899 .data = "ETM 3.3",
900 },
901 { /* ETM 3.5 - Cortex-A5 */
902 .id = 0x000bb955,
903 .mask = 0x000fffff,
904 .data = "ETM 3.5",
905 },
906 { /* ETM 3.5 */
907 .id = 0x000bb956,
908 .mask = 0x000fffff,
909 .data = "ETM 3.5",
910 },
911 { /* PTM 1.0 */
912 .id = 0x000bb950,
913 .mask = 0x000fffff,
914 .data = "PTM 1.0",
915 },
916 { /* PTM 1.1 */
917 .id = 0x000bb95f,
918 .mask = 0x000fffff,
919 .data = "PTM 1.1",
920 },
921 { /* PTM 1.1 Qualcomm */
922 .id = 0x000b006f,
923 .mask = 0x000fffff,
924 .data = "PTM 1.1",
925 },
926 { 0, 0},
927 };
928
929 static struct amba_driver etm_driver = {
930 .drv = {
931 .name = "coresight-etm3x",
932 .owner = THIS_MODULE,
933 .pm = &etm_dev_pm_ops,
934 .suppress_bind_attrs = true,
935 },
936 .probe = etm_probe,
937 .id_table = etm_ids,
938 };
939 builtin_amba_driver(etm_driver);
Linux with added FPC-III support