drivers/memory/fsl_ifc.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc
   3  *
   4  * Freescale Integrated Flash Controller
   5  *
   6  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/compiler.h>
  25 #include <linux/sched.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/io.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/fsl_ifc.h>
  34 #include <linux/irqdomain.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37
  38 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
  39 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
  40
  41 /*
  42  * convert_ifc_address - convert the base address
  43  * @addr_base:  base address of the memory bank
  44  */
  45 unsigned int convert_ifc_address(phys_addr_t addr_base)
  46 {
  47         return addr_base & CSPR_BA;
  48 }
  49 EXPORT_SYMBOL(convert_ifc_address);
  50
  51 /*
  52  * fsl_ifc_find - find IFC bank
  53  * @addr_base:  base address of the memory bank
  54  *
  55  * This function walks IFC banks comparing "Base address" field of the CSPR
  56  * registers with the supplied addr_base argument. When bases match this
  57  * function returns bank number (starting with 0), otherwise it returns
  58  * appropriate errno value.
  59  */
  60 int fsl_ifc_find(phys_addr_t addr_base)
  61 {
  62         int i = 0;
  63
  64         if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
  65                 return -ENODEV;
  66
  67         for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
  68                 u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
  69                 if (cspr & CSPR_V && (cspr & CSPR_BA) ==
  70                                 convert_ifc_address(addr_base))
  71                         return i;
  72         }
  73
  74         return -ENOENT;
  75 }
  76 EXPORT_SYMBOL(fsl_ifc_find);
  77
  78 static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
  79 {
  80         struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
  81
  82         /*
  83          * Clear all the common status and event registers
  84          */
  85         if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
  86                 ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
  87
  88         /* enable all error and events */
  89         ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
  90
  91         /* enable all error and event interrupts */
  92         ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
  93         ifc_out32(0x0, &ifc->cm_erattr0);
  94         ifc_out32(0x0, &ifc->cm_erattr1);
  95
  96         return 0;
  97 }
  98
  99 static int fsl_ifc_ctrl_remove(struct platform_device *dev)
 100 {
 101         struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
 102
 103         free_irq(ctrl->nand_irq, ctrl);
 104         free_irq(ctrl->irq, ctrl);
 105
 106         irq_dispose_mapping(ctrl->nand_irq);
 107         irq_dispose_mapping(ctrl->irq);
 108
 109         iounmap(ctrl->gregs);
 110
 111         dev_set_drvdata(&dev->dev, NULL);
 112         kfree(ctrl);
 113
 114         return 0;
 115 }
 116
 117 /*
 118  * NAND events are split between an operational interrupt which only
 119  * receives OPC, and an error interrupt that receives everything else,
 120  * including non-NAND errors.  Whichever interrupt gets to it first
 121  * records the status and wakes the wait queue.
 122  */
 123 static DEFINE_SPINLOCK(nand_irq_lock);
 124
 125 static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
 126 {
 127         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 128         unsigned long flags;
 129         u32 stat;
 130
 131         spin_lock_irqsave(&nand_irq_lock, flags);
 132
 133         stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 134         if (stat) {
 135                 ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
 136                 ctrl->nand_stat = stat;
 137                 wake_up(&ctrl->nand_wait);
 138         }
 139
 140         spin_unlock_irqrestore(&nand_irq_lock, flags);
 141
 142         return stat;
 143 }
 144
 145 static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
 146 {
 147         struct fsl_ifc_ctrl *ctrl = data;
 148
 149         if (check_nand_stat(ctrl))
 150                 return IRQ_HANDLED;
 151
 152         return IRQ_NONE;
 153 }
 154
 155 /*
 156  * NOTE: This interrupt is used to report ifc events of various kinds,
 157  * such as transaction errors on the chipselects.
 158  */
 159 static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
 160 {
 161         struct fsl_ifc_ctrl *ctrl = data;
 162         struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
 163         u32 err_axiid, err_srcid, status, cs_err, err_addr;
 164         irqreturn_t ret = IRQ_NONE;
 165
 166         /* read for chip select error */
 167         cs_err = ifc_in32(&ifc->cm_evter_stat);
 168         if (cs_err) {
 169                 dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
 170                                 "any memory bank 0x%08X\n", cs_err);
 171                 /* clear the chip select error */
 172                 ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
 173
 174                 /* read error attribute registers print the error information */
 175                 status = ifc_in32(&ifc->cm_erattr0);
 176                 err_addr = ifc_in32(&ifc->cm_erattr1);
 177
 178                 if (status & IFC_CM_ERATTR0_ERTYP_READ)
 179                         dev_err(ctrl->dev, "Read transaction error"
 180                                 "CM_ERATTR0 0x%08X\n", status);
 181                 else
 182                         dev_err(ctrl->dev, "Write transaction error"
 183                                 "CM_ERATTR0 0x%08X\n", status);
 184
 185                 err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
 186                                         IFC_CM_ERATTR0_ERAID_SHIFT;
 187                 dev_err(ctrl->dev, "AXI ID of the error"
 188                                         "transaction 0x%08X\n", err_axiid);
 189
 190                 err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
 191                                         IFC_CM_ERATTR0_ESRCID_SHIFT;
 192                 dev_err(ctrl->dev, "SRC ID of the error"
 193                                         "transaction 0x%08X\n", err_srcid);
 194
 195                 dev_err(ctrl->dev, "Transaction Address corresponding to error"
 196                                         "ERADDR 0x%08X\n", err_addr);
 197
 198                 ret = IRQ_HANDLED;
 199         }
 200
 201         if (check_nand_stat(ctrl))
 202                 ret = IRQ_HANDLED;
 203
 204         return ret;
 205 }
 206
 207 /*
 208  * fsl_ifc_ctrl_probe
 209  *
 210  * called by device layer when it finds a device matching
 211  * one our driver can handled. This code allocates all of
 212  * the resources needed for the controller only.  The
 213  * resources for the NAND banks themselves are allocated
 214  * in the chip probe function.
 215 */
 216 static int fsl_ifc_ctrl_probe(struct platform_device *dev)
 217 {
 218         int ret = 0;
 219         int version, banks;
 220         void __iomem *addr;
 221
 222         dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
 223
 224         fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
 225         if (!fsl_ifc_ctrl_dev)
 226                 return -ENOMEM;
 227
 228         dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
 229
 230         /* IOMAP the entire IFC region */
 231         fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
 232         if (!fsl_ifc_ctrl_dev->gregs) {
 233                 dev_err(&dev->dev, "failed to get memory region\n");
 234                 ret = -ENODEV;
 235                 goto err;
 236         }
 237
 238         if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
 239                 fsl_ifc_ctrl_dev->little_endian = true;
 240                 dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
 241         } else {
 242                 fsl_ifc_ctrl_dev->little_endian = false;
 243                 dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
 244         }
 245
 246         version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
 247                         FSL_IFC_VERSION_MASK;
 248
 249         banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
 250         dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
 251                 version >> 24, (version >> 16) & 0xf, banks);
 252
 253         fsl_ifc_ctrl_dev->version = version;
 254         fsl_ifc_ctrl_dev->banks = banks;
 255
 256         addr = fsl_ifc_ctrl_dev->gregs;
 257         if (version >= FSL_IFC_VERSION_2_0_0)
 258                 addr += PGOFFSET_64K;
 259         else
 260                 addr += PGOFFSET_4K;
 261         fsl_ifc_ctrl_dev->rregs = addr;
 262
 263         /* get the Controller level irq */
 264         fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
 265         if (fsl_ifc_ctrl_dev->irq == 0) {
 266                 dev_err(&dev->dev, "failed to get irq resource "
 267                                                         "for IFC\n");
 268                 ret = -ENODEV;
 269                 goto err;
 270         }
 271
 272         /* get the nand machine irq */
 273         fsl_ifc_ctrl_dev->nand_irq =
 274                         irq_of_parse_and_map(dev->dev.of_node, 1);
 275
 276         fsl_ifc_ctrl_dev->dev = &dev->dev;
 277
 278         ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
 279         if (ret < 0)
 280                 goto err;
 281
 282         init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
 283
 284         ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
 285                           "fsl-ifc", fsl_ifc_ctrl_dev);
 286         if (ret != 0) {
 287                 dev_err(&dev->dev, "failed to install irq (%d)\n",
 288                         fsl_ifc_ctrl_dev->irq);
 289                 goto err_irq;
 290         }
 291
 292         if (fsl_ifc_ctrl_dev->nand_irq) {
 293                 ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
 294                                 0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
 295                 if (ret != 0) {
 296                         dev_err(&dev->dev, "failed to install irq (%d)\n",
 297                                 fsl_ifc_ctrl_dev->nand_irq);
 298                         goto err_nandirq;
 299                 }
 300         }
 301
 302         return 0;
 303
 304 err_nandirq:
 305         free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
 306         irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
 307 err_irq:
 308         free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
 309         irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
 310 err:
 311         return ret;
 312 }
 313
 314 static const struct of_device_id fsl_ifc_match[] = {
 315         {
 316                 .compatible = "fsl,ifc",
 317         },
 318         {},
 319 };
 320
 321 static struct platform_driver fsl_ifc_ctrl_driver = {
 322         .driver = {
 323                 .name   = "fsl-ifc",
 324                 .of_match_table = fsl_ifc_match,
 325         },
 326         .probe       = fsl_ifc_ctrl_probe,
 327         .remove      = fsl_ifc_ctrl_remove,
 328 };
 329
 330 static int __init fsl_ifc_init(void)
 331 {
 332         return platform_driver_register(&fsl_ifc_ctrl_driver);
 333 }
 334 subsys_initcall(fsl_ifc_init);
 335
 336 MODULE_LICENSE("GPL");
 337 MODULE_AUTHOR("Freescale Semiconductor");
 338 MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");