drivers/rtc/rtc-zynqmp.c

   1 /*
   2  * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
   3  *
   4  * Copyright (C) 2015 Xilinx, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program. If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/rtc.h>
  27
  28 /* RTC Registers */
  29 #define RTC_SET_TM_WR           0x00
  30 #define RTC_SET_TM_RD           0x04
  31 #define RTC_CALIB_WR            0x08
  32 #define RTC_CALIB_RD            0x0C
  33 #define RTC_CUR_TM              0x10
  34 #define RTC_CUR_TICK            0x14
  35 #define RTC_ALRM                0x18
  36 #define RTC_INT_STS             0x20
  37 #define RTC_INT_MASK            0x24
  38 #define RTC_INT_EN              0x28
  39 #define RTC_INT_DIS             0x2C
  40 #define RTC_CTRL                0x40
  41
  42 #define RTC_FR_EN               BIT(20)
  43 #define RTC_FR_DATSHIFT         16
  44 #define RTC_TICK_MASK           0xFFFF
  45 #define RTC_INT_SEC             BIT(0)
  46 #define RTC_INT_ALRM            BIT(1)
  47 #define RTC_OSC_EN              BIT(24)
  48 #define RTC_BATT_EN             BIT(31)
  49
  50 #define RTC_CALIB_DEF           0x198233
  51 #define RTC_CALIB_MASK          0x1FFFFF
  52 #define RTC_SEC_MAX_VAL         0xFFFFFFFF
  53
  54 struct xlnx_rtc_dev {
  55         struct rtc_device       *rtc;
  56         void __iomem            *reg_base;
  57         int                     alarm_irq;
  58         int                     sec_irq;
  59         int                     calibval;
  60 };
  61
  62 static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
  63 {
  64         struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  65         unsigned long new_time;
  66
  67         /*
  68          * The value written will be updated after 1 sec into the
  69          * seconds read register, so we need to program time +1 sec
  70          * to get the correct time on read.
  71          */
  72         new_time = rtc_tm_to_time64(tm) + 1;
  73
  74         if (new_time > RTC_SEC_MAX_VAL)
  75                 return -EINVAL;
  76
  77         /*
  78          * Writing into calibration register will clear the Tick Counter and
  79          * force the next second to be signaled exactly in 1 second period
  80          */
  81         xrtcdev->calibval &= RTC_CALIB_MASK;
  82         writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
  83
  84         writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
  85
  86         /*
  87          * Clear the rtc interrupt status register after setting the
  88          * time. During a read_time function, the code should read the
  89          * RTC_INT_STATUS register and if bit 0 is still 0, it means
  90          * that one second has not elapsed yet since RTC was set and
  91          * the current time should be read from SET_TIME_READ register;
  92          * otherwise, CURRENT_TIME register is read to report the time
  93          */
  94         writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
  95
  96         return 0;
  97 }
  98
  99 static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
 100 {
 101         u32 status;
 102         unsigned long read_time;
 103         struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
 104
 105         status = readl(xrtcdev->reg_base + RTC_INT_STS);
 106
 107         if (status & RTC_INT_SEC) {
 108                 /*
 109                  * RTC has updated the CURRENT_TIME with the time written into
 110                  * SET_TIME_WRITE register.
 111                  */
 112                 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);
 113         } else {
 114                 /*
 115                  * Time written in SET_TIME_WRITE has not yet updated into
 116                  * the seconds read register, so read the time from the
 117                  * SET_TIME_WRITE instead of CURRENT_TIME register.
 118                  * Since we add +1 sec while writing, we need to -1 sec while
 119                  * reading.
 120                  */
 121                 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
 122                 rtc_time64_to_tm(read_time, tm);
 123         }
 124
 125         return 0;
 126 }
 127
 128 static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 129 {
 130         struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
 131
 132         rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
 133         alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
 134
 135         return 0;
 136 }
 137
 138 static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
 139 {
 140         struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
 141
 142         if (enabled)
 143                 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
 144         else
 145                 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
 146
 147         return 0;
 148 }
 149
 150 static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 151 {
 152         struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
 153         unsigned long alarm_time;
 154
 155         alarm_time = rtc_tm_to_time64(&alrm->time);
 156
 157         if (alarm_time > RTC_SEC_MAX_VAL)
 158                 return -EINVAL;
 159
 160         writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
 161
 162         xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
 163
 164         return 0;
 165 }
 166
 167 static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
 168 {
 169         u32 rtc_ctrl;
 170
 171         /* Enable RTC switch to battery when VCC_PSAUX is not available */
 172         rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
 173         rtc_ctrl |= RTC_BATT_EN;
 174         writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
 175
 176         /*
 177          * Based on crystal freq of 33.330 KHz
 178          * set the seconds counter and enable, set fractions counter
 179          * to default value suggested as per design spec
 180          * to correct RTC delay in frequency over period of time.
 181          */
 182         xrtcdev->calibval &= RTC_CALIB_MASK;
 183         writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
 184 }
 185
 186 static const struct rtc_class_ops xlnx_rtc_ops = {
 187         .set_time         = xlnx_rtc_set_time,
 188         .read_time        = xlnx_rtc_read_time,
 189         .read_alarm       = xlnx_rtc_read_alarm,
 190         .set_alarm        = xlnx_rtc_set_alarm,
 191         .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
 192 };
 193
 194 static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
 195 {
 196         struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
 197         unsigned int status;
 198
 199         status = readl(xrtcdev->reg_base + RTC_INT_STS);
 200         /* Check if interrupt asserted */
 201         if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
 202                 return IRQ_NONE;
 203
 204         /* Clear RTC_INT_ALRM interrupt only */
 205         writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
 206
 207         if (status & RTC_INT_ALRM)
 208                 rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
 209
 210         return IRQ_HANDLED;
 211 }
 212
 213 static int xlnx_rtc_probe(struct platform_device *pdev)
 214 {
 215         struct xlnx_rtc_dev *xrtcdev;
 216         struct resource *res;
 217         int ret;
 218
 219         xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
 220         if (!xrtcdev)
 221                 return -ENOMEM;
 222
 223         platform_set_drvdata(pdev, xrtcdev);
 224
 225         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 226
 227         xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res);
 228         if (IS_ERR(xrtcdev->reg_base))
 229                 return PTR_ERR(xrtcdev->reg_base);
 230
 231         xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
 232         if (xrtcdev->alarm_irq < 0) {
 233                 dev_err(&pdev->dev, "no irq resource\n");
 234                 return xrtcdev->alarm_irq;
 235         }
 236         ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
 237                                xlnx_rtc_interrupt, 0,
 238                                dev_name(&pdev->dev), xrtcdev);
 239         if (ret) {
 240                 dev_err(&pdev->dev, "request irq failed\n");
 241                 return ret;
 242         }
 243
 244         xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
 245         if (xrtcdev->sec_irq < 0) {
 246                 dev_err(&pdev->dev, "no irq resource\n");
 247                 return xrtcdev->sec_irq;
 248         }
 249         ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
 250                                xlnx_rtc_interrupt, 0,
 251                                dev_name(&pdev->dev), xrtcdev);
 252         if (ret) {
 253                 dev_err(&pdev->dev, "request irq failed\n");
 254                 return ret;
 255         }
 256
 257         ret = of_property_read_u32(pdev->dev.of_node, "calibration",
 258                                    &xrtcdev->calibval);
 259         if (ret)
 260                 xrtcdev->calibval = RTC_CALIB_DEF;
 261
 262         xlnx_init_rtc(xrtcdev);
 263
 264         device_init_wakeup(&pdev->dev, 1);
 265
 266         xrtcdev->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
 267                                          &xlnx_rtc_ops, THIS_MODULE);
 268         return PTR_ERR_OR_ZERO(xrtcdev->rtc);
 269 }
 270
 271 static int xlnx_rtc_remove(struct platform_device *pdev)
 272 {
 273         xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
 274         device_init_wakeup(&pdev->dev, 0);
 275
 276         return 0;
 277 }
 278
 279 static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
 280 {
 281         struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
 282
 283         if (device_may_wakeup(dev))
 284                 enable_irq_wake(xrtcdev->alarm_irq);
 285         else
 286                 xlnx_rtc_alarm_irq_enable(dev, 0);
 287
 288         return 0;
 289 }
 290
 291 static int __maybe_unused xlnx_rtc_resume(struct device *dev)
 292 {
 293         struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
 294
 295         if (device_may_wakeup(dev))
 296                 disable_irq_wake(xrtcdev->alarm_irq);
 297         else
 298                 xlnx_rtc_alarm_irq_enable(dev, 1);
 299
 300         return 0;
 301 }
 302
 303 static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
 304
 305 static const struct of_device_id xlnx_rtc_of_match[] = {
 306         {.compatible = "xlnx,zynqmp-rtc" },
 307         { }
 308 };
 309 MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
 310
 311 static struct platform_driver xlnx_rtc_driver = {
 312         .probe          = xlnx_rtc_probe,
 313         .remove         = xlnx_rtc_remove,
 314         .driver         = {
 315                 .name   = KBUILD_MODNAME,
 316                 .pm     = &xlnx_rtc_pm_ops,
 317                 .of_match_table = xlnx_rtc_of_match,
 318         },
 319 };
 320
 321 module_platform_driver(xlnx_rtc_driver);
 322
 323 MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
 324 MODULE_AUTHOR("Xilinx Inc.");
 325 MODULE_LICENSE("GPL v2");