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Linux 4.18.10
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_def.h
blob0f94b1d62d3f2f8611fb5a0924bf374b368a7028
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 #include <linux/btree.h>
29
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport_fc.h>
35 #include <scsi/scsi_bsg_fc.h>
36
37 #include "qla_bsg.h"
38 #include "qla_nx.h"
39 #include "qla_nx2.h"
40 #include "qla_nvme.h"
41 #define QLA2XXX_DRIVER_NAME "qla2xxx"
42 #define QLA2XXX_APIDEV "ql2xapidev"
43 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
44
45 /*
46 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
47 * but that's fine as we don't look at the last 24 ones for
48 * ISP2100 HBAs.
49 */
50 #define MAILBOX_REGISTER_COUNT_2100 8
51 #define MAILBOX_REGISTER_COUNT_2200 24
52 #define MAILBOX_REGISTER_COUNT 32
53
54 #define QLA2200A_RISC_ROM_VER 4
55 #define FPM_2300 6
56 #define FPM_2310 7
57
58 #include "qla_settings.h"
59
60 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
61
62 /*
63 * Data bit definitions
64 */
65 #define BIT_0 0x1
66 #define BIT_1 0x2
67 #define BIT_2 0x4
68 #define BIT_3 0x8
69 #define BIT_4 0x10
70 #define BIT_5 0x20
71 #define BIT_6 0x40
72 #define BIT_7 0x80
73 #define BIT_8 0x100
74 #define BIT_9 0x200
75 #define BIT_10 0x400
76 #define BIT_11 0x800
77 #define BIT_12 0x1000
78 #define BIT_13 0x2000
79 #define BIT_14 0x4000
80 #define BIT_15 0x8000
81 #define BIT_16 0x10000
82 #define BIT_17 0x20000
83 #define BIT_18 0x40000
84 #define BIT_19 0x80000
85 #define BIT_20 0x100000
86 #define BIT_21 0x200000
87 #define BIT_22 0x400000
88 #define BIT_23 0x800000
89 #define BIT_24 0x1000000
90 #define BIT_25 0x2000000
91 #define BIT_26 0x4000000
92 #define BIT_27 0x8000000
93 #define BIT_28 0x10000000
94 #define BIT_29 0x20000000
95 #define BIT_30 0x40000000
96 #define BIT_31 0x80000000
97
98 #define LSB(x) ((uint8_t)(x))
99 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
100
101 #define LSW(x) ((uint16_t)(x))
102 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
103
104 #define LSD(x) ((uint32_t)((uint64_t)(x)))
105 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
106
107 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
108
109 /*
110 * I/O register
111 */
112
113 #define RD_REG_BYTE(addr) readb(addr)
114 #define RD_REG_WORD(addr) readw(addr)
115 #define RD_REG_DWORD(addr) readl(addr)
116 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
117 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
118 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
119 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
120 #define WRT_REG_WORD(addr, data) writew(data,addr)
121 #define WRT_REG_DWORD(addr, data) writel(data,addr)
122
123 /*
124 * ISP83XX specific remote register addresses
125 */
126 #define QLA83XX_LED_PORT0 0x00201320
127 #define QLA83XX_LED_PORT1 0x00201328
128 #define QLA83XX_IDC_DEV_STATE 0x22102384
129 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
130 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
131 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
132 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
133 #define QLA83XX_IDC_CONTROL 0x22102390
134 #define QLA83XX_IDC_AUDIT 0x22102394
135 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
136 #define QLA83XX_DRIVER_LOCKID 0x22102104
137 #define QLA83XX_DRIVER_LOCK 0x8111c028
138 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
139 #define QLA83XX_FLASH_LOCKID 0x22102100
140 #define QLA83XX_FLASH_LOCK 0x8111c010
141 #define QLA83XX_FLASH_UNLOCK 0x8111c014
142 #define QLA83XX_DEV_PARTINFO1 0x221023e0
143 #define QLA83XX_DEV_PARTINFO2 0x221023e4
144 #define QLA83XX_FW_HEARTBEAT 0x221020b0
145 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
146 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
147
148 /* 83XX: Macros defining 8200 AEN Reason codes */
149 #define IDC_DEVICE_STATE_CHANGE BIT_0
150 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
151 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
152 #define IDC_HEARTBEAT_FAILURE BIT_3
153
154 /* 83XX: Macros defining 8200 AEN Error-levels */
155 #define ERR_LEVEL_NON_FATAL 0x1
156 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
157 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
158
159 /* 83XX: Macros for IDC Version */
160 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
161 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
162
163 /* 83XX: Macros for scheduling dpc tasks */
164 #define QLA83XX_NIC_CORE_RESET 0x1
165 #define QLA83XX_IDC_STATE_HANDLER 0x2
166 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
167
168 /* 83XX: Macros for defining IDC-Control bits */
169 #define QLA83XX_IDC_RESET_DISABLED BIT_0
170 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
171
172 /* 83XX: Macros for different timeouts */
173 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
174 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
175 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
176
177 /* 83XX: Macros for defining class in DEV-Partition Info register */
178 #define QLA83XX_CLASS_TYPE_NONE 0x0
179 #define QLA83XX_CLASS_TYPE_NIC 0x1
180 #define QLA83XX_CLASS_TYPE_FCOE 0x2
181 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
182
183 /* 83XX: Macros for IDC Lock-Recovery stages */
184 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
185 * lock-recovery
186 */
187 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
188
189 /* 83XX: Macros for IDC Audit type */
190 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
191 * dev-state change to NEED-RESET
192 * or NEED-QUIESCENT
193 */
194 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
195 * reset-recovery completion is
196 * second
197 */
198 /* ISP2031: Values for laser on/off */
199 #define PORT_0_2031 0x00201340
200 #define PORT_1_2031 0x00201350
201 #define LASER_ON_2031 0x01800100
202 #define LASER_OFF_2031 0x01800180
203
204 /*
205 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
206 * 133Mhz slot.
207 */
208 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
209 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
210
211 /*
212 * Fibre Channel device definitions.
213 */
214 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
215 #define MAX_FIBRE_DEVICES_2100 512
216 #define MAX_FIBRE_DEVICES_2400 2048
217 #define MAX_FIBRE_DEVICES_LOOP 128
218 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
219 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
220 #define MAX_FIBRE_LUNS 0xFFFF
221 #define MAX_HOST_COUNT 16
222
223 /*
224 * Host adapter default definitions.
225 */
226 #define MAX_BUSES 1 /* We only have one bus today */
227 #define MIN_LUNS 8
228 #define MAX_LUNS MAX_FIBRE_LUNS
229 #define MAX_CMDS_PER_LUN 255
230
231 /*
232 * Fibre Channel device definitions.
233 */
234 #define SNS_LAST_LOOP_ID_2100 0xfe
235 #define SNS_LAST_LOOP_ID_2300 0x7ff
236
237 #define LAST_LOCAL_LOOP_ID 0x7d
238 #define SNS_FL_PORT 0x7e
239 #define FABRIC_CONTROLLER 0x7f
240 #define SIMPLE_NAME_SERVER 0x80
241 #define SNS_FIRST_LOOP_ID 0x81
242 #define MANAGEMENT_SERVER 0xfe
243 #define BROADCAST 0xff
244
245 /*
246 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
247 * valid range of an N-PORT id is 0 through 0x7ef.
248 */
249 #define NPH_LAST_HANDLE 0x7ee
250 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
251 #define NPH_SNS 0x7fc /* FFFFFC */
252 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
253 #define NPH_F_PORT 0x7fe /* FFFFFE */
254 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
255
256 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
257
258 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
259 #include "qla_fw.h"
260
261 struct name_list_extended {
262 struct get_name_list_extended *l;
263 dma_addr_t ldma;
264 struct list_head fcports;
265 spinlock_t fcports_lock;
266 u32 size;
267 };
268 /*
269 * Timeout timer counts in seconds
270 */
271 #define PORT_RETRY_TIME 1
272 #define LOOP_DOWN_TIMEOUT 60
273 #define LOOP_DOWN_TIME 255 /* 240 */
274 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
275
276 #define DEFAULT_OUTSTANDING_COMMANDS 4096
277 #define MIN_OUTSTANDING_COMMANDS 128
278
279 /* ISP request and response entry counts (37-65535) */
280 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
281 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
282 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
283 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
284 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
285 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
286 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
287 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
288 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
289 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
290 #define FW_DEF_EXCHANGES_CNT 2048
291 #define FW_MAX_EXCHANGES_CNT (32 * 1024)
292 #define REDUCE_EXCHANGES_CNT (8 * 1024)
293
294 struct req_que;
295 struct qla_tgt_sess;
296
297 /*
298 * SCSI Request Block
299 */
300 struct srb_cmd {
301 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
302 uint32_t request_sense_length;
303 uint32_t fw_sense_length;
304 uint8_t *request_sense_ptr;
305 void *ctx;
306 };
307
308 /*
309 * SRB flag definitions
310 */
311 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
312 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
313 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
314 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
315 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
316
317 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
318 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
319
320 /*
321 * 24 bit port ID type definition.
322 */
323 typedef union {
324 uint32_t b24 : 24;
325
326 struct {
327 #ifdef __BIG_ENDIAN
328 uint8_t domain;
329 uint8_t area;
330 uint8_t al_pa;
331 #elif defined(__LITTLE_ENDIAN)
332 uint8_t al_pa;
333 uint8_t area;
334 uint8_t domain;
335 #else
336 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
337 #endif
338 uint8_t rsvd_1;
339 } b;
340 } port_id_t;
341 #define INVALID_PORT_ID 0xFFFFFF
342
343 struct els_logo_payload {
344 uint8_t opcode;
345 uint8_t rsvd[3];
346 uint8_t s_id[3];
347 uint8_t rsvd1[1];
348 uint8_t wwpn[WWN_SIZE];
349 };
350
351 struct els_plogi_payload {
352 uint8_t opcode;
353 uint8_t rsvd[3];
354 uint8_t data[112];
355 };
356
357 struct ct_arg {
358 void *iocb;
359 u16 nport_handle;
360 dma_addr_t req_dma;
361 dma_addr_t rsp_dma;
362 u32 req_size;
363 u32 rsp_size;
364 u32 req_allocated_size;
365 u32 rsp_allocated_size;
366 void *req;
367 void *rsp;
368 port_id_t id;
369 };
370
371 /*
372 * SRB extensions.
373 */
374 struct srb_iocb {
375 union {
376 struct {
377 uint16_t flags;
378 #define SRB_LOGIN_RETRIED BIT_0
379 #define SRB_LOGIN_COND_PLOGI BIT_1
380 #define SRB_LOGIN_SKIP_PRLI BIT_2
381 #define SRB_LOGIN_NVME_PRLI BIT_3
382 uint16_t data[2];
383 u32 iop[2];
384 } logio;
385 struct {
386 #define ELS_DCMD_TIMEOUT 20
387 #define ELS_DCMD_LOGO 0x5
388 uint32_t flags;
389 uint32_t els_cmd;
390 struct completion comp;
391 struct els_logo_payload *els_logo_pyld;
392 dma_addr_t els_logo_pyld_dma;
393 } els_logo;
394 struct {
395 #define ELS_DCMD_PLOGI 0x3
396 uint32_t flags;
397 uint32_t els_cmd;
398 struct completion comp;
399 struct els_plogi_payload *els_plogi_pyld;
400 struct els_plogi_payload *els_resp_pyld;
401 dma_addr_t els_plogi_pyld_dma;
402 dma_addr_t els_resp_pyld_dma;
403 uint32_t fw_status[3];
404 __le16 comp_status;
405 __le16 len;
406 } els_plogi;
407 struct {
408 /*
409 * Values for flags field below are as
410 * defined in tsk_mgmt_entry struct
411 * for control_flags field in qla_fw.h.
412 */
413 uint64_t lun;
414 uint32_t flags;
415 uint32_t data;
416 struct completion comp;
417 __le16 comp_status;
418 } tmf;
419 struct {
420 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
421 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
422 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
423 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
424 #define FXDISC_TIMEOUT 20
425 uint8_t flags;
426 uint32_t req_len;
427 uint32_t rsp_len;
428 void *req_addr;
429 void *rsp_addr;
430 dma_addr_t req_dma_handle;
431 dma_addr_t rsp_dma_handle;
432 __le32 adapter_id;
433 __le32 adapter_id_hi;
434 __le16 req_func_type;
435 __le32 req_data;
436 __le32 req_data_extra;
437 __le32 result;
438 __le32 seq_number;
439 __le16 fw_flags;
440 struct completion fxiocb_comp;
441 __le32 reserved_0;
442 uint8_t reserved_1;
443 } fxiocb;
444 struct {
445 uint32_t cmd_hndl;
446 __le16 comp_status;
447 __le16 req_que_no;
448 struct completion comp;
449 } abt;
450 struct ct_arg ctarg;
451 #define MAX_IOCB_MB_REG 28
452 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
453 struct {
454 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
455 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
456 void *out, *in;
457 dma_addr_t out_dma, in_dma;
458 struct completion comp;
459 int rc;
460 } mbx;
461 struct {
462 struct imm_ntfy_from_isp *ntfy;
463 } nack;
464 struct {
465 __le16 comp_status;
466 uint16_t rsp_pyld_len;
467 uint8_t aen_op;
468 void *desc;
469
470 /* These are only used with ls4 requests */
471 int cmd_len;
472 int rsp_len;
473 dma_addr_t cmd_dma;
474 dma_addr_t rsp_dma;
475 enum nvmefc_fcp_datadir dir;
476 uint32_t dl;
477 uint32_t timeout_sec;
478 struct list_head entry;
479 } nvme;
480 struct {
481 u16 cmd;
482 u16 vp_index;
483 } ctrlvp;
484 } u;
485
486 struct timer_list timer;
487 void (*timeout)(void *);
488 };
489
490 /* Values for srb_ctx type */
491 #define SRB_LOGIN_CMD 1
492 #define SRB_LOGOUT_CMD 2
493 #define SRB_ELS_CMD_RPT 3
494 #define SRB_ELS_CMD_HST 4
495 #define SRB_CT_CMD 5
496 #define SRB_ADISC_CMD 6
497 #define SRB_TM_CMD 7
498 #define SRB_SCSI_CMD 8
499 #define SRB_BIDI_CMD 9
500 #define SRB_FXIOCB_DCMD 10
501 #define SRB_FXIOCB_BCMD 11
502 #define SRB_ABT_CMD 12
503 #define SRB_ELS_DCMD 13
504 #define SRB_MB_IOCB 14
505 #define SRB_CT_PTHRU_CMD 15
506 #define SRB_NACK_PLOGI 16
507 #define SRB_NACK_PRLI 17
508 #define SRB_NACK_LOGO 18
509 #define SRB_NVME_CMD 19
510 #define SRB_NVME_LS 20
511 #define SRB_PRLI_CMD 21
512 #define SRB_CTRL_VP 22
513 #define SRB_PRLO_CMD 23
514
515 enum {
516 TYPE_SRB,
517 TYPE_TGT_CMD,
518 };
519
520 typedef struct srb {
521 /*
522 * Do not move cmd_type field, it needs to
523 * line up with qla_tgt_cmd->cmd_type
524 */
525 uint8_t cmd_type;
526 uint8_t pad[3];
527 atomic_t ref_count;
528 wait_queue_head_t nvme_ls_waitq;
529 struct fc_port *fcport;
530 struct scsi_qla_host *vha;
531 uint32_t handle;
532 uint16_t flags;
533 uint16_t type;
534 const char *name;
535 int iocbs;
536 struct qla_qpair *qpair;
537 struct list_head elem;
538 u32 gen1; /* scratch */
539 u32 gen2; /* scratch */
540 int rc;
541 int retry_count;
542 struct completion comp;
543 union {
544 struct srb_iocb iocb_cmd;
545 struct bsg_job *bsg_job;
546 struct srb_cmd scmd;
547 } u;
548 void (*done)(void *, int);
549 void (*free)(void *);
550 } srb_t;
551
552 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
553 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
554 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
555
556 #define GET_CMD_SENSE_LEN(sp) \
557 (sp->u.scmd.request_sense_length)
558 #define SET_CMD_SENSE_LEN(sp, len) \
559 (sp->u.scmd.request_sense_length = len)
560 #define GET_CMD_SENSE_PTR(sp) \
561 (sp->u.scmd.request_sense_ptr)
562 #define SET_CMD_SENSE_PTR(sp, ptr) \
563 (sp->u.scmd.request_sense_ptr = ptr)
564 #define GET_FW_SENSE_LEN(sp) \
565 (sp->u.scmd.fw_sense_length)
566 #define SET_FW_SENSE_LEN(sp, len) \
567 (sp->u.scmd.fw_sense_length = len)
568
569 struct msg_echo_lb {
570 dma_addr_t send_dma;
571 dma_addr_t rcv_dma;
572 uint16_t req_sg_cnt;
573 uint16_t rsp_sg_cnt;
574 uint16_t options;
575 uint32_t transfer_size;
576 uint32_t iteration_count;
577 };
578
579 /*
580 * ISP I/O Register Set structure definitions.
581 */
582 struct device_reg_2xxx {
583 uint16_t flash_address; /* Flash BIOS address */
584 uint16_t flash_data; /* Flash BIOS data */
585 uint16_t unused_1[1]; /* Gap */
586 uint16_t ctrl_status; /* Control/Status */
587 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
588 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
589 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
590
591 uint16_t ictrl; /* Interrupt control */
592 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
593 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
594
595 uint16_t istatus; /* Interrupt status */
596 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
597
598 uint16_t semaphore; /* Semaphore */
599 uint16_t nvram; /* NVRAM register. */
600 #define NVR_DESELECT 0
601 #define NVR_BUSY BIT_15
602 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
603 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
604 #define NVR_DATA_IN BIT_3
605 #define NVR_DATA_OUT BIT_2
606 #define NVR_SELECT BIT_1
607 #define NVR_CLOCK BIT_0
608
609 #define NVR_WAIT_CNT 20000
610
611 union {
612 struct {
613 uint16_t mailbox0;
614 uint16_t mailbox1;
615 uint16_t mailbox2;
616 uint16_t mailbox3;
617 uint16_t mailbox4;
618 uint16_t mailbox5;
619 uint16_t mailbox6;
620 uint16_t mailbox7;
621 uint16_t unused_2[59]; /* Gap */
622 } __attribute__((packed)) isp2100;
623 struct {
624 /* Request Queue */
625 uint16_t req_q_in; /* In-Pointer */
626 uint16_t req_q_out; /* Out-Pointer */
627 /* Response Queue */
628 uint16_t rsp_q_in; /* In-Pointer */
629 uint16_t rsp_q_out; /* Out-Pointer */
630
631 /* RISC to Host Status */
632 uint32_t host_status;
633 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
634 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
635
636 /* Host to Host Semaphore */
637 uint16_t host_semaphore;
638 uint16_t unused_3[17]; /* Gap */
639 uint16_t mailbox0;
640 uint16_t mailbox1;
641 uint16_t mailbox2;
642 uint16_t mailbox3;
643 uint16_t mailbox4;
644 uint16_t mailbox5;
645 uint16_t mailbox6;
646 uint16_t mailbox7;
647 uint16_t mailbox8;
648 uint16_t mailbox9;
649 uint16_t mailbox10;
650 uint16_t mailbox11;
651 uint16_t mailbox12;
652 uint16_t mailbox13;
653 uint16_t mailbox14;
654 uint16_t mailbox15;
655 uint16_t mailbox16;
656 uint16_t mailbox17;
657 uint16_t mailbox18;
658 uint16_t mailbox19;
659 uint16_t mailbox20;
660 uint16_t mailbox21;
661 uint16_t mailbox22;
662 uint16_t mailbox23;
663 uint16_t mailbox24;
664 uint16_t mailbox25;
665 uint16_t mailbox26;
666 uint16_t mailbox27;
667 uint16_t mailbox28;
668 uint16_t mailbox29;
669 uint16_t mailbox30;
670 uint16_t mailbox31;
671 uint16_t fb_cmd;
672 uint16_t unused_4[10]; /* Gap */
673 } __attribute__((packed)) isp2300;
674 } u;
675
676 uint16_t fpm_diag_config;
677 uint16_t unused_5[0x4]; /* Gap */
678 uint16_t risc_hw;
679 uint16_t unused_5_1; /* Gap */
680 uint16_t pcr; /* Processor Control Register. */
681 uint16_t unused_6[0x5]; /* Gap */
682 uint16_t mctr; /* Memory Configuration and Timing. */
683 uint16_t unused_7[0x3]; /* Gap */
684 uint16_t fb_cmd_2100; /* Unused on 23XX */
685 uint16_t unused_8[0x3]; /* Gap */
686 uint16_t hccr; /* Host command & control register. */
687 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
688 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
689 /* HCCR commands */
690 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
691 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
692 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
693 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
694 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
695 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
696 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
697 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
698
699 uint16_t unused_9[5]; /* Gap */
700 uint16_t gpiod; /* GPIO Data register. */
701 uint16_t gpioe; /* GPIO Enable register. */
702 #define GPIO_LED_MASK 0x00C0
703 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
704 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
705 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
706 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
707 #define GPIO_LED_ALL_OFF 0x0000
708 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
709 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
710
711 union {
712 struct {
713 uint16_t unused_10[8]; /* Gap */
714 uint16_t mailbox8;
715 uint16_t mailbox9;
716 uint16_t mailbox10;
717 uint16_t mailbox11;
718 uint16_t mailbox12;
719 uint16_t mailbox13;
720 uint16_t mailbox14;
721 uint16_t mailbox15;
722 uint16_t mailbox16;
723 uint16_t mailbox17;
724 uint16_t mailbox18;
725 uint16_t mailbox19;
726 uint16_t mailbox20;
727 uint16_t mailbox21;
728 uint16_t mailbox22;
729 uint16_t mailbox23; /* Also probe reg. */
730 } __attribute__((packed)) isp2200;
731 } u_end;
732 };
733
734 struct device_reg_25xxmq {
735 uint32_t req_q_in;
736 uint32_t req_q_out;
737 uint32_t rsp_q_in;
738 uint32_t rsp_q_out;
739 uint32_t atio_q_in;
740 uint32_t atio_q_out;
741 };
742
743
744 struct device_reg_fx00 {
745 uint32_t mailbox0; /* 00 */
746 uint32_t mailbox1; /* 04 */
747 uint32_t mailbox2; /* 08 */
748 uint32_t mailbox3; /* 0C */
749 uint32_t mailbox4; /* 10 */
750 uint32_t mailbox5; /* 14 */
751 uint32_t mailbox6; /* 18 */
752 uint32_t mailbox7; /* 1C */
753 uint32_t mailbox8; /* 20 */
754 uint32_t mailbox9; /* 24 */
755 uint32_t mailbox10; /* 28 */
756 uint32_t mailbox11;
757 uint32_t mailbox12;
758 uint32_t mailbox13;
759 uint32_t mailbox14;
760 uint32_t mailbox15;
761 uint32_t mailbox16;
762 uint32_t mailbox17;
763 uint32_t mailbox18;
764 uint32_t mailbox19;
765 uint32_t mailbox20;
766 uint32_t mailbox21;
767 uint32_t mailbox22;
768 uint32_t mailbox23;
769 uint32_t mailbox24;
770 uint32_t mailbox25;
771 uint32_t mailbox26;
772 uint32_t mailbox27;
773 uint32_t mailbox28;
774 uint32_t mailbox29;
775 uint32_t mailbox30;
776 uint32_t mailbox31;
777 uint32_t aenmailbox0;
778 uint32_t aenmailbox1;
779 uint32_t aenmailbox2;
780 uint32_t aenmailbox3;
781 uint32_t aenmailbox4;
782 uint32_t aenmailbox5;
783 uint32_t aenmailbox6;
784 uint32_t aenmailbox7;
785 /* Request Queue. */
786 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
787 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
788 /* Response Queue. */
789 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
790 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
791 /* Init values shadowed on FW Up Event */
792 uint32_t initval0; /* B0 */
793 uint32_t initval1; /* B4 */
794 uint32_t initval2; /* B8 */
795 uint32_t initval3; /* BC */
796 uint32_t initval4; /* C0 */
797 uint32_t initval5; /* C4 */
798 uint32_t initval6; /* C8 */
799 uint32_t initval7; /* CC */
800 uint32_t fwheartbeat; /* D0 */
801 uint32_t pseudoaen; /* D4 */
802 };
803
804
805
806 typedef union {
807 struct device_reg_2xxx isp;
808 struct device_reg_24xx isp24;
809 struct device_reg_25xxmq isp25mq;
810 struct device_reg_82xx isp82;
811 struct device_reg_fx00 ispfx00;
812 } __iomem device_reg_t;
813
814 #define ISP_REQ_Q_IN(ha, reg) \
815 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
816 &(reg)->u.isp2100.mailbox4 : \
817 &(reg)->u.isp2300.req_q_in)
818 #define ISP_REQ_Q_OUT(ha, reg) \
819 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
820 &(reg)->u.isp2100.mailbox4 : \
821 &(reg)->u.isp2300.req_q_out)
822 #define ISP_RSP_Q_IN(ha, reg) \
823 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
824 &(reg)->u.isp2100.mailbox5 : \
825 &(reg)->u.isp2300.rsp_q_in)
826 #define ISP_RSP_Q_OUT(ha, reg) \
827 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
828 &(reg)->u.isp2100.mailbox5 : \
829 &(reg)->u.isp2300.rsp_q_out)
830
831 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
832 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
833
834 #define MAILBOX_REG(ha, reg, num) \
835 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
836 (num < 8 ? \
837 &(reg)->u.isp2100.mailbox0 + (num) : \
838 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
839 &(reg)->u.isp2300.mailbox0 + (num))
840 #define RD_MAILBOX_REG(ha, reg, num) \
841 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
842 #define WRT_MAILBOX_REG(ha, reg, num, data) \
843 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
844
845 #define FB_CMD_REG(ha, reg) \
846 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
847 &(reg)->fb_cmd_2100 : \
848 &(reg)->u.isp2300.fb_cmd)
849 #define RD_FB_CMD_REG(ha, reg) \
850 RD_REG_WORD(FB_CMD_REG(ha, reg))
851 #define WRT_FB_CMD_REG(ha, reg, data) \
852 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
853
854 typedef struct {
855 uint32_t out_mb; /* outbound from driver */
856 uint32_t in_mb; /* Incoming from RISC */
857 uint16_t mb[MAILBOX_REGISTER_COUNT];
858 long buf_size;
859 void *bufp;
860 uint32_t tov;
861 uint8_t flags;
862 #define MBX_DMA_IN BIT_0
863 #define MBX_DMA_OUT BIT_1
864 #define IOCTL_CMD BIT_2
865 } mbx_cmd_t;
866
867 struct mbx_cmd_32 {
868 uint32_t out_mb; /* outbound from driver */
869 uint32_t in_mb; /* Incoming from RISC */
870 uint32_t mb[MAILBOX_REGISTER_COUNT];
871 long buf_size;
872 void *bufp;
873 uint32_t tov;
874 uint8_t flags;
875 #define MBX_DMA_IN BIT_0
876 #define MBX_DMA_OUT BIT_1
877 #define IOCTL_CMD BIT_2
878 };
879
880
881 #define MBX_TOV_SECONDS 30
882
883 /*
884 * ISP product identification definitions in mailboxes after reset.
885 */
886 #define PROD_ID_1 0x4953
887 #define PROD_ID_2 0x0000
888 #define PROD_ID_2a 0x5020
889 #define PROD_ID_3 0x2020
890
891 /*
892 * ISP mailbox Self-Test status codes
893 */
894 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
895 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
896 #define MBS_BUSY 4 /* Busy. */
897
898 /*
899 * ISP mailbox command complete status codes
900 */
901 #define MBS_COMMAND_COMPLETE 0x4000
902 #define MBS_INVALID_COMMAND 0x4001
903 #define MBS_HOST_INTERFACE_ERROR 0x4002
904 #define MBS_TEST_FAILED 0x4003
905 #define MBS_COMMAND_ERROR 0x4005
906 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
907 #define MBS_PORT_ID_USED 0x4007
908 #define MBS_LOOP_ID_USED 0x4008
909 #define MBS_ALL_IDS_IN_USE 0x4009
910 #define MBS_NOT_LOGGED_IN 0x400A
911 #define MBS_LINK_DOWN_ERROR 0x400B
912 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
913
914 /*
915 * ISP mailbox asynchronous event status codes
916 */
917 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
918 #define MBA_RESET 0x8001 /* Reset Detected. */
919 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
920 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
921 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
922 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
923 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
924 /* occurred. */
925 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
926 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
927 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
928 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
929 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
930 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
931 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
932 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
933 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
934 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
935 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
936 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
937 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
938 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
939 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
940 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
941 /* used. */
942 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
943 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
944 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
945 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
946 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
947 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
948 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
949 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
950 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
951 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
952 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
953 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
954 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
955 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
956 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
957 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
958 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
959 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
960 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
961 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
962 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
963 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
964 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
965 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
966 Notification */
967 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
968 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
969 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
970 /* 83XX FCoE specific */
971 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
972
973 /* Interrupt type codes */
974 #define INTR_ROM_MB_SUCCESS 0x1
975 #define INTR_ROM_MB_FAILED 0x2
976 #define INTR_MB_SUCCESS 0x10
977 #define INTR_MB_FAILED 0x11
978 #define INTR_ASYNC_EVENT 0x12
979 #define INTR_RSP_QUE_UPDATE 0x13
980 #define INTR_RSP_QUE_UPDATE_83XX 0x14
981 #define INTR_ATIO_QUE_UPDATE 0x1C
982 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
983 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
984
985 /* ISP mailbox loopback echo diagnostic error code */
986 #define MBS_LB_RESET 0x17
987 /*
988 * Firmware options 1, 2, 3.
989 */
990 #define FO1_AE_ON_LIPF8 BIT_0
991 #define FO1_AE_ALL_LIP_RESET BIT_1
992 #define FO1_CTIO_RETRY BIT_3
993 #define FO1_DISABLE_LIP_F7_SW BIT_4
994 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
995 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
996 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
997 #define FO1_SET_EMPHASIS_SWING BIT_8
998 #define FO1_AE_AUTO_BYPASS BIT_9
999 #define FO1_ENABLE_PURE_IOCB BIT_10
1000 #define FO1_AE_PLOGI_RJT BIT_11
1001 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1002 #define FO1_AE_QUEUE_FULL BIT_13
1003
1004 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1005 #define FO2_REV_LOOPBACK BIT_1
1006
1007 #define FO3_ENABLE_EMERG_IOCB BIT_0
1008 #define FO3_AE_RND_ERROR BIT_1
1009
1010 /* 24XX additional firmware options */
1011 #define ADD_FO_COUNT 3
1012 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
1013 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1014
1015 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1016
1017 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1018
1019 /*
1020 * ISP mailbox commands
1021 */
1022 #define MBC_LOAD_RAM 1 /* Load RAM. */
1023 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
1024 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
1025 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
1026 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
1027 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1028 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1029 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
1030 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1031 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1032 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
1033 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1034 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
1035 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1036 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1037 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1038 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1039 #define MBC_RESET 0x18 /* Reset. */
1040 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
1041 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
1042 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1043 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1044 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1045 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1046 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1047 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
1048 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1049 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1050 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1051 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1052 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1053 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1054 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1055 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
1056 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1057 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1058 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
1059 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1060 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1061 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
1062 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1063 #define MBC_DATA_RATE 0x5d /* Data Rate */
1064 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1065 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1066 /* Initialization Procedure */
1067 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1068 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1069 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1070 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
1071 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1072 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1073 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1074 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1075 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1076 #define MBC_LIP_RESET 0x6c /* LIP reset. */
1077 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1078 /* commandd. */
1079 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1080 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1081 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1082 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1083 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1084 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1085 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1086 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1087 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1088 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1089 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1090
1091 /*
1092 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1093 * should be defined with MBC_MR_*
1094 */
1095 #define MBC_MR_DRV_SHUTDOWN 0x6A
1096
1097 /*
1098 * ISP24xx mailbox commands
1099 */
1100 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1101 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1102 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1103 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1104 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1105 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1106 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1107 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1108 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1109 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1110 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1111 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1112 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1113 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1114 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1115 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1116 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1117 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1118 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1119 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1120 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1121 #define MBC_PORT_RESET 0x120 /* Port Reset */
1122 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1123 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1124
1125 /*
1126 * ISP81xx mailbox commands
1127 */
1128 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1129
1130 /*
1131 * ISP8044 mailbox commands
1132 */
1133 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1134 #define HCS_WRITE_SERDES 0x3
1135 #define HCS_READ_SERDES 0x4
1136
1137 /* Firmware return data sizes */
1138 #define FCAL_MAP_SIZE 128
1139
1140 /* Mailbox bit definitions for out_mb and in_mb */
1141 #define MBX_31 BIT_31
1142 #define MBX_30 BIT_30
1143 #define MBX_29 BIT_29
1144 #define MBX_28 BIT_28
1145 #define MBX_27 BIT_27
1146 #define MBX_26 BIT_26
1147 #define MBX_25 BIT_25
1148 #define MBX_24 BIT_24
1149 #define MBX_23 BIT_23
1150 #define MBX_22 BIT_22
1151 #define MBX_21 BIT_21
1152 #define MBX_20 BIT_20
1153 #define MBX_19 BIT_19
1154 #define MBX_18 BIT_18
1155 #define MBX_17 BIT_17
1156 #define MBX_16 BIT_16
1157 #define MBX_15 BIT_15
1158 #define MBX_14 BIT_14
1159 #define MBX_13 BIT_13
1160 #define MBX_12 BIT_12
1161 #define MBX_11 BIT_11
1162 #define MBX_10 BIT_10
1163 #define MBX_9 BIT_9
1164 #define MBX_8 BIT_8
1165 #define MBX_7 BIT_7
1166 #define MBX_6 BIT_6
1167 #define MBX_5 BIT_5
1168 #define MBX_4 BIT_4
1169 #define MBX_3 BIT_3
1170 #define MBX_2 BIT_2
1171 #define MBX_1 BIT_1
1172 #define MBX_0 BIT_0
1173
1174 #define RNID_TYPE_PORT_LOGIN 0x7
1175 #define RNID_TYPE_SET_VERSION 0x9
1176 #define RNID_TYPE_ASIC_TEMP 0xC
1177
1178 /*
1179 * Firmware state codes from get firmware state mailbox command
1180 */
1181 #define FSTATE_CONFIG_WAIT 0
1182 #define FSTATE_WAIT_AL_PA 1
1183 #define FSTATE_WAIT_LOGIN 2
1184 #define FSTATE_READY 3
1185 #define FSTATE_LOSS_OF_SYNC 4
1186 #define FSTATE_ERROR 5
1187 #define FSTATE_REINIT 6
1188 #define FSTATE_NON_PART 7
1189
1190 #define FSTATE_CONFIG_CORRECT 0
1191 #define FSTATE_P2P_RCV_LIP 1
1192 #define FSTATE_P2P_CHOOSE_LOOP 2
1193 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1194 #define FSTATE_FATAL_ERROR 4
1195 #define FSTATE_LOOP_BACK_CONN 5
1196
1197 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1198 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1199 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1200 #define QLA27XX_PRIMARY_IMAGE 1
1201 #define QLA27XX_SECONDARY_IMAGE 2
1202
1203 /*
1204 * Port Database structure definition
1205 * Little endian except where noted.
1206 */
1207 #define PORT_DATABASE_SIZE 128 /* bytes */
1208 typedef struct {
1209 uint8_t options;
1210 uint8_t control;
1211 uint8_t master_state;
1212 uint8_t slave_state;
1213 uint8_t reserved[2];
1214 uint8_t hard_address;
1215 uint8_t reserved_1;
1216 uint8_t port_id[4];
1217 uint8_t node_name[WWN_SIZE];
1218 uint8_t port_name[WWN_SIZE];
1219 uint16_t execution_throttle;
1220 uint16_t execution_count;
1221 uint8_t reset_count;
1222 uint8_t reserved_2;
1223 uint16_t resource_allocation;
1224 uint16_t current_allocation;
1225 uint16_t queue_head;
1226 uint16_t queue_tail;
1227 uint16_t transmit_execution_list_next;
1228 uint16_t transmit_execution_list_previous;
1229 uint16_t common_features;
1230 uint16_t total_concurrent_sequences;
1231 uint16_t RO_by_information_category;
1232 uint8_t recipient;
1233 uint8_t initiator;
1234 uint16_t receive_data_size;
1235 uint16_t concurrent_sequences;
1236 uint16_t open_sequences_per_exchange;
1237 uint16_t lun_abort_flags;
1238 uint16_t lun_stop_flags;
1239 uint16_t stop_queue_head;
1240 uint16_t stop_queue_tail;
1241 uint16_t port_retry_timer;
1242 uint16_t next_sequence_id;
1243 uint16_t frame_count;
1244 uint16_t PRLI_payload_length;
1245 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1246 /* Bits 15-0 of word 0 */
1247 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1248 /* Bits 15-0 of word 3 */
1249 uint16_t loop_id;
1250 uint16_t extended_lun_info_list_pointer;
1251 uint16_t extended_lun_stop_list_pointer;
1252 } port_database_t;
1253
1254 /*
1255 * Port database slave/master states
1256 */
1257 #define PD_STATE_DISCOVERY 0
1258 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1259 #define PD_STATE_PORT_LOGIN 2
1260 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1261 #define PD_STATE_PROCESS_LOGIN 4
1262 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1263 #define PD_STATE_PORT_LOGGED_IN 6
1264 #define PD_STATE_PORT_UNAVAILABLE 7
1265 #define PD_STATE_PROCESS_LOGOUT 8
1266 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1267 #define PD_STATE_PORT_LOGOUT 10
1268 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1269
1270
1271 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1272 #define QLA_ZIO_DISABLED 0
1273 #define QLA_ZIO_DEFAULT_TIMER 2
1274
1275 /*
1276 * ISP Initialization Control Block.
1277 * Little endian except where noted.
1278 */
1279 #define ICB_VERSION 1
1280 typedef struct {
1281 uint8_t version;
1282 uint8_t reserved_1;
1283
1284 /*
1285 * LSB BIT 0 = Enable Hard Loop Id
1286 * LSB BIT 1 = Enable Fairness
1287 * LSB BIT 2 = Enable Full-Duplex
1288 * LSB BIT 3 = Enable Fast Posting
1289 * LSB BIT 4 = Enable Target Mode
1290 * LSB BIT 5 = Disable Initiator Mode
1291 * LSB BIT 6 = Enable ADISC
1292 * LSB BIT 7 = Enable Target Inquiry Data
1293 *
1294 * MSB BIT 0 = Enable PDBC Notify
1295 * MSB BIT 1 = Non Participating LIP
1296 * MSB BIT 2 = Descending Loop ID Search
1297 * MSB BIT 3 = Acquire Loop ID in LIPA
1298 * MSB BIT 4 = Stop PortQ on Full Status
1299 * MSB BIT 5 = Full Login after LIP
1300 * MSB BIT 6 = Node Name Option
1301 * MSB BIT 7 = Ext IFWCB enable bit
1302 */
1303 uint8_t firmware_options[2];
1304
1305 uint16_t frame_payload_size;
1306 uint16_t max_iocb_allocation;
1307 uint16_t execution_throttle;
1308 uint8_t retry_count;
1309 uint8_t retry_delay; /* unused */
1310 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1311 uint16_t hard_address;
1312 uint8_t inquiry_data;
1313 uint8_t login_timeout;
1314 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1315
1316 uint16_t request_q_outpointer;
1317 uint16_t response_q_inpointer;
1318 uint16_t request_q_length;
1319 uint16_t response_q_length;
1320 uint32_t request_q_address[2];
1321 uint32_t response_q_address[2];
1322
1323 uint16_t lun_enables;
1324 uint8_t command_resource_count;
1325 uint8_t immediate_notify_resource_count;
1326 uint16_t timeout;
1327 uint8_t reserved_2[2];
1328
1329 /*
1330 * LSB BIT 0 = Timer Operation mode bit 0
1331 * LSB BIT 1 = Timer Operation mode bit 1
1332 * LSB BIT 2 = Timer Operation mode bit 2
1333 * LSB BIT 3 = Timer Operation mode bit 3
1334 * LSB BIT 4 = Init Config Mode bit 0
1335 * LSB BIT 5 = Init Config Mode bit 1
1336 * LSB BIT 6 = Init Config Mode bit 2
1337 * LSB BIT 7 = Enable Non part on LIHA failure
1338 *
1339 * MSB BIT 0 = Enable class 2
1340 * MSB BIT 1 = Enable ACK0
1341 * MSB BIT 2 =
1342 * MSB BIT 3 =
1343 * MSB BIT 4 = FC Tape Enable
1344 * MSB BIT 5 = Enable FC Confirm
1345 * MSB BIT 6 = Enable command queuing in target mode
1346 * MSB BIT 7 = No Logo On Link Down
1347 */
1348 uint8_t add_firmware_options[2];
1349
1350 uint8_t response_accumulation_timer;
1351 uint8_t interrupt_delay_timer;
1352
1353 /*
1354 * LSB BIT 0 = Enable Read xfr_rdy
1355 * LSB BIT 1 = Soft ID only
1356 * LSB BIT 2 =
1357 * LSB BIT 3 =
1358 * LSB BIT 4 = FCP RSP Payload [0]
1359 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1360 * LSB BIT 6 = Enable Out-of-Order frame handling
1361 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1362 *
1363 * MSB BIT 0 = Sbus enable - 2300
1364 * MSB BIT 1 =
1365 * MSB BIT 2 =
1366 * MSB BIT 3 =
1367 * MSB BIT 4 = LED mode
1368 * MSB BIT 5 = enable 50 ohm termination
1369 * MSB BIT 6 = Data Rate (2300 only)
1370 * MSB BIT 7 = Data Rate (2300 only)
1371 */
1372 uint8_t special_options[2];
1373
1374 uint8_t reserved_3[26];
1375 } init_cb_t;
1376
1377 /*
1378 * Get Link Status mailbox command return buffer.
1379 */
1380 #define GLSO_SEND_RPS BIT_0
1381 #define GLSO_USE_DID BIT_3
1382
1383 struct link_statistics {
1384 uint32_t link_fail_cnt;
1385 uint32_t loss_sync_cnt;
1386 uint32_t loss_sig_cnt;
1387 uint32_t prim_seq_err_cnt;
1388 uint32_t inval_xmit_word_cnt;
1389 uint32_t inval_crc_cnt;
1390 uint32_t lip_cnt;
1391 uint32_t link_up_cnt;
1392 uint32_t link_down_loop_init_tmo;
1393 uint32_t link_down_los;
1394 uint32_t link_down_loss_rcv_clk;
1395 uint32_t reserved0[5];
1396 uint32_t port_cfg_chg;
1397 uint32_t reserved1[11];
1398 uint32_t rsp_q_full;
1399 uint32_t atio_q_full;
1400 uint32_t drop_ae;
1401 uint32_t els_proto_err;
1402 uint32_t reserved2;
1403 uint32_t tx_frames;
1404 uint32_t rx_frames;
1405 uint32_t discarded_frames;
1406 uint32_t dropped_frames;
1407 uint32_t reserved3;
1408 uint32_t nos_rcvd;
1409 uint32_t reserved4[4];
1410 uint32_t tx_prjt;
1411 uint32_t rcv_exfail;
1412 uint32_t rcv_abts;
1413 uint32_t seq_frm_miss;
1414 uint32_t corr_err;
1415 uint32_t mb_rqst;
1416 uint32_t nport_full;
1417 uint32_t eofa;
1418 uint32_t reserved5;
1419 uint32_t fpm_recv_word_cnt_lo;
1420 uint32_t fpm_recv_word_cnt_hi;
1421 uint32_t fpm_disc_word_cnt_lo;
1422 uint32_t fpm_disc_word_cnt_hi;
1423 uint32_t fpm_xmit_word_cnt_lo;
1424 uint32_t fpm_xmit_word_cnt_hi;
1425 uint32_t reserved6[70];
1426 };
1427
1428 /*
1429 * NVRAM Command values.
1430 */
1431 #define NV_START_BIT BIT_2
1432 #define NV_WRITE_OP (BIT_26+BIT_24)
1433 #define NV_READ_OP (BIT_26+BIT_25)
1434 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1435 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1436 #define NV_DELAY_COUNT 10
1437
1438 /*
1439 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1440 */
1441 typedef struct {
1442 /*
1443 * NVRAM header
1444 */
1445 uint8_t id[4];
1446 uint8_t nvram_version;
1447 uint8_t reserved_0;
1448
1449 /*
1450 * NVRAM RISC parameter block
1451 */
1452 uint8_t parameter_block_version;
1453 uint8_t reserved_1;
1454
1455 /*
1456 * LSB BIT 0 = Enable Hard Loop Id
1457 * LSB BIT 1 = Enable Fairness
1458 * LSB BIT 2 = Enable Full-Duplex
1459 * LSB BIT 3 = Enable Fast Posting
1460 * LSB BIT 4 = Enable Target Mode
1461 * LSB BIT 5 = Disable Initiator Mode
1462 * LSB BIT 6 = Enable ADISC
1463 * LSB BIT 7 = Enable Target Inquiry Data
1464 *
1465 * MSB BIT 0 = Enable PDBC Notify
1466 * MSB BIT 1 = Non Participating LIP
1467 * MSB BIT 2 = Descending Loop ID Search
1468 * MSB BIT 3 = Acquire Loop ID in LIPA
1469 * MSB BIT 4 = Stop PortQ on Full Status
1470 * MSB BIT 5 = Full Login after LIP
1471 * MSB BIT 6 = Node Name Option
1472 * MSB BIT 7 = Ext IFWCB enable bit
1473 */
1474 uint8_t firmware_options[2];
1475
1476 uint16_t frame_payload_size;
1477 uint16_t max_iocb_allocation;
1478 uint16_t execution_throttle;
1479 uint8_t retry_count;
1480 uint8_t retry_delay; /* unused */
1481 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1482 uint16_t hard_address;
1483 uint8_t inquiry_data;
1484 uint8_t login_timeout;
1485 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1486
1487 /*
1488 * LSB BIT 0 = Timer Operation mode bit 0
1489 * LSB BIT 1 = Timer Operation mode bit 1
1490 * LSB BIT 2 = Timer Operation mode bit 2
1491 * LSB BIT 3 = Timer Operation mode bit 3
1492 * LSB BIT 4 = Init Config Mode bit 0
1493 * LSB BIT 5 = Init Config Mode bit 1
1494 * LSB BIT 6 = Init Config Mode bit 2
1495 * LSB BIT 7 = Enable Non part on LIHA failure
1496 *
1497 * MSB BIT 0 = Enable class 2
1498 * MSB BIT 1 = Enable ACK0
1499 * MSB BIT 2 =
1500 * MSB BIT 3 =
1501 * MSB BIT 4 = FC Tape Enable
1502 * MSB BIT 5 = Enable FC Confirm
1503 * MSB BIT 6 = Enable command queuing in target mode
1504 * MSB BIT 7 = No Logo On Link Down
1505 */
1506 uint8_t add_firmware_options[2];
1507
1508 uint8_t response_accumulation_timer;
1509 uint8_t interrupt_delay_timer;
1510
1511 /*
1512 * LSB BIT 0 = Enable Read xfr_rdy
1513 * LSB BIT 1 = Soft ID only
1514 * LSB BIT 2 =
1515 * LSB BIT 3 =
1516 * LSB BIT 4 = FCP RSP Payload [0]
1517 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1518 * LSB BIT 6 = Enable Out-of-Order frame handling
1519 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1520 *
1521 * MSB BIT 0 = Sbus enable - 2300
1522 * MSB BIT 1 =
1523 * MSB BIT 2 =
1524 * MSB BIT 3 =
1525 * MSB BIT 4 = LED mode
1526 * MSB BIT 5 = enable 50 ohm termination
1527 * MSB BIT 6 = Data Rate (2300 only)
1528 * MSB BIT 7 = Data Rate (2300 only)
1529 */
1530 uint8_t special_options[2];
1531
1532 /* Reserved for expanded RISC parameter block */
1533 uint8_t reserved_2[22];
1534
1535 /*
1536 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1537 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1538 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1539 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1540 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1541 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1542 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1543 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1544 *
1545 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1546 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1547 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1548 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1549 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1550 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1551 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1552 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1553 *
1554 * LSB BIT 0 = Output Swing 1G bit 0
1555 * LSB BIT 1 = Output Swing 1G bit 1
1556 * LSB BIT 2 = Output Swing 1G bit 2
1557 * LSB BIT 3 = Output Emphasis 1G bit 0
1558 * LSB BIT 4 = Output Emphasis 1G bit 1
1559 * LSB BIT 5 = Output Swing 2G bit 0
1560 * LSB BIT 6 = Output Swing 2G bit 1
1561 * LSB BIT 7 = Output Swing 2G bit 2
1562 *
1563 * MSB BIT 0 = Output Emphasis 2G bit 0
1564 * MSB BIT 1 = Output Emphasis 2G bit 1
1565 * MSB BIT 2 = Output Enable
1566 * MSB BIT 3 =
1567 * MSB BIT 4 =
1568 * MSB BIT 5 =
1569 * MSB BIT 6 =
1570 * MSB BIT 7 =
1571 */
1572 uint8_t seriallink_options[4];
1573
1574 /*
1575 * NVRAM host parameter block
1576 *
1577 * LSB BIT 0 = Enable spinup delay
1578 * LSB BIT 1 = Disable BIOS
1579 * LSB BIT 2 = Enable Memory Map BIOS
1580 * LSB BIT 3 = Enable Selectable Boot
1581 * LSB BIT 4 = Disable RISC code load
1582 * LSB BIT 5 = Set cache line size 1
1583 * LSB BIT 6 = PCI Parity Disable
1584 * LSB BIT 7 = Enable extended logging
1585 *
1586 * MSB BIT 0 = Enable 64bit addressing
1587 * MSB BIT 1 = Enable lip reset
1588 * MSB BIT 2 = Enable lip full login
1589 * MSB BIT 3 = Enable target reset
1590 * MSB BIT 4 = Enable database storage
1591 * MSB BIT 5 = Enable cache flush read
1592 * MSB BIT 6 = Enable database load
1593 * MSB BIT 7 = Enable alternate WWN
1594 */
1595 uint8_t host_p[2];
1596
1597 uint8_t boot_node_name[WWN_SIZE];
1598 uint8_t boot_lun_number;
1599 uint8_t reset_delay;
1600 uint8_t port_down_retry_count;
1601 uint8_t boot_id_number;
1602 uint16_t max_luns_per_target;
1603 uint8_t fcode_boot_port_name[WWN_SIZE];
1604 uint8_t alternate_port_name[WWN_SIZE];
1605 uint8_t alternate_node_name[WWN_SIZE];
1606
1607 /*
1608 * BIT 0 = Selective Login
1609 * BIT 1 = Alt-Boot Enable
1610 * BIT 2 =
1611 * BIT 3 = Boot Order List
1612 * BIT 4 =
1613 * BIT 5 = Selective LUN
1614 * BIT 6 =
1615 * BIT 7 = unused
1616 */
1617 uint8_t efi_parameters;
1618
1619 uint8_t link_down_timeout;
1620
1621 uint8_t adapter_id[16];
1622
1623 uint8_t alt1_boot_node_name[WWN_SIZE];
1624 uint16_t alt1_boot_lun_number;
1625 uint8_t alt2_boot_node_name[WWN_SIZE];
1626 uint16_t alt2_boot_lun_number;
1627 uint8_t alt3_boot_node_name[WWN_SIZE];
1628 uint16_t alt3_boot_lun_number;
1629 uint8_t alt4_boot_node_name[WWN_SIZE];
1630 uint16_t alt4_boot_lun_number;
1631 uint8_t alt5_boot_node_name[WWN_SIZE];
1632 uint16_t alt5_boot_lun_number;
1633 uint8_t alt6_boot_node_name[WWN_SIZE];
1634 uint16_t alt6_boot_lun_number;
1635 uint8_t alt7_boot_node_name[WWN_SIZE];
1636 uint16_t alt7_boot_lun_number;
1637
1638 uint8_t reserved_3[2];
1639
1640 /* Offset 200-215 : Model Number */
1641 uint8_t model_number[16];
1642
1643 /* OEM related items */
1644 uint8_t oem_specific[16];
1645
1646 /*
1647 * NVRAM Adapter Features offset 232-239
1648 *
1649 * LSB BIT 0 = External GBIC
1650 * LSB BIT 1 = Risc RAM parity
1651 * LSB BIT 2 = Buffer Plus Module
1652 * LSB BIT 3 = Multi Chip Adapter
1653 * LSB BIT 4 = Internal connector
1654 * LSB BIT 5 =
1655 * LSB BIT 6 =
1656 * LSB BIT 7 =
1657 *
1658 * MSB BIT 0 =
1659 * MSB BIT 1 =
1660 * MSB BIT 2 =
1661 * MSB BIT 3 =
1662 * MSB BIT 4 =
1663 * MSB BIT 5 =
1664 * MSB BIT 6 =
1665 * MSB BIT 7 =
1666 */
1667 uint8_t adapter_features[2];
1668
1669 uint8_t reserved_4[16];
1670
1671 /* Subsystem vendor ID for ISP2200 */
1672 uint16_t subsystem_vendor_id_2200;
1673
1674 /* Subsystem device ID for ISP2200 */
1675 uint16_t subsystem_device_id_2200;
1676
1677 uint8_t reserved_5;
1678 uint8_t checksum;
1679 } nvram_t;
1680
1681 /*
1682 * ISP queue - response queue entry definition.
1683 */
1684 typedef struct {
1685 uint8_t entry_type; /* Entry type. */
1686 uint8_t entry_count; /* Entry count. */
1687 uint8_t sys_define; /* System defined. */
1688 uint8_t entry_status; /* Entry Status. */
1689 uint32_t handle; /* System defined handle */
1690 uint8_t data[52];
1691 uint32_t signature;
1692 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1693 } response_t;
1694
1695 /*
1696 * ISP queue - ATIO queue entry definition.
1697 */
1698 struct atio {
1699 uint8_t entry_type; /* Entry type. */
1700 uint8_t entry_count; /* Entry count. */
1701 __le16 attr_n_length;
1702 uint8_t data[56];
1703 uint32_t signature;
1704 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1705 };
1706
1707 typedef union {
1708 uint16_t extended;
1709 struct {
1710 uint8_t reserved;
1711 uint8_t standard;
1712 } id;
1713 } target_id_t;
1714
1715 #define SET_TARGET_ID(ha, to, from) \
1716 do { \
1717 if (HAS_EXTENDED_IDS(ha)) \
1718 to.extended = cpu_to_le16(from); \
1719 else \
1720 to.id.standard = (uint8_t)from; \
1721 } while (0)
1722
1723 /*
1724 * ISP queue - command entry structure definition.
1725 */
1726 #define COMMAND_TYPE 0x11 /* Command entry */
1727 typedef struct {
1728 uint8_t entry_type; /* Entry type. */
1729 uint8_t entry_count; /* Entry count. */
1730 uint8_t sys_define; /* System defined. */
1731 uint8_t entry_status; /* Entry Status. */
1732 uint32_t handle; /* System handle. */
1733 target_id_t target; /* SCSI ID */
1734 uint16_t lun; /* SCSI LUN */
1735 uint16_t control_flags; /* Control flags. */
1736 #define CF_WRITE BIT_6
1737 #define CF_READ BIT_5
1738 #define CF_SIMPLE_TAG BIT_3
1739 #define CF_ORDERED_TAG BIT_2
1740 #define CF_HEAD_TAG BIT_1
1741 uint16_t reserved_1;
1742 uint16_t timeout; /* Command timeout. */
1743 uint16_t dseg_count; /* Data segment count. */
1744 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1745 uint32_t byte_count; /* Total byte count. */
1746 uint32_t dseg_0_address; /* Data segment 0 address. */
1747 uint32_t dseg_0_length; /* Data segment 0 length. */
1748 uint32_t dseg_1_address; /* Data segment 1 address. */
1749 uint32_t dseg_1_length; /* Data segment 1 length. */
1750 uint32_t dseg_2_address; /* Data segment 2 address. */
1751 uint32_t dseg_2_length; /* Data segment 2 length. */
1752 } cmd_entry_t;
1753
1754 /*
1755 * ISP queue - 64-Bit addressing, command entry structure definition.
1756 */
1757 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1758 typedef struct {
1759 uint8_t entry_type; /* Entry type. */
1760 uint8_t entry_count; /* Entry count. */
1761 uint8_t sys_define; /* System defined. */
1762 uint8_t entry_status; /* Entry Status. */
1763 uint32_t handle; /* System handle. */
1764 target_id_t target; /* SCSI ID */
1765 uint16_t lun; /* SCSI LUN */
1766 uint16_t control_flags; /* Control flags. */
1767 uint16_t reserved_1;
1768 uint16_t timeout; /* Command timeout. */
1769 uint16_t dseg_count; /* Data segment count. */
1770 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1771 uint32_t byte_count; /* Total byte count. */
1772 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1773 uint32_t dseg_0_length; /* Data segment 0 length. */
1774 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1775 uint32_t dseg_1_length; /* Data segment 1 length. */
1776 } cmd_a64_entry_t, request_t;
1777
1778 /*
1779 * ISP queue - continuation entry structure definition.
1780 */
1781 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1782 typedef struct {
1783 uint8_t entry_type; /* Entry type. */
1784 uint8_t entry_count; /* Entry count. */
1785 uint8_t sys_define; /* System defined. */
1786 uint8_t entry_status; /* Entry Status. */
1787 uint32_t reserved;
1788 uint32_t dseg_0_address; /* Data segment 0 address. */
1789 uint32_t dseg_0_length; /* Data segment 0 length. */
1790 uint32_t dseg_1_address; /* Data segment 1 address. */
1791 uint32_t dseg_1_length; /* Data segment 1 length. */
1792 uint32_t dseg_2_address; /* Data segment 2 address. */
1793 uint32_t dseg_2_length; /* Data segment 2 length. */
1794 uint32_t dseg_3_address; /* Data segment 3 address. */
1795 uint32_t dseg_3_length; /* Data segment 3 length. */
1796 uint32_t dseg_4_address; /* Data segment 4 address. */
1797 uint32_t dseg_4_length; /* Data segment 4 length. */
1798 uint32_t dseg_5_address; /* Data segment 5 address. */
1799 uint32_t dseg_5_length; /* Data segment 5 length. */
1800 uint32_t dseg_6_address; /* Data segment 6 address. */
1801 uint32_t dseg_6_length; /* Data segment 6 length. */
1802 } cont_entry_t;
1803
1804 /*
1805 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1806 */
1807 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1808 typedef struct {
1809 uint8_t entry_type; /* Entry type. */
1810 uint8_t entry_count; /* Entry count. */
1811 uint8_t sys_define; /* System defined. */
1812 uint8_t entry_status; /* Entry Status. */
1813 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1814 uint32_t dseg_0_length; /* Data segment 0 length. */
1815 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1816 uint32_t dseg_1_length; /* Data segment 1 length. */
1817 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1818 uint32_t dseg_2_length; /* Data segment 2 length. */
1819 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1820 uint32_t dseg_3_length; /* Data segment 3 length. */
1821 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1822 uint32_t dseg_4_length; /* Data segment 4 length. */
1823 } cont_a64_entry_t;
1824
1825 #define PO_MODE_DIF_INSERT 0
1826 #define PO_MODE_DIF_REMOVE 1
1827 #define PO_MODE_DIF_PASS 2
1828 #define PO_MODE_DIF_REPLACE 3
1829 #define PO_MODE_DIF_TCP_CKSUM 6
1830 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1831 #define PO_DISABLE_GUARD_CHECK BIT_4
1832 #define PO_DISABLE_INCR_REF_TAG BIT_5
1833 #define PO_DIS_HEADER_MODE BIT_7
1834 #define PO_ENABLE_DIF_BUNDLING BIT_8
1835 #define PO_DIS_FRAME_MODE BIT_9
1836 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1837 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1838
1839 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1840 #define PO_DIS_REF_TAG_REPL BIT_13
1841 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1842 #define PO_DIS_REF_TAG_VALD BIT_15
1843
1844 /*
1845 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1846 */
1847 struct crc_context {
1848 uint32_t handle; /* System handle. */
1849 __le32 ref_tag;
1850 __le16 app_tag;
1851 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1852 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1853 __le16 guard_seed; /* Initial Guard Seed */
1854 __le16 prot_opts; /* Requested Data Protection Mode */
1855 __le16 blk_size; /* Data size in bytes */
1856 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1857 * only) */
1858 __le32 byte_count; /* Total byte count/ total data
1859 * transfer count */
1860 union {
1861 struct {
1862 uint32_t reserved_1;
1863 uint16_t reserved_2;
1864 uint16_t reserved_3;
1865 uint32_t reserved_4;
1866 uint32_t data_address[2];
1867 uint32_t data_length;
1868 uint32_t reserved_5[2];
1869 uint32_t reserved_6;
1870 } nobundling;
1871 struct {
1872 __le32 dif_byte_count; /* Total DIF byte
1873 * count */
1874 uint16_t reserved_1;
1875 __le16 dseg_count; /* Data segment count */
1876 uint32_t reserved_2;
1877 uint32_t data_address[2];
1878 uint32_t data_length;
1879 uint32_t dif_address[2];
1880 uint32_t dif_length; /* Data segment 0
1881 * length */
1882 } bundling;
1883 } u;
1884
1885 struct fcp_cmnd fcp_cmnd;
1886 dma_addr_t crc_ctx_dma;
1887 /* List of DMA context transfers */
1888 struct list_head dsd_list;
1889
1890 /* This structure should not exceed 512 bytes */
1891 };
1892
1893 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1894 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1895
1896 /*
1897 * ISP queue - status entry structure definition.
1898 */
1899 #define STATUS_TYPE 0x03 /* Status entry. */
1900 typedef struct {
1901 uint8_t entry_type; /* Entry type. */
1902 uint8_t entry_count; /* Entry count. */
1903 uint8_t sys_define; /* System defined. */
1904 uint8_t entry_status; /* Entry Status. */
1905 uint32_t handle; /* System handle. */
1906 uint16_t scsi_status; /* SCSI status. */
1907 uint16_t comp_status; /* Completion status. */
1908 uint16_t state_flags; /* State flags. */
1909 uint16_t status_flags; /* Status flags. */
1910 uint16_t rsp_info_len; /* Response Info Length. */
1911 uint16_t req_sense_length; /* Request sense data length. */
1912 uint32_t residual_length; /* Residual transfer length. */
1913 uint8_t rsp_info[8]; /* FCP response information. */
1914 uint8_t req_sense_data[32]; /* Request sense data. */
1915 } sts_entry_t;
1916
1917 /*
1918 * Status entry entry status
1919 */
1920 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1921 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1922 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1923 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1924 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1925 #define RF_BUSY BIT_1 /* Busy */
1926 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1927 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1928 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1929 RF_INV_E_TYPE)
1930
1931 /*
1932 * Status entry SCSI status bit definitions.
1933 */
1934 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1935 #define SS_RESIDUAL_UNDER BIT_11
1936 #define SS_RESIDUAL_OVER BIT_10
1937 #define SS_SENSE_LEN_VALID BIT_9
1938 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1939 #define SS_SCSI_STATUS_BYTE 0xff
1940
1941 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1942 #define SS_BUSY_CONDITION BIT_3
1943 #define SS_CONDITION_MET BIT_2
1944 #define SS_CHECK_CONDITION BIT_1
1945
1946 /*
1947 * Status entry completion status
1948 */
1949 #define CS_COMPLETE 0x0 /* No errors */
1950 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1951 #define CS_DMA 0x2 /* A DMA direction error. */
1952 #define CS_TRANSPORT 0x3 /* Transport error. */
1953 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1954 #define CS_ABORTED 0x5 /* System aborted command. */
1955 #define CS_TIMEOUT 0x6 /* Timeout error. */
1956 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1957 #define CS_DIF_ERROR 0xC /* DIF error detected */
1958
1959 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1960 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1961 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1962 /* (selection timeout) */
1963 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1964 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1965 #define CS_PORT_BUSY 0x2B /* Port Busy */
1966 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1967 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
1968 failure */
1969 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1970 #define CS_UNKNOWN 0x81 /* Driver defined */
1971 #define CS_RETRY 0x82 /* Driver defined */
1972 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1973
1974 #define CS_BIDIR_RD_OVERRUN 0x700
1975 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1976 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1977 #define CS_BIDIR_RD_UNDERRUN 0x1500
1978 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1979 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1980 #define CS_BIDIR_DMA 0x200
1981 /*
1982 * Status entry status flags
1983 */
1984 #define SF_ABTS_TERMINATED BIT_10
1985 #define SF_LOGOUT_SENT BIT_13
1986
1987 /*
1988 * ISP queue - status continuation entry structure definition.
1989 */
1990 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1991 typedef struct {
1992 uint8_t entry_type; /* Entry type. */
1993 uint8_t entry_count; /* Entry count. */
1994 uint8_t sys_define; /* System defined. */
1995 uint8_t entry_status; /* Entry Status. */
1996 uint8_t data[60]; /* data */
1997 } sts_cont_entry_t;
1998
1999 /*
2000 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
2001 * structure definition.
2002 */
2003 #define STATUS_TYPE_21 0x21 /* Status entry. */
2004 typedef struct {
2005 uint8_t entry_type; /* Entry type. */
2006 uint8_t entry_count; /* Entry count. */
2007 uint8_t handle_count; /* Handle count. */
2008 uint8_t entry_status; /* Entry Status. */
2009 uint32_t handle[15]; /* System handles. */
2010 } sts21_entry_t;
2011
2012 /*
2013 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
2014 * structure definition.
2015 */
2016 #define STATUS_TYPE_22 0x22 /* Status entry. */
2017 typedef struct {
2018 uint8_t entry_type; /* Entry type. */
2019 uint8_t entry_count; /* Entry count. */
2020 uint8_t handle_count; /* Handle count. */
2021 uint8_t entry_status; /* Entry Status. */
2022 uint16_t handle[30]; /* System handles. */
2023 } sts22_entry_t;
2024
2025 /*
2026 * ISP queue - marker entry structure definition.
2027 */
2028 #define MARKER_TYPE 0x04 /* Marker entry. */
2029 typedef struct {
2030 uint8_t entry_type; /* Entry type. */
2031 uint8_t entry_count; /* Entry count. */
2032 uint8_t handle_count; /* Handle count. */
2033 uint8_t entry_status; /* Entry Status. */
2034 uint32_t sys_define_2; /* System defined. */
2035 target_id_t target; /* SCSI ID */
2036 uint8_t modifier; /* Modifier (7-0). */
2037 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2038 #define MK_SYNC_ID 1 /* Synchronize ID */
2039 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2040 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2041 /* clear port changed, */
2042 /* use sequence number. */
2043 uint8_t reserved_1;
2044 uint16_t sequence_number; /* Sequence number of event */
2045 uint16_t lun; /* SCSI LUN */
2046 uint8_t reserved_2[48];
2047 } mrk_entry_t;
2048
2049 /*
2050 * ISP queue - Management Server entry structure definition.
2051 */
2052 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2053 typedef struct {
2054 uint8_t entry_type; /* Entry type. */
2055 uint8_t entry_count; /* Entry count. */
2056 uint8_t handle_count; /* Handle count. */
2057 uint8_t entry_status; /* Entry Status. */
2058 uint32_t handle1; /* System handle. */
2059 target_id_t loop_id;
2060 uint16_t status;
2061 uint16_t control_flags; /* Control flags. */
2062 uint16_t reserved2;
2063 uint16_t timeout;
2064 uint16_t cmd_dsd_count;
2065 uint16_t total_dsd_count;
2066 uint8_t type;
2067 uint8_t r_ctl;
2068 uint16_t rx_id;
2069 uint16_t reserved3;
2070 uint32_t handle2;
2071 uint32_t rsp_bytecount;
2072 uint32_t req_bytecount;
2073 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
2074 uint32_t dseg_req_length; /* Data segment 0 length. */
2075 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
2076 uint32_t dseg_rsp_length; /* Data segment 1 length. */
2077 } ms_iocb_entry_t;
2078
2079
2080 /*
2081 * ISP queue - Mailbox Command entry structure definition.
2082 */
2083 #define MBX_IOCB_TYPE 0x39
2084 struct mbx_entry {
2085 uint8_t entry_type;
2086 uint8_t entry_count;
2087 uint8_t sys_define1;
2088 /* Use sys_define1 for source type */
2089 #define SOURCE_SCSI 0x00
2090 #define SOURCE_IP 0x01
2091 #define SOURCE_VI 0x02
2092 #define SOURCE_SCTP 0x03
2093 #define SOURCE_MP 0x04
2094 #define SOURCE_MPIOCTL 0x05
2095 #define SOURCE_ASYNC_IOCB 0x07
2096
2097 uint8_t entry_status;
2098
2099 uint32_t handle;
2100 target_id_t loop_id;
2101
2102 uint16_t status;
2103 uint16_t state_flags;
2104 uint16_t status_flags;
2105
2106 uint32_t sys_define2[2];
2107
2108 uint16_t mb0;
2109 uint16_t mb1;
2110 uint16_t mb2;
2111 uint16_t mb3;
2112 uint16_t mb6;
2113 uint16_t mb7;
2114 uint16_t mb9;
2115 uint16_t mb10;
2116 uint32_t reserved_2[2];
2117 uint8_t node_name[WWN_SIZE];
2118 uint8_t port_name[WWN_SIZE];
2119 };
2120
2121 #ifndef IMMED_NOTIFY_TYPE
2122 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2123 /*
2124 * ISP queue - immediate notify entry structure definition.
2125 * This is sent by the ISP to the Target driver.
2126 * This IOCB would have report of events sent by the
2127 * initiator, that needs to be handled by the target
2128 * driver immediately.
2129 */
2130 struct imm_ntfy_from_isp {
2131 uint8_t entry_type; /* Entry type. */
2132 uint8_t entry_count; /* Entry count. */
2133 uint8_t sys_define; /* System defined. */
2134 uint8_t entry_status; /* Entry Status. */
2135 union {
2136 struct {
2137 uint32_t sys_define_2; /* System defined. */
2138 target_id_t target;
2139 uint16_t lun;
2140 uint8_t target_id;
2141 uint8_t reserved_1;
2142 uint16_t status_modifier;
2143 uint16_t status;
2144 uint16_t task_flags;
2145 uint16_t seq_id;
2146 uint16_t srr_rx_id;
2147 uint32_t srr_rel_offs;
2148 uint16_t srr_ui;
2149 #define SRR_IU_DATA_IN 0x1
2150 #define SRR_IU_DATA_OUT 0x5
2151 #define SRR_IU_STATUS 0x7
2152 uint16_t srr_ox_id;
2153 uint8_t reserved_2[28];
2154 } isp2x;
2155 struct {
2156 uint32_t reserved;
2157 uint16_t nport_handle;
2158 uint16_t reserved_2;
2159 uint16_t flags;
2160 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2161 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2162 uint16_t srr_rx_id;
2163 uint16_t status;
2164 uint8_t status_subcode;
2165 uint8_t fw_handle;
2166 uint32_t exchange_address;
2167 uint32_t srr_rel_offs;
2168 uint16_t srr_ui;
2169 uint16_t srr_ox_id;
2170 union {
2171 struct {
2172 uint8_t node_name[8];
2173 } plogi; /* PLOGI/ADISC/PDISC */
2174 struct {
2175 /* PRLI word 3 bit 0-15 */
2176 uint16_t wd3_lo;
2177 uint8_t resv0[6];
2178 } prli;
2179 struct {
2180 uint8_t port_id[3];
2181 uint8_t resv1;
2182 uint16_t nport_handle;
2183 uint16_t resv2;
2184 } req_els;
2185 } u;
2186 uint8_t port_name[8];
2187 uint8_t resv3[3];
2188 uint8_t vp_index;
2189 uint32_t reserved_5;
2190 uint8_t port_id[3];
2191 uint8_t reserved_6;
2192 } isp24;
2193 } u;
2194 uint16_t reserved_7;
2195 uint16_t ox_id;
2196 } __packed;
2197 #endif
2198
2199 /*
2200 * ISP request and response queue entry sizes
2201 */
2202 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2203 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2204
2205
2206
2207 /*
2208 * Switch info gathering structure.
2209 */
2210 typedef struct {
2211 port_id_t d_id;
2212 uint8_t node_name[WWN_SIZE];
2213 uint8_t port_name[WWN_SIZE];
2214 uint8_t fabric_port_name[WWN_SIZE];
2215 uint16_t fp_speed;
2216 uint8_t fc4_type;
2217 uint8_t fc4f_nvme; /* nvme fc4 feature bits */
2218 } sw_info_t;
2219
2220 /* FCP-4 types */
2221 #define FC4_TYPE_FCP_SCSI 0x08
2222 #define FC4_TYPE_NVME 0x28
2223 #define FC4_TYPE_OTHER 0x0
2224 #define FC4_TYPE_UNKNOWN 0xff
2225
2226 /* mailbox command 4G & above */
2227 struct mbx_24xx_entry {
2228 uint8_t entry_type;
2229 uint8_t entry_count;
2230 uint8_t sys_define1;
2231 uint8_t entry_status;
2232 uint32_t handle;
2233 uint16_t mb[28];
2234 };
2235
2236 #define IOCB_SIZE 64
2237
2238 /*
2239 * Fibre channel port type.
2240 */
2241 typedef enum {
2242 FCT_UNKNOWN,
2243 FCT_RSCN,
2244 FCT_SWITCH,
2245 FCT_BROADCAST,
2246 FCT_INITIATOR,
2247 FCT_TARGET,
2248 FCT_NVME
2249 } fc_port_type_t;
2250
2251 enum qla_sess_deletion {
2252 QLA_SESS_DELETION_NONE = 0,
2253 QLA_SESS_DELETION_IN_PROGRESS,
2254 QLA_SESS_DELETED,
2255 };
2256
2257 enum qlt_plogi_link_t {
2258 QLT_PLOGI_LINK_SAME_WWN,
2259 QLT_PLOGI_LINK_CONFLICT,
2260 QLT_PLOGI_LINK_MAX
2261 };
2262
2263 struct qlt_plogi_ack_t {
2264 struct list_head list;
2265 struct imm_ntfy_from_isp iocb;
2266 port_id_t id;
2267 int ref_count;
2268 void *fcport;
2269 };
2270
2271 struct ct_sns_desc {
2272 struct ct_sns_pkt *ct_sns;
2273 dma_addr_t ct_sns_dma;
2274 };
2275
2276 enum discovery_state {
2277 DSC_DELETED,
2278 DSC_GNN_ID,
2279 DSC_GID_PN,
2280 DSC_GNL,
2281 DSC_LOGIN_PEND,
2282 DSC_LOGIN_FAILED,
2283 DSC_GPDB,
2284 DSC_UPD_FCPORT,
2285 DSC_LOGIN_COMPLETE,
2286 DSC_ADISC,
2287 DSC_DELETE_PEND,
2288 };
2289
2290 enum login_state { /* FW control Target side */
2291 DSC_LS_LLIOCB_SENT = 2,
2292 DSC_LS_PLOGI_PEND,
2293 DSC_LS_PLOGI_COMP,
2294 DSC_LS_PRLI_PEND,
2295 DSC_LS_PRLI_COMP,
2296 DSC_LS_PORT_UNAVAIL,
2297 DSC_LS_PRLO_PEND = 9,
2298 DSC_LS_LOGO_PEND,
2299 };
2300
2301 enum fcport_mgt_event {
2302 FCME_RELOGIN = 1,
2303 FCME_RSCN,
2304 FCME_GIDPN_DONE,
2305 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */
2306 FCME_PRLI_DONE,
2307 FCME_GNL_DONE,
2308 FCME_GPSC_DONE,
2309 FCME_GPDB_DONE,
2310 FCME_GPNID_DONE,
2311 FCME_GFFID_DONE,
2312 FCME_ADISC_DONE,
2313 FCME_GNNID_DONE,
2314 FCME_GFPNID_DONE,
2315 };
2316
2317 enum rscn_addr_format {
2318 RSCN_PORT_ADDR,
2319 RSCN_AREA_ADDR,
2320 RSCN_DOM_ADDR,
2321 RSCN_FAB_ADDR,
2322 };
2323
2324 /*
2325 * Fibre channel port structure.
2326 */
2327 typedef struct fc_port {
2328 struct list_head list;
2329 struct scsi_qla_host *vha;
2330
2331 uint8_t node_name[WWN_SIZE];
2332 uint8_t port_name[WWN_SIZE];
2333 port_id_t d_id;
2334 uint16_t loop_id;
2335 uint16_t old_loop_id;
2336
2337 unsigned int conf_compl_supported:1;
2338 unsigned int deleted:2;
2339 unsigned int free_pending:1;
2340 unsigned int local:1;
2341 unsigned int logout_on_delete:1;
2342 unsigned int logo_ack_needed:1;
2343 unsigned int keep_nport_handle:1;
2344 unsigned int send_els_logo:1;
2345 unsigned int login_pause:1;
2346 unsigned int login_succ:1;
2347 unsigned int query:1;
2348 unsigned int id_changed:1;
2349 unsigned int rscn_rcvd:1;
2350
2351 struct work_struct nvme_del_work;
2352 struct completion nvme_del_done;
2353 uint32_t nvme_prli_service_param;
2354 #define NVME_PRLI_SP_CONF BIT_7
2355 #define NVME_PRLI_SP_INITIATOR BIT_5
2356 #define NVME_PRLI_SP_TARGET BIT_4
2357 #define NVME_PRLI_SP_DISCOVERY BIT_3
2358 uint8_t nvme_flag;
2359 #define NVME_FLAG_REGISTERED 4
2360 #define NVME_FLAG_DELETING 2
2361 #define NVME_FLAG_RESETTING 1
2362
2363 struct fc_port *conflict;
2364 unsigned char logout_completed;
2365 int generation;
2366
2367 struct se_session *se_sess;
2368 struct kref sess_kref;
2369 struct qla_tgt *tgt;
2370 unsigned long expires;
2371 struct list_head del_list_entry;
2372 struct work_struct free_work;
2373
2374 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2375
2376 uint16_t tgt_id;
2377 uint16_t old_tgt_id;
2378
2379 uint8_t fcp_prio;
2380
2381 uint8_t fabric_port_name[WWN_SIZE];
2382 uint16_t fp_speed;
2383
2384 fc_port_type_t port_type;
2385
2386 atomic_t state;
2387 uint32_t flags;
2388
2389 int login_retry;
2390
2391 struct fc_rport *rport, *drport;
2392 u32 supported_classes;
2393
2394 uint8_t fc4_type;
2395 uint8_t fc4f_nvme;
2396 uint8_t scan_state;
2397 uint8_t n2n_flag;
2398
2399 unsigned long last_queue_full;
2400 unsigned long last_ramp_up;
2401
2402 uint16_t port_id;
2403
2404 struct nvme_fc_remote_port *nvme_remote_port;
2405
2406 unsigned long retry_delay_timestamp;
2407 struct qla_tgt_sess *tgt_session;
2408 struct ct_sns_desc ct_desc;
2409 enum discovery_state disc_state;
2410 enum login_state fw_login_state;
2411 unsigned long plogi_nack_done_deadline;
2412
2413 u32 login_gen, last_login_gen;
2414 u32 rscn_gen, last_rscn_gen;
2415 u32 chip_reset;
2416 struct list_head gnl_entry;
2417 struct work_struct del_work;
2418 u8 iocb[IOCB_SIZE];
2419 u8 current_login_state;
2420 u8 last_login_state;
2421 struct completion n2n_done;
2422 } fc_port_t;
2423
2424 #define QLA_FCPORT_SCAN 1
2425 #define QLA_FCPORT_FOUND 2
2426
2427 struct event_arg {
2428 enum fcport_mgt_event event;
2429 fc_port_t *fcport;
2430 srb_t *sp;
2431 port_id_t id;
2432 u16 data[2], rc;
2433 u8 port_name[WWN_SIZE];
2434 u32 iop[2];
2435 };
2436
2437 #include "qla_mr.h"
2438
2439 /*
2440 * Fibre channel port/lun states.
2441 */
2442 #define FCS_UNCONFIGURED 1
2443 #define FCS_DEVICE_DEAD 2
2444 #define FCS_DEVICE_LOST 3
2445 #define FCS_ONLINE 4
2446
2447 static const char * const port_state_str[] = {
2448 "Unknown",
2449 "UNCONFIGURED",
2450 "DEAD",
2451 "LOST",
2452 "ONLINE"
2453 };
2454
2455 /*
2456 * FC port flags.
2457 */
2458 #define FCF_FABRIC_DEVICE BIT_0
2459 #define FCF_LOGIN_NEEDED BIT_1
2460 #define FCF_FCP2_DEVICE BIT_2
2461 #define FCF_ASYNC_SENT BIT_3
2462 #define FCF_CONF_COMP_SUPPORTED BIT_4
2463 #define FCF_ASYNC_ACTIVE BIT_5
2464
2465 /* No loop ID flag. */
2466 #define FC_NO_LOOP_ID 0x1000
2467
2468 /*
2469 * FC-CT interface
2470 *
2471 * NOTE: All structures are big-endian in form.
2472 */
2473
2474 #define CT_REJECT_RESPONSE 0x8001
2475 #define CT_ACCEPT_RESPONSE 0x8002
2476 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2477 #define CT_REASON_CANNOT_PERFORM 0x09
2478 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2479 #define CT_EXPL_ALREADY_REGISTERED 0x10
2480 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2481 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2482 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2483 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2484 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2485 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2486 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2487 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2488 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2489 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2490 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2491
2492 #define NS_N_PORT_TYPE 0x01
2493 #define NS_NL_PORT_TYPE 0x02
2494 #define NS_NX_PORT_TYPE 0x7F
2495
2496 #define GA_NXT_CMD 0x100
2497 #define GA_NXT_REQ_SIZE (16 + 4)
2498 #define GA_NXT_RSP_SIZE (16 + 620)
2499
2500 #define GPN_FT_CMD 0x172
2501 #define GPN_FT_REQ_SIZE (16 + 4)
2502 #define GNN_FT_CMD 0x173
2503 #define GNN_FT_REQ_SIZE (16 + 4)
2504
2505 #define GID_PT_CMD 0x1A1
2506 #define GID_PT_REQ_SIZE (16 + 4)
2507
2508 #define GPN_ID_CMD 0x112
2509 #define GPN_ID_REQ_SIZE (16 + 4)
2510 #define GPN_ID_RSP_SIZE (16 + 8)
2511
2512 #define GNN_ID_CMD 0x113
2513 #define GNN_ID_REQ_SIZE (16 + 4)
2514 #define GNN_ID_RSP_SIZE (16 + 8)
2515
2516 #define GFT_ID_CMD 0x117
2517 #define GFT_ID_REQ_SIZE (16 + 4)
2518 #define GFT_ID_RSP_SIZE (16 + 32)
2519
2520 #define GID_PN_CMD 0x121
2521 #define GID_PN_REQ_SIZE (16 + 8)
2522 #define GID_PN_RSP_SIZE (16 + 4)
2523
2524 #define RFT_ID_CMD 0x217
2525 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2526 #define RFT_ID_RSP_SIZE 16
2527
2528 #define RFF_ID_CMD 0x21F
2529 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2530 #define RFF_ID_RSP_SIZE 16
2531
2532 #define RNN_ID_CMD 0x213
2533 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2534 #define RNN_ID_RSP_SIZE 16
2535
2536 #define RSNN_NN_CMD 0x239
2537 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2538 #define RSNN_NN_RSP_SIZE 16
2539
2540 #define GFPN_ID_CMD 0x11C
2541 #define GFPN_ID_REQ_SIZE (16 + 4)
2542 #define GFPN_ID_RSP_SIZE (16 + 8)
2543
2544 #define GPSC_CMD 0x127
2545 #define GPSC_REQ_SIZE (16 + 8)
2546 #define GPSC_RSP_SIZE (16 + 2 + 2)
2547
2548 #define GFF_ID_CMD 0x011F
2549 #define GFF_ID_REQ_SIZE (16 + 4)
2550 #define GFF_ID_RSP_SIZE (16 + 128)
2551
2552 /*
2553 * HBA attribute types.
2554 */
2555 #define FDMI_HBA_ATTR_COUNT 9
2556 #define FDMIV2_HBA_ATTR_COUNT 17
2557 #define FDMI_HBA_NODE_NAME 0x1
2558 #define FDMI_HBA_MANUFACTURER 0x2
2559 #define FDMI_HBA_SERIAL_NUMBER 0x3
2560 #define FDMI_HBA_MODEL 0x4
2561 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2562 #define FDMI_HBA_HARDWARE_VERSION 0x6
2563 #define FDMI_HBA_DRIVER_VERSION 0x7
2564 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2565 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2566 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2567 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2568 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2569 #define FDMI_HBA_VENDOR_ID 0xd
2570 #define FDMI_HBA_NUM_PORTS 0xe
2571 #define FDMI_HBA_FABRIC_NAME 0xf
2572 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2573 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2574
2575 struct ct_fdmi_hba_attr {
2576 uint16_t type;
2577 uint16_t len;
2578 union {
2579 uint8_t node_name[WWN_SIZE];
2580 uint8_t manufacturer[64];
2581 uint8_t serial_num[32];
2582 uint8_t model[16+1];
2583 uint8_t model_desc[80];
2584 uint8_t hw_version[32];
2585 uint8_t driver_version[32];
2586 uint8_t orom_version[16];
2587 uint8_t fw_version[32];
2588 uint8_t os_version[128];
2589 uint32_t max_ct_len;
2590 } a;
2591 };
2592
2593 struct ct_fdmi_hba_attributes {
2594 uint32_t count;
2595 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2596 };
2597
2598 struct ct_fdmiv2_hba_attr {
2599 uint16_t type;
2600 uint16_t len;
2601 union {
2602 uint8_t node_name[WWN_SIZE];
2603 uint8_t manufacturer[64];
2604 uint8_t serial_num[32];
2605 uint8_t model[16+1];
2606 uint8_t model_desc[80];
2607 uint8_t hw_version[16];
2608 uint8_t driver_version[32];
2609 uint8_t orom_version[16];
2610 uint8_t fw_version[32];
2611 uint8_t os_version[128];
2612 uint32_t max_ct_len;
2613 uint8_t sym_name[256];
2614 uint32_t vendor_id;
2615 uint32_t num_ports;
2616 uint8_t fabric_name[WWN_SIZE];
2617 uint8_t bios_name[32];
2618 uint8_t vendor_identifier[8];
2619 } a;
2620 };
2621
2622 struct ct_fdmiv2_hba_attributes {
2623 uint32_t count;
2624 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2625 };
2626
2627 /*
2628 * Port attribute types.
2629 */
2630 #define FDMI_PORT_ATTR_COUNT 6
2631 #define FDMIV2_PORT_ATTR_COUNT 16
2632 #define FDMI_PORT_FC4_TYPES 0x1
2633 #define FDMI_PORT_SUPPORT_SPEED 0x2
2634 #define FDMI_PORT_CURRENT_SPEED 0x3
2635 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2636 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2637 #define FDMI_PORT_HOST_NAME 0x6
2638 #define FDMI_PORT_NODE_NAME 0x7
2639 #define FDMI_PORT_NAME 0x8
2640 #define FDMI_PORT_SYM_NAME 0x9
2641 #define FDMI_PORT_TYPE 0xa
2642 #define FDMI_PORT_SUPP_COS 0xb
2643 #define FDMI_PORT_FABRIC_NAME 0xc
2644 #define FDMI_PORT_FC4_TYPE 0xd
2645 #define FDMI_PORT_STATE 0x101
2646 #define FDMI_PORT_COUNT 0x102
2647 #define FDMI_PORT_ID 0x103
2648
2649 #define FDMI_PORT_SPEED_1GB 0x1
2650 #define FDMI_PORT_SPEED_2GB 0x2
2651 #define FDMI_PORT_SPEED_10GB 0x4
2652 #define FDMI_PORT_SPEED_4GB 0x8
2653 #define FDMI_PORT_SPEED_8GB 0x10
2654 #define FDMI_PORT_SPEED_16GB 0x20
2655 #define FDMI_PORT_SPEED_32GB 0x40
2656 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2657
2658 #define FC_CLASS_2 0x04
2659 #define FC_CLASS_3 0x08
2660 #define FC_CLASS_2_3 0x0C
2661
2662 struct ct_fdmiv2_port_attr {
2663 uint16_t type;
2664 uint16_t len;
2665 union {
2666 uint8_t fc4_types[32];
2667 uint32_t sup_speed;
2668 uint32_t cur_speed;
2669 uint32_t max_frame_size;
2670 uint8_t os_dev_name[32];
2671 uint8_t host_name[256];
2672 uint8_t node_name[WWN_SIZE];
2673 uint8_t port_name[WWN_SIZE];
2674 uint8_t port_sym_name[128];
2675 uint32_t port_type;
2676 uint32_t port_supported_cos;
2677 uint8_t fabric_name[WWN_SIZE];
2678 uint8_t port_fc4_type[32];
2679 uint32_t port_state;
2680 uint32_t num_ports;
2681 uint32_t port_id;
2682 } a;
2683 };
2684
2685 /*
2686 * Port Attribute Block.
2687 */
2688 struct ct_fdmiv2_port_attributes {
2689 uint32_t count;
2690 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2691 };
2692
2693 struct ct_fdmi_port_attr {
2694 uint16_t type;
2695 uint16_t len;
2696 union {
2697 uint8_t fc4_types[32];
2698 uint32_t sup_speed;
2699 uint32_t cur_speed;
2700 uint32_t max_frame_size;
2701 uint8_t os_dev_name[32];
2702 uint8_t host_name[256];
2703 } a;
2704 };
2705
2706 struct ct_fdmi_port_attributes {
2707 uint32_t count;
2708 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2709 };
2710
2711 /* FDMI definitions. */
2712 #define GRHL_CMD 0x100
2713 #define GHAT_CMD 0x101
2714 #define GRPL_CMD 0x102
2715 #define GPAT_CMD 0x110
2716
2717 #define RHBA_CMD 0x200
2718 #define RHBA_RSP_SIZE 16
2719
2720 #define RHAT_CMD 0x201
2721 #define RPRT_CMD 0x210
2722
2723 #define RPA_CMD 0x211
2724 #define RPA_RSP_SIZE 16
2725
2726 #define DHBA_CMD 0x300
2727 #define DHBA_REQ_SIZE (16 + 8)
2728 #define DHBA_RSP_SIZE 16
2729
2730 #define DHAT_CMD 0x301
2731 #define DPRT_CMD 0x310
2732 #define DPA_CMD 0x311
2733
2734 /* CT command header -- request/response common fields */
2735 struct ct_cmd_hdr {
2736 uint8_t revision;
2737 uint8_t in_id[3];
2738 uint8_t gs_type;
2739 uint8_t gs_subtype;
2740 uint8_t options;
2741 uint8_t reserved;
2742 };
2743
2744 /* CT command request */
2745 struct ct_sns_req {
2746 struct ct_cmd_hdr header;
2747 uint16_t command;
2748 uint16_t max_rsp_size;
2749 uint8_t fragment_id;
2750 uint8_t reserved[3];
2751
2752 union {
2753 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2754 struct {
2755 uint8_t reserved;
2756 uint8_t port_id[3];
2757 } port_id;
2758
2759 struct {
2760 uint8_t reserved;
2761 uint8_t domain;
2762 uint8_t area;
2763 uint8_t port_type;
2764 } gpn_ft;
2765
2766 struct {
2767 uint8_t port_type;
2768 uint8_t domain;
2769 uint8_t area;
2770 uint8_t reserved;
2771 } gid_pt;
2772
2773 struct {
2774 uint8_t reserved;
2775 uint8_t port_id[3];
2776 uint8_t fc4_types[32];
2777 } rft_id;
2778
2779 struct {
2780 uint8_t reserved;
2781 uint8_t port_id[3];
2782 uint16_t reserved2;
2783 uint8_t fc4_feature;
2784 uint8_t fc4_type;
2785 } rff_id;
2786
2787 struct {
2788 uint8_t reserved;
2789 uint8_t port_id[3];
2790 uint8_t node_name[8];
2791 } rnn_id;
2792
2793 struct {
2794 uint8_t node_name[8];
2795 uint8_t name_len;
2796 uint8_t sym_node_name[255];
2797 } rsnn_nn;
2798
2799 struct {
2800 uint8_t hba_identifier[8];
2801 } ghat;
2802
2803 struct {
2804 uint8_t hba_identifier[8];
2805 uint32_t entry_count;
2806 uint8_t port_name[8];
2807 struct ct_fdmi_hba_attributes attrs;
2808 } rhba;
2809
2810 struct {
2811 uint8_t hba_identifier[8];
2812 uint32_t entry_count;
2813 uint8_t port_name[8];
2814 struct ct_fdmiv2_hba_attributes attrs;
2815 } rhba2;
2816
2817 struct {
2818 uint8_t hba_identifier[8];
2819 struct ct_fdmi_hba_attributes attrs;
2820 } rhat;
2821
2822 struct {
2823 uint8_t port_name[8];
2824 struct ct_fdmi_port_attributes attrs;
2825 } rpa;
2826
2827 struct {
2828 uint8_t port_name[8];
2829 struct ct_fdmiv2_port_attributes attrs;
2830 } rpa2;
2831
2832 struct {
2833 uint8_t port_name[8];
2834 } dhba;
2835
2836 struct {
2837 uint8_t port_name[8];
2838 } dhat;
2839
2840 struct {
2841 uint8_t port_name[8];
2842 } dprt;
2843
2844 struct {
2845 uint8_t port_name[8];
2846 } dpa;
2847
2848 struct {
2849 uint8_t port_name[8];
2850 } gpsc;
2851
2852 struct {
2853 uint8_t reserved;
2854 uint8_t port_id[3];
2855 } gff_id;
2856
2857 struct {
2858 uint8_t port_name[8];
2859 } gid_pn;
2860 } req;
2861 };
2862
2863 /* CT command response header */
2864 struct ct_rsp_hdr {
2865 struct ct_cmd_hdr header;
2866 uint16_t response;
2867 uint16_t residual;
2868 uint8_t fragment_id;
2869 uint8_t reason_code;
2870 uint8_t explanation_code;
2871 uint8_t vendor_unique;
2872 };
2873
2874 struct ct_sns_gid_pt_data {
2875 uint8_t control_byte;
2876 uint8_t port_id[3];
2877 };
2878
2879 /* It's the same for both GPN_FT and GNN_FT */
2880 struct ct_sns_gpnft_rsp {
2881 struct {
2882 struct ct_cmd_hdr header;
2883 uint16_t response;
2884 uint16_t residual;
2885 uint8_t fragment_id;
2886 uint8_t reason_code;
2887 uint8_t explanation_code;
2888 uint8_t vendor_unique;
2889 };
2890 /* Assume the largest number of targets for the union */
2891 struct ct_sns_gpn_ft_data {
2892 u8 control_byte;
2893 u8 port_id[3];
2894 u32 reserved;
2895 u8 port_name[8];
2896 } entries[1];
2897 };
2898
2899 /* CT command response */
2900 struct ct_sns_rsp {
2901 struct ct_rsp_hdr header;
2902
2903 union {
2904 struct {
2905 uint8_t port_type;
2906 uint8_t port_id[3];
2907 uint8_t port_name[8];
2908 uint8_t sym_port_name_len;
2909 uint8_t sym_port_name[255];
2910 uint8_t node_name[8];
2911 uint8_t sym_node_name_len;
2912 uint8_t sym_node_name[255];
2913 uint8_t init_proc_assoc[8];
2914 uint8_t node_ip_addr[16];
2915 uint8_t class_of_service[4];
2916 uint8_t fc4_types[32];
2917 uint8_t ip_address[16];
2918 uint8_t fabric_port_name[8];
2919 uint8_t reserved;
2920 uint8_t hard_address[3];
2921 } ga_nxt;
2922
2923 struct {
2924 /* Assume the largest number of targets for the union */
2925 struct ct_sns_gid_pt_data
2926 entries[MAX_FIBRE_DEVICES_MAX];
2927 } gid_pt;
2928
2929 struct {
2930 uint8_t port_name[8];
2931 } gpn_id;
2932
2933 struct {
2934 uint8_t node_name[8];
2935 } gnn_id;
2936
2937 struct {
2938 uint8_t fc4_types[32];
2939 } gft_id;
2940
2941 struct {
2942 uint32_t entry_count;
2943 uint8_t port_name[8];
2944 struct ct_fdmi_hba_attributes attrs;
2945 } ghat;
2946
2947 struct {
2948 uint8_t port_name[8];
2949 } gfpn_id;
2950
2951 struct {
2952 uint16_t speeds;
2953 uint16_t speed;
2954 } gpsc;
2955
2956 #define GFF_FCP_SCSI_OFFSET 7
2957 #define GFF_NVME_OFFSET 23 /* type = 28h */
2958 struct {
2959 uint8_t fc4_features[128];
2960 } gff_id;
2961 struct {
2962 uint8_t reserved;
2963 uint8_t port_id[3];
2964 } gid_pn;
2965 } rsp;
2966 };
2967
2968 struct ct_sns_pkt {
2969 union {
2970 struct ct_sns_req req;
2971 struct ct_sns_rsp rsp;
2972 } p;
2973 };
2974
2975 struct ct_sns_gpnft_pkt {
2976 union {
2977 struct ct_sns_req req;
2978 struct ct_sns_gpnft_rsp rsp;
2979 } p;
2980 };
2981
2982 enum scan_flags_t {
2983 SF_SCANNING = BIT_0,
2984 SF_QUEUED = BIT_1,
2985 };
2986
2987 enum fc4type_t {
2988 FS_FC4TYPE_FCP = BIT_0,
2989 FS_FC4TYPE_NVME = BIT_1,
2990 };
2991
2992 struct fab_scan_rp {
2993 port_id_t id;
2994 enum fc4type_t fc4type;
2995 u8 port_name[8];
2996 u8 node_name[8];
2997 };
2998
2999 struct fab_scan {
3000 struct fab_scan_rp *l;
3001 u32 size;
3002 u16 scan_retry;
3003 #define MAX_SCAN_RETRIES 5
3004 enum scan_flags_t scan_flags;
3005 struct delayed_work scan_work;
3006 };
3007
3008 /*
3009 * SNS command structures -- for 2200 compatibility.
3010 */
3011 #define RFT_ID_SNS_SCMD_LEN 22
3012 #define RFT_ID_SNS_CMD_SIZE 60
3013 #define RFT_ID_SNS_DATA_SIZE 16
3014
3015 #define RNN_ID_SNS_SCMD_LEN 10
3016 #define RNN_ID_SNS_CMD_SIZE 36
3017 #define RNN_ID_SNS_DATA_SIZE 16
3018
3019 #define GA_NXT_SNS_SCMD_LEN 6
3020 #define GA_NXT_SNS_CMD_SIZE 28
3021 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
3022
3023 #define GID_PT_SNS_SCMD_LEN 6
3024 #define GID_PT_SNS_CMD_SIZE 28
3025 /*
3026 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
3027 * adapters.
3028 */
3029 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3030
3031 #define GPN_ID_SNS_SCMD_LEN 6
3032 #define GPN_ID_SNS_CMD_SIZE 28
3033 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
3034
3035 #define GNN_ID_SNS_SCMD_LEN 6
3036 #define GNN_ID_SNS_CMD_SIZE 28
3037 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
3038
3039 struct sns_cmd_pkt {
3040 union {
3041 struct {
3042 uint16_t buffer_length;
3043 uint16_t reserved_1;
3044 uint32_t buffer_address[2];
3045 uint16_t subcommand_length;
3046 uint16_t reserved_2;
3047 uint16_t subcommand;
3048 uint16_t size;
3049 uint32_t reserved_3;
3050 uint8_t param[36];
3051 } cmd;
3052
3053 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3054 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3055 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3056 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3057 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3058 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3059 } p;
3060 };
3061
3062 struct fw_blob {
3063 char *name;
3064 uint32_t segs[4];
3065 const struct firmware *fw;
3066 };
3067
3068 /* Return data from MBC_GET_ID_LIST call. */
3069 struct gid_list_info {
3070 uint8_t al_pa;
3071 uint8_t area;
3072 uint8_t domain;
3073 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
3074 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3075 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
3076 };
3077
3078 /* NPIV */
3079 typedef struct vport_info {
3080 uint8_t port_name[WWN_SIZE];
3081 uint8_t node_name[WWN_SIZE];
3082 int vp_id;
3083 uint16_t loop_id;
3084 unsigned long host_no;
3085 uint8_t port_id[3];
3086 int loop_state;
3087 } vport_info_t;
3088
3089 typedef struct vport_params {
3090 uint8_t port_name[WWN_SIZE];
3091 uint8_t node_name[WWN_SIZE];
3092 uint32_t options;
3093 #define VP_OPTS_RETRY_ENABLE BIT_0
3094 #define VP_OPTS_VP_DISABLE BIT_1
3095 } vport_params_t;
3096
3097 /* NPIV - return codes of VP create and modify */
3098 #define VP_RET_CODE_OK 0
3099 #define VP_RET_CODE_FATAL 1
3100 #define VP_RET_CODE_WRONG_ID 2
3101 #define VP_RET_CODE_WWPN 3
3102 #define VP_RET_CODE_RESOURCES 4
3103 #define VP_RET_CODE_NO_MEM 5
3104 #define VP_RET_CODE_NOT_FOUND 6
3105
3106 struct qla_hw_data;
3107 struct rsp_que;
3108 /*
3109 * ISP operations
3110 */
3111 struct isp_operations {
3112
3113 int (*pci_config) (struct scsi_qla_host *);
3114 void (*reset_chip) (struct scsi_qla_host *);
3115 int (*chip_diag) (struct scsi_qla_host *);
3116 void (*config_rings) (struct scsi_qla_host *);
3117 void (*reset_adapter) (struct scsi_qla_host *);
3118 int (*nvram_config) (struct scsi_qla_host *);
3119 void (*update_fw_options) (struct scsi_qla_host *);
3120 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3121
3122 char * (*pci_info_str) (struct scsi_qla_host *, char *);
3123 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3124
3125 irq_handler_t intr_handler;
3126 void (*enable_intrs) (struct qla_hw_data *);
3127 void (*disable_intrs) (struct qla_hw_data *);
3128
3129 int (*abort_command) (srb_t *);
3130 int (*target_reset) (struct fc_port *, uint64_t, int);
3131 int (*lun_reset) (struct fc_port *, uint64_t, int);
3132 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3133 uint8_t, uint8_t, uint16_t *, uint8_t);
3134 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3135 uint8_t, uint8_t);
3136
3137 uint16_t (*calc_req_entries) (uint16_t);
3138 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3139 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3140 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3141 uint32_t);
3142
3143 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *,
3144 uint32_t, uint32_t);
3145 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
3146 uint32_t);
3147
3148 void (*fw_dump) (struct scsi_qla_host *, int);
3149
3150 int (*beacon_on) (struct scsi_qla_host *);
3151 int (*beacon_off) (struct scsi_qla_host *);
3152 void (*beacon_blink) (struct scsi_qla_host *);
3153
3154 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
3155 uint32_t, uint32_t);
3156 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
3157 uint32_t);
3158
3159 int (*get_flash_version) (struct scsi_qla_host *, void *);
3160 int (*start_scsi) (srb_t *);
3161 int (*start_scsi_mq) (srb_t *);
3162 int (*abort_isp) (struct scsi_qla_host *);
3163 int (*iospace_config)(struct qla_hw_data*);
3164 int (*initialize_adapter)(struct scsi_qla_host *);
3165 };
3166
3167 /* MSI-X Support *************************************************************/
3168
3169 #define QLA_MSIX_CHIP_REV_24XX 3
3170 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3171 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3172
3173 #define QLA_BASE_VECTORS 2 /* default + RSP */
3174 #define QLA_MSIX_RSP_Q 0x01
3175 #define QLA_ATIO_VECTOR 0x02
3176 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3177
3178 #define QLA_MIDX_DEFAULT 0
3179 #define QLA_MIDX_RSP_Q 1
3180 #define QLA_PCI_MSIX_CONTROL 0xa2
3181 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3182
3183 struct scsi_qla_host;
3184
3185
3186 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3187
3188 struct qla_msix_entry {
3189 int have_irq;
3190 int in_use;
3191 uint32_t vector;
3192 uint16_t entry;
3193 char name[30];
3194 void *handle;
3195 int cpuid;
3196 };
3197
3198 #define WATCH_INTERVAL 1 /* number of seconds */
3199
3200 /* Work events. */
3201 enum qla_work_type {
3202 QLA_EVT_AEN,
3203 QLA_EVT_IDC_ACK,
3204 QLA_EVT_ASYNC_LOGIN,
3205 QLA_EVT_ASYNC_LOGOUT,
3206 QLA_EVT_ASYNC_LOGOUT_DONE,
3207 QLA_EVT_ASYNC_ADISC,
3208 QLA_EVT_ASYNC_ADISC_DONE,
3209 QLA_EVT_UEVENT,
3210 QLA_EVT_AENFX,
3211 QLA_EVT_GIDPN,
3212 QLA_EVT_GPNID,
3213 QLA_EVT_UNMAP,
3214 QLA_EVT_NEW_SESS,
3215 QLA_EVT_GPDB,
3216 QLA_EVT_PRLI,
3217 QLA_EVT_GPSC,
3218 QLA_EVT_UPD_FCPORT,
3219 QLA_EVT_GNL,
3220 QLA_EVT_NACK,
3221 QLA_EVT_RELOGIN,
3222 QLA_EVT_ASYNC_PRLO,
3223 QLA_EVT_ASYNC_PRLO_DONE,
3224 QLA_EVT_GPNFT,
3225 QLA_EVT_GPNFT_DONE,
3226 QLA_EVT_GNNFT_DONE,
3227 QLA_EVT_GNNID,
3228 QLA_EVT_GFPNID,
3229 QLA_EVT_SP_RETRY,
3230 QLA_EVT_IIDMA,
3231 };
3232
3233
3234 struct qla_work_evt {
3235 struct list_head list;
3236 enum qla_work_type type;
3237 u32 flags;
3238 #define QLA_EVT_FLAG_FREE 0x1
3239
3240 union {
3241 struct {
3242 enum fc_host_event_code code;
3243 u32 data;
3244 } aen;
3245 struct {
3246 #define QLA_IDC_ACK_REGS 7
3247 uint16_t mb[QLA_IDC_ACK_REGS];
3248 } idc_ack;
3249 struct {
3250 struct fc_port *fcport;
3251 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3252 u16 data[2];
3253 } logio;
3254 struct {
3255 u32 code;
3256 #define QLA_UEVENT_CODE_FW_DUMP 0
3257 } uevent;
3258 struct {
3259 uint32_t evtcode;
3260 uint32_t mbx[8];
3261 uint32_t count;
3262 } aenfx;
3263 struct {
3264 srb_t *sp;
3265 } iosb;
3266 struct {
3267 port_id_t id;
3268 } gpnid;
3269 struct {
3270 port_id_t id;
3271 u8 port_name[8];
3272 u8 node_name[8];
3273 void *pla;
3274 u8 fc4_type;
3275 } new_sess;
3276 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3277 fc_port_t *fcport;
3278 u8 opt;
3279 } fcport;
3280 struct {
3281 fc_port_t *fcport;
3282 u8 iocb[IOCB_SIZE];
3283 int type;
3284 } nack;
3285 struct {
3286 u8 fc4_type;
3287 srb_t *sp;
3288 } gpnft;
3289 } u;
3290 };
3291
3292 struct qla_chip_state_84xx {
3293 struct list_head list;
3294 struct kref kref;
3295
3296 void *bus;
3297 spinlock_t access_lock;
3298 struct mutex fw_update_mutex;
3299 uint32_t fw_update;
3300 uint32_t op_fw_version;
3301 uint32_t op_fw_size;
3302 uint32_t op_fw_seq_size;
3303 uint32_t diag_fw_version;
3304 uint32_t gold_fw_version;
3305 };
3306
3307 struct qla_dif_statistics {
3308 uint64_t dif_input_bytes;
3309 uint64_t dif_output_bytes;
3310 uint64_t dif_input_requests;
3311 uint64_t dif_output_requests;
3312 uint32_t dif_guard_err;
3313 uint32_t dif_ref_tag_err;
3314 uint32_t dif_app_tag_err;
3315 };
3316
3317 struct qla_statistics {
3318 uint32_t total_isp_aborts;
3319 uint64_t input_bytes;
3320 uint64_t output_bytes;
3321 uint64_t input_requests;
3322 uint64_t output_requests;
3323 uint32_t control_requests;
3324
3325 uint64_t jiffies_at_last_reset;
3326 uint32_t stat_max_pend_cmds;
3327 uint32_t stat_max_qfull_cmds_alloc;
3328 uint32_t stat_max_qfull_cmds_dropped;
3329
3330 struct qla_dif_statistics qla_dif_stats;
3331 };
3332
3333 struct bidi_statistics {
3334 unsigned long long io_count;
3335 unsigned long long transfer_bytes;
3336 };
3337
3338 struct qla_tc_param {
3339 struct scsi_qla_host *vha;
3340 uint32_t blk_sz;
3341 uint32_t bufflen;
3342 struct scatterlist *sg;
3343 struct scatterlist *prot_sg;
3344 struct crc_context *ctx;
3345 uint8_t *ctx_dsd_alloced;
3346 };
3347
3348 /* Multi queue support */
3349 #define MBC_INITIALIZE_MULTIQ 0x1f
3350 #define QLA_QUE_PAGE 0X1000
3351 #define QLA_MQ_SIZE 32
3352 #define QLA_MAX_QUEUES 256
3353 #define ISP_QUE_REG(ha, id) \
3354 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
3355 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3356 ((void __iomem *)ha->iobase))
3357 #define QLA_REQ_QUE_ID(tag) \
3358 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3359 #define QLA_DEFAULT_QUE_QOS 5
3360 #define QLA_PRECONFIG_VPORTS 32
3361 #define QLA_MAX_VPORTS_QLA24XX 128
3362 #define QLA_MAX_VPORTS_QLA25XX 256
3363
3364 struct qla_tgt_counters {
3365 uint64_t qla_core_sbt_cmd;
3366 uint64_t core_qla_que_buf;
3367 uint64_t qla_core_ret_ctio;
3368 uint64_t core_qla_snd_status;
3369 uint64_t qla_core_ret_sta_ctio;
3370 uint64_t core_qla_free_cmd;
3371 uint64_t num_q_full_sent;
3372 uint64_t num_alloc_iocb_failed;
3373 uint64_t num_term_xchg_sent;
3374 };
3375
3376 struct qla_qpair;
3377
3378 /* Response queue data structure */
3379 struct rsp_que {
3380 dma_addr_t dma;
3381 response_t *ring;
3382 response_t *ring_ptr;
3383 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
3384 uint32_t __iomem *rsp_q_out;
3385 uint16_t ring_index;
3386 uint16_t out_ptr;
3387 uint16_t *in_ptr; /* queue shadow in index */
3388 uint16_t length;
3389 uint16_t options;
3390 uint16_t rid;
3391 uint16_t id;
3392 uint16_t vp_idx;
3393 struct qla_hw_data *hw;
3394 struct qla_msix_entry *msix;
3395 struct req_que *req;
3396 srb_t *status_srb; /* status continuation entry */
3397 struct qla_qpair *qpair;
3398
3399 dma_addr_t dma_fx00;
3400 response_t *ring_fx00;
3401 uint16_t length_fx00;
3402 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3403 };
3404
3405 /* Request queue data structure */
3406 struct req_que {
3407 dma_addr_t dma;
3408 request_t *ring;
3409 request_t *ring_ptr;
3410 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
3411 uint32_t __iomem *req_q_out;
3412 uint16_t ring_index;
3413 uint16_t in_ptr;
3414 uint16_t *out_ptr; /* queue shadow out index */
3415 uint16_t cnt;
3416 uint16_t length;
3417 uint16_t options;
3418 uint16_t rid;
3419 uint16_t id;
3420 uint16_t qos;
3421 uint16_t vp_idx;
3422 struct rsp_que *rsp;
3423 srb_t **outstanding_cmds;
3424 uint32_t current_outstanding_cmd;
3425 uint16_t num_outstanding_cmds;
3426 int max_q_depth;
3427
3428 dma_addr_t dma_fx00;
3429 request_t *ring_fx00;
3430 uint16_t length_fx00;
3431 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3432 };
3433
3434 /*Queue pair data structure */
3435 struct qla_qpair {
3436 spinlock_t qp_lock;
3437 atomic_t ref_count;
3438 uint32_t lun_cnt;
3439 /*
3440 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3441 * legacy code. For other Qpair(s), it will point at qp_lock.
3442 */
3443 spinlock_t *qp_lock_ptr;
3444 struct scsi_qla_host *vha;
3445 u32 chip_reset;
3446
3447 /* distill these fields down to 'online=0/1'
3448 * ha->flags.eeh_busy
3449 * ha->flags.pci_channel_io_perm_failure
3450 * base_vha->loop_state
3451 */
3452 uint32_t online:1;
3453 /* move vha->flags.difdix_supported here */
3454 uint32_t difdix_supported:1;
3455 uint32_t delete_in_progress:1;
3456 uint32_t fw_started:1;
3457 uint32_t enable_class_2:1;
3458 uint32_t enable_explicit_conf:1;
3459 uint32_t use_shadow_reg:1;
3460
3461 uint16_t id; /* qp number used with FW */
3462 uint16_t vp_idx; /* vport ID */
3463 mempool_t *srb_mempool;
3464
3465 struct pci_dev *pdev;
3466 void (*reqq_start_iocbs)(struct qla_qpair *);
3467
3468 /* to do: New driver: move queues to here instead of pointers */
3469 struct req_que *req;
3470 struct rsp_que *rsp;
3471 struct atio_que *atio;
3472 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3473 struct qla_hw_data *hw;
3474 struct work_struct q_work;
3475 struct list_head qp_list_elem; /* vha->qp_list */
3476 struct list_head hints_list;
3477 uint16_t cpuid;
3478 struct qla_tgt_counters tgt_counters;
3479 };
3480
3481 /* Place holder for FW buffer parameters */
3482 struct qlfc_fw {
3483 void *fw_buf;
3484 dma_addr_t fw_dma;
3485 uint32_t len;
3486 };
3487
3488 struct scsi_qlt_host {
3489 void *target_lport_ptr;
3490 struct mutex tgt_mutex;
3491 struct mutex tgt_host_action_mutex;
3492 struct qla_tgt *qla_tgt;
3493 };
3494
3495 struct qlt_hw_data {
3496 /* Protected by hw lock */
3497 uint32_t node_name_set:1;
3498
3499 dma_addr_t atio_dma; /* Physical address. */
3500 struct atio *atio_ring; /* Base virtual address */
3501 struct atio *atio_ring_ptr; /* Current address. */
3502 uint16_t atio_ring_index; /* Current index. */
3503 uint16_t atio_q_length;
3504 uint32_t __iomem *atio_q_in;
3505 uint32_t __iomem *atio_q_out;
3506
3507 struct qla_tgt_func_tmpl *tgt_ops;
3508 struct qla_tgt_vp_map *tgt_vp_map;
3509
3510 int saved_set;
3511 uint16_t saved_exchange_count;
3512 uint32_t saved_firmware_options_1;
3513 uint32_t saved_firmware_options_2;
3514 uint32_t saved_firmware_options_3;
3515 uint8_t saved_firmware_options[2];
3516 uint8_t saved_add_firmware_options[2];
3517
3518 uint8_t tgt_node_name[WWN_SIZE];
3519
3520 struct dentry *dfs_tgt_sess;
3521 struct dentry *dfs_tgt_port_database;
3522 struct dentry *dfs_naqp;
3523
3524 struct list_head q_full_list;
3525 uint32_t num_pend_cmds;
3526 uint32_t num_qfull_cmds_alloc;
3527 uint32_t num_qfull_cmds_dropped;
3528 spinlock_t q_full_lock;
3529 uint32_t leak_exchg_thresh_hold;
3530 spinlock_t sess_lock;
3531 int num_act_qpairs;
3532 #define DEFAULT_NAQP 2
3533 spinlock_t atio_lock ____cacheline_aligned;
3534 struct btree_head32 host_map;
3535 };
3536
3537 #define MAX_QFULL_CMDS_ALLOC 8192
3538 #define Q_FULL_THRESH_HOLD_PERCENT 90
3539 #define Q_FULL_THRESH_HOLD(ha) \
3540 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3541
3542 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3543
3544 /*
3545 * Qlogic host adapter specific data structure.
3546 */
3547 struct qla_hw_data {
3548 struct pci_dev *pdev;
3549 /* SRB cache. */
3550 #define SRB_MIN_REQ 128
3551 mempool_t *srb_mempool;
3552
3553 volatile struct {
3554 uint32_t mbox_int :1;
3555 uint32_t mbox_busy :1;
3556 uint32_t disable_risc_code_load :1;
3557 uint32_t enable_64bit_addressing :1;
3558 uint32_t enable_lip_reset :1;
3559 uint32_t enable_target_reset :1;
3560 uint32_t enable_lip_full_login :1;
3561 uint32_t enable_led_scheme :1;
3562
3563 uint32_t msi_enabled :1;
3564 uint32_t msix_enabled :1;
3565 uint32_t disable_serdes :1;
3566 uint32_t gpsc_supported :1;
3567 uint32_t npiv_supported :1;
3568 uint32_t pci_channel_io_perm_failure :1;
3569 uint32_t fce_enabled :1;
3570 uint32_t fac_supported :1;
3571
3572 uint32_t chip_reset_done :1;
3573 uint32_t running_gold_fw :1;
3574 uint32_t eeh_busy :1;
3575 uint32_t disable_msix_handshake :1;
3576 uint32_t fcp_prio_enabled :1;
3577 uint32_t isp82xx_fw_hung:1;
3578 uint32_t nic_core_hung:1;
3579
3580 uint32_t quiesce_owner:1;
3581 uint32_t nic_core_reset_hdlr_active:1;
3582 uint32_t nic_core_reset_owner:1;
3583 uint32_t isp82xx_no_md_cap:1;
3584 uint32_t host_shutting_down:1;
3585 uint32_t idc_compl_status:1;
3586 uint32_t mr_reset_hdlr_active:1;
3587 uint32_t mr_intr_valid:1;
3588
3589 uint32_t dport_enabled:1;
3590 uint32_t fawwpn_enabled:1;
3591 uint32_t exlogins_enabled:1;
3592 uint32_t exchoffld_enabled:1;
3593
3594 uint32_t lip_ae:1;
3595 uint32_t n2n_ae:1;
3596 uint32_t fw_started:1;
3597 uint32_t fw_init_done:1;
3598
3599 uint32_t detected_lr_sfp:1;
3600 uint32_t using_lr_setting:1;
3601 uint32_t rida_fmt2:1;
3602 } flags;
3603
3604 uint16_t max_exchg;
3605 uint16_t long_range_distance; /* 32G & above */
3606 #define LR_DISTANCE_5K 1
3607 #define LR_DISTANCE_10K 0
3608
3609 /* This spinlock is used to protect "io transactions", you must
3610 * acquire it before doing any IO to the card, eg with RD_REG*() and
3611 * WRT_REG*() for the duration of your entire commandtransaction.
3612 *
3613 * This spinlock is of lower priority than the io request lock.
3614 */
3615
3616 spinlock_t hardware_lock ____cacheline_aligned;
3617 int bars;
3618 int mem_only;
3619 device_reg_t *iobase; /* Base I/O address */
3620 resource_size_t pio_address;
3621
3622 #define MIN_IOBASE_LEN 0x100
3623 dma_addr_t bar0_hdl;
3624
3625 void __iomem *cregbase;
3626 dma_addr_t bar2_hdl;
3627 #define BAR0_LEN_FX00 (1024 * 1024)
3628 #define BAR2_LEN_FX00 (128 * 1024)
3629
3630 uint32_t rqstq_intr_code;
3631 uint32_t mbx_intr_code;
3632 uint32_t req_que_len;
3633 uint32_t rsp_que_len;
3634 uint32_t req_que_off;
3635 uint32_t rsp_que_off;
3636
3637 /* Multi queue data structs */
3638 device_reg_t *mqiobase;
3639 device_reg_t *msixbase;
3640 uint16_t msix_count;
3641 uint8_t mqenable;
3642 struct req_que **req_q_map;
3643 struct rsp_que **rsp_q_map;
3644 struct qla_qpair **queue_pair_map;
3645 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3646 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3647 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3648 / sizeof(unsigned long)];
3649 uint8_t max_req_queues;
3650 uint8_t max_rsp_queues;
3651 uint8_t max_qpairs;
3652 uint8_t num_qpairs;
3653 struct qla_qpair *base_qpair;
3654 struct qla_npiv_entry *npiv_info;
3655 uint16_t nvram_npiv_size;
3656
3657 uint16_t switch_cap;
3658 #define FLOGI_SEQ_DEL BIT_8
3659 #define FLOGI_MID_SUPPORT BIT_10
3660 #define FLOGI_VSAN_SUPPORT BIT_12
3661 #define FLOGI_SP_SUPPORT BIT_13
3662
3663 uint8_t port_no; /* Physical port of adapter */
3664 uint8_t exch_starvation;
3665
3666 /* Timeout timers. */
3667 uint8_t loop_down_abort_time; /* port down timer */
3668 atomic_t loop_down_timer; /* loop down timer */
3669 uint8_t link_down_timeout; /* link down timeout */
3670 uint16_t max_loop_id;
3671 uint16_t max_fibre_devices; /* Maximum number of targets */
3672
3673 uint16_t fb_rev;
3674 uint16_t min_external_loopid; /* First external loop Id */
3675
3676 #define PORT_SPEED_UNKNOWN 0xFFFF
3677 #define PORT_SPEED_1GB 0x00
3678 #define PORT_SPEED_2GB 0x01
3679 #define PORT_SPEED_4GB 0x03
3680 #define PORT_SPEED_8GB 0x04
3681 #define PORT_SPEED_16GB 0x05
3682 #define PORT_SPEED_32GB 0x06
3683 #define PORT_SPEED_10GB 0x13
3684 uint16_t link_data_rate; /* F/W operating speed */
3685
3686 uint8_t current_topology;
3687 uint8_t prev_topology;
3688 #define ISP_CFG_NL 1
3689 #define ISP_CFG_N 2
3690 #define ISP_CFG_FL 4
3691 #define ISP_CFG_F 8
3692
3693 uint8_t operating_mode; /* F/W operating mode */
3694 #define LOOP 0
3695 #define P2P 1
3696 #define LOOP_P2P 2
3697 #define P2P_LOOP 3
3698 uint8_t interrupts_on;
3699 uint32_t isp_abort_cnt;
3700 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3701 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3702 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3703 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3704 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3705 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3706 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3707 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3708
3709 uint32_t isp_type;
3710 #define DT_ISP2100 BIT_0
3711 #define DT_ISP2200 BIT_1
3712 #define DT_ISP2300 BIT_2
3713 #define DT_ISP2312 BIT_3
3714 #define DT_ISP2322 BIT_4
3715 #define DT_ISP6312 BIT_5
3716 #define DT_ISP6322 BIT_6
3717 #define DT_ISP2422 BIT_7
3718 #define DT_ISP2432 BIT_8
3719 #define DT_ISP5422 BIT_9
3720 #define DT_ISP5432 BIT_10
3721 #define DT_ISP2532 BIT_11
3722 #define DT_ISP8432 BIT_12
3723 #define DT_ISP8001 BIT_13
3724 #define DT_ISP8021 BIT_14
3725 #define DT_ISP2031 BIT_15
3726 #define DT_ISP8031 BIT_16
3727 #define DT_ISPFX00 BIT_17
3728 #define DT_ISP8044 BIT_18
3729 #define DT_ISP2071 BIT_19
3730 #define DT_ISP2271 BIT_20
3731 #define DT_ISP2261 BIT_21
3732 #define DT_ISP_LAST (DT_ISP2261 << 1)
3733
3734 uint32_t device_type;
3735 #define DT_T10_PI BIT_25
3736 #define DT_IIDMA BIT_26
3737 #define DT_FWI2 BIT_27
3738 #define DT_ZIO_SUPPORTED BIT_28
3739 #define DT_OEM_001 BIT_29
3740 #define DT_ISP2200A BIT_30
3741 #define DT_EXTENDED_IDS BIT_31
3742
3743 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3744 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3745 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3746 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3747 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3748 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3749 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3750 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3751 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3752 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3753 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3754 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3755 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3756 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3757 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3758 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3759 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3760 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3761 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3762 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3763 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3764 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3765 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3766 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3767
3768 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3769 IS_QLA6312(ha) || IS_QLA6322(ha))
3770 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3771 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3772 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3773 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3774 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3775 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3776 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3777 IS_QLA84XX(ha))
3778 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3779 IS_QLA8031(ha) || IS_QLA8044(ha))
3780 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3781 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3782 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3783 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3784 IS_QLA8044(ha) || IS_QLA27XX(ha))
3785 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3786 IS_QLA27XX(ha))
3787 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3788 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3789 IS_QLA27XX(ha))
3790 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3791 IS_QLA27XX(ha))
3792 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3793
3794 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3795 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3796 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3797 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3798 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3799 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3800 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3801 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3802 IS_QLA27XX(ha))
3803 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
3804 /* Bit 21 of fw_attributes decides the MCTP capabilities */
3805 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3806 ((ha)->fw_attributes_ext[0] & BIT_0))
3807 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3808 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3809 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3810 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3811 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3812 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3813 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3814 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3815 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
3816 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3817 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3818 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
3819 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3820 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3821 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3822 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
3823 IS_QLA83XX(ha) || IS_QLA27XX(ha))
3824
3825 /* HBA serial number */
3826 uint8_t serial0;
3827 uint8_t serial1;
3828 uint8_t serial2;
3829
3830 /* NVRAM configuration data */
3831 #define MAX_NVRAM_SIZE 4096
3832 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
3833 uint16_t nvram_size;
3834 uint16_t nvram_base;
3835 void *nvram;
3836 uint16_t vpd_size;
3837 uint16_t vpd_base;
3838 void *vpd;
3839
3840 uint16_t loop_reset_delay;
3841 uint8_t retry_count;
3842 uint8_t login_timeout;
3843 uint16_t r_a_tov;
3844 int port_down_retry_count;
3845 uint8_t mbx_count;
3846 uint8_t aen_mbx_count;
3847
3848 uint32_t login_retry_count;
3849 /* SNS command interfaces. */
3850 ms_iocb_entry_t *ms_iocb;
3851 dma_addr_t ms_iocb_dma;
3852 struct ct_sns_pkt *ct_sns;
3853 dma_addr_t ct_sns_dma;
3854 /* SNS command interfaces for 2200. */
3855 struct sns_cmd_pkt *sns_cmd;
3856 dma_addr_t sns_cmd_dma;
3857
3858 #define SFP_DEV_SIZE 512
3859 #define SFP_BLOCK_SIZE 64
3860 void *sfp_data;
3861 dma_addr_t sfp_data_dma;
3862
3863 #define XGMAC_DATA_SIZE 4096
3864 void *xgmac_data;
3865 dma_addr_t xgmac_data_dma;
3866
3867 #define DCBX_TLV_DATA_SIZE 4096
3868 void *dcbx_tlv;
3869 dma_addr_t dcbx_tlv_dma;
3870
3871 struct task_struct *dpc_thread;
3872 uint8_t dpc_active; /* DPC routine is active */
3873
3874 dma_addr_t gid_list_dma;
3875 struct gid_list_info *gid_list;
3876 int gid_list_info_size;
3877
3878 /* Small DMA pool allocations -- maximum 256 bytes in length. */
3879 #define DMA_POOL_SIZE 256
3880 struct dma_pool *s_dma_pool;
3881
3882 dma_addr_t init_cb_dma;
3883 init_cb_t *init_cb;
3884 int init_cb_size;
3885 dma_addr_t ex_init_cb_dma;
3886 struct ex_init_cb_81xx *ex_init_cb;
3887
3888 void *async_pd;
3889 dma_addr_t async_pd_dma;
3890
3891 #define ENABLE_EXTENDED_LOGIN BIT_7
3892
3893 /* Extended Logins */
3894 void *exlogin_buf;
3895 dma_addr_t exlogin_buf_dma;
3896 int exlogin_size;
3897
3898 #define ENABLE_EXCHANGE_OFFLD BIT_2
3899
3900 /* Exchange Offload */
3901 void *exchoffld_buf;
3902 dma_addr_t exchoffld_buf_dma;
3903 int exchoffld_size;
3904 int exchoffld_count;
3905
3906 void *swl;
3907
3908 /* These are used by mailbox operations. */
3909 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3910 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3911 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3912
3913 mbx_cmd_t *mcp;
3914 struct mbx_cmd_32 *mcp32;
3915
3916 unsigned long mbx_cmd_flags;
3917 #define MBX_INTERRUPT 1
3918 #define MBX_INTR_WAIT 2
3919 #define MBX_UPDATE_FLASH_ACTIVE 3
3920
3921 struct mutex vport_lock; /* Virtual port synchronization */
3922 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
3923 struct mutex mq_lock; /* multi-queue synchronization */
3924 struct completion mbx_cmd_comp; /* Serialize mbx access */
3925 struct completion mbx_intr_comp; /* Used for completion notification */
3926 struct completion dcbx_comp; /* For set port config notification */
3927 struct completion lb_portup_comp; /* Used to wait for link up during
3928 * loopback */
3929 #define DCBX_COMP_TIMEOUT 20
3930 #define LB_PORTUP_COMP_TIMEOUT 10
3931
3932 int notify_dcbx_comp;
3933 int notify_lb_portup_comp;
3934 struct mutex selflogin_lock;
3935
3936 /* Basic firmware related information. */
3937 uint16_t fw_major_version;
3938 uint16_t fw_minor_version;
3939 uint16_t fw_subminor_version;
3940 uint16_t fw_attributes;
3941 uint16_t fw_attributes_h;
3942 uint16_t fw_attributes_ext[2];
3943 uint32_t fw_memory_size;
3944 uint32_t fw_transfer_size;
3945 uint32_t fw_srisc_address;
3946 #define RISC_START_ADDRESS_2100 0x1000
3947 #define RISC_START_ADDRESS_2300 0x800
3948 #define RISC_START_ADDRESS_2400 0x100000
3949
3950 uint16_t orig_fw_tgt_xcb_count;
3951 uint16_t cur_fw_tgt_xcb_count;
3952 uint16_t orig_fw_xcb_count;
3953 uint16_t cur_fw_xcb_count;
3954 uint16_t orig_fw_iocb_count;
3955 uint16_t cur_fw_iocb_count;
3956 uint16_t fw_max_fcf_count;
3957
3958 uint32_t fw_shared_ram_start;
3959 uint32_t fw_shared_ram_end;
3960 uint32_t fw_ddr_ram_start;
3961 uint32_t fw_ddr_ram_end;
3962
3963 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3964 uint8_t fw_seriallink_options[4];
3965 uint16_t fw_seriallink_options24[4];
3966
3967 uint8_t mpi_version[3];
3968 uint32_t mpi_capabilities;
3969 uint8_t phy_version[3];
3970 uint8_t pep_version[3];
3971
3972 /* Firmware dump template */
3973 void *fw_dump_template;
3974 uint32_t fw_dump_template_len;
3975 /* Firmware dump information. */
3976 struct qla2xxx_fw_dump *fw_dump;
3977 uint32_t fw_dump_len;
3978 int fw_dumped;
3979 unsigned long fw_dump_cap_flags;
3980 #define RISC_PAUSE_CMPL 0
3981 #define DMA_SHUTDOWN_CMPL 1
3982 #define ISP_RESET_CMPL 2
3983 #define RISC_RDY_AFT_RESET 3
3984 #define RISC_SRAM_DUMP_CMPL 4
3985 #define RISC_EXT_MEM_DUMP_CMPL 5
3986 #define ISP_MBX_RDY 6
3987 #define ISP_SOFT_RESET_CMPL 7
3988 int fw_dump_reading;
3989 int prev_minidump_failed;
3990 dma_addr_t eft_dma;
3991 void *eft;
3992 /* Current size of mctp dump is 0x086064 bytes */
3993 #define MCTP_DUMP_SIZE 0x086064
3994 dma_addr_t mctp_dump_dma;
3995 void *mctp_dump;
3996 int mctp_dumped;
3997 int mctp_dump_reading;
3998 uint32_t chain_offset;
3999 struct dentry *dfs_dir;
4000 struct dentry *dfs_fce;
4001 struct dentry *dfs_tgt_counters;
4002 struct dentry *dfs_fw_resource_cnt;
4003
4004 dma_addr_t fce_dma;
4005 void *fce;
4006 uint32_t fce_bufs;
4007 uint16_t fce_mb[8];
4008 uint64_t fce_wr, fce_rd;
4009 struct mutex fce_mutex;
4010
4011 uint32_t pci_attr;
4012 uint16_t chip_revision;
4013
4014 uint16_t product_id[4];
4015
4016 uint8_t model_number[16+1];
4017 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
4018 char model_desc[80];
4019 uint8_t adapter_id[16+1];
4020
4021 /* Option ROM information. */
4022 char *optrom_buffer;
4023 uint32_t optrom_size;
4024 int optrom_state;
4025 #define QLA_SWAITING 0
4026 #define QLA_SREADING 1
4027 #define QLA_SWRITING 2
4028 uint32_t optrom_region_start;
4029 uint32_t optrom_region_size;
4030 struct mutex optrom_mutex;
4031
4032 /* PCI expansion ROM image information. */
4033 #define ROM_CODE_TYPE_BIOS 0
4034 #define ROM_CODE_TYPE_FCODE 1
4035 #define ROM_CODE_TYPE_EFI 3
4036 uint8_t bios_revision[2];
4037 uint8_t efi_revision[2];
4038 uint8_t fcode_revision[16];
4039 uint32_t fw_revision[4];
4040
4041 uint32_t gold_fw_version[4];
4042
4043 /* Offsets for flash/nvram access (set to ~0 if not used). */
4044 uint32_t flash_conf_off;
4045 uint32_t flash_data_off;
4046 uint32_t nvram_conf_off;
4047 uint32_t nvram_data_off;
4048
4049 uint32_t fdt_wrt_disable;
4050 uint32_t fdt_wrt_enable;
4051 uint32_t fdt_erase_cmd;
4052 uint32_t fdt_block_size;
4053 uint32_t fdt_unprotect_sec_cmd;
4054 uint32_t fdt_protect_sec_cmd;
4055 uint32_t fdt_wrt_sts_reg_cmd;
4056
4057 uint32_t flt_region_flt;
4058 uint32_t flt_region_fdt;
4059 uint32_t flt_region_boot;
4060 uint32_t flt_region_boot_sec;
4061 uint32_t flt_region_fw;
4062 uint32_t flt_region_fw_sec;
4063 uint32_t flt_region_vpd_nvram;
4064 uint32_t flt_region_vpd;
4065 uint32_t flt_region_vpd_sec;
4066 uint32_t flt_region_nvram;
4067 uint32_t flt_region_npiv_conf;
4068 uint32_t flt_region_gold_fw;
4069 uint32_t flt_region_fcp_prio;
4070 uint32_t flt_region_bootload;
4071 uint32_t flt_region_img_status_pri;
4072 uint32_t flt_region_img_status_sec;
4073 uint8_t active_image;
4074
4075 /* Needed for BEACON */
4076 uint16_t beacon_blink_led;
4077 uint8_t beacon_color_state;
4078 #define QLA_LED_GRN_ON 0x01
4079 #define QLA_LED_YLW_ON 0x02
4080 #define QLA_LED_ABR_ON 0x04
4081 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
4082 /* ISP2322: red, green, amber. */
4083 uint16_t zio_mode;
4084 uint16_t zio_timer;
4085
4086 struct qla_msix_entry *msix_entries;
4087
4088 struct list_head vp_list; /* list of VP */
4089 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4090 sizeof(unsigned long)];
4091 uint16_t num_vhosts; /* number of vports created */
4092 uint16_t num_vsans; /* number of vsan created */
4093 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
4094 int cur_vport_count;
4095
4096 struct qla_chip_state_84xx *cs84xx;
4097 struct isp_operations *isp_ops;
4098 struct workqueue_struct *wq;
4099 struct qlfc_fw fw_buf;
4100
4101 /* FCP_CMND priority support */
4102 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4103
4104 struct dma_pool *dl_dma_pool;
4105 #define DSD_LIST_DMA_POOL_SIZE 512
4106
4107 struct dma_pool *fcp_cmnd_dma_pool;
4108 mempool_t *ctx_mempool;
4109 #define FCP_CMND_DMA_POOL_SIZE 512
4110
4111 void __iomem *nx_pcibase; /* Base I/O address */
4112 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
4113 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
4114
4115 uint32_t crb_win;
4116 uint32_t curr_window;
4117 uint32_t ddr_mn_window;
4118 unsigned long mn_win_crb;
4119 unsigned long ms_win_crb;
4120 int qdr_sn_window;
4121 uint32_t fcoe_dev_init_timeout;
4122 uint32_t fcoe_reset_timeout;
4123 rwlock_t hw_lock;
4124 uint16_t portnum; /* port number */
4125 int link_width;
4126 struct fw_blob *hablob;
4127 struct qla82xx_legacy_intr_set nx_legacy_intr;
4128
4129 uint16_t gbl_dsd_inuse;
4130 uint16_t gbl_dsd_avail;
4131 struct list_head gbl_dsd_list;
4132 #define NUM_DSD_CHAIN 4096
4133
4134 uint8_t fw_type;
4135 __le32 file_prd_off; /* File firmware product offset */
4136
4137 uint32_t md_template_size;
4138 void *md_tmplt_hdr;
4139 dma_addr_t md_tmplt_hdr_dma;
4140 void *md_dump;
4141 uint32_t md_dump_size;
4142
4143 void *loop_id_map;
4144
4145 /* QLA83XX IDC specific fields */
4146 uint32_t idc_audit_ts;
4147 uint32_t idc_extend_tmo;
4148
4149 /* DPC low-priority workqueue */
4150 struct workqueue_struct *dpc_lp_wq;
4151 struct work_struct idc_aen;
4152 /* DPC high-priority workqueue */
4153 struct workqueue_struct *dpc_hp_wq;
4154 struct work_struct nic_core_reset;
4155 struct work_struct idc_state_handler;
4156 struct work_struct nic_core_unrecoverable;
4157 struct work_struct board_disable;
4158
4159 struct mr_data_fx00 mr;
4160
4161 struct qlt_hw_data tgt;
4162 int allow_cna_fw_dump;
4163 uint32_t fw_ability_mask;
4164 uint16_t min_link_speed;
4165 uint16_t max_speed_sup;
4166
4167 atomic_t nvme_active_aen_cnt;
4168 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
4169 };
4170
4171 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4172 #define FW_ABILITY_MAX_SPEED_16G 0x0
4173 #define FW_ABILITY_MAX_SPEED_32G 0x1
4174 #define FW_ABILITY_MAX_SPEED(ha) \
4175 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4176
4177 /*
4178 * Qlogic scsi host structure
4179 */
4180 typedef struct scsi_qla_host {
4181 struct list_head list;
4182 struct list_head vp_fcports; /* list of fcports */
4183 struct list_head work_list;
4184 spinlock_t work_lock;
4185 struct work_struct iocb_work;
4186
4187 /* Commonly used flags and state information. */
4188 struct Scsi_Host *host;
4189 unsigned long host_no;
4190 uint8_t host_str[16];
4191
4192 volatile struct {
4193 uint32_t init_done :1;
4194 uint32_t online :1;
4195 uint32_t reset_active :1;
4196
4197 uint32_t management_server_logged_in :1;
4198 uint32_t process_response_queue :1;
4199 uint32_t difdix_supported:1;
4200 uint32_t delete_progress:1;
4201
4202 uint32_t fw_tgt_reported:1;
4203 uint32_t bbcr_enable:1;
4204 uint32_t qpairs_available:1;
4205 uint32_t qpairs_req_created:1;
4206 uint32_t qpairs_rsp_created:1;
4207 uint32_t nvme_enabled:1;
4208 } flags;
4209
4210 atomic_t loop_state;
4211 #define LOOP_TIMEOUT 1
4212 #define LOOP_DOWN 2
4213 #define LOOP_UP 3
4214 #define LOOP_UPDATE 4
4215 #define LOOP_READY 5
4216 #define LOOP_DEAD 6
4217
4218 unsigned long relogin_jif;
4219 unsigned long dpc_flags;
4220 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4221 #define RESET_ACTIVE 1
4222 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4223 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4224 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4225 #define LOOP_RESYNC_ACTIVE 5
4226 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4227 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4228 #define RELOGIN_NEEDED 8
4229 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4230 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4231 #define BEACON_BLINK_NEEDED 11
4232 #define REGISTER_FDMI_NEEDED 12
4233 #define FCPORT_UPDATE_NEEDED 13
4234 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4235 #define UNLOADING 15
4236 #define NPIV_CONFIG_NEEDED 16
4237 #define ISP_UNRECOVERABLE 17
4238 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4239 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4240 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4241 #define FREE_BIT 21
4242 #define PORT_UPDATE_NEEDED 22
4243 #define FX00_RESET_RECOVERY 23
4244 #define FX00_TARGET_SCAN 24
4245 #define FX00_CRITEMP_RECOVERY 25
4246 #define FX00_HOST_INFO_RESEND 26
4247 #define QPAIR_ONLINE_CHECK_NEEDED 27
4248 #define SET_ZIO_THRESHOLD_NEEDED 28
4249 #define DETECT_SFP_CHANGE 29
4250 #define N2N_LOGIN_NEEDED 30
4251 #define IOCB_WORK_ACTIVE 31
4252
4253 unsigned long pci_flags;
4254 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4255 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4256 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4257
4258 uint32_t device_flags;
4259 #define SWITCH_FOUND BIT_0
4260 #define DFLG_NO_CABLE BIT_1
4261 #define DFLG_DEV_FAILED BIT_5
4262
4263 /* ISP configuration data. */
4264 uint16_t loop_id; /* Host adapter loop id */
4265 uint16_t self_login_loop_id; /* host adapter loop id
4266 * get it on self login
4267 */
4268 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4269 * no need of allocating it for
4270 * each command
4271 */
4272
4273 port_id_t d_id; /* Host adapter port id */
4274 uint8_t marker_needed;
4275 uint16_t mgmt_svr_loop_id;
4276
4277
4278
4279 /* Timeout timers. */
4280 uint8_t loop_down_abort_time; /* port down timer */
4281 atomic_t loop_down_timer; /* loop down timer */
4282 uint8_t link_down_timeout; /* link down timeout */
4283
4284 uint32_t timer_active;
4285 struct timer_list timer;
4286
4287 uint8_t node_name[WWN_SIZE];
4288 uint8_t port_name[WWN_SIZE];
4289 uint8_t fabric_node_name[WWN_SIZE];
4290
4291 struct nvme_fc_local_port *nvme_local_port;
4292 struct completion nvme_del_done;
4293 struct list_head nvme_rport_list;
4294
4295 uint16_t fcoe_vlan_id;
4296 uint16_t fcoe_fcf_idx;
4297 uint8_t fcoe_vn_port_mac[6];
4298
4299 /* list of commands waiting on workqueue */
4300 struct list_head qla_cmd_list;
4301 struct list_head qla_sess_op_cmd_list;
4302 struct list_head unknown_atio_list;
4303 spinlock_t cmd_list_lock;
4304 struct delayed_work unknown_atio_work;
4305
4306 /* Counter to detect races between ELS and RSCN events */
4307 atomic_t generation_tick;
4308 /* Time when global fcport update has been scheduled */
4309 int total_fcport_update_gen;
4310 /* List of pending LOGOs, protected by tgt_mutex */
4311 struct list_head logo_list;
4312 /* List of pending PLOGI acks, protected by hw lock */
4313 struct list_head plogi_ack_list;
4314
4315 struct list_head qp_list;
4316
4317 uint32_t vp_abort_cnt;
4318
4319 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4320 uint16_t vp_idx; /* vport ID */
4321 struct qla_qpair *qpair; /* base qpair */
4322
4323 unsigned long vp_flags;
4324 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4325 #define VP_CREATE_NEEDED 1
4326 #define VP_BIND_NEEDED 2
4327 #define VP_DELETE_NEEDED 3
4328 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4329 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4330 atomic_t vp_state;
4331 #define VP_OFFLINE 0
4332 #define VP_ACTIVE 1
4333 #define VP_FAILED 2
4334 // #define VP_DISABLE 3
4335 uint16_t vp_err_state;
4336 uint16_t vp_prev_err_state;
4337 #define VP_ERR_UNKWN 0
4338 #define VP_ERR_PORTDWN 1
4339 #define VP_ERR_FAB_UNSUPPORTED 2
4340 #define VP_ERR_FAB_NORESOURCES 3
4341 #define VP_ERR_FAB_LOGOUT 4
4342 #define VP_ERR_ADAP_NORESOURCES 5
4343 struct qla_hw_data *hw;
4344 struct scsi_qlt_host vha_tgt;
4345 struct req_que *req;
4346 int fw_heartbeat_counter;
4347 int seconds_since_last_heartbeat;
4348 struct fc_host_statistics fc_host_stat;
4349 struct qla_statistics qla_stats;
4350 struct bidi_statistics bidi_stats;
4351 atomic_t vref_count;
4352 struct qla8044_reset_template reset_tmplt;
4353 uint16_t bbcr;
4354 struct name_list_extended gnl;
4355 /* Count of active session/fcport */
4356 int fcport_count;
4357 wait_queue_head_t fcport_waitQ;
4358 wait_queue_head_t vref_waitq;
4359 uint8_t min_link_speed_feat;
4360 uint8_t n2n_node_name[WWN_SIZE];
4361 uint8_t n2n_port_name[WWN_SIZE];
4362 uint16_t n2n_id;
4363 struct list_head gpnid_list;
4364 struct fab_scan scan;
4365 } scsi_qla_host_t;
4366
4367 struct qla27xx_image_status {
4368 uint8_t image_status_mask;
4369 uint16_t generation_number;
4370 uint8_t reserved[3];
4371 uint8_t ver_minor;
4372 uint8_t ver_major;
4373 uint32_t checksum;
4374 uint32_t signature;
4375 } __packed;
4376
4377 #define SET_VP_IDX 1
4378 #define SET_AL_PA 2
4379 #define RESET_VP_IDX 3
4380 #define RESET_AL_PA 4
4381 struct qla_tgt_vp_map {
4382 uint8_t idx;
4383 scsi_qla_host_t *vha;
4384 };
4385
4386 struct qla2_sgx {
4387 dma_addr_t dma_addr; /* OUT */
4388 uint32_t dma_len; /* OUT */
4389
4390 uint32_t tot_bytes; /* IN */
4391 struct scatterlist *cur_sg; /* IN */
4392
4393 /* for book keeping, bzero on initial invocation */
4394 uint32_t bytes_consumed;
4395 uint32_t num_bytes;
4396 uint32_t tot_partial;
4397
4398 /* for debugging */
4399 uint32_t num_sg;
4400 srb_t *sp;
4401 };
4402
4403 #define QLA_FW_STARTED(_ha) { \
4404 int i; \
4405 _ha->flags.fw_started = 1; \
4406 _ha->base_qpair->fw_started = 1; \
4407 for (i = 0; i < _ha->max_qpairs; i++) { \
4408 if (_ha->queue_pair_map[i]) \
4409 _ha->queue_pair_map[i]->fw_started = 1; \
4410 } \
4411 }
4412
4413 #define QLA_FW_STOPPED(_ha) { \
4414 int i; \
4415 _ha->flags.fw_started = 0; \
4416 _ha->base_qpair->fw_started = 0; \
4417 for (i = 0; i < _ha->max_qpairs; i++) { \
4418 if (_ha->queue_pair_map[i]) \
4419 _ha->queue_pair_map[i]->fw_started = 0; \
4420 } \
4421 }
4422
4423 /*
4424 * Macros to help code, maintain, etc.
4425 */
4426 #define LOOP_TRANSITION(ha) \
4427 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4428 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4429 atomic_read(&ha->loop_state) == LOOP_DOWN)
4430
4431 #define STATE_TRANSITION(ha) \
4432 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4433 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4434
4435 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4436 atomic_inc(&__vha->vref_count); \
4437 mb(); \
4438 if (__vha->flags.delete_progress) { \
4439 atomic_dec(&__vha->vref_count); \
4440 wake_up(&__vha->vref_waitq); \
4441 __bail = 1; \
4442 } else { \
4443 __bail = 0; \
4444 } \
4445 } while (0)
4446
4447 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4448 atomic_dec(&__vha->vref_count); \
4449 wake_up(&__vha->vref_waitq); \
4450 } while (0) \
4451
4452 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4453 atomic_inc(&__qpair->ref_count); \
4454 mb(); \
4455 if (__qpair->delete_in_progress) { \
4456 atomic_dec(&__qpair->ref_count); \
4457 __bail = 1; \
4458 } else { \
4459 __bail = 0; \
4460 } \
4461 } while (0)
4462
4463 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4464 atomic_dec(&__qpair->ref_count); \
4465
4466
4467 #define QLA_ENA_CONF(_ha) {\
4468 int i;\
4469 _ha->base_qpair->enable_explicit_conf = 1; \
4470 for (i = 0; i < _ha->max_qpairs; i++) { \
4471 if (_ha->queue_pair_map[i]) \
4472 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4473 } \
4474 }
4475
4476 #define QLA_DIS_CONF(_ha) {\
4477 int i;\
4478 _ha->base_qpair->enable_explicit_conf = 0; \
4479 for (i = 0; i < _ha->max_qpairs; i++) { \
4480 if (_ha->queue_pair_map[i]) \
4481 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4482 } \
4483 }
4484
4485 /*
4486 * qla2x00 local function return status codes
4487 */
4488 #define MBS_MASK 0x3fff
4489
4490 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4491 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4492 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4493 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4494 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4495 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4496 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4497 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4498 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4499 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4500
4501 #define QLA_FUNCTION_TIMEOUT 0x100
4502 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
4503 #define QLA_FUNCTION_FAILED 0x102
4504 #define QLA_MEMORY_ALLOC_FAILED 0x103
4505 #define QLA_LOCK_TIMEOUT 0x104
4506 #define QLA_ABORTED 0x105
4507 #define QLA_SUSPENDED 0x106
4508 #define QLA_BUSY 0x107
4509 #define QLA_ALREADY_REGISTERED 0x109
4510
4511 #define NVRAM_DELAY() udelay(10)
4512
4513 /*
4514 * Flash support definitions
4515 */
4516 #define OPTROM_SIZE_2300 0x20000
4517 #define OPTROM_SIZE_2322 0x100000
4518 #define OPTROM_SIZE_24XX 0x100000
4519 #define OPTROM_SIZE_25XX 0x200000
4520 #define OPTROM_SIZE_81XX 0x400000
4521 #define OPTROM_SIZE_82XX 0x800000
4522 #define OPTROM_SIZE_83XX 0x1000000
4523
4524 #define OPTROM_BURST_SIZE 0x1000
4525 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4526
4527 #define QLA_DSDS_PER_IOCB 37
4528
4529 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4530
4531 #define QLA_SG_ALL 1024
4532
4533 enum nexus_wait_type {
4534 WAIT_HOST = 0,
4535 WAIT_TARGET,
4536 WAIT_LUN,
4537 };
4538
4539 /* Refer to SNIA SFF 8247 */
4540 struct sff_8247_a0 {
4541 u8 txid; /* transceiver id */
4542 u8 ext_txid;
4543 u8 connector;
4544 /* compliance code */
4545 u8 eth_infi_cc3; /* ethernet, inifiband */
4546 u8 sonet_cc4[2];
4547 u8 eth_cc6;
4548 /* link length */
4549 #define FC_LL_VL BIT_7 /* very long */
4550 #define FC_LL_S BIT_6 /* Short */
4551 #define FC_LL_I BIT_5 /* Intermidiate*/
4552 #define FC_LL_L BIT_4 /* Long */
4553 #define FC_LL_M BIT_3 /* Medium */
4554 #define FC_LL_SA BIT_2 /* ShortWave laser */
4555 #define FC_LL_LC BIT_1 /* LongWave laser */
4556 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
4557 u8 fc_ll_cc7;
4558 /* FC technology */
4559 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
4560 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
4561 #define FC_TEC_SL BIT_5 /* short wave with OFC */
4562 #define FC_TEC_LL BIT_4 /* Longwave Laser */
4563 #define FC_TEC_ACT BIT_3 /* Active cable */
4564 #define FC_TEC_PAS BIT_2 /* Passive cable */
4565 u8 fc_tec_cc8;
4566 /* Transmission Media */
4567 #define FC_MED_TW BIT_7 /* Twin Ax */
4568 #define FC_MED_TP BIT_6 /* Twited Pair */
4569 #define FC_MED_MI BIT_5 /* Min Coax */
4570 #define FC_MED_TV BIT_4 /* Video Coax */
4571 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
4572 #define FC_MED_M5 BIT_2 /* Multimode, 50um */
4573 #define FC_MED_SM BIT_0 /* Single Mode */
4574 u8 fc_med_cc9;
4575 /* speed FC_SP_12: 12*100M = 1200 MB/s */
4576 #define FC_SP_12 BIT_7
4577 #define FC_SP_8 BIT_6
4578 #define FC_SP_16 BIT_5
4579 #define FC_SP_4 BIT_4
4580 #define FC_SP_32 BIT_3
4581 #define FC_SP_2 BIT_2
4582 #define FC_SP_1 BIT_0
4583 u8 fc_sp_cc10;
4584 u8 encode;
4585 u8 bitrate;
4586 u8 rate_id;
4587 u8 length_km; /* offset 14/eh */
4588 u8 length_100m;
4589 u8 length_50um_10m;
4590 u8 length_62um_10m;
4591 u8 length_om4_10m;
4592 u8 length_om3_10m;
4593 #define SFF_VEN_NAME_LEN 16
4594 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
4595 u8 tx_compat;
4596 u8 vendor_oui[3];
4597 #define SFF_PART_NAME_LEN 16
4598 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
4599 u8 vendor_rev[4];
4600 u8 wavelength[2];
4601 u8 resv;
4602 u8 cc_base;
4603 u8 options[2]; /* offset 64 */
4604 u8 br_max;
4605 u8 br_min;
4606 u8 vendor_sn[16];
4607 u8 date_code[8];
4608 u8 diag;
4609 u8 enh_options;
4610 u8 sff_revision;
4611 u8 cc_ext;
4612 u8 vendor_specific[32];
4613 u8 resv2[128];
4614 };
4615
4616 #define AUTO_DETECT_SFP_SUPPORT(_vha)\
4617 (ql2xautodetectsfp && !_vha->vp_idx && \
4618 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\
4619 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw)))
4620
4621 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4622 (IS_QLA27XX(_ha) || IS_QLA83XX(_ha)))
4623
4624 #define SAVE_TOPO(_ha) { \
4625 if (_ha->current_topology) \
4626 _ha->prev_topology = _ha->current_topology; \
4627 }
4628
4629 #define N2N_TOPO(ha) \
4630 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
4631 ha->current_topology == ISP_CFG_N || \
4632 !ha->current_topology)
4633
4634 #include "qla_target.h"
4635 #include "qla_gbl.h"
4636 #include "qla_dbg.h"
4637 #include "qla_inline.h"
4638 #endif
Linux with added FPC-III support