drivers/video/fbdev/omap2/omapfb/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #include <linux/interrupt.h>
  27
  28 #ifdef pr_fmt
  29 #undef pr_fmt
  30 #endif
  31
  32 #ifdef DSS_SUBSYS_NAME
  33 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
  34 #else
  35 #define pr_fmt(fmt) fmt
  36 #endif
  37
  38 #define DSSDBG(format, ...) \
  39         pr_debug(format, ## __VA_ARGS__)
  40
  41 #ifdef DSS_SUBSYS_NAME
  42 #define DSSERR(format, ...) \
  43         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  44         ## __VA_ARGS__)
  45 #else
  46 #define DSSERR(format, ...) \
  47         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  48 #endif
  49
  50 #ifdef DSS_SUBSYS_NAME
  51 #define DSSINFO(format, ...) \
  52         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  53         ## __VA_ARGS__)
  54 #else
  55 #define DSSINFO(format, ...) \
  56         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  57 #endif
  58
  59 #ifdef DSS_SUBSYS_NAME
  60 #define DSSWARN(format, ...) \
  61         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  62         ## __VA_ARGS__)
  63 #else
  64 #define DSSWARN(format, ...) \
  65         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  66 #endif
  67
  68 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  69    number. For example 7:0 */
  70 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  71 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  72 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  73 #define FLD_MOD(orig, val, start, end) \
  74         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  75
  76 enum omap_dss_clk_source {
  77         OMAP_DSS_CLK_SRC_FCK = 0,               /* OMAP2/3: DSS1_ALWON_FCLK
  78                                                  * OMAP4: DSS_FCLK */
  79         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,   /* OMAP3: DSI1_PLL_FCLK
  80                                                  * OMAP4: PLL1_CLK1 */
  81         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,     /* OMAP3: DSI2_PLL_FCLK
  82                                                  * OMAP4: PLL1_CLK2 */
  83         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,  /* OMAP4: PLL2_CLK1 */
  84         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,    /* OMAP4: PLL2_CLK2 */
  85 };
  86
  87 enum dss_io_pad_mode {
  88         DSS_IO_PAD_MODE_RESET,
  89         DSS_IO_PAD_MODE_RFBI,
  90         DSS_IO_PAD_MODE_BYPASS,
  91 };
  92
  93 enum dss_hdmi_venc_clk_source_select {
  94         DSS_VENC_TV_CLK = 0,
  95         DSS_HDMI_M_PCLK = 1,
  96 };
  97
  98 enum dss_dsi_content_type {
  99         DSS_DSI_CONTENT_DCS,
 100         DSS_DSI_CONTENT_GENERIC,
 101 };
 102
 103 enum dss_writeback_channel {
 104         DSS_WB_LCD1_MGR =       0,
 105         DSS_WB_LCD2_MGR =       1,
 106         DSS_WB_TV_MGR =         2,
 107         DSS_WB_OVL0 =           3,
 108         DSS_WB_OVL1 =           4,
 109         DSS_WB_OVL2 =           5,
 110         DSS_WB_OVL3 =           6,
 111         DSS_WB_LCD3_MGR =       7,
 112 };
 113
 114 enum dss_pll_id {
 115         DSS_PLL_DSI1,
 116         DSS_PLL_DSI2,
 117         DSS_PLL_HDMI,
 118         DSS_PLL_VIDEO1,
 119         DSS_PLL_VIDEO2,
 120 };
 121
 122 struct dss_pll;
 123
 124 #define DSS_PLL_MAX_HSDIVS 4
 125
 126 /*
 127  * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
 128  * Type-B PLLs: clkout[0] refers to m2.
 129  */
 130 struct dss_pll_clock_info {
 131         /* rates that we get with dividers below */
 132         unsigned long fint;
 133         unsigned long clkdco;
 134         unsigned long clkout[DSS_PLL_MAX_HSDIVS];
 135
 136         /* dividers */
 137         u16 n;
 138         u16 m;
 139         u32 mf;
 140         u16 mX[DSS_PLL_MAX_HSDIVS];
 141         u16 sd;
 142 };
 143
 144 struct dss_pll_ops {
 145         int (*enable)(struct dss_pll *pll);
 146         void (*disable)(struct dss_pll *pll);
 147         int (*set_config)(struct dss_pll *pll,
 148                 const struct dss_pll_clock_info *cinfo);
 149 };
 150
 151 struct dss_pll_hw {
 152         unsigned n_max;
 153         unsigned m_min;
 154         unsigned m_max;
 155         unsigned mX_max;
 156
 157         unsigned long fint_min, fint_max;
 158         unsigned long clkdco_min, clkdco_low, clkdco_max;
 159
 160         u8 n_msb, n_lsb;
 161         u8 m_msb, m_lsb;
 162         u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
 163
 164         bool has_stopmode;
 165         bool has_freqsel;
 166         bool has_selfreqdco;
 167         bool has_refsel;
 168 };
 169
 170 struct dss_pll {
 171         const char *name;
 172         enum dss_pll_id id;
 173
 174         struct clk *clkin;
 175         struct regulator *regulator;
 176
 177         void __iomem *base;
 178
 179         const struct dss_pll_hw *hw;
 180
 181         const struct dss_pll_ops *ops;
 182
 183         struct dss_pll_clock_info cinfo;
 184 };
 185
 186 struct dispc_clock_info {
 187         /* rates that we get with dividers below */
 188         unsigned long lck;
 189         unsigned long pck;
 190
 191         /* dividers */
 192         u16 lck_div;
 193         u16 pck_div;
 194 };
 195
 196 struct dss_lcd_mgr_config {
 197         enum dss_io_pad_mode io_pad_mode;
 198
 199         bool stallmode;
 200         bool fifohandcheck;
 201
 202         struct dispc_clock_info clock_info;
 203
 204         int video_port_width;
 205
 206         int lcden_sig_polarity;
 207 };
 208
 209 struct seq_file;
 210 struct platform_device;
 211
 212 /* core */
 213 struct platform_device *dss_get_core_pdev(void);
 214 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
 215 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
 216 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
 217 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
 218
 219 /* display */
 220 int dss_suspend_all_devices(void);
 221 int dss_resume_all_devices(void);
 222 void dss_disable_all_devices(void);
 223
 224 int display_init_sysfs(struct platform_device *pdev);
 225 void display_uninit_sysfs(struct platform_device *pdev);
 226
 227 /* manager */
 228 int dss_init_overlay_managers(void);
 229 void dss_uninit_overlay_managers(void);
 230 int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
 231 void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
 232 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
 233                 const struct omap_overlay_manager_info *info);
 234 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
 235                 const struct omap_video_timings *timings);
 236 int dss_mgr_check(struct omap_overlay_manager *mgr,
 237                 struct omap_overlay_manager_info *info,
 238                 const struct omap_video_timings *mgr_timings,
 239                 const struct dss_lcd_mgr_config *config,
 240                 struct omap_overlay_info **overlay_infos);
 241
 242 static inline bool dss_mgr_is_lcd(enum omap_channel id)
 243 {
 244         if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
 245                         id == OMAP_DSS_CHANNEL_LCD3)
 246                 return true;
 247         else
 248                 return false;
 249 }
 250
 251 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
 252                 struct platform_device *pdev);
 253 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
 254
 255 /* overlay */
 256 void dss_init_overlays(struct platform_device *pdev);
 257 void dss_uninit_overlays(struct platform_device *pdev);
 258 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 259 int dss_ovl_simple_check(struct omap_overlay *ovl,
 260                 const struct omap_overlay_info *info);
 261 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
 262                 const struct omap_video_timings *mgr_timings);
 263 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
 264                 enum omap_color_mode mode);
 265 int dss_overlay_kobj_init(struct omap_overlay *ovl,
 266                 struct platform_device *pdev);
 267 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
 268
 269 /* DSS */
 270 int dss_init_platform_driver(void) __init;
 271 void dss_uninit_platform_driver(void);
 272
 273 int dss_runtime_get(void);
 274 void dss_runtime_put(void);
 275
 276 unsigned long dss_get_dispc_clk_rate(void);
 277 int dss_dpi_select_source(int port, enum omap_channel channel);
 278 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 279 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 280 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 281 void dss_dump_clocks(struct seq_file *s);
 282
 283 /* DSS VIDEO PLL */
 284 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
 285         struct regulator *regulator);
 286 void dss_video_pll_uninit(struct dss_pll *pll);
 287
 288 /* dss-of */
 289 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
 290 u32 dss_of_port_get_port_number(struct device_node *port);
 291
 292 #if defined(CONFIG_FB_OMAP2_DSS_DEBUGFS)
 293 void dss_debug_dump_clocks(struct seq_file *s);
 294 #endif
 295
 296 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
 297 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
 298         enum omap_channel channel);
 299
 300 void dss_sdi_init(int datapairs);
 301 int dss_sdi_enable(void);
 302 void dss_sdi_disable(void);
 303
 304 void dss_select_dsi_clk_source(int dsi_module,
 305                 enum omap_dss_clk_source clk_src);
 306 void dss_select_lcd_clk_source(enum omap_channel channel,
 307                 enum omap_dss_clk_source clk_src);
 308 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 309 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 310 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 311
 312 void dss_set_venc_output(enum omap_dss_venc_type type);
 313 void dss_set_dac_pwrdn_bgz(bool enable);
 314
 315 int dss_set_fck_rate(unsigned long rate);
 316
 317 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
 318 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
 319                 dss_div_calc_func func, void *data);
 320
 321 /* SDI */
 322 int sdi_init_platform_driver(void) __init;
 323 void sdi_uninit_platform_driver(void);
 324
 325 #ifdef CONFIG_FB_OMAP2_DSS_SDI
 326 int sdi_init_port(struct platform_device *pdev, struct device_node *port);
 327 void sdi_uninit_port(struct device_node *port);
 328 #else
 329 static inline int sdi_init_port(struct platform_device *pdev,
 330                 struct device_node *port)
 331 {
 332         return 0;
 333 }
 334 static inline void sdi_uninit_port(struct device_node *port)
 335 {
 336 }
 337 #endif
 338
 339 /* DSI */
 340
 341 #ifdef CONFIG_FB_OMAP2_DSS_DSI
 342
 343 struct dentry;
 344 struct file_operations;
 345
 346 int dsi_init_platform_driver(void) __init;
 347 void dsi_uninit_platform_driver(void);
 348
 349 void dsi_dump_clocks(struct seq_file *s);
 350
 351 void dsi_irq_handler(void);
 352 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 353
 354 #else
 355 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 356 {
 357         WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
 358              __func__);
 359         return 0;
 360 }
 361 #endif
 362
 363 /* DPI */
 364 int dpi_init_platform_driver(void) __init;
 365 void dpi_uninit_platform_driver(void);
 366
 367 #ifdef CONFIG_FB_OMAP2_DSS_DPI
 368 int dpi_init_port(struct platform_device *pdev, struct device_node *port);
 369 void dpi_uninit_port(struct device_node *port);
 370 #else
 371 static inline int dpi_init_port(struct platform_device *pdev,
 372                 struct device_node *port)
 373 {
 374         return 0;
 375 }
 376 static inline void dpi_uninit_port(struct device_node *port)
 377 {
 378 }
 379 #endif
 380
 381 /* DISPC */
 382 int dispc_init_platform_driver(void) __init;
 383 void dispc_uninit_platform_driver(void);
 384 void dispc_dump_clocks(struct seq_file *s);
 385
 386 void dispc_enable_sidle(void);
 387 void dispc_disable_sidle(void);
 388
 389 void dispc_lcd_enable_signal(bool enable);
 390 void dispc_pck_free_enable(bool enable);
 391 void dispc_enable_fifomerge(bool enable);
 392 void dispc_enable_gamma_table(bool enable);
 393
 394 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
 395                 unsigned long pck, void *data);
 396 bool dispc_div_calc(unsigned long dispc,
 397                 unsigned long pck_min, unsigned long pck_max,
 398                 dispc_div_calc_func func, void *data);
 399
 400 bool dispc_mgr_timings_ok(enum omap_channel channel,
 401                 const struct omap_video_timings *timings);
 402 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 403                 struct dispc_clock_info *cinfo);
 404
 405
 406 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 407 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
 408                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
 409                 bool manual_update);
 410
 411 void dispc_mgr_set_clock_div(enum omap_channel channel,
 412                 const struct dispc_clock_info *cinfo);
 413 int dispc_mgr_get_clock_div(enum omap_channel channel,
 414                 struct dispc_clock_info *cinfo);
 415 void dispc_set_tv_pclk(unsigned long pclk);
 416
 417 u32 dispc_wb_get_framedone_irq(void);
 418 bool dispc_wb_go_busy(void);
 419 void dispc_wb_go(void);
 420 void dispc_wb_enable(bool enable);
 421 bool dispc_wb_is_enabled(void);
 422 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
 423 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
 424                 bool mem_to_mem, const struct omap_video_timings *timings);
 425
 426 u32 dispc_read_irqstatus(void);
 427 void dispc_clear_irqstatus(u32 mask);
 428 u32 dispc_read_irqenable(void);
 429 void dispc_write_irqenable(u32 mask);
 430
 431 int dispc_request_irq(irq_handler_t handler, void *dev_id);
 432 void dispc_free_irq(void *dev_id);
 433
 434 int dispc_runtime_get(void);
 435 void dispc_runtime_put(void);
 436
 437 void dispc_mgr_enable(enum omap_channel channel, bool enable);
 438 bool dispc_mgr_is_enabled(enum omap_channel channel);
 439 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
 440 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
 441 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
 442 bool dispc_mgr_go_busy(enum omap_channel channel);
 443 void dispc_mgr_go(enum omap_channel channel);
 444 void dispc_mgr_set_lcd_config(enum omap_channel channel,
 445                 const struct dss_lcd_mgr_config *config);
 446 void dispc_mgr_set_timings(enum omap_channel channel,
 447                 const struct omap_video_timings *timings);
 448 void dispc_mgr_setup(enum omap_channel channel,
 449                 const struct omap_overlay_manager_info *info);
 450
 451 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
 452                 const struct omap_overlay_info *oi,
 453                 const struct omap_video_timings *timings,
 454                 int *x_predecim, int *y_predecim);
 455
 456 int dispc_ovl_enable(enum omap_plane plane, bool enable);
 457 bool dispc_ovl_enabled(enum omap_plane plane);
 458 void dispc_ovl_set_channel_out(enum omap_plane plane,
 459                 enum omap_channel channel);
 460 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
 461                 bool replication, const struct omap_video_timings *mgr_timings,
 462                 bool mem_to_mem);
 463
 464 /* VENC */
 465 int venc_init_platform_driver(void) __init;
 466 void venc_uninit_platform_driver(void);
 467
 468 /* HDMI */
 469 int hdmi4_init_platform_driver(void) __init;
 470 void hdmi4_uninit_platform_driver(void);
 471
 472 int hdmi5_init_platform_driver(void) __init;
 473 void hdmi5_uninit_platform_driver(void);
 474
 475 /* RFBI */
 476 int rfbi_init_platform_driver(void) __init;
 477 void rfbi_uninit_platform_driver(void);
 478
 479
 480 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
 481 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 482 {
 483         int b;
 484         for (b = 0; b < 32; ++b) {
 485                 if (irqstatus & (1 << b))
 486                         irq_arr[b]++;
 487         }
 488 }
 489 #endif
 490
 491 /* PLL */
 492 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
 493                 unsigned long clkdco, void *data);
 494 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
 495                 void *data);
 496
 497 int dss_pll_register(struct dss_pll *pll);
 498 void dss_pll_unregister(struct dss_pll *pll);
 499 struct dss_pll *dss_pll_find(const char *name);
 500 int dss_pll_enable(struct dss_pll *pll);
 501 void dss_pll_disable(struct dss_pll *pll);
 502 int dss_pll_set_config(struct dss_pll *pll,
 503                 const struct dss_pll_clock_info *cinfo);
 504
 505 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
 506                 unsigned long out_min, unsigned long out_max,
 507                 dss_hsdiv_calc_func func, void *data);
 508 bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
 509                 unsigned long pll_min, unsigned long pll_max,
 510                 dss_pll_calc_func func, void *data);
 511 int dss_pll_write_config_type_a(struct dss_pll *pll,
 512                 const struct dss_pll_clock_info *cinfo);
 513 int dss_pll_write_config_type_b(struct dss_pll *pll,
 514                 const struct dss_pll_clock_info *cinfo);
 515 int dss_pll_wait_reset_done(struct dss_pll *pll);
 516
 517 /* compat */
 518
 519 struct dss_mgr_ops {
 520         int (*connect)(struct omap_overlay_manager *mgr,
 521                 struct omap_dss_device *dst);
 522         void (*disconnect)(struct omap_overlay_manager *mgr,
 523                 struct omap_dss_device *dst);
 524
 525         void (*start_update)(struct omap_overlay_manager *mgr);
 526         int (*enable)(struct omap_overlay_manager *mgr);
 527         void (*disable)(struct omap_overlay_manager *mgr);
 528         void (*set_timings)(struct omap_overlay_manager *mgr,
 529                         const struct omap_video_timings *timings);
 530         void (*set_lcd_config)(struct omap_overlay_manager *mgr,
 531                         const struct dss_lcd_mgr_config *config);
 532         int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
 533                         void (*handler)(void *), void *data);
 534         void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
 535                         void (*handler)(void *), void *data);
 536 };
 537
 538 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
 539 void dss_uninstall_mgr_ops(void);
 540
 541 int dss_mgr_connect(struct omap_overlay_manager *mgr,
 542                 struct omap_dss_device *dst);
 543 void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
 544                 struct omap_dss_device *dst);
 545 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
 546                 const struct omap_video_timings *timings);
 547 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
 548                 const struct dss_lcd_mgr_config *config);
 549 int dss_mgr_enable(struct omap_overlay_manager *mgr);
 550 void dss_mgr_disable(struct omap_overlay_manager *mgr);
 551 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
 552 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
 553                 void (*handler)(void *), void *data);
 554 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
 555                 void (*handler)(void *), void *data);
 556
 557 #endif